1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 4 /* ethtool support for igb */ 5 6 #include <linux/vmalloc.h> 7 #include <linux/netdevice.h> 8 #include <linux/pci.h> 9 #include <linux/delay.h> 10 #include <linux/interrupt.h> 11 #include <linux/if_ether.h> 12 #include <linux/ethtool.h> 13 #include <linux/sched.h> 14 #include <linux/slab.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/highmem.h> 17 #include <linux/mdio.h> 18 19 #include "igb.h" 20 21 struct igb_stats { 22 char stat_string[ETH_GSTRING_LEN]; 23 int sizeof_stat; 24 int stat_offset; 25 }; 26 27 #define IGB_STAT(_name, _stat) { \ 28 .stat_string = _name, \ 29 .sizeof_stat = sizeof_field(struct igb_adapter, _stat), \ 30 .stat_offset = offsetof(struct igb_adapter, _stat) \ 31 } 32 static const struct igb_stats igb_gstrings_stats[] = { 33 IGB_STAT("rx_packets", stats.gprc), 34 IGB_STAT("tx_packets", stats.gptc), 35 IGB_STAT("rx_bytes", stats.gorc), 36 IGB_STAT("tx_bytes", stats.gotc), 37 IGB_STAT("rx_broadcast", stats.bprc), 38 IGB_STAT("tx_broadcast", stats.bptc), 39 IGB_STAT("rx_multicast", stats.mprc), 40 IGB_STAT("tx_multicast", stats.mptc), 41 IGB_STAT("multicast", stats.mprc), 42 IGB_STAT("collisions", stats.colc), 43 IGB_STAT("rx_crc_errors", stats.crcerrs), 44 IGB_STAT("rx_no_buffer_count", stats.rnbc), 45 IGB_STAT("rx_missed_errors", stats.mpc), 46 IGB_STAT("tx_aborted_errors", stats.ecol), 47 IGB_STAT("tx_carrier_errors", stats.tncrs), 48 IGB_STAT("tx_window_errors", stats.latecol), 49 IGB_STAT("tx_abort_late_coll", stats.latecol), 50 IGB_STAT("tx_deferred_ok", stats.dc), 51 IGB_STAT("tx_single_coll_ok", stats.scc), 52 IGB_STAT("tx_multi_coll_ok", stats.mcc), 53 IGB_STAT("tx_timeout_count", tx_timeout_count), 54 IGB_STAT("rx_long_length_errors", stats.roc), 55 IGB_STAT("rx_short_length_errors", stats.ruc), 56 IGB_STAT("rx_align_errors", stats.algnerrc), 57 IGB_STAT("tx_tcp_seg_good", stats.tsctc), 58 IGB_STAT("tx_tcp_seg_failed", stats.tsctfc), 59 IGB_STAT("rx_flow_control_xon", stats.xonrxc), 60 IGB_STAT("rx_flow_control_xoff", stats.xoffrxc), 61 IGB_STAT("tx_flow_control_xon", stats.xontxc), 62 IGB_STAT("tx_flow_control_xoff", stats.xofftxc), 63 IGB_STAT("rx_long_byte_count", stats.gorc), 64 IGB_STAT("tx_dma_out_of_sync", stats.doosync), 65 IGB_STAT("tx_smbus", stats.mgptc), 66 IGB_STAT("rx_smbus", stats.mgprc), 67 IGB_STAT("dropped_smbus", stats.mgpdc), 68 IGB_STAT("os2bmc_rx_by_bmc", stats.o2bgptc), 69 IGB_STAT("os2bmc_tx_by_bmc", stats.b2ospc), 70 IGB_STAT("os2bmc_tx_by_host", stats.o2bspc), 71 IGB_STAT("os2bmc_rx_by_host", stats.b2ogprc), 72 IGB_STAT("tx_hwtstamp_timeouts", tx_hwtstamp_timeouts), 73 IGB_STAT("tx_hwtstamp_skipped", tx_hwtstamp_skipped), 74 IGB_STAT("rx_hwtstamp_cleared", rx_hwtstamp_cleared), 75 }; 76 77 #define IGB_NETDEV_STAT(_net_stat) { \ 78 .stat_string = __stringify(_net_stat), \ 79 .sizeof_stat = sizeof_field(struct rtnl_link_stats64, _net_stat), \ 80 .stat_offset = offsetof(struct rtnl_link_stats64, _net_stat) \ 81 } 82 static const struct igb_stats igb_gstrings_net_stats[] = { 83 IGB_NETDEV_STAT(rx_errors), 84 IGB_NETDEV_STAT(tx_errors), 85 IGB_NETDEV_STAT(tx_dropped), 86 IGB_NETDEV_STAT(rx_length_errors), 87 IGB_NETDEV_STAT(rx_over_errors), 88 IGB_NETDEV_STAT(rx_frame_errors), 89 IGB_NETDEV_STAT(rx_fifo_errors), 90 IGB_NETDEV_STAT(tx_fifo_errors), 91 IGB_NETDEV_STAT(tx_heartbeat_errors) 92 }; 93 94 #define IGB_GLOBAL_STATS_LEN \ 95 (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats)) 96 #define IGB_NETDEV_STATS_LEN \ 97 (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats)) 98 #define IGB_RX_QUEUE_STATS_LEN \ 99 (sizeof(struct igb_rx_queue_stats) / sizeof(u64)) 100 101 #define IGB_TX_QUEUE_STATS_LEN 3 /* packets, bytes, restart_queue */ 102 103 #define IGB_QUEUE_STATS_LEN \ 104 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \ 105 IGB_RX_QUEUE_STATS_LEN) + \ 106 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \ 107 IGB_TX_QUEUE_STATS_LEN)) 108 #define IGB_STATS_LEN \ 109 (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN) 110 111 enum igb_diagnostics_results { 112 TEST_REG = 0, 113 TEST_EEP, 114 TEST_IRQ, 115 TEST_LOOP, 116 TEST_LINK 117 }; 118 119 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = { 120 [TEST_REG] = "Register test (offline)", 121 [TEST_EEP] = "Eeprom test (offline)", 122 [TEST_IRQ] = "Interrupt test (offline)", 123 [TEST_LOOP] = "Loopback test (offline)", 124 [TEST_LINK] = "Link test (on/offline)" 125 }; 126 #define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN) 127 128 static const char igb_priv_flags_strings[][ETH_GSTRING_LEN] = { 129 #define IGB_PRIV_FLAGS_LEGACY_RX BIT(0) 130 "legacy-rx", 131 }; 132 133 #define IGB_PRIV_FLAGS_STR_LEN ARRAY_SIZE(igb_priv_flags_strings) 134 135 static int igb_get_link_ksettings(struct net_device *netdev, 136 struct ethtool_link_ksettings *cmd) 137 { 138 struct igb_adapter *adapter = netdev_priv(netdev); 139 struct e1000_hw *hw = &adapter->hw; 140 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 141 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags; 142 u32 status; 143 u32 speed; 144 u32 supported, advertising; 145 146 status = pm_runtime_suspended(&adapter->pdev->dev) ? 147 0 : rd32(E1000_STATUS); 148 if (hw->phy.media_type == e1000_media_type_copper) { 149 150 supported = (SUPPORTED_10baseT_Half | 151 SUPPORTED_10baseT_Full | 152 SUPPORTED_100baseT_Half | 153 SUPPORTED_100baseT_Full | 154 SUPPORTED_1000baseT_Full| 155 SUPPORTED_Autoneg | 156 SUPPORTED_TP | 157 SUPPORTED_Pause); 158 advertising = ADVERTISED_TP; 159 160 if (hw->mac.autoneg == 1) { 161 advertising |= ADVERTISED_Autoneg; 162 /* the e1000 autoneg seems to match ethtool nicely */ 163 advertising |= hw->phy.autoneg_advertised; 164 } 165 166 cmd->base.port = PORT_TP; 167 cmd->base.phy_address = hw->phy.addr; 168 } else { 169 supported = (SUPPORTED_FIBRE | 170 SUPPORTED_1000baseKX_Full | 171 SUPPORTED_Autoneg | 172 SUPPORTED_Pause); 173 advertising = (ADVERTISED_FIBRE | 174 ADVERTISED_1000baseKX_Full); 175 if (hw->mac.type == e1000_i354) { 176 if ((hw->device_id == 177 E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) && 178 !(status & E1000_STATUS_2P5_SKU_OVER)) { 179 supported |= SUPPORTED_2500baseX_Full; 180 supported &= ~SUPPORTED_1000baseKX_Full; 181 advertising |= ADVERTISED_2500baseX_Full; 182 advertising &= ~ADVERTISED_1000baseKX_Full; 183 } 184 } 185 if (eth_flags->e100_base_fx || eth_flags->e100_base_lx) { 186 supported |= SUPPORTED_100baseT_Full; 187 advertising |= ADVERTISED_100baseT_Full; 188 } 189 if (hw->mac.autoneg == 1) 190 advertising |= ADVERTISED_Autoneg; 191 192 cmd->base.port = PORT_FIBRE; 193 } 194 if (hw->mac.autoneg != 1) 195 advertising &= ~(ADVERTISED_Pause | 196 ADVERTISED_Asym_Pause); 197 198 switch (hw->fc.requested_mode) { 199 case e1000_fc_full: 200 advertising |= ADVERTISED_Pause; 201 break; 202 case e1000_fc_rx_pause: 203 advertising |= (ADVERTISED_Pause | 204 ADVERTISED_Asym_Pause); 205 break; 206 case e1000_fc_tx_pause: 207 advertising |= ADVERTISED_Asym_Pause; 208 break; 209 default: 210 advertising &= ~(ADVERTISED_Pause | 211 ADVERTISED_Asym_Pause); 212 } 213 if (status & E1000_STATUS_LU) { 214 if ((status & E1000_STATUS_2P5_SKU) && 215 !(status & E1000_STATUS_2P5_SKU_OVER)) { 216 speed = SPEED_2500; 217 } else if (status & E1000_STATUS_SPEED_1000) { 218 speed = SPEED_1000; 219 } else if (status & E1000_STATUS_SPEED_100) { 220 speed = SPEED_100; 221 } else { 222 speed = SPEED_10; 223 } 224 if ((status & E1000_STATUS_FD) || 225 hw->phy.media_type != e1000_media_type_copper) 226 cmd->base.duplex = DUPLEX_FULL; 227 else 228 cmd->base.duplex = DUPLEX_HALF; 229 } else { 230 speed = SPEED_UNKNOWN; 231 cmd->base.duplex = DUPLEX_UNKNOWN; 232 } 233 cmd->base.speed = speed; 234 if ((hw->phy.media_type == e1000_media_type_fiber) || 235 hw->mac.autoneg) 236 cmd->base.autoneg = AUTONEG_ENABLE; 237 else 238 cmd->base.autoneg = AUTONEG_DISABLE; 239 240 /* MDI-X => 2; MDI =>1; Invalid =>0 */ 241 if (hw->phy.media_type == e1000_media_type_copper) 242 cmd->base.eth_tp_mdix = hw->phy.is_mdix ? ETH_TP_MDI_X : 243 ETH_TP_MDI; 244 else 245 cmd->base.eth_tp_mdix = ETH_TP_MDI_INVALID; 246 247 if (hw->phy.mdix == AUTO_ALL_MODES) 248 cmd->base.eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO; 249 else 250 cmd->base.eth_tp_mdix_ctrl = hw->phy.mdix; 251 252 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 253 supported); 254 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 255 advertising); 256 257 return 0; 258 } 259 260 static int igb_set_link_ksettings(struct net_device *netdev, 261 const struct ethtool_link_ksettings *cmd) 262 { 263 struct igb_adapter *adapter = netdev_priv(netdev); 264 struct e1000_hw *hw = &adapter->hw; 265 u32 advertising; 266 267 /* When SoL/IDER sessions are active, autoneg/speed/duplex 268 * cannot be changed 269 */ 270 if (igb_check_reset_block(hw)) { 271 dev_err(&adapter->pdev->dev, 272 "Cannot change link characteristics when SoL/IDER is active.\n"); 273 return -EINVAL; 274 } 275 276 /* MDI setting is only allowed when autoneg enabled because 277 * some hardware doesn't allow MDI setting when speed or 278 * duplex is forced. 279 */ 280 if (cmd->base.eth_tp_mdix_ctrl) { 281 if (hw->phy.media_type != e1000_media_type_copper) 282 return -EOPNOTSUPP; 283 284 if ((cmd->base.eth_tp_mdix_ctrl != ETH_TP_MDI_AUTO) && 285 (cmd->base.autoneg != AUTONEG_ENABLE)) { 286 dev_err(&adapter->pdev->dev, "forcing MDI/MDI-X state is not supported when link speed and/or duplex are forced\n"); 287 return -EINVAL; 288 } 289 } 290 291 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 292 usleep_range(1000, 2000); 293 294 ethtool_convert_link_mode_to_legacy_u32(&advertising, 295 cmd->link_modes.advertising); 296 297 if (cmd->base.autoneg == AUTONEG_ENABLE) { 298 hw->mac.autoneg = 1; 299 if (hw->phy.media_type == e1000_media_type_fiber) { 300 hw->phy.autoneg_advertised = advertising | 301 ADVERTISED_FIBRE | 302 ADVERTISED_Autoneg; 303 switch (adapter->link_speed) { 304 case SPEED_2500: 305 hw->phy.autoneg_advertised = 306 ADVERTISED_2500baseX_Full; 307 break; 308 case SPEED_1000: 309 hw->phy.autoneg_advertised = 310 ADVERTISED_1000baseT_Full; 311 break; 312 case SPEED_100: 313 hw->phy.autoneg_advertised = 314 ADVERTISED_100baseT_Full; 315 break; 316 default: 317 break; 318 } 319 } else { 320 hw->phy.autoneg_advertised = advertising | 321 ADVERTISED_TP | 322 ADVERTISED_Autoneg; 323 } 324 advertising = hw->phy.autoneg_advertised; 325 if (adapter->fc_autoneg) 326 hw->fc.requested_mode = e1000_fc_default; 327 } else { 328 u32 speed = cmd->base.speed; 329 /* calling this overrides forced MDI setting */ 330 if (igb_set_spd_dplx(adapter, speed, cmd->base.duplex)) { 331 clear_bit(__IGB_RESETTING, &adapter->state); 332 return -EINVAL; 333 } 334 } 335 336 /* MDI-X => 2; MDI => 1; Auto => 3 */ 337 if (cmd->base.eth_tp_mdix_ctrl) { 338 /* fix up the value for auto (3 => 0) as zero is mapped 339 * internally to auto 340 */ 341 if (cmd->base.eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO) 342 hw->phy.mdix = AUTO_ALL_MODES; 343 else 344 hw->phy.mdix = cmd->base.eth_tp_mdix_ctrl; 345 } 346 347 /* reset the link */ 348 if (netif_running(adapter->netdev)) { 349 igb_down(adapter); 350 igb_up(adapter); 351 } else 352 igb_reset(adapter); 353 354 clear_bit(__IGB_RESETTING, &adapter->state); 355 return 0; 356 } 357 358 static u32 igb_get_link(struct net_device *netdev) 359 { 360 struct igb_adapter *adapter = netdev_priv(netdev); 361 struct e1000_mac_info *mac = &adapter->hw.mac; 362 363 /* If the link is not reported up to netdev, interrupts are disabled, 364 * and so the physical link state may have changed since we last 365 * looked. Set get_link_status to make sure that the true link 366 * state is interrogated, rather than pulling a cached and possibly 367 * stale link state from the driver. 368 */ 369 if (!netif_carrier_ok(netdev)) 370 mac->get_link_status = 1; 371 372 return igb_has_link(adapter); 373 } 374 375 static void igb_get_pauseparam(struct net_device *netdev, 376 struct ethtool_pauseparam *pause) 377 { 378 struct igb_adapter *adapter = netdev_priv(netdev); 379 struct e1000_hw *hw = &adapter->hw; 380 381 pause->autoneg = 382 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE); 383 384 if (hw->fc.current_mode == e1000_fc_rx_pause) 385 pause->rx_pause = 1; 386 else if (hw->fc.current_mode == e1000_fc_tx_pause) 387 pause->tx_pause = 1; 388 else if (hw->fc.current_mode == e1000_fc_full) { 389 pause->rx_pause = 1; 390 pause->tx_pause = 1; 391 } 392 } 393 394 static int igb_set_pauseparam(struct net_device *netdev, 395 struct ethtool_pauseparam *pause) 396 { 397 struct igb_adapter *adapter = netdev_priv(netdev); 398 struct e1000_hw *hw = &adapter->hw; 399 int retval = 0; 400 int i; 401 402 /* 100basefx does not support setting link flow control */ 403 if (hw->dev_spec._82575.eth_flags.e100_base_fx) 404 return -EINVAL; 405 406 adapter->fc_autoneg = pause->autoneg; 407 408 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 409 usleep_range(1000, 2000); 410 411 if (adapter->fc_autoneg == AUTONEG_ENABLE) { 412 hw->fc.requested_mode = e1000_fc_default; 413 if (netif_running(adapter->netdev)) { 414 igb_down(adapter); 415 igb_up(adapter); 416 } else { 417 igb_reset(adapter); 418 } 419 } else { 420 if (pause->rx_pause && pause->tx_pause) 421 hw->fc.requested_mode = e1000_fc_full; 422 else if (pause->rx_pause && !pause->tx_pause) 423 hw->fc.requested_mode = e1000_fc_rx_pause; 424 else if (!pause->rx_pause && pause->tx_pause) 425 hw->fc.requested_mode = e1000_fc_tx_pause; 426 else if (!pause->rx_pause && !pause->tx_pause) 427 hw->fc.requested_mode = e1000_fc_none; 428 429 hw->fc.current_mode = hw->fc.requested_mode; 430 431 retval = ((hw->phy.media_type == e1000_media_type_copper) ? 432 igb_force_mac_fc(hw) : igb_setup_link(hw)); 433 434 /* Make sure SRRCTL considers new fc settings for each ring */ 435 for (i = 0; i < adapter->num_rx_queues; i++) { 436 struct igb_ring *ring = adapter->rx_ring[i]; 437 438 igb_setup_srrctl(adapter, ring); 439 } 440 } 441 442 clear_bit(__IGB_RESETTING, &adapter->state); 443 return retval; 444 } 445 446 static u32 igb_get_msglevel(struct net_device *netdev) 447 { 448 struct igb_adapter *adapter = netdev_priv(netdev); 449 return adapter->msg_enable; 450 } 451 452 static void igb_set_msglevel(struct net_device *netdev, u32 data) 453 { 454 struct igb_adapter *adapter = netdev_priv(netdev); 455 adapter->msg_enable = data; 456 } 457 458 static int igb_get_regs_len(struct net_device *netdev) 459 { 460 #define IGB_REGS_LEN 740 461 return IGB_REGS_LEN * sizeof(u32); 462 } 463 464 static void igb_get_regs(struct net_device *netdev, 465 struct ethtool_regs *regs, void *p) 466 { 467 struct igb_adapter *adapter = netdev_priv(netdev); 468 struct e1000_hw *hw = &adapter->hw; 469 u32 *regs_buff = p; 470 u8 i; 471 472 memset(p, 0, IGB_REGS_LEN * sizeof(u32)); 473 474 regs->version = (1u << 24) | (hw->revision_id << 16) | hw->device_id; 475 476 /* General Registers */ 477 regs_buff[0] = rd32(E1000_CTRL); 478 regs_buff[1] = rd32(E1000_STATUS); 479 regs_buff[2] = rd32(E1000_CTRL_EXT); 480 regs_buff[3] = rd32(E1000_MDIC); 481 regs_buff[4] = rd32(E1000_SCTL); 482 regs_buff[5] = rd32(E1000_CONNSW); 483 regs_buff[6] = rd32(E1000_VET); 484 regs_buff[7] = rd32(E1000_LEDCTL); 485 regs_buff[8] = rd32(E1000_PBA); 486 regs_buff[9] = rd32(E1000_PBS); 487 regs_buff[10] = rd32(E1000_FRTIMER); 488 regs_buff[11] = rd32(E1000_TCPTIMER); 489 490 /* NVM Register */ 491 regs_buff[12] = rd32(E1000_EECD); 492 493 /* Interrupt */ 494 /* Reading EICS for EICR because they read the 495 * same but EICS does not clear on read 496 */ 497 regs_buff[13] = rd32(E1000_EICS); 498 regs_buff[14] = rd32(E1000_EICS); 499 regs_buff[15] = rd32(E1000_EIMS); 500 regs_buff[16] = rd32(E1000_EIMC); 501 regs_buff[17] = rd32(E1000_EIAC); 502 regs_buff[18] = rd32(E1000_EIAM); 503 /* Reading ICS for ICR because they read the 504 * same but ICS does not clear on read 505 */ 506 regs_buff[19] = rd32(E1000_ICS); 507 regs_buff[20] = rd32(E1000_ICS); 508 regs_buff[21] = rd32(E1000_IMS); 509 regs_buff[22] = rd32(E1000_IMC); 510 regs_buff[23] = rd32(E1000_IAC); 511 regs_buff[24] = rd32(E1000_IAM); 512 regs_buff[25] = rd32(E1000_IMIRVP); 513 514 /* Flow Control */ 515 regs_buff[26] = rd32(E1000_FCAL); 516 regs_buff[27] = rd32(E1000_FCAH); 517 regs_buff[28] = rd32(E1000_FCTTV); 518 regs_buff[29] = rd32(E1000_FCRTL); 519 regs_buff[30] = rd32(E1000_FCRTH); 520 regs_buff[31] = rd32(E1000_FCRTV); 521 522 /* Receive */ 523 regs_buff[32] = rd32(E1000_RCTL); 524 regs_buff[33] = rd32(E1000_RXCSUM); 525 regs_buff[34] = rd32(E1000_RLPML); 526 regs_buff[35] = rd32(E1000_RFCTL); 527 regs_buff[36] = rd32(E1000_MRQC); 528 regs_buff[37] = rd32(E1000_VT_CTL); 529 530 /* Transmit */ 531 regs_buff[38] = rd32(E1000_TCTL); 532 regs_buff[39] = rd32(E1000_TCTL_EXT); 533 regs_buff[40] = rd32(E1000_TIPG); 534 regs_buff[41] = rd32(E1000_DTXCTL); 535 536 /* Wake Up */ 537 regs_buff[42] = rd32(E1000_WUC); 538 regs_buff[43] = rd32(E1000_WUFC); 539 regs_buff[44] = rd32(E1000_WUS); 540 regs_buff[45] = rd32(E1000_IPAV); 541 regs_buff[46] = rd32(E1000_WUPL); 542 543 /* MAC */ 544 regs_buff[47] = rd32(E1000_PCS_CFG0); 545 regs_buff[48] = rd32(E1000_PCS_LCTL); 546 regs_buff[49] = rd32(E1000_PCS_LSTAT); 547 regs_buff[50] = rd32(E1000_PCS_ANADV); 548 regs_buff[51] = rd32(E1000_PCS_LPAB); 549 regs_buff[52] = rd32(E1000_PCS_NPTX); 550 regs_buff[53] = rd32(E1000_PCS_LPABNP); 551 552 /* Statistics */ 553 regs_buff[54] = adapter->stats.crcerrs; 554 regs_buff[55] = adapter->stats.algnerrc; 555 regs_buff[56] = adapter->stats.symerrs; 556 regs_buff[57] = adapter->stats.rxerrc; 557 regs_buff[58] = adapter->stats.mpc; 558 regs_buff[59] = adapter->stats.scc; 559 regs_buff[60] = adapter->stats.ecol; 560 regs_buff[61] = adapter->stats.mcc; 561 regs_buff[62] = adapter->stats.latecol; 562 regs_buff[63] = adapter->stats.colc; 563 regs_buff[64] = adapter->stats.dc; 564 regs_buff[65] = adapter->stats.tncrs; 565 regs_buff[66] = adapter->stats.sec; 566 regs_buff[67] = adapter->stats.htdpmc; 567 regs_buff[68] = adapter->stats.rlec; 568 regs_buff[69] = adapter->stats.xonrxc; 569 regs_buff[70] = adapter->stats.xontxc; 570 regs_buff[71] = adapter->stats.xoffrxc; 571 regs_buff[72] = adapter->stats.xofftxc; 572 regs_buff[73] = adapter->stats.fcruc; 573 regs_buff[74] = adapter->stats.prc64; 574 regs_buff[75] = adapter->stats.prc127; 575 regs_buff[76] = adapter->stats.prc255; 576 regs_buff[77] = adapter->stats.prc511; 577 regs_buff[78] = adapter->stats.prc1023; 578 regs_buff[79] = adapter->stats.prc1522; 579 regs_buff[80] = adapter->stats.gprc; 580 regs_buff[81] = adapter->stats.bprc; 581 regs_buff[82] = adapter->stats.mprc; 582 regs_buff[83] = adapter->stats.gptc; 583 regs_buff[84] = adapter->stats.gorc; 584 regs_buff[86] = adapter->stats.gotc; 585 regs_buff[88] = adapter->stats.rnbc; 586 regs_buff[89] = adapter->stats.ruc; 587 regs_buff[90] = adapter->stats.rfc; 588 regs_buff[91] = adapter->stats.roc; 589 regs_buff[92] = adapter->stats.rjc; 590 regs_buff[93] = adapter->stats.mgprc; 591 regs_buff[94] = adapter->stats.mgpdc; 592 regs_buff[95] = adapter->stats.mgptc; 593 regs_buff[96] = adapter->stats.tor; 594 regs_buff[98] = adapter->stats.tot; 595 regs_buff[100] = adapter->stats.tpr; 596 regs_buff[101] = adapter->stats.tpt; 597 regs_buff[102] = adapter->stats.ptc64; 598 regs_buff[103] = adapter->stats.ptc127; 599 regs_buff[104] = adapter->stats.ptc255; 600 regs_buff[105] = adapter->stats.ptc511; 601 regs_buff[106] = adapter->stats.ptc1023; 602 regs_buff[107] = adapter->stats.ptc1522; 603 regs_buff[108] = adapter->stats.mptc; 604 regs_buff[109] = adapter->stats.bptc; 605 regs_buff[110] = adapter->stats.tsctc; 606 regs_buff[111] = adapter->stats.iac; 607 regs_buff[112] = adapter->stats.rpthc; 608 regs_buff[113] = adapter->stats.hgptc; 609 regs_buff[114] = adapter->stats.hgorc; 610 regs_buff[116] = adapter->stats.hgotc; 611 regs_buff[118] = adapter->stats.lenerrs; 612 regs_buff[119] = adapter->stats.scvpc; 613 regs_buff[120] = adapter->stats.hrmpc; 614 615 for (i = 0; i < 4; i++) 616 regs_buff[121 + i] = rd32(E1000_SRRCTL(i)); 617 for (i = 0; i < 4; i++) 618 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i)); 619 for (i = 0; i < 4; i++) 620 regs_buff[129 + i] = rd32(E1000_RDBAL(i)); 621 for (i = 0; i < 4; i++) 622 regs_buff[133 + i] = rd32(E1000_RDBAH(i)); 623 for (i = 0; i < 4; i++) 624 regs_buff[137 + i] = rd32(E1000_RDLEN(i)); 625 for (i = 0; i < 4; i++) 626 regs_buff[141 + i] = rd32(E1000_RDH(i)); 627 for (i = 0; i < 4; i++) 628 regs_buff[145 + i] = rd32(E1000_RDT(i)); 629 for (i = 0; i < 4; i++) 630 regs_buff[149 + i] = rd32(E1000_RXDCTL(i)); 631 632 for (i = 0; i < 10; i++) 633 regs_buff[153 + i] = rd32(E1000_EITR(i)); 634 for (i = 0; i < 8; i++) 635 regs_buff[163 + i] = rd32(E1000_IMIR(i)); 636 for (i = 0; i < 8; i++) 637 regs_buff[171 + i] = rd32(E1000_IMIREXT(i)); 638 for (i = 0; i < 16; i++) 639 regs_buff[179 + i] = rd32(E1000_RAL(i)); 640 for (i = 0; i < 16; i++) 641 regs_buff[195 + i] = rd32(E1000_RAH(i)); 642 643 for (i = 0; i < 4; i++) 644 regs_buff[211 + i] = rd32(E1000_TDBAL(i)); 645 for (i = 0; i < 4; i++) 646 regs_buff[215 + i] = rd32(E1000_TDBAH(i)); 647 for (i = 0; i < 4; i++) 648 regs_buff[219 + i] = rd32(E1000_TDLEN(i)); 649 for (i = 0; i < 4; i++) 650 regs_buff[223 + i] = rd32(E1000_TDH(i)); 651 for (i = 0; i < 4; i++) 652 regs_buff[227 + i] = rd32(E1000_TDT(i)); 653 for (i = 0; i < 4; i++) 654 regs_buff[231 + i] = rd32(E1000_TXDCTL(i)); 655 for (i = 0; i < 4; i++) 656 regs_buff[235 + i] = rd32(E1000_TDWBAL(i)); 657 for (i = 0; i < 4; i++) 658 regs_buff[239 + i] = rd32(E1000_TDWBAH(i)); 659 for (i = 0; i < 4; i++) 660 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i)); 661 662 for (i = 0; i < 4; i++) 663 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i)); 664 for (i = 0; i < 4; i++) 665 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i)); 666 for (i = 0; i < 32; i++) 667 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i)); 668 for (i = 0; i < 128; i++) 669 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i)); 670 for (i = 0; i < 128; i++) 671 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i)); 672 for (i = 0; i < 4; i++) 673 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i)); 674 675 regs_buff[547] = rd32(E1000_TDFH); 676 regs_buff[548] = rd32(E1000_TDFT); 677 regs_buff[549] = rd32(E1000_TDFHS); 678 regs_buff[550] = rd32(E1000_TDFPC); 679 680 if (hw->mac.type > e1000_82580) { 681 regs_buff[551] = adapter->stats.o2bgptc; 682 regs_buff[552] = adapter->stats.b2ospc; 683 regs_buff[553] = adapter->stats.o2bspc; 684 regs_buff[554] = adapter->stats.b2ogprc; 685 } 686 687 if (hw->mac.type == e1000_82576) { 688 for (i = 0; i < 12; i++) 689 regs_buff[555 + i] = rd32(E1000_SRRCTL(i + 4)); 690 for (i = 0; i < 4; i++) 691 regs_buff[567 + i] = rd32(E1000_PSRTYPE(i + 4)); 692 for (i = 0; i < 12; i++) 693 regs_buff[571 + i] = rd32(E1000_RDBAL(i + 4)); 694 for (i = 0; i < 12; i++) 695 regs_buff[583 + i] = rd32(E1000_RDBAH(i + 4)); 696 for (i = 0; i < 12; i++) 697 regs_buff[595 + i] = rd32(E1000_RDLEN(i + 4)); 698 for (i = 0; i < 12; i++) 699 regs_buff[607 + i] = rd32(E1000_RDH(i + 4)); 700 for (i = 0; i < 12; i++) 701 regs_buff[619 + i] = rd32(E1000_RDT(i + 4)); 702 for (i = 0; i < 12; i++) 703 regs_buff[631 + i] = rd32(E1000_RXDCTL(i + 4)); 704 705 for (i = 0; i < 12; i++) 706 regs_buff[643 + i] = rd32(E1000_TDBAL(i + 4)); 707 for (i = 0; i < 12; i++) 708 regs_buff[655 + i] = rd32(E1000_TDBAH(i + 4)); 709 for (i = 0; i < 12; i++) 710 regs_buff[667 + i] = rd32(E1000_TDLEN(i + 4)); 711 for (i = 0; i < 12; i++) 712 regs_buff[679 + i] = rd32(E1000_TDH(i + 4)); 713 for (i = 0; i < 12; i++) 714 regs_buff[691 + i] = rd32(E1000_TDT(i + 4)); 715 for (i = 0; i < 12; i++) 716 regs_buff[703 + i] = rd32(E1000_TXDCTL(i + 4)); 717 for (i = 0; i < 12; i++) 718 regs_buff[715 + i] = rd32(E1000_TDWBAL(i + 4)); 719 for (i = 0; i < 12; i++) 720 regs_buff[727 + i] = rd32(E1000_TDWBAH(i + 4)); 721 } 722 723 if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) 724 regs_buff[739] = rd32(E1000_I210_RR2DCDELAY); 725 } 726 727 static int igb_get_eeprom_len(struct net_device *netdev) 728 { 729 struct igb_adapter *adapter = netdev_priv(netdev); 730 return adapter->hw.nvm.word_size * 2; 731 } 732 733 static int igb_get_eeprom(struct net_device *netdev, 734 struct ethtool_eeprom *eeprom, u8 *bytes) 735 { 736 struct igb_adapter *adapter = netdev_priv(netdev); 737 struct e1000_hw *hw = &adapter->hw; 738 u16 *eeprom_buff; 739 int first_word, last_word; 740 int ret_val = 0; 741 u16 i; 742 743 if (eeprom->len == 0) 744 return -EINVAL; 745 746 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 747 748 first_word = eeprom->offset >> 1; 749 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 750 751 eeprom_buff = kmalloc_array(last_word - first_word + 1, sizeof(u16), 752 GFP_KERNEL); 753 if (!eeprom_buff) 754 return -ENOMEM; 755 756 if (hw->nvm.type == e1000_nvm_eeprom_spi) 757 ret_val = hw->nvm.ops.read(hw, first_word, 758 last_word - first_word + 1, 759 eeprom_buff); 760 else { 761 for (i = 0; i < last_word - first_word + 1; i++) { 762 ret_val = hw->nvm.ops.read(hw, first_word + i, 1, 763 &eeprom_buff[i]); 764 if (ret_val) 765 break; 766 } 767 } 768 769 /* Device's eeprom is always little-endian, word addressable */ 770 for (i = 0; i < last_word - first_word + 1; i++) 771 le16_to_cpus(&eeprom_buff[i]); 772 773 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), 774 eeprom->len); 775 kfree(eeprom_buff); 776 777 return ret_val; 778 } 779 780 static int igb_set_eeprom(struct net_device *netdev, 781 struct ethtool_eeprom *eeprom, u8 *bytes) 782 { 783 struct igb_adapter *adapter = netdev_priv(netdev); 784 struct e1000_hw *hw = &adapter->hw; 785 u16 *eeprom_buff; 786 void *ptr; 787 int max_len, first_word, last_word, ret_val = 0; 788 u16 i; 789 790 if (eeprom->len == 0) 791 return -EOPNOTSUPP; 792 793 if ((hw->mac.type >= e1000_i210) && 794 !igb_get_flash_presence_i210(hw)) { 795 return -EOPNOTSUPP; 796 } 797 798 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) 799 return -EFAULT; 800 801 max_len = hw->nvm.word_size * 2; 802 803 first_word = eeprom->offset >> 1; 804 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 805 eeprom_buff = kmalloc(max_len, GFP_KERNEL); 806 if (!eeprom_buff) 807 return -ENOMEM; 808 809 ptr = (void *)eeprom_buff; 810 811 if (eeprom->offset & 1) { 812 /* need read/modify/write of first changed EEPROM word 813 * only the second byte of the word is being modified 814 */ 815 ret_val = hw->nvm.ops.read(hw, first_word, 1, 816 &eeprom_buff[0]); 817 ptr++; 818 } 819 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) { 820 /* need read/modify/write of last changed EEPROM word 821 * only the first byte of the word is being modified 822 */ 823 ret_val = hw->nvm.ops.read(hw, last_word, 1, 824 &eeprom_buff[last_word - first_word]); 825 } 826 827 /* Device's eeprom is always little-endian, word addressable */ 828 for (i = 0; i < last_word - first_word + 1; i++) 829 le16_to_cpus(&eeprom_buff[i]); 830 831 memcpy(ptr, bytes, eeprom->len); 832 833 for (i = 0; i < last_word - first_word + 1; i++) 834 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]); 835 836 ret_val = hw->nvm.ops.write(hw, first_word, 837 last_word - first_word + 1, eeprom_buff); 838 839 /* Update the checksum if nvm write succeeded */ 840 if (ret_val == 0) 841 hw->nvm.ops.update(hw); 842 843 igb_set_fw_version(adapter); 844 kfree(eeprom_buff); 845 return ret_val; 846 } 847 848 static void igb_get_drvinfo(struct net_device *netdev, 849 struct ethtool_drvinfo *drvinfo) 850 { 851 struct igb_adapter *adapter = netdev_priv(netdev); 852 853 strlcpy(drvinfo->driver, igb_driver_name, sizeof(drvinfo->driver)); 854 strlcpy(drvinfo->version, igb_driver_version, sizeof(drvinfo->version)); 855 856 /* EEPROM image version # is reported as firmware version # for 857 * 82575 controllers 858 */ 859 strlcpy(drvinfo->fw_version, adapter->fw_version, 860 sizeof(drvinfo->fw_version)); 861 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev), 862 sizeof(drvinfo->bus_info)); 863 864 drvinfo->n_priv_flags = IGB_PRIV_FLAGS_STR_LEN; 865 } 866 867 static void igb_get_ringparam(struct net_device *netdev, 868 struct ethtool_ringparam *ring) 869 { 870 struct igb_adapter *adapter = netdev_priv(netdev); 871 872 ring->rx_max_pending = IGB_MAX_RXD; 873 ring->tx_max_pending = IGB_MAX_TXD; 874 ring->rx_pending = adapter->rx_ring_count; 875 ring->tx_pending = adapter->tx_ring_count; 876 } 877 878 static int igb_set_ringparam(struct net_device *netdev, 879 struct ethtool_ringparam *ring) 880 { 881 struct igb_adapter *adapter = netdev_priv(netdev); 882 struct igb_ring *temp_ring; 883 int i, err = 0; 884 u16 new_rx_count, new_tx_count; 885 886 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) 887 return -EINVAL; 888 889 new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD); 890 new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD); 891 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE); 892 893 new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD); 894 new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD); 895 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE); 896 897 if ((new_tx_count == adapter->tx_ring_count) && 898 (new_rx_count == adapter->rx_ring_count)) { 899 /* nothing to do */ 900 return 0; 901 } 902 903 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 904 usleep_range(1000, 2000); 905 906 if (!netif_running(adapter->netdev)) { 907 for (i = 0; i < adapter->num_tx_queues; i++) 908 adapter->tx_ring[i]->count = new_tx_count; 909 for (i = 0; i < adapter->num_rx_queues; i++) 910 adapter->rx_ring[i]->count = new_rx_count; 911 adapter->tx_ring_count = new_tx_count; 912 adapter->rx_ring_count = new_rx_count; 913 goto clear_reset; 914 } 915 916 if (adapter->num_tx_queues > adapter->num_rx_queues) 917 temp_ring = vmalloc(array_size(sizeof(struct igb_ring), 918 adapter->num_tx_queues)); 919 else 920 temp_ring = vmalloc(array_size(sizeof(struct igb_ring), 921 adapter->num_rx_queues)); 922 923 if (!temp_ring) { 924 err = -ENOMEM; 925 goto clear_reset; 926 } 927 928 igb_down(adapter); 929 930 /* We can't just free everything and then setup again, 931 * because the ISRs in MSI-X mode get passed pointers 932 * to the Tx and Rx ring structs. 933 */ 934 if (new_tx_count != adapter->tx_ring_count) { 935 for (i = 0; i < adapter->num_tx_queues; i++) { 936 memcpy(&temp_ring[i], adapter->tx_ring[i], 937 sizeof(struct igb_ring)); 938 939 temp_ring[i].count = new_tx_count; 940 err = igb_setup_tx_resources(&temp_ring[i]); 941 if (err) { 942 while (i) { 943 i--; 944 igb_free_tx_resources(&temp_ring[i]); 945 } 946 goto err_setup; 947 } 948 } 949 950 for (i = 0; i < adapter->num_tx_queues; i++) { 951 igb_free_tx_resources(adapter->tx_ring[i]); 952 953 memcpy(adapter->tx_ring[i], &temp_ring[i], 954 sizeof(struct igb_ring)); 955 } 956 957 adapter->tx_ring_count = new_tx_count; 958 } 959 960 if (new_rx_count != adapter->rx_ring_count) { 961 for (i = 0; i < adapter->num_rx_queues; i++) { 962 memcpy(&temp_ring[i], adapter->rx_ring[i], 963 sizeof(struct igb_ring)); 964 965 temp_ring[i].count = new_rx_count; 966 err = igb_setup_rx_resources(&temp_ring[i]); 967 if (err) { 968 while (i) { 969 i--; 970 igb_free_rx_resources(&temp_ring[i]); 971 } 972 goto err_setup; 973 } 974 975 } 976 977 for (i = 0; i < adapter->num_rx_queues; i++) { 978 igb_free_rx_resources(adapter->rx_ring[i]); 979 980 memcpy(adapter->rx_ring[i], &temp_ring[i], 981 sizeof(struct igb_ring)); 982 } 983 984 adapter->rx_ring_count = new_rx_count; 985 } 986 err_setup: 987 igb_up(adapter); 988 vfree(temp_ring); 989 clear_reset: 990 clear_bit(__IGB_RESETTING, &adapter->state); 991 return err; 992 } 993 994 /* ethtool register test data */ 995 struct igb_reg_test { 996 u16 reg; 997 u16 reg_offset; 998 u16 array_len; 999 u16 test_type; 1000 u32 mask; 1001 u32 write; 1002 }; 1003 1004 /* In the hardware, registers are laid out either singly, in arrays 1005 * spaced 0x100 bytes apart, or in contiguous tables. We assume 1006 * most tests take place on arrays or single registers (handled 1007 * as a single-element array) and special-case the tables. 1008 * Table tests are always pattern tests. 1009 * 1010 * We also make provision for some required setup steps by specifying 1011 * registers to be written without any read-back testing. 1012 */ 1013 1014 #define PATTERN_TEST 1 1015 #define SET_READ_TEST 2 1016 #define WRITE_NO_TEST 3 1017 #define TABLE32_TEST 4 1018 #define TABLE64_TEST_LO 5 1019 #define TABLE64_TEST_HI 6 1020 1021 /* i210 reg test */ 1022 static struct igb_reg_test reg_test_i210[] = { 1023 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1024 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1025 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1026 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1027 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1028 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1029 /* RDH is read-only for i210, only test RDT. */ 1030 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1031 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1032 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1033 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1034 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1035 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1036 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1037 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1038 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1039 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 1040 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 1041 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1042 { E1000_RA, 0, 16, TABLE64_TEST_LO, 1043 0xFFFFFFFF, 0xFFFFFFFF }, 1044 { E1000_RA, 0, 16, TABLE64_TEST_HI, 1045 0x900FFFFF, 0xFFFFFFFF }, 1046 { E1000_MTA, 0, 128, TABLE32_TEST, 1047 0xFFFFFFFF, 0xFFFFFFFF }, 1048 { 0, 0, 0, 0, 0 } 1049 }; 1050 1051 /* i350 reg test */ 1052 static struct igb_reg_test reg_test_i350[] = { 1053 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1054 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1055 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1056 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 }, 1057 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1058 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1059 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1060 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1061 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1062 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1063 /* RDH is read-only for i350, only test RDT. */ 1064 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1065 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1066 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1067 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1068 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1069 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1070 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1071 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1072 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1073 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1074 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1075 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1076 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1077 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1078 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 1079 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 1080 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1081 { E1000_RA, 0, 16, TABLE64_TEST_LO, 1082 0xFFFFFFFF, 0xFFFFFFFF }, 1083 { E1000_RA, 0, 16, TABLE64_TEST_HI, 1084 0xC3FFFFFF, 0xFFFFFFFF }, 1085 { E1000_RA2, 0, 16, TABLE64_TEST_LO, 1086 0xFFFFFFFF, 0xFFFFFFFF }, 1087 { E1000_RA2, 0, 16, TABLE64_TEST_HI, 1088 0xC3FFFFFF, 0xFFFFFFFF }, 1089 { E1000_MTA, 0, 128, TABLE32_TEST, 1090 0xFFFFFFFF, 0xFFFFFFFF }, 1091 { 0, 0, 0, 0 } 1092 }; 1093 1094 /* 82580 reg test */ 1095 static struct igb_reg_test reg_test_82580[] = { 1096 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1097 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1098 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1099 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1100 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1101 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1102 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1103 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1104 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1105 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1106 /* RDH is read-only for 82580, only test RDT. */ 1107 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1108 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1109 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1110 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1111 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1112 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1113 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1114 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1115 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1116 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1117 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1118 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1119 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1120 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1121 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 1122 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 1123 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1124 { E1000_RA, 0, 16, TABLE64_TEST_LO, 1125 0xFFFFFFFF, 0xFFFFFFFF }, 1126 { E1000_RA, 0, 16, TABLE64_TEST_HI, 1127 0x83FFFFFF, 0xFFFFFFFF }, 1128 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 1129 0xFFFFFFFF, 0xFFFFFFFF }, 1130 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 1131 0x83FFFFFF, 0xFFFFFFFF }, 1132 { E1000_MTA, 0, 128, TABLE32_TEST, 1133 0xFFFFFFFF, 0xFFFFFFFF }, 1134 { 0, 0, 0, 0 } 1135 }; 1136 1137 /* 82576 reg test */ 1138 static struct igb_reg_test reg_test_82576[] = { 1139 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1140 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1141 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1142 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1143 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1144 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1145 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1146 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1147 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1148 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1149 /* Enable all RX queues before testing. */ 1150 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 1151 E1000_RXDCTL_QUEUE_ENABLE }, 1152 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 1153 E1000_RXDCTL_QUEUE_ENABLE }, 1154 /* RDH is read-only for 82576, only test RDT. */ 1155 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1156 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1157 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 }, 1158 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 }, 1159 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1160 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1161 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1162 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1163 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1164 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1165 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1166 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1167 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1168 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1169 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 1170 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 1171 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1172 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1173 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF }, 1174 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1175 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF }, 1176 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1177 { 0, 0, 0, 0 } 1178 }; 1179 1180 /* 82575 register test */ 1181 static struct igb_reg_test reg_test_82575[] = { 1182 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1183 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1184 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1185 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1186 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1187 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1188 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1189 /* Enable all four RX queues before testing. */ 1190 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 1191 E1000_RXDCTL_QUEUE_ENABLE }, 1192 /* RDH is read-only for 82575, only test RDT. */ 1193 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1194 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 }, 1195 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1196 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1197 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1198 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1199 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1200 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1201 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1202 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB }, 1203 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF }, 1204 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1205 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF }, 1206 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1207 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF }, 1208 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1209 { 0, 0, 0, 0 } 1210 }; 1211 1212 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data, 1213 int reg, u32 mask, u32 write) 1214 { 1215 struct e1000_hw *hw = &adapter->hw; 1216 u32 pat, val; 1217 static const u32 _test[] = { 1218 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; 1219 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) { 1220 wr32(reg, (_test[pat] & write)); 1221 val = rd32(reg) & mask; 1222 if (val != (_test[pat] & write & mask)) { 1223 dev_err(&adapter->pdev->dev, 1224 "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n", 1225 reg, val, (_test[pat] & write & mask)); 1226 *data = reg; 1227 return true; 1228 } 1229 } 1230 1231 return false; 1232 } 1233 1234 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data, 1235 int reg, u32 mask, u32 write) 1236 { 1237 struct e1000_hw *hw = &adapter->hw; 1238 u32 val; 1239 1240 wr32(reg, write & mask); 1241 val = rd32(reg); 1242 if ((write & mask) != (val & mask)) { 1243 dev_err(&adapter->pdev->dev, 1244 "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n", 1245 reg, (val & mask), (write & mask)); 1246 *data = reg; 1247 return true; 1248 } 1249 1250 return false; 1251 } 1252 1253 #define REG_PATTERN_TEST(reg, mask, write) \ 1254 do { \ 1255 if (reg_pattern_test(adapter, data, reg, mask, write)) \ 1256 return 1; \ 1257 } while (0) 1258 1259 #define REG_SET_AND_CHECK(reg, mask, write) \ 1260 do { \ 1261 if (reg_set_and_check(adapter, data, reg, mask, write)) \ 1262 return 1; \ 1263 } while (0) 1264 1265 static int igb_reg_test(struct igb_adapter *adapter, u64 *data) 1266 { 1267 struct e1000_hw *hw = &adapter->hw; 1268 struct igb_reg_test *test; 1269 u32 value, before, after; 1270 u32 i, toggle; 1271 1272 switch (adapter->hw.mac.type) { 1273 case e1000_i350: 1274 case e1000_i354: 1275 test = reg_test_i350; 1276 toggle = 0x7FEFF3FF; 1277 break; 1278 case e1000_i210: 1279 case e1000_i211: 1280 test = reg_test_i210; 1281 toggle = 0x7FEFF3FF; 1282 break; 1283 case e1000_82580: 1284 test = reg_test_82580; 1285 toggle = 0x7FEFF3FF; 1286 break; 1287 case e1000_82576: 1288 test = reg_test_82576; 1289 toggle = 0x7FFFF3FF; 1290 break; 1291 default: 1292 test = reg_test_82575; 1293 toggle = 0x7FFFF3FF; 1294 break; 1295 } 1296 1297 /* Because the status register is such a special case, 1298 * we handle it separately from the rest of the register 1299 * tests. Some bits are read-only, some toggle, and some 1300 * are writable on newer MACs. 1301 */ 1302 before = rd32(E1000_STATUS); 1303 value = (rd32(E1000_STATUS) & toggle); 1304 wr32(E1000_STATUS, toggle); 1305 after = rd32(E1000_STATUS) & toggle; 1306 if (value != after) { 1307 dev_err(&adapter->pdev->dev, 1308 "failed STATUS register test got: 0x%08X expected: 0x%08X\n", 1309 after, value); 1310 *data = 1; 1311 return 1; 1312 } 1313 /* restore previous status */ 1314 wr32(E1000_STATUS, before); 1315 1316 /* Perform the remainder of the register test, looping through 1317 * the test table until we either fail or reach the null entry. 1318 */ 1319 while (test->reg) { 1320 for (i = 0; i < test->array_len; i++) { 1321 switch (test->test_type) { 1322 case PATTERN_TEST: 1323 REG_PATTERN_TEST(test->reg + 1324 (i * test->reg_offset), 1325 test->mask, 1326 test->write); 1327 break; 1328 case SET_READ_TEST: 1329 REG_SET_AND_CHECK(test->reg + 1330 (i * test->reg_offset), 1331 test->mask, 1332 test->write); 1333 break; 1334 case WRITE_NO_TEST: 1335 writel(test->write, 1336 (adapter->hw.hw_addr + test->reg) 1337 + (i * test->reg_offset)); 1338 break; 1339 case TABLE32_TEST: 1340 REG_PATTERN_TEST(test->reg + (i * 4), 1341 test->mask, 1342 test->write); 1343 break; 1344 case TABLE64_TEST_LO: 1345 REG_PATTERN_TEST(test->reg + (i * 8), 1346 test->mask, 1347 test->write); 1348 break; 1349 case TABLE64_TEST_HI: 1350 REG_PATTERN_TEST((test->reg + 4) + (i * 8), 1351 test->mask, 1352 test->write); 1353 break; 1354 } 1355 } 1356 test++; 1357 } 1358 1359 *data = 0; 1360 return 0; 1361 } 1362 1363 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data) 1364 { 1365 struct e1000_hw *hw = &adapter->hw; 1366 1367 *data = 0; 1368 1369 /* Validate eeprom on all parts but flashless */ 1370 switch (hw->mac.type) { 1371 case e1000_i210: 1372 case e1000_i211: 1373 if (igb_get_flash_presence_i210(hw)) { 1374 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0) 1375 *data = 2; 1376 } 1377 break; 1378 default: 1379 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0) 1380 *data = 2; 1381 break; 1382 } 1383 1384 return *data; 1385 } 1386 1387 static irqreturn_t igb_test_intr(int irq, void *data) 1388 { 1389 struct igb_adapter *adapter = (struct igb_adapter *) data; 1390 struct e1000_hw *hw = &adapter->hw; 1391 1392 adapter->test_icr |= rd32(E1000_ICR); 1393 1394 return IRQ_HANDLED; 1395 } 1396 1397 static int igb_intr_test(struct igb_adapter *adapter, u64 *data) 1398 { 1399 struct e1000_hw *hw = &adapter->hw; 1400 struct net_device *netdev = adapter->netdev; 1401 u32 mask, ics_mask, i = 0, shared_int = true; 1402 u32 irq = adapter->pdev->irq; 1403 1404 *data = 0; 1405 1406 /* Hook up test interrupt handler just for this test */ 1407 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1408 if (request_irq(adapter->msix_entries[0].vector, 1409 igb_test_intr, 0, netdev->name, adapter)) { 1410 *data = 1; 1411 return -1; 1412 } 1413 } else if (adapter->flags & IGB_FLAG_HAS_MSI) { 1414 shared_int = false; 1415 if (request_irq(irq, 1416 igb_test_intr, 0, netdev->name, adapter)) { 1417 *data = 1; 1418 return -1; 1419 } 1420 } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED, 1421 netdev->name, adapter)) { 1422 shared_int = false; 1423 } else if (request_irq(irq, igb_test_intr, IRQF_SHARED, 1424 netdev->name, adapter)) { 1425 *data = 1; 1426 return -1; 1427 } 1428 dev_info(&adapter->pdev->dev, "testing %s interrupt\n", 1429 (shared_int ? "shared" : "unshared")); 1430 1431 /* Disable all the interrupts */ 1432 wr32(E1000_IMC, ~0); 1433 wrfl(); 1434 usleep_range(10000, 11000); 1435 1436 /* Define all writable bits for ICS */ 1437 switch (hw->mac.type) { 1438 case e1000_82575: 1439 ics_mask = 0x37F47EDD; 1440 break; 1441 case e1000_82576: 1442 ics_mask = 0x77D4FBFD; 1443 break; 1444 case e1000_82580: 1445 ics_mask = 0x77DCFED5; 1446 break; 1447 case e1000_i350: 1448 case e1000_i354: 1449 case e1000_i210: 1450 case e1000_i211: 1451 ics_mask = 0x77DCFED5; 1452 break; 1453 default: 1454 ics_mask = 0x7FFFFFFF; 1455 break; 1456 } 1457 1458 /* Test each interrupt */ 1459 for (; i < 31; i++) { 1460 /* Interrupt to test */ 1461 mask = BIT(i); 1462 1463 if (!(mask & ics_mask)) 1464 continue; 1465 1466 if (!shared_int) { 1467 /* Disable the interrupt to be reported in 1468 * the cause register and then force the same 1469 * interrupt and see if one gets posted. If 1470 * an interrupt was posted to the bus, the 1471 * test failed. 1472 */ 1473 adapter->test_icr = 0; 1474 1475 /* Flush any pending interrupts */ 1476 wr32(E1000_ICR, ~0); 1477 1478 wr32(E1000_IMC, mask); 1479 wr32(E1000_ICS, mask); 1480 wrfl(); 1481 usleep_range(10000, 11000); 1482 1483 if (adapter->test_icr & mask) { 1484 *data = 3; 1485 break; 1486 } 1487 } 1488 1489 /* Enable the interrupt to be reported in 1490 * the cause register and then force the same 1491 * interrupt and see if one gets posted. If 1492 * an interrupt was not posted to the bus, the 1493 * test failed. 1494 */ 1495 adapter->test_icr = 0; 1496 1497 /* Flush any pending interrupts */ 1498 wr32(E1000_ICR, ~0); 1499 1500 wr32(E1000_IMS, mask); 1501 wr32(E1000_ICS, mask); 1502 wrfl(); 1503 usleep_range(10000, 11000); 1504 1505 if (!(adapter->test_icr & mask)) { 1506 *data = 4; 1507 break; 1508 } 1509 1510 if (!shared_int) { 1511 /* Disable the other interrupts to be reported in 1512 * the cause register and then force the other 1513 * interrupts and see if any get posted. If 1514 * an interrupt was posted to the bus, the 1515 * test failed. 1516 */ 1517 adapter->test_icr = 0; 1518 1519 /* Flush any pending interrupts */ 1520 wr32(E1000_ICR, ~0); 1521 1522 wr32(E1000_IMC, ~mask); 1523 wr32(E1000_ICS, ~mask); 1524 wrfl(); 1525 usleep_range(10000, 11000); 1526 1527 if (adapter->test_icr & mask) { 1528 *data = 5; 1529 break; 1530 } 1531 } 1532 } 1533 1534 /* Disable all the interrupts */ 1535 wr32(E1000_IMC, ~0); 1536 wrfl(); 1537 usleep_range(10000, 11000); 1538 1539 /* Unhook test interrupt handler */ 1540 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1541 free_irq(adapter->msix_entries[0].vector, adapter); 1542 else 1543 free_irq(irq, adapter); 1544 1545 return *data; 1546 } 1547 1548 static void igb_free_desc_rings(struct igb_adapter *adapter) 1549 { 1550 igb_free_tx_resources(&adapter->test_tx_ring); 1551 igb_free_rx_resources(&adapter->test_rx_ring); 1552 } 1553 1554 static int igb_setup_desc_rings(struct igb_adapter *adapter) 1555 { 1556 struct igb_ring *tx_ring = &adapter->test_tx_ring; 1557 struct igb_ring *rx_ring = &adapter->test_rx_ring; 1558 struct e1000_hw *hw = &adapter->hw; 1559 int ret_val; 1560 1561 /* Setup Tx descriptor ring and Tx buffers */ 1562 tx_ring->count = IGB_DEFAULT_TXD; 1563 tx_ring->dev = &adapter->pdev->dev; 1564 tx_ring->netdev = adapter->netdev; 1565 tx_ring->reg_idx = adapter->vfs_allocated_count; 1566 1567 if (igb_setup_tx_resources(tx_ring)) { 1568 ret_val = 1; 1569 goto err_nomem; 1570 } 1571 1572 igb_setup_tctl(adapter); 1573 igb_configure_tx_ring(adapter, tx_ring); 1574 1575 /* Setup Rx descriptor ring and Rx buffers */ 1576 rx_ring->count = IGB_DEFAULT_RXD; 1577 rx_ring->dev = &adapter->pdev->dev; 1578 rx_ring->netdev = adapter->netdev; 1579 rx_ring->reg_idx = adapter->vfs_allocated_count; 1580 1581 if (igb_setup_rx_resources(rx_ring)) { 1582 ret_val = 3; 1583 goto err_nomem; 1584 } 1585 1586 /* set the default queue to queue 0 of PF */ 1587 wr32(E1000_MRQC, adapter->vfs_allocated_count << 3); 1588 1589 /* enable receive ring */ 1590 igb_setup_rctl(adapter); 1591 igb_configure_rx_ring(adapter, rx_ring); 1592 1593 igb_alloc_rx_buffers(rx_ring, igb_desc_unused(rx_ring)); 1594 1595 return 0; 1596 1597 err_nomem: 1598 igb_free_desc_rings(adapter); 1599 return ret_val; 1600 } 1601 1602 static void igb_phy_disable_receiver(struct igb_adapter *adapter) 1603 { 1604 struct e1000_hw *hw = &adapter->hw; 1605 1606 /* Write out to PHY registers 29 and 30 to disable the Receiver. */ 1607 igb_write_phy_reg(hw, 29, 0x001F); 1608 igb_write_phy_reg(hw, 30, 0x8FFC); 1609 igb_write_phy_reg(hw, 29, 0x001A); 1610 igb_write_phy_reg(hw, 30, 0x8FF0); 1611 } 1612 1613 static int igb_integrated_phy_loopback(struct igb_adapter *adapter) 1614 { 1615 struct e1000_hw *hw = &adapter->hw; 1616 u32 ctrl_reg = 0; 1617 1618 hw->mac.autoneg = false; 1619 1620 if (hw->phy.type == e1000_phy_m88) { 1621 if (hw->phy.id != I210_I_PHY_ID) { 1622 /* Auto-MDI/MDIX Off */ 1623 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 1624 /* reset to update Auto-MDI/MDIX */ 1625 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140); 1626 /* autoneg off */ 1627 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140); 1628 } else { 1629 /* force 1000, set loopback */ 1630 igb_write_phy_reg(hw, I347AT4_PAGE_SELECT, 0); 1631 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140); 1632 } 1633 } else if (hw->phy.type == e1000_phy_82580) { 1634 /* enable MII loopback */ 1635 igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041); 1636 } 1637 1638 /* add small delay to avoid loopback test failure */ 1639 msleep(50); 1640 1641 /* force 1000, set loopback */ 1642 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140); 1643 1644 /* Now set up the MAC to the same speed/duplex as the PHY. */ 1645 ctrl_reg = rd32(E1000_CTRL); 1646 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 1647 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 1648 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 1649 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */ 1650 E1000_CTRL_FD | /* Force Duplex to FULL */ 1651 E1000_CTRL_SLU); /* Set link up enable bit */ 1652 1653 if (hw->phy.type == e1000_phy_m88) 1654 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */ 1655 1656 wr32(E1000_CTRL, ctrl_reg); 1657 1658 /* Disable the receiver on the PHY so when a cable is plugged in, the 1659 * PHY does not begin to autoneg when a cable is reconnected to the NIC. 1660 */ 1661 if (hw->phy.type == e1000_phy_m88) 1662 igb_phy_disable_receiver(adapter); 1663 1664 msleep(500); 1665 return 0; 1666 } 1667 1668 static int igb_set_phy_loopback(struct igb_adapter *adapter) 1669 { 1670 return igb_integrated_phy_loopback(adapter); 1671 } 1672 1673 static int igb_setup_loopback_test(struct igb_adapter *adapter) 1674 { 1675 struct e1000_hw *hw = &adapter->hw; 1676 u32 reg; 1677 1678 reg = rd32(E1000_CTRL_EXT); 1679 1680 /* use CTRL_EXT to identify link type as SGMII can appear as copper */ 1681 if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) { 1682 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) || 1683 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) || 1684 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) || 1685 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) || 1686 (hw->device_id == E1000_DEV_ID_I354_SGMII) || 1687 (hw->device_id == E1000_DEV_ID_I354_BACKPLANE_2_5GBPS)) { 1688 /* Enable DH89xxCC MPHY for near end loopback */ 1689 reg = rd32(E1000_MPHY_ADDR_CTL); 1690 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) | 1691 E1000_MPHY_PCS_CLK_REG_OFFSET; 1692 wr32(E1000_MPHY_ADDR_CTL, reg); 1693 1694 reg = rd32(E1000_MPHY_DATA); 1695 reg |= E1000_MPHY_PCS_CLK_REG_DIGINELBEN; 1696 wr32(E1000_MPHY_DATA, reg); 1697 } 1698 1699 reg = rd32(E1000_RCTL); 1700 reg |= E1000_RCTL_LBM_TCVR; 1701 wr32(E1000_RCTL, reg); 1702 1703 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK); 1704 1705 reg = rd32(E1000_CTRL); 1706 reg &= ~(E1000_CTRL_RFCE | 1707 E1000_CTRL_TFCE | 1708 E1000_CTRL_LRST); 1709 reg |= E1000_CTRL_SLU | 1710 E1000_CTRL_FD; 1711 wr32(E1000_CTRL, reg); 1712 1713 /* Unset switch control to serdes energy detect */ 1714 reg = rd32(E1000_CONNSW); 1715 reg &= ~E1000_CONNSW_ENRGSRC; 1716 wr32(E1000_CONNSW, reg); 1717 1718 /* Unset sigdetect for SERDES loopback on 1719 * 82580 and newer devices. 1720 */ 1721 if (hw->mac.type >= e1000_82580) { 1722 reg = rd32(E1000_PCS_CFG0); 1723 reg |= E1000_PCS_CFG_IGN_SD; 1724 wr32(E1000_PCS_CFG0, reg); 1725 } 1726 1727 /* Set PCS register for forced speed */ 1728 reg = rd32(E1000_PCS_LCTL); 1729 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/ 1730 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */ 1731 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */ 1732 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ 1733 E1000_PCS_LCTL_FSD | /* Force Speed */ 1734 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */ 1735 wr32(E1000_PCS_LCTL, reg); 1736 1737 return 0; 1738 } 1739 1740 return igb_set_phy_loopback(adapter); 1741 } 1742 1743 static void igb_loopback_cleanup(struct igb_adapter *adapter) 1744 { 1745 struct e1000_hw *hw = &adapter->hw; 1746 u32 rctl; 1747 u16 phy_reg; 1748 1749 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) || 1750 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) || 1751 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) || 1752 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) || 1753 (hw->device_id == E1000_DEV_ID_I354_SGMII)) { 1754 u32 reg; 1755 1756 /* Disable near end loopback on DH89xxCC */ 1757 reg = rd32(E1000_MPHY_ADDR_CTL); 1758 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) | 1759 E1000_MPHY_PCS_CLK_REG_OFFSET; 1760 wr32(E1000_MPHY_ADDR_CTL, reg); 1761 1762 reg = rd32(E1000_MPHY_DATA); 1763 reg &= ~E1000_MPHY_PCS_CLK_REG_DIGINELBEN; 1764 wr32(E1000_MPHY_DATA, reg); 1765 } 1766 1767 rctl = rd32(E1000_RCTL); 1768 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 1769 wr32(E1000_RCTL, rctl); 1770 1771 hw->mac.autoneg = true; 1772 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg); 1773 if (phy_reg & MII_CR_LOOPBACK) { 1774 phy_reg &= ~MII_CR_LOOPBACK; 1775 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg); 1776 igb_phy_sw_reset(hw); 1777 } 1778 } 1779 1780 static void igb_create_lbtest_frame(struct sk_buff *skb, 1781 unsigned int frame_size) 1782 { 1783 memset(skb->data, 0xFF, frame_size); 1784 frame_size /= 2; 1785 memset(&skb->data[frame_size], 0xAA, frame_size - 1); 1786 memset(&skb->data[frame_size + 10], 0xBE, 1); 1787 memset(&skb->data[frame_size + 12], 0xAF, 1); 1788 } 1789 1790 static int igb_check_lbtest_frame(struct igb_rx_buffer *rx_buffer, 1791 unsigned int frame_size) 1792 { 1793 unsigned char *data; 1794 bool match = true; 1795 1796 frame_size >>= 1; 1797 1798 data = kmap(rx_buffer->page); 1799 1800 if (data[3] != 0xFF || 1801 data[frame_size + 10] != 0xBE || 1802 data[frame_size + 12] != 0xAF) 1803 match = false; 1804 1805 kunmap(rx_buffer->page); 1806 1807 return match; 1808 } 1809 1810 static int igb_clean_test_rings(struct igb_ring *rx_ring, 1811 struct igb_ring *tx_ring, 1812 unsigned int size) 1813 { 1814 union e1000_adv_rx_desc *rx_desc; 1815 struct igb_rx_buffer *rx_buffer_info; 1816 struct igb_tx_buffer *tx_buffer_info; 1817 u16 rx_ntc, tx_ntc, count = 0; 1818 1819 /* initialize next to clean and descriptor values */ 1820 rx_ntc = rx_ring->next_to_clean; 1821 tx_ntc = tx_ring->next_to_clean; 1822 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc); 1823 1824 while (rx_desc->wb.upper.length) { 1825 /* check Rx buffer */ 1826 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc]; 1827 1828 /* sync Rx buffer for CPU read */ 1829 dma_sync_single_for_cpu(rx_ring->dev, 1830 rx_buffer_info->dma, 1831 size, 1832 DMA_FROM_DEVICE); 1833 1834 /* verify contents of skb */ 1835 if (igb_check_lbtest_frame(rx_buffer_info, size)) 1836 count++; 1837 1838 /* sync Rx buffer for device write */ 1839 dma_sync_single_for_device(rx_ring->dev, 1840 rx_buffer_info->dma, 1841 size, 1842 DMA_FROM_DEVICE); 1843 1844 /* unmap buffer on Tx side */ 1845 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc]; 1846 1847 /* Free all the Tx ring sk_buffs */ 1848 dev_kfree_skb_any(tx_buffer_info->skb); 1849 1850 /* unmap skb header data */ 1851 dma_unmap_single(tx_ring->dev, 1852 dma_unmap_addr(tx_buffer_info, dma), 1853 dma_unmap_len(tx_buffer_info, len), 1854 DMA_TO_DEVICE); 1855 dma_unmap_len_set(tx_buffer_info, len, 0); 1856 1857 /* increment Rx/Tx next to clean counters */ 1858 rx_ntc++; 1859 if (rx_ntc == rx_ring->count) 1860 rx_ntc = 0; 1861 tx_ntc++; 1862 if (tx_ntc == tx_ring->count) 1863 tx_ntc = 0; 1864 1865 /* fetch next descriptor */ 1866 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc); 1867 } 1868 1869 netdev_tx_reset_queue(txring_txq(tx_ring)); 1870 1871 /* re-map buffers to ring, store next to clean values */ 1872 igb_alloc_rx_buffers(rx_ring, count); 1873 rx_ring->next_to_clean = rx_ntc; 1874 tx_ring->next_to_clean = tx_ntc; 1875 1876 return count; 1877 } 1878 1879 static int igb_run_loopback_test(struct igb_adapter *adapter) 1880 { 1881 struct igb_ring *tx_ring = &adapter->test_tx_ring; 1882 struct igb_ring *rx_ring = &adapter->test_rx_ring; 1883 u16 i, j, lc, good_cnt; 1884 int ret_val = 0; 1885 unsigned int size = IGB_RX_HDR_LEN; 1886 netdev_tx_t tx_ret_val; 1887 struct sk_buff *skb; 1888 1889 /* allocate test skb */ 1890 skb = alloc_skb(size, GFP_KERNEL); 1891 if (!skb) 1892 return 11; 1893 1894 /* place data into test skb */ 1895 igb_create_lbtest_frame(skb, size); 1896 skb_put(skb, size); 1897 1898 /* Calculate the loop count based on the largest descriptor ring 1899 * The idea is to wrap the largest ring a number of times using 64 1900 * send/receive pairs during each loop 1901 */ 1902 1903 if (rx_ring->count <= tx_ring->count) 1904 lc = ((tx_ring->count / 64) * 2) + 1; 1905 else 1906 lc = ((rx_ring->count / 64) * 2) + 1; 1907 1908 for (j = 0; j <= lc; j++) { /* loop count loop */ 1909 /* reset count of good packets */ 1910 good_cnt = 0; 1911 1912 /* place 64 packets on the transmit queue*/ 1913 for (i = 0; i < 64; i++) { 1914 skb_get(skb); 1915 tx_ret_val = igb_xmit_frame_ring(skb, tx_ring); 1916 if (tx_ret_val == NETDEV_TX_OK) 1917 good_cnt++; 1918 } 1919 1920 if (good_cnt != 64) { 1921 ret_val = 12; 1922 break; 1923 } 1924 1925 /* allow 200 milliseconds for packets to go from Tx to Rx */ 1926 msleep(200); 1927 1928 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size); 1929 if (good_cnt != 64) { 1930 ret_val = 13; 1931 break; 1932 } 1933 } /* end loop count loop */ 1934 1935 /* free the original skb */ 1936 kfree_skb(skb); 1937 1938 return ret_val; 1939 } 1940 1941 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data) 1942 { 1943 /* PHY loopback cannot be performed if SoL/IDER 1944 * sessions are active 1945 */ 1946 if (igb_check_reset_block(&adapter->hw)) { 1947 dev_err(&adapter->pdev->dev, 1948 "Cannot do PHY loopback test when SoL/IDER is active.\n"); 1949 *data = 0; 1950 goto out; 1951 } 1952 1953 if (adapter->hw.mac.type == e1000_i354) { 1954 dev_info(&adapter->pdev->dev, 1955 "Loopback test not supported on i354.\n"); 1956 *data = 0; 1957 goto out; 1958 } 1959 *data = igb_setup_desc_rings(adapter); 1960 if (*data) 1961 goto out; 1962 *data = igb_setup_loopback_test(adapter); 1963 if (*data) 1964 goto err_loopback; 1965 *data = igb_run_loopback_test(adapter); 1966 igb_loopback_cleanup(adapter); 1967 1968 err_loopback: 1969 igb_free_desc_rings(adapter); 1970 out: 1971 return *data; 1972 } 1973 1974 static int igb_link_test(struct igb_adapter *adapter, u64 *data) 1975 { 1976 struct e1000_hw *hw = &adapter->hw; 1977 *data = 0; 1978 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 1979 int i = 0; 1980 1981 hw->mac.serdes_has_link = false; 1982 1983 /* On some blade server designs, link establishment 1984 * could take as long as 2-3 minutes 1985 */ 1986 do { 1987 hw->mac.ops.check_for_link(&adapter->hw); 1988 if (hw->mac.serdes_has_link) 1989 return *data; 1990 msleep(20); 1991 } while (i++ < 3750); 1992 1993 *data = 1; 1994 } else { 1995 hw->mac.ops.check_for_link(&adapter->hw); 1996 if (hw->mac.autoneg) 1997 msleep(5000); 1998 1999 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) 2000 *data = 1; 2001 } 2002 return *data; 2003 } 2004 2005 static void igb_diag_test(struct net_device *netdev, 2006 struct ethtool_test *eth_test, u64 *data) 2007 { 2008 struct igb_adapter *adapter = netdev_priv(netdev); 2009 u16 autoneg_advertised; 2010 u8 forced_speed_duplex, autoneg; 2011 bool if_running = netif_running(netdev); 2012 2013 set_bit(__IGB_TESTING, &adapter->state); 2014 2015 /* can't do offline tests on media switching devices */ 2016 if (adapter->hw.dev_spec._82575.mas_capable) 2017 eth_test->flags &= ~ETH_TEST_FL_OFFLINE; 2018 if (eth_test->flags == ETH_TEST_FL_OFFLINE) { 2019 /* Offline tests */ 2020 2021 /* save speed, duplex, autoneg settings */ 2022 autoneg_advertised = adapter->hw.phy.autoneg_advertised; 2023 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex; 2024 autoneg = adapter->hw.mac.autoneg; 2025 2026 dev_info(&adapter->pdev->dev, "offline testing starting\n"); 2027 2028 /* power up link for link test */ 2029 igb_power_up_link(adapter); 2030 2031 /* Link test performed before hardware reset so autoneg doesn't 2032 * interfere with test result 2033 */ 2034 if (igb_link_test(adapter, &data[TEST_LINK])) 2035 eth_test->flags |= ETH_TEST_FL_FAILED; 2036 2037 if (if_running) 2038 /* indicate we're in test mode */ 2039 igb_close(netdev); 2040 else 2041 igb_reset(adapter); 2042 2043 if (igb_reg_test(adapter, &data[TEST_REG])) 2044 eth_test->flags |= ETH_TEST_FL_FAILED; 2045 2046 igb_reset(adapter); 2047 if (igb_eeprom_test(adapter, &data[TEST_EEP])) 2048 eth_test->flags |= ETH_TEST_FL_FAILED; 2049 2050 igb_reset(adapter); 2051 if (igb_intr_test(adapter, &data[TEST_IRQ])) 2052 eth_test->flags |= ETH_TEST_FL_FAILED; 2053 2054 igb_reset(adapter); 2055 /* power up link for loopback test */ 2056 igb_power_up_link(adapter); 2057 if (igb_loopback_test(adapter, &data[TEST_LOOP])) 2058 eth_test->flags |= ETH_TEST_FL_FAILED; 2059 2060 /* restore speed, duplex, autoneg settings */ 2061 adapter->hw.phy.autoneg_advertised = autoneg_advertised; 2062 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex; 2063 adapter->hw.mac.autoneg = autoneg; 2064 2065 /* force this routine to wait until autoneg complete/timeout */ 2066 adapter->hw.phy.autoneg_wait_to_complete = true; 2067 igb_reset(adapter); 2068 adapter->hw.phy.autoneg_wait_to_complete = false; 2069 2070 clear_bit(__IGB_TESTING, &adapter->state); 2071 if (if_running) 2072 igb_open(netdev); 2073 } else { 2074 dev_info(&adapter->pdev->dev, "online testing starting\n"); 2075 2076 /* PHY is powered down when interface is down */ 2077 if (if_running && igb_link_test(adapter, &data[TEST_LINK])) 2078 eth_test->flags |= ETH_TEST_FL_FAILED; 2079 else 2080 data[TEST_LINK] = 0; 2081 2082 /* Online tests aren't run; pass by default */ 2083 data[TEST_REG] = 0; 2084 data[TEST_EEP] = 0; 2085 data[TEST_IRQ] = 0; 2086 data[TEST_LOOP] = 0; 2087 2088 clear_bit(__IGB_TESTING, &adapter->state); 2089 } 2090 msleep_interruptible(4 * 1000); 2091 } 2092 2093 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2094 { 2095 struct igb_adapter *adapter = netdev_priv(netdev); 2096 2097 wol->wolopts = 0; 2098 2099 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED)) 2100 return; 2101 2102 wol->supported = WAKE_UCAST | WAKE_MCAST | 2103 WAKE_BCAST | WAKE_MAGIC | 2104 WAKE_PHY; 2105 2106 /* apply any specific unsupported masks here */ 2107 switch (adapter->hw.device_id) { 2108 default: 2109 break; 2110 } 2111 2112 if (adapter->wol & E1000_WUFC_EX) 2113 wol->wolopts |= WAKE_UCAST; 2114 if (adapter->wol & E1000_WUFC_MC) 2115 wol->wolopts |= WAKE_MCAST; 2116 if (adapter->wol & E1000_WUFC_BC) 2117 wol->wolopts |= WAKE_BCAST; 2118 if (adapter->wol & E1000_WUFC_MAG) 2119 wol->wolopts |= WAKE_MAGIC; 2120 if (adapter->wol & E1000_WUFC_LNKC) 2121 wol->wolopts |= WAKE_PHY; 2122 } 2123 2124 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2125 { 2126 struct igb_adapter *adapter = netdev_priv(netdev); 2127 2128 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE | WAKE_FILTER)) 2129 return -EOPNOTSUPP; 2130 2131 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED)) 2132 return wol->wolopts ? -EOPNOTSUPP : 0; 2133 2134 /* these settings will always override what we currently have */ 2135 adapter->wol = 0; 2136 2137 if (wol->wolopts & WAKE_UCAST) 2138 adapter->wol |= E1000_WUFC_EX; 2139 if (wol->wolopts & WAKE_MCAST) 2140 adapter->wol |= E1000_WUFC_MC; 2141 if (wol->wolopts & WAKE_BCAST) 2142 adapter->wol |= E1000_WUFC_BC; 2143 if (wol->wolopts & WAKE_MAGIC) 2144 adapter->wol |= E1000_WUFC_MAG; 2145 if (wol->wolopts & WAKE_PHY) 2146 adapter->wol |= E1000_WUFC_LNKC; 2147 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 2148 2149 return 0; 2150 } 2151 2152 /* bit defines for adapter->led_status */ 2153 #define IGB_LED_ON 0 2154 2155 static int igb_set_phys_id(struct net_device *netdev, 2156 enum ethtool_phys_id_state state) 2157 { 2158 struct igb_adapter *adapter = netdev_priv(netdev); 2159 struct e1000_hw *hw = &adapter->hw; 2160 2161 switch (state) { 2162 case ETHTOOL_ID_ACTIVE: 2163 igb_blink_led(hw); 2164 return 2; 2165 case ETHTOOL_ID_ON: 2166 igb_blink_led(hw); 2167 break; 2168 case ETHTOOL_ID_OFF: 2169 igb_led_off(hw); 2170 break; 2171 case ETHTOOL_ID_INACTIVE: 2172 igb_led_off(hw); 2173 clear_bit(IGB_LED_ON, &adapter->led_status); 2174 igb_cleanup_led(hw); 2175 break; 2176 } 2177 2178 return 0; 2179 } 2180 2181 static int igb_set_coalesce(struct net_device *netdev, 2182 struct ethtool_coalesce *ec) 2183 { 2184 struct igb_adapter *adapter = netdev_priv(netdev); 2185 int i; 2186 2187 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) || 2188 ((ec->rx_coalesce_usecs > 3) && 2189 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) || 2190 (ec->rx_coalesce_usecs == 2)) 2191 return -EINVAL; 2192 2193 if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) || 2194 ((ec->tx_coalesce_usecs > 3) && 2195 (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) || 2196 (ec->tx_coalesce_usecs == 2)) 2197 return -EINVAL; 2198 2199 if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs) 2200 return -EINVAL; 2201 2202 /* If ITR is disabled, disable DMAC */ 2203 if (ec->rx_coalesce_usecs == 0) { 2204 if (adapter->flags & IGB_FLAG_DMAC) 2205 adapter->flags &= ~IGB_FLAG_DMAC; 2206 } 2207 2208 /* convert to rate of irq's per second */ 2209 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3) 2210 adapter->rx_itr_setting = ec->rx_coalesce_usecs; 2211 else 2212 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2; 2213 2214 /* convert to rate of irq's per second */ 2215 if (adapter->flags & IGB_FLAG_QUEUE_PAIRS) 2216 adapter->tx_itr_setting = adapter->rx_itr_setting; 2217 else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3) 2218 adapter->tx_itr_setting = ec->tx_coalesce_usecs; 2219 else 2220 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2; 2221 2222 for (i = 0; i < adapter->num_q_vectors; i++) { 2223 struct igb_q_vector *q_vector = adapter->q_vector[i]; 2224 q_vector->tx.work_limit = adapter->tx_work_limit; 2225 if (q_vector->rx.ring) 2226 q_vector->itr_val = adapter->rx_itr_setting; 2227 else 2228 q_vector->itr_val = adapter->tx_itr_setting; 2229 if (q_vector->itr_val && q_vector->itr_val <= 3) 2230 q_vector->itr_val = IGB_START_ITR; 2231 q_vector->set_itr = 1; 2232 } 2233 2234 return 0; 2235 } 2236 2237 static int igb_get_coalesce(struct net_device *netdev, 2238 struct ethtool_coalesce *ec) 2239 { 2240 struct igb_adapter *adapter = netdev_priv(netdev); 2241 2242 if (adapter->rx_itr_setting <= 3) 2243 ec->rx_coalesce_usecs = adapter->rx_itr_setting; 2244 else 2245 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2; 2246 2247 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) { 2248 if (adapter->tx_itr_setting <= 3) 2249 ec->tx_coalesce_usecs = adapter->tx_itr_setting; 2250 else 2251 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2; 2252 } 2253 2254 return 0; 2255 } 2256 2257 static int igb_nway_reset(struct net_device *netdev) 2258 { 2259 struct igb_adapter *adapter = netdev_priv(netdev); 2260 if (netif_running(netdev)) 2261 igb_reinit_locked(adapter); 2262 return 0; 2263 } 2264 2265 static int igb_get_sset_count(struct net_device *netdev, int sset) 2266 { 2267 switch (sset) { 2268 case ETH_SS_STATS: 2269 return IGB_STATS_LEN; 2270 case ETH_SS_TEST: 2271 return IGB_TEST_LEN; 2272 case ETH_SS_PRIV_FLAGS: 2273 return IGB_PRIV_FLAGS_STR_LEN; 2274 default: 2275 return -ENOTSUPP; 2276 } 2277 } 2278 2279 static void igb_get_ethtool_stats(struct net_device *netdev, 2280 struct ethtool_stats *stats, u64 *data) 2281 { 2282 struct igb_adapter *adapter = netdev_priv(netdev); 2283 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 2284 unsigned int start; 2285 struct igb_ring *ring; 2286 int i, j; 2287 char *p; 2288 2289 spin_lock(&adapter->stats64_lock); 2290 igb_update_stats(adapter); 2291 2292 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) { 2293 p = (char *)adapter + igb_gstrings_stats[i].stat_offset; 2294 data[i] = (igb_gstrings_stats[i].sizeof_stat == 2295 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 2296 } 2297 for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) { 2298 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset; 2299 data[i] = (igb_gstrings_net_stats[j].sizeof_stat == 2300 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 2301 } 2302 for (j = 0; j < adapter->num_tx_queues; j++) { 2303 u64 restart2; 2304 2305 ring = adapter->tx_ring[j]; 2306 do { 2307 start = u64_stats_fetch_begin_irq(&ring->tx_syncp); 2308 data[i] = ring->tx_stats.packets; 2309 data[i+1] = ring->tx_stats.bytes; 2310 data[i+2] = ring->tx_stats.restart_queue; 2311 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start)); 2312 do { 2313 start = u64_stats_fetch_begin_irq(&ring->tx_syncp2); 2314 restart2 = ring->tx_stats.restart_queue2; 2315 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp2, start)); 2316 data[i+2] += restart2; 2317 2318 i += IGB_TX_QUEUE_STATS_LEN; 2319 } 2320 for (j = 0; j < adapter->num_rx_queues; j++) { 2321 ring = adapter->rx_ring[j]; 2322 do { 2323 start = u64_stats_fetch_begin_irq(&ring->rx_syncp); 2324 data[i] = ring->rx_stats.packets; 2325 data[i+1] = ring->rx_stats.bytes; 2326 data[i+2] = ring->rx_stats.drops; 2327 data[i+3] = ring->rx_stats.csum_err; 2328 data[i+4] = ring->rx_stats.alloc_failed; 2329 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start)); 2330 i += IGB_RX_QUEUE_STATS_LEN; 2331 } 2332 spin_unlock(&adapter->stats64_lock); 2333 } 2334 2335 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data) 2336 { 2337 struct igb_adapter *adapter = netdev_priv(netdev); 2338 u8 *p = data; 2339 int i; 2340 2341 switch (stringset) { 2342 case ETH_SS_TEST: 2343 memcpy(data, *igb_gstrings_test, 2344 IGB_TEST_LEN*ETH_GSTRING_LEN); 2345 break; 2346 case ETH_SS_STATS: 2347 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) { 2348 memcpy(p, igb_gstrings_stats[i].stat_string, 2349 ETH_GSTRING_LEN); 2350 p += ETH_GSTRING_LEN; 2351 } 2352 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) { 2353 memcpy(p, igb_gstrings_net_stats[i].stat_string, 2354 ETH_GSTRING_LEN); 2355 p += ETH_GSTRING_LEN; 2356 } 2357 for (i = 0; i < adapter->num_tx_queues; i++) { 2358 sprintf(p, "tx_queue_%u_packets", i); 2359 p += ETH_GSTRING_LEN; 2360 sprintf(p, "tx_queue_%u_bytes", i); 2361 p += ETH_GSTRING_LEN; 2362 sprintf(p, "tx_queue_%u_restart", i); 2363 p += ETH_GSTRING_LEN; 2364 } 2365 for (i = 0; i < adapter->num_rx_queues; i++) { 2366 sprintf(p, "rx_queue_%u_packets", i); 2367 p += ETH_GSTRING_LEN; 2368 sprintf(p, "rx_queue_%u_bytes", i); 2369 p += ETH_GSTRING_LEN; 2370 sprintf(p, "rx_queue_%u_drops", i); 2371 p += ETH_GSTRING_LEN; 2372 sprintf(p, "rx_queue_%u_csum_err", i); 2373 p += ETH_GSTRING_LEN; 2374 sprintf(p, "rx_queue_%u_alloc_failed", i); 2375 p += ETH_GSTRING_LEN; 2376 } 2377 /* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */ 2378 break; 2379 case ETH_SS_PRIV_FLAGS: 2380 memcpy(data, igb_priv_flags_strings, 2381 IGB_PRIV_FLAGS_STR_LEN * ETH_GSTRING_LEN); 2382 break; 2383 } 2384 } 2385 2386 static int igb_get_ts_info(struct net_device *dev, 2387 struct ethtool_ts_info *info) 2388 { 2389 struct igb_adapter *adapter = netdev_priv(dev); 2390 2391 if (adapter->ptp_clock) 2392 info->phc_index = ptp_clock_index(adapter->ptp_clock); 2393 else 2394 info->phc_index = -1; 2395 2396 switch (adapter->hw.mac.type) { 2397 case e1000_82575: 2398 info->so_timestamping = 2399 SOF_TIMESTAMPING_TX_SOFTWARE | 2400 SOF_TIMESTAMPING_RX_SOFTWARE | 2401 SOF_TIMESTAMPING_SOFTWARE; 2402 return 0; 2403 case e1000_82576: 2404 case e1000_82580: 2405 case e1000_i350: 2406 case e1000_i354: 2407 case e1000_i210: 2408 case e1000_i211: 2409 info->so_timestamping = 2410 SOF_TIMESTAMPING_TX_SOFTWARE | 2411 SOF_TIMESTAMPING_RX_SOFTWARE | 2412 SOF_TIMESTAMPING_SOFTWARE | 2413 SOF_TIMESTAMPING_TX_HARDWARE | 2414 SOF_TIMESTAMPING_RX_HARDWARE | 2415 SOF_TIMESTAMPING_RAW_HARDWARE; 2416 2417 info->tx_types = 2418 BIT(HWTSTAMP_TX_OFF) | 2419 BIT(HWTSTAMP_TX_ON); 2420 2421 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE); 2422 2423 /* 82576 does not support timestamping all packets. */ 2424 if (adapter->hw.mac.type >= e1000_82580) 2425 info->rx_filters |= BIT(HWTSTAMP_FILTER_ALL); 2426 else 2427 info->rx_filters |= 2428 BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 2429 BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 2430 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT); 2431 2432 return 0; 2433 default: 2434 return -EOPNOTSUPP; 2435 } 2436 } 2437 2438 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0) 2439 static int igb_get_ethtool_nfc_entry(struct igb_adapter *adapter, 2440 struct ethtool_rxnfc *cmd) 2441 { 2442 struct ethtool_rx_flow_spec *fsp = &cmd->fs; 2443 struct igb_nfc_filter *rule = NULL; 2444 2445 /* report total rule count */ 2446 cmd->data = IGB_MAX_RXNFC_FILTERS; 2447 2448 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) { 2449 if (fsp->location <= rule->sw_idx) 2450 break; 2451 } 2452 2453 if (!rule || fsp->location != rule->sw_idx) 2454 return -EINVAL; 2455 2456 if (rule->filter.match_flags) { 2457 fsp->flow_type = ETHER_FLOW; 2458 fsp->ring_cookie = rule->action; 2459 if (rule->filter.match_flags & IGB_FILTER_FLAG_ETHER_TYPE) { 2460 fsp->h_u.ether_spec.h_proto = rule->filter.etype; 2461 fsp->m_u.ether_spec.h_proto = ETHER_TYPE_FULL_MASK; 2462 } 2463 if (rule->filter.match_flags & IGB_FILTER_FLAG_VLAN_TCI) { 2464 fsp->flow_type |= FLOW_EXT; 2465 fsp->h_ext.vlan_tci = rule->filter.vlan_tci; 2466 fsp->m_ext.vlan_tci = htons(VLAN_PRIO_MASK); 2467 } 2468 if (rule->filter.match_flags & IGB_FILTER_FLAG_DST_MAC_ADDR) { 2469 ether_addr_copy(fsp->h_u.ether_spec.h_dest, 2470 rule->filter.dst_addr); 2471 /* As we only support matching by the full 2472 * mask, return the mask to userspace 2473 */ 2474 eth_broadcast_addr(fsp->m_u.ether_spec.h_dest); 2475 } 2476 if (rule->filter.match_flags & IGB_FILTER_FLAG_SRC_MAC_ADDR) { 2477 ether_addr_copy(fsp->h_u.ether_spec.h_source, 2478 rule->filter.src_addr); 2479 /* As we only support matching by the full 2480 * mask, return the mask to userspace 2481 */ 2482 eth_broadcast_addr(fsp->m_u.ether_spec.h_source); 2483 } 2484 2485 return 0; 2486 } 2487 return -EINVAL; 2488 } 2489 2490 static int igb_get_ethtool_nfc_all(struct igb_adapter *adapter, 2491 struct ethtool_rxnfc *cmd, 2492 u32 *rule_locs) 2493 { 2494 struct igb_nfc_filter *rule; 2495 int cnt = 0; 2496 2497 /* report total rule count */ 2498 cmd->data = IGB_MAX_RXNFC_FILTERS; 2499 2500 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) { 2501 if (cnt == cmd->rule_cnt) 2502 return -EMSGSIZE; 2503 rule_locs[cnt] = rule->sw_idx; 2504 cnt++; 2505 } 2506 2507 cmd->rule_cnt = cnt; 2508 2509 return 0; 2510 } 2511 2512 static int igb_get_rss_hash_opts(struct igb_adapter *adapter, 2513 struct ethtool_rxnfc *cmd) 2514 { 2515 cmd->data = 0; 2516 2517 /* Report default options for RSS on igb */ 2518 switch (cmd->flow_type) { 2519 case TCP_V4_FLOW: 2520 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2521 /* Fall through */ 2522 case UDP_V4_FLOW: 2523 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 2524 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2525 /* Fall through */ 2526 case SCTP_V4_FLOW: 2527 case AH_ESP_V4_FLOW: 2528 case AH_V4_FLOW: 2529 case ESP_V4_FLOW: 2530 case IPV4_FLOW: 2531 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2532 break; 2533 case TCP_V6_FLOW: 2534 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2535 /* Fall through */ 2536 case UDP_V6_FLOW: 2537 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 2538 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2539 /* Fall through */ 2540 case SCTP_V6_FLOW: 2541 case AH_ESP_V6_FLOW: 2542 case AH_V6_FLOW: 2543 case ESP_V6_FLOW: 2544 case IPV6_FLOW: 2545 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2546 break; 2547 default: 2548 return -EINVAL; 2549 } 2550 2551 return 0; 2552 } 2553 2554 static int igb_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2555 u32 *rule_locs) 2556 { 2557 struct igb_adapter *adapter = netdev_priv(dev); 2558 int ret = -EOPNOTSUPP; 2559 2560 switch (cmd->cmd) { 2561 case ETHTOOL_GRXRINGS: 2562 cmd->data = adapter->num_rx_queues; 2563 ret = 0; 2564 break; 2565 case ETHTOOL_GRXCLSRLCNT: 2566 cmd->rule_cnt = adapter->nfc_filter_count; 2567 ret = 0; 2568 break; 2569 case ETHTOOL_GRXCLSRULE: 2570 ret = igb_get_ethtool_nfc_entry(adapter, cmd); 2571 break; 2572 case ETHTOOL_GRXCLSRLALL: 2573 ret = igb_get_ethtool_nfc_all(adapter, cmd, rule_locs); 2574 break; 2575 case ETHTOOL_GRXFH: 2576 ret = igb_get_rss_hash_opts(adapter, cmd); 2577 break; 2578 default: 2579 break; 2580 } 2581 2582 return ret; 2583 } 2584 2585 #define UDP_RSS_FLAGS (IGB_FLAG_RSS_FIELD_IPV4_UDP | \ 2586 IGB_FLAG_RSS_FIELD_IPV6_UDP) 2587 static int igb_set_rss_hash_opt(struct igb_adapter *adapter, 2588 struct ethtool_rxnfc *nfc) 2589 { 2590 u32 flags = adapter->flags; 2591 2592 /* RSS does not support anything other than hashing 2593 * to queues on src and dst IPs and ports 2594 */ 2595 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST | 2596 RXH_L4_B_0_1 | RXH_L4_B_2_3)) 2597 return -EINVAL; 2598 2599 switch (nfc->flow_type) { 2600 case TCP_V4_FLOW: 2601 case TCP_V6_FLOW: 2602 if (!(nfc->data & RXH_IP_SRC) || 2603 !(nfc->data & RXH_IP_DST) || 2604 !(nfc->data & RXH_L4_B_0_1) || 2605 !(nfc->data & RXH_L4_B_2_3)) 2606 return -EINVAL; 2607 break; 2608 case UDP_V4_FLOW: 2609 if (!(nfc->data & RXH_IP_SRC) || 2610 !(nfc->data & RXH_IP_DST)) 2611 return -EINVAL; 2612 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2613 case 0: 2614 flags &= ~IGB_FLAG_RSS_FIELD_IPV4_UDP; 2615 break; 2616 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2617 flags |= IGB_FLAG_RSS_FIELD_IPV4_UDP; 2618 break; 2619 default: 2620 return -EINVAL; 2621 } 2622 break; 2623 case UDP_V6_FLOW: 2624 if (!(nfc->data & RXH_IP_SRC) || 2625 !(nfc->data & RXH_IP_DST)) 2626 return -EINVAL; 2627 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2628 case 0: 2629 flags &= ~IGB_FLAG_RSS_FIELD_IPV6_UDP; 2630 break; 2631 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2632 flags |= IGB_FLAG_RSS_FIELD_IPV6_UDP; 2633 break; 2634 default: 2635 return -EINVAL; 2636 } 2637 break; 2638 case AH_ESP_V4_FLOW: 2639 case AH_V4_FLOW: 2640 case ESP_V4_FLOW: 2641 case SCTP_V4_FLOW: 2642 case AH_ESP_V6_FLOW: 2643 case AH_V6_FLOW: 2644 case ESP_V6_FLOW: 2645 case SCTP_V6_FLOW: 2646 if (!(nfc->data & RXH_IP_SRC) || 2647 !(nfc->data & RXH_IP_DST) || 2648 (nfc->data & RXH_L4_B_0_1) || 2649 (nfc->data & RXH_L4_B_2_3)) 2650 return -EINVAL; 2651 break; 2652 default: 2653 return -EINVAL; 2654 } 2655 2656 /* if we changed something we need to update flags */ 2657 if (flags != adapter->flags) { 2658 struct e1000_hw *hw = &adapter->hw; 2659 u32 mrqc = rd32(E1000_MRQC); 2660 2661 if ((flags & UDP_RSS_FLAGS) && 2662 !(adapter->flags & UDP_RSS_FLAGS)) 2663 dev_err(&adapter->pdev->dev, 2664 "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n"); 2665 2666 adapter->flags = flags; 2667 2668 /* Perform hash on these packet types */ 2669 mrqc |= E1000_MRQC_RSS_FIELD_IPV4 | 2670 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2671 E1000_MRQC_RSS_FIELD_IPV6 | 2672 E1000_MRQC_RSS_FIELD_IPV6_TCP; 2673 2674 mrqc &= ~(E1000_MRQC_RSS_FIELD_IPV4_UDP | 2675 E1000_MRQC_RSS_FIELD_IPV6_UDP); 2676 2677 if (flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 2678 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 2679 2680 if (flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 2681 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 2682 2683 wr32(E1000_MRQC, mrqc); 2684 } 2685 2686 return 0; 2687 } 2688 2689 static int igb_rxnfc_write_etype_filter(struct igb_adapter *adapter, 2690 struct igb_nfc_filter *input) 2691 { 2692 struct e1000_hw *hw = &adapter->hw; 2693 u8 i; 2694 u32 etqf; 2695 u16 etype; 2696 2697 /* find an empty etype filter register */ 2698 for (i = 0; i < MAX_ETYPE_FILTER; ++i) { 2699 if (!adapter->etype_bitmap[i]) 2700 break; 2701 } 2702 if (i == MAX_ETYPE_FILTER) { 2703 dev_err(&adapter->pdev->dev, "ethtool -N: etype filters are all used.\n"); 2704 return -EINVAL; 2705 } 2706 2707 adapter->etype_bitmap[i] = true; 2708 2709 etqf = rd32(E1000_ETQF(i)); 2710 etype = ntohs(input->filter.etype & ETHER_TYPE_FULL_MASK); 2711 2712 etqf |= E1000_ETQF_FILTER_ENABLE; 2713 etqf &= ~E1000_ETQF_ETYPE_MASK; 2714 etqf |= (etype & E1000_ETQF_ETYPE_MASK); 2715 2716 etqf &= ~E1000_ETQF_QUEUE_MASK; 2717 etqf |= ((input->action << E1000_ETQF_QUEUE_SHIFT) 2718 & E1000_ETQF_QUEUE_MASK); 2719 etqf |= E1000_ETQF_QUEUE_ENABLE; 2720 2721 wr32(E1000_ETQF(i), etqf); 2722 2723 input->etype_reg_index = i; 2724 2725 return 0; 2726 } 2727 2728 static int igb_rxnfc_write_vlan_prio_filter(struct igb_adapter *adapter, 2729 struct igb_nfc_filter *input) 2730 { 2731 struct e1000_hw *hw = &adapter->hw; 2732 u8 vlan_priority; 2733 u16 queue_index; 2734 u32 vlapqf; 2735 2736 vlapqf = rd32(E1000_VLAPQF); 2737 vlan_priority = (ntohs(input->filter.vlan_tci) & VLAN_PRIO_MASK) 2738 >> VLAN_PRIO_SHIFT; 2739 queue_index = (vlapqf >> (vlan_priority * 4)) & E1000_VLAPQF_QUEUE_MASK; 2740 2741 /* check whether this vlan prio is already set */ 2742 if ((vlapqf & E1000_VLAPQF_P_VALID(vlan_priority)) && 2743 (queue_index != input->action)) { 2744 dev_err(&adapter->pdev->dev, "ethtool rxnfc set vlan prio filter failed.\n"); 2745 return -EEXIST; 2746 } 2747 2748 vlapqf |= E1000_VLAPQF_P_VALID(vlan_priority); 2749 vlapqf |= E1000_VLAPQF_QUEUE_SEL(vlan_priority, input->action); 2750 2751 wr32(E1000_VLAPQF, vlapqf); 2752 2753 return 0; 2754 } 2755 2756 int igb_add_filter(struct igb_adapter *adapter, struct igb_nfc_filter *input) 2757 { 2758 struct e1000_hw *hw = &adapter->hw; 2759 int err = -EINVAL; 2760 2761 if (hw->mac.type == e1000_i210 && 2762 !(input->filter.match_flags & ~IGB_FILTER_FLAG_SRC_MAC_ADDR)) { 2763 dev_err(&adapter->pdev->dev, 2764 "i210 doesn't support flow classification rules specifying only source addresses.\n"); 2765 return -EOPNOTSUPP; 2766 } 2767 2768 if (input->filter.match_flags & IGB_FILTER_FLAG_ETHER_TYPE) { 2769 err = igb_rxnfc_write_etype_filter(adapter, input); 2770 if (err) 2771 return err; 2772 } 2773 2774 if (input->filter.match_flags & IGB_FILTER_FLAG_DST_MAC_ADDR) { 2775 err = igb_add_mac_steering_filter(adapter, 2776 input->filter.dst_addr, 2777 input->action, 0); 2778 err = min_t(int, err, 0); 2779 if (err) 2780 return err; 2781 } 2782 2783 if (input->filter.match_flags & IGB_FILTER_FLAG_SRC_MAC_ADDR) { 2784 err = igb_add_mac_steering_filter(adapter, 2785 input->filter.src_addr, 2786 input->action, 2787 IGB_MAC_STATE_SRC_ADDR); 2788 err = min_t(int, err, 0); 2789 if (err) 2790 return err; 2791 } 2792 2793 if (input->filter.match_flags & IGB_FILTER_FLAG_VLAN_TCI) 2794 err = igb_rxnfc_write_vlan_prio_filter(adapter, input); 2795 2796 return err; 2797 } 2798 2799 static void igb_clear_etype_filter_regs(struct igb_adapter *adapter, 2800 u16 reg_index) 2801 { 2802 struct e1000_hw *hw = &adapter->hw; 2803 u32 etqf = rd32(E1000_ETQF(reg_index)); 2804 2805 etqf &= ~E1000_ETQF_QUEUE_ENABLE; 2806 etqf &= ~E1000_ETQF_QUEUE_MASK; 2807 etqf &= ~E1000_ETQF_FILTER_ENABLE; 2808 2809 wr32(E1000_ETQF(reg_index), etqf); 2810 2811 adapter->etype_bitmap[reg_index] = false; 2812 } 2813 2814 static void igb_clear_vlan_prio_filter(struct igb_adapter *adapter, 2815 u16 vlan_tci) 2816 { 2817 struct e1000_hw *hw = &adapter->hw; 2818 u8 vlan_priority; 2819 u32 vlapqf; 2820 2821 vlan_priority = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT; 2822 2823 vlapqf = rd32(E1000_VLAPQF); 2824 vlapqf &= ~E1000_VLAPQF_P_VALID(vlan_priority); 2825 vlapqf &= ~E1000_VLAPQF_QUEUE_SEL(vlan_priority, 2826 E1000_VLAPQF_QUEUE_MASK); 2827 2828 wr32(E1000_VLAPQF, vlapqf); 2829 } 2830 2831 int igb_erase_filter(struct igb_adapter *adapter, struct igb_nfc_filter *input) 2832 { 2833 if (input->filter.match_flags & IGB_FILTER_FLAG_ETHER_TYPE) 2834 igb_clear_etype_filter_regs(adapter, 2835 input->etype_reg_index); 2836 2837 if (input->filter.match_flags & IGB_FILTER_FLAG_VLAN_TCI) 2838 igb_clear_vlan_prio_filter(adapter, 2839 ntohs(input->filter.vlan_tci)); 2840 2841 if (input->filter.match_flags & IGB_FILTER_FLAG_SRC_MAC_ADDR) 2842 igb_del_mac_steering_filter(adapter, input->filter.src_addr, 2843 input->action, 2844 IGB_MAC_STATE_SRC_ADDR); 2845 2846 if (input->filter.match_flags & IGB_FILTER_FLAG_DST_MAC_ADDR) 2847 igb_del_mac_steering_filter(adapter, input->filter.dst_addr, 2848 input->action, 0); 2849 2850 return 0; 2851 } 2852 2853 static int igb_update_ethtool_nfc_entry(struct igb_adapter *adapter, 2854 struct igb_nfc_filter *input, 2855 u16 sw_idx) 2856 { 2857 struct igb_nfc_filter *rule, *parent; 2858 int err = -EINVAL; 2859 2860 parent = NULL; 2861 rule = NULL; 2862 2863 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) { 2864 /* hash found, or no matching entry */ 2865 if (rule->sw_idx >= sw_idx) 2866 break; 2867 parent = rule; 2868 } 2869 2870 /* if there is an old rule occupying our place remove it */ 2871 if (rule && (rule->sw_idx == sw_idx)) { 2872 if (!input) 2873 err = igb_erase_filter(adapter, rule); 2874 2875 hlist_del(&rule->nfc_node); 2876 kfree(rule); 2877 adapter->nfc_filter_count--; 2878 } 2879 2880 /* If no input this was a delete, err should be 0 if a rule was 2881 * successfully found and removed from the list else -EINVAL 2882 */ 2883 if (!input) 2884 return err; 2885 2886 /* initialize node */ 2887 INIT_HLIST_NODE(&input->nfc_node); 2888 2889 /* add filter to the list */ 2890 if (parent) 2891 hlist_add_behind(&input->nfc_node, &parent->nfc_node); 2892 else 2893 hlist_add_head(&input->nfc_node, &adapter->nfc_filter_list); 2894 2895 /* update counts */ 2896 adapter->nfc_filter_count++; 2897 2898 return 0; 2899 } 2900 2901 static int igb_add_ethtool_nfc_entry(struct igb_adapter *adapter, 2902 struct ethtool_rxnfc *cmd) 2903 { 2904 struct net_device *netdev = adapter->netdev; 2905 struct ethtool_rx_flow_spec *fsp = 2906 (struct ethtool_rx_flow_spec *)&cmd->fs; 2907 struct igb_nfc_filter *input, *rule; 2908 int err = 0; 2909 2910 if (!(netdev->hw_features & NETIF_F_NTUPLE)) 2911 return -EOPNOTSUPP; 2912 2913 /* Don't allow programming if the action is a queue greater than 2914 * the number of online Rx queues. 2915 */ 2916 if ((fsp->ring_cookie == RX_CLS_FLOW_DISC) || 2917 (fsp->ring_cookie >= adapter->num_rx_queues)) { 2918 dev_err(&adapter->pdev->dev, "ethtool -N: The specified action is invalid\n"); 2919 return -EINVAL; 2920 } 2921 2922 /* Don't allow indexes to exist outside of available space */ 2923 if (fsp->location >= IGB_MAX_RXNFC_FILTERS) { 2924 dev_err(&adapter->pdev->dev, "Location out of range\n"); 2925 return -EINVAL; 2926 } 2927 2928 if ((fsp->flow_type & ~FLOW_EXT) != ETHER_FLOW) 2929 return -EINVAL; 2930 2931 input = kzalloc(sizeof(*input), GFP_KERNEL); 2932 if (!input) 2933 return -ENOMEM; 2934 2935 if (fsp->m_u.ether_spec.h_proto == ETHER_TYPE_FULL_MASK) { 2936 input->filter.etype = fsp->h_u.ether_spec.h_proto; 2937 input->filter.match_flags = IGB_FILTER_FLAG_ETHER_TYPE; 2938 } 2939 2940 /* Only support matching addresses by the full mask */ 2941 if (is_broadcast_ether_addr(fsp->m_u.ether_spec.h_source)) { 2942 input->filter.match_flags |= IGB_FILTER_FLAG_SRC_MAC_ADDR; 2943 ether_addr_copy(input->filter.src_addr, 2944 fsp->h_u.ether_spec.h_source); 2945 } 2946 2947 /* Only support matching addresses by the full mask */ 2948 if (is_broadcast_ether_addr(fsp->m_u.ether_spec.h_dest)) { 2949 input->filter.match_flags |= IGB_FILTER_FLAG_DST_MAC_ADDR; 2950 ether_addr_copy(input->filter.dst_addr, 2951 fsp->h_u.ether_spec.h_dest); 2952 } 2953 2954 if ((fsp->flow_type & FLOW_EXT) && fsp->m_ext.vlan_tci) { 2955 if (fsp->m_ext.vlan_tci != htons(VLAN_PRIO_MASK)) { 2956 err = -EINVAL; 2957 goto err_out; 2958 } 2959 input->filter.vlan_tci = fsp->h_ext.vlan_tci; 2960 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI; 2961 } 2962 2963 input->action = fsp->ring_cookie; 2964 input->sw_idx = fsp->location; 2965 2966 spin_lock(&adapter->nfc_lock); 2967 2968 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) { 2969 if (!memcmp(&input->filter, &rule->filter, 2970 sizeof(input->filter))) { 2971 err = -EEXIST; 2972 dev_err(&adapter->pdev->dev, 2973 "ethtool: this filter is already set\n"); 2974 goto err_out_w_lock; 2975 } 2976 } 2977 2978 err = igb_add_filter(adapter, input); 2979 if (err) 2980 goto err_out_w_lock; 2981 2982 igb_update_ethtool_nfc_entry(adapter, input, input->sw_idx); 2983 2984 spin_unlock(&adapter->nfc_lock); 2985 return 0; 2986 2987 err_out_w_lock: 2988 spin_unlock(&adapter->nfc_lock); 2989 err_out: 2990 kfree(input); 2991 return err; 2992 } 2993 2994 static int igb_del_ethtool_nfc_entry(struct igb_adapter *adapter, 2995 struct ethtool_rxnfc *cmd) 2996 { 2997 struct ethtool_rx_flow_spec *fsp = 2998 (struct ethtool_rx_flow_spec *)&cmd->fs; 2999 int err; 3000 3001 spin_lock(&adapter->nfc_lock); 3002 err = igb_update_ethtool_nfc_entry(adapter, NULL, fsp->location); 3003 spin_unlock(&adapter->nfc_lock); 3004 3005 return err; 3006 } 3007 3008 static int igb_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 3009 { 3010 struct igb_adapter *adapter = netdev_priv(dev); 3011 int ret = -EOPNOTSUPP; 3012 3013 switch (cmd->cmd) { 3014 case ETHTOOL_SRXFH: 3015 ret = igb_set_rss_hash_opt(adapter, cmd); 3016 break; 3017 case ETHTOOL_SRXCLSRLINS: 3018 ret = igb_add_ethtool_nfc_entry(adapter, cmd); 3019 break; 3020 case ETHTOOL_SRXCLSRLDEL: 3021 ret = igb_del_ethtool_nfc_entry(adapter, cmd); 3022 default: 3023 break; 3024 } 3025 3026 return ret; 3027 } 3028 3029 static int igb_get_eee(struct net_device *netdev, struct ethtool_eee *edata) 3030 { 3031 struct igb_adapter *adapter = netdev_priv(netdev); 3032 struct e1000_hw *hw = &adapter->hw; 3033 u32 ret_val; 3034 u16 phy_data; 3035 3036 if ((hw->mac.type < e1000_i350) || 3037 (hw->phy.media_type != e1000_media_type_copper)) 3038 return -EOPNOTSUPP; 3039 3040 edata->supported = (SUPPORTED_1000baseT_Full | 3041 SUPPORTED_100baseT_Full); 3042 if (!hw->dev_spec._82575.eee_disable) 3043 edata->advertised = 3044 mmd_eee_adv_to_ethtool_adv_t(adapter->eee_advert); 3045 3046 /* The IPCNFG and EEER registers are not supported on I354. */ 3047 if (hw->mac.type == e1000_i354) { 3048 igb_get_eee_status_i354(hw, (bool *)&edata->eee_active); 3049 } else { 3050 u32 eeer; 3051 3052 eeer = rd32(E1000_EEER); 3053 3054 /* EEE status on negotiated link */ 3055 if (eeer & E1000_EEER_EEE_NEG) 3056 edata->eee_active = true; 3057 3058 if (eeer & E1000_EEER_TX_LPI_EN) 3059 edata->tx_lpi_enabled = true; 3060 } 3061 3062 /* EEE Link Partner Advertised */ 3063 switch (hw->mac.type) { 3064 case e1000_i350: 3065 ret_val = igb_read_emi_reg(hw, E1000_EEE_LP_ADV_ADDR_I350, 3066 &phy_data); 3067 if (ret_val) 3068 return -ENODATA; 3069 3070 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data); 3071 break; 3072 case e1000_i354: 3073 case e1000_i210: 3074 case e1000_i211: 3075 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_LP_ADV_ADDR_I210, 3076 E1000_EEE_LP_ADV_DEV_I210, 3077 &phy_data); 3078 if (ret_val) 3079 return -ENODATA; 3080 3081 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data); 3082 3083 break; 3084 default: 3085 break; 3086 } 3087 3088 edata->eee_enabled = !hw->dev_spec._82575.eee_disable; 3089 3090 if ((hw->mac.type == e1000_i354) && 3091 (edata->eee_enabled)) 3092 edata->tx_lpi_enabled = true; 3093 3094 /* Report correct negotiated EEE status for devices that 3095 * wrongly report EEE at half-duplex 3096 */ 3097 if (adapter->link_duplex == HALF_DUPLEX) { 3098 edata->eee_enabled = false; 3099 edata->eee_active = false; 3100 edata->tx_lpi_enabled = false; 3101 edata->advertised &= ~edata->advertised; 3102 } 3103 3104 return 0; 3105 } 3106 3107 static int igb_set_eee(struct net_device *netdev, 3108 struct ethtool_eee *edata) 3109 { 3110 struct igb_adapter *adapter = netdev_priv(netdev); 3111 struct e1000_hw *hw = &adapter->hw; 3112 struct ethtool_eee eee_curr; 3113 bool adv1g_eee = true, adv100m_eee = true; 3114 s32 ret_val; 3115 3116 if ((hw->mac.type < e1000_i350) || 3117 (hw->phy.media_type != e1000_media_type_copper)) 3118 return -EOPNOTSUPP; 3119 3120 memset(&eee_curr, 0, sizeof(struct ethtool_eee)); 3121 3122 ret_val = igb_get_eee(netdev, &eee_curr); 3123 if (ret_val) 3124 return ret_val; 3125 3126 if (eee_curr.eee_enabled) { 3127 if (eee_curr.tx_lpi_enabled != edata->tx_lpi_enabled) { 3128 dev_err(&adapter->pdev->dev, 3129 "Setting EEE tx-lpi is not supported\n"); 3130 return -EINVAL; 3131 } 3132 3133 /* Tx LPI timer is not implemented currently */ 3134 if (edata->tx_lpi_timer) { 3135 dev_err(&adapter->pdev->dev, 3136 "Setting EEE Tx LPI timer is not supported\n"); 3137 return -EINVAL; 3138 } 3139 3140 if (!edata->advertised || (edata->advertised & 3141 ~(ADVERTISE_100_FULL | ADVERTISE_1000_FULL))) { 3142 dev_err(&adapter->pdev->dev, 3143 "EEE Advertisement supports only 100Tx and/or 100T full duplex\n"); 3144 return -EINVAL; 3145 } 3146 adv100m_eee = !!(edata->advertised & ADVERTISE_100_FULL); 3147 adv1g_eee = !!(edata->advertised & ADVERTISE_1000_FULL); 3148 3149 } else if (!edata->eee_enabled) { 3150 dev_err(&adapter->pdev->dev, 3151 "Setting EEE options are not supported with EEE disabled\n"); 3152 return -EINVAL; 3153 } 3154 3155 adapter->eee_advert = ethtool_adv_to_mmd_eee_adv_t(edata->advertised); 3156 if (hw->dev_spec._82575.eee_disable != !edata->eee_enabled) { 3157 hw->dev_spec._82575.eee_disable = !edata->eee_enabled; 3158 adapter->flags |= IGB_FLAG_EEE; 3159 3160 /* reset link */ 3161 if (netif_running(netdev)) 3162 igb_reinit_locked(adapter); 3163 else 3164 igb_reset(adapter); 3165 } 3166 3167 if (hw->mac.type == e1000_i354) 3168 ret_val = igb_set_eee_i354(hw, adv1g_eee, adv100m_eee); 3169 else 3170 ret_val = igb_set_eee_i350(hw, adv1g_eee, adv100m_eee); 3171 3172 if (ret_val) { 3173 dev_err(&adapter->pdev->dev, 3174 "Problem setting EEE advertisement options\n"); 3175 return -EINVAL; 3176 } 3177 3178 return 0; 3179 } 3180 3181 static int igb_get_module_info(struct net_device *netdev, 3182 struct ethtool_modinfo *modinfo) 3183 { 3184 struct igb_adapter *adapter = netdev_priv(netdev); 3185 struct e1000_hw *hw = &adapter->hw; 3186 u32 status = 0; 3187 u16 sff8472_rev, addr_mode; 3188 bool page_swap = false; 3189 3190 if ((hw->phy.media_type == e1000_media_type_copper) || 3191 (hw->phy.media_type == e1000_media_type_unknown)) 3192 return -EOPNOTSUPP; 3193 3194 /* Check whether we support SFF-8472 or not */ 3195 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev); 3196 if (status) 3197 return -EIO; 3198 3199 /* addressing mode is not supported */ 3200 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode); 3201 if (status) 3202 return -EIO; 3203 3204 /* addressing mode is not supported */ 3205 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) { 3206 hw_dbg("Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n"); 3207 page_swap = true; 3208 } 3209 3210 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) { 3211 /* We have an SFP, but it does not support SFF-8472 */ 3212 modinfo->type = ETH_MODULE_SFF_8079; 3213 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 3214 } else { 3215 /* We have an SFP which supports a revision of SFF-8472 */ 3216 modinfo->type = ETH_MODULE_SFF_8472; 3217 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 3218 } 3219 3220 return 0; 3221 } 3222 3223 static int igb_get_module_eeprom(struct net_device *netdev, 3224 struct ethtool_eeprom *ee, u8 *data) 3225 { 3226 struct igb_adapter *adapter = netdev_priv(netdev); 3227 struct e1000_hw *hw = &adapter->hw; 3228 u32 status = 0; 3229 u16 *dataword; 3230 u16 first_word, last_word; 3231 int i = 0; 3232 3233 if (ee->len == 0) 3234 return -EINVAL; 3235 3236 first_word = ee->offset >> 1; 3237 last_word = (ee->offset + ee->len - 1) >> 1; 3238 3239 dataword = kmalloc_array(last_word - first_word + 1, sizeof(u16), 3240 GFP_KERNEL); 3241 if (!dataword) 3242 return -ENOMEM; 3243 3244 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */ 3245 for (i = 0; i < last_word - first_word + 1; i++) { 3246 status = igb_read_phy_reg_i2c(hw, (first_word + i) * 2, 3247 &dataword[i]); 3248 if (status) { 3249 /* Error occurred while reading module */ 3250 kfree(dataword); 3251 return -EIO; 3252 } 3253 3254 be16_to_cpus(&dataword[i]); 3255 } 3256 3257 memcpy(data, (u8 *)dataword + (ee->offset & 1), ee->len); 3258 kfree(dataword); 3259 3260 return 0; 3261 } 3262 3263 static int igb_ethtool_begin(struct net_device *netdev) 3264 { 3265 struct igb_adapter *adapter = netdev_priv(netdev); 3266 pm_runtime_get_sync(&adapter->pdev->dev); 3267 return 0; 3268 } 3269 3270 static void igb_ethtool_complete(struct net_device *netdev) 3271 { 3272 struct igb_adapter *adapter = netdev_priv(netdev); 3273 pm_runtime_put(&adapter->pdev->dev); 3274 } 3275 3276 static u32 igb_get_rxfh_indir_size(struct net_device *netdev) 3277 { 3278 return IGB_RETA_SIZE; 3279 } 3280 3281 static int igb_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, 3282 u8 *hfunc) 3283 { 3284 struct igb_adapter *adapter = netdev_priv(netdev); 3285 int i; 3286 3287 if (hfunc) 3288 *hfunc = ETH_RSS_HASH_TOP; 3289 if (!indir) 3290 return 0; 3291 for (i = 0; i < IGB_RETA_SIZE; i++) 3292 indir[i] = adapter->rss_indir_tbl[i]; 3293 3294 return 0; 3295 } 3296 3297 void igb_write_rss_indir_tbl(struct igb_adapter *adapter) 3298 { 3299 struct e1000_hw *hw = &adapter->hw; 3300 u32 reg = E1000_RETA(0); 3301 u32 shift = 0; 3302 int i = 0; 3303 3304 switch (hw->mac.type) { 3305 case e1000_82575: 3306 shift = 6; 3307 break; 3308 case e1000_82576: 3309 /* 82576 supports 2 RSS queues for SR-IOV */ 3310 if (adapter->vfs_allocated_count) 3311 shift = 3; 3312 break; 3313 default: 3314 break; 3315 } 3316 3317 while (i < IGB_RETA_SIZE) { 3318 u32 val = 0; 3319 int j; 3320 3321 for (j = 3; j >= 0; j--) { 3322 val <<= 8; 3323 val |= adapter->rss_indir_tbl[i + j]; 3324 } 3325 3326 wr32(reg, val << shift); 3327 reg += 4; 3328 i += 4; 3329 } 3330 } 3331 3332 static int igb_set_rxfh(struct net_device *netdev, const u32 *indir, 3333 const u8 *key, const u8 hfunc) 3334 { 3335 struct igb_adapter *adapter = netdev_priv(netdev); 3336 struct e1000_hw *hw = &adapter->hw; 3337 int i; 3338 u32 num_queues; 3339 3340 /* We do not allow change in unsupported parameters */ 3341 if (key || 3342 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) 3343 return -EOPNOTSUPP; 3344 if (!indir) 3345 return 0; 3346 3347 num_queues = adapter->rss_queues; 3348 3349 switch (hw->mac.type) { 3350 case e1000_82576: 3351 /* 82576 supports 2 RSS queues for SR-IOV */ 3352 if (adapter->vfs_allocated_count) 3353 num_queues = 2; 3354 break; 3355 default: 3356 break; 3357 } 3358 3359 /* Verify user input. */ 3360 for (i = 0; i < IGB_RETA_SIZE; i++) 3361 if (indir[i] >= num_queues) 3362 return -EINVAL; 3363 3364 3365 for (i = 0; i < IGB_RETA_SIZE; i++) 3366 adapter->rss_indir_tbl[i] = indir[i]; 3367 3368 igb_write_rss_indir_tbl(adapter); 3369 3370 return 0; 3371 } 3372 3373 static unsigned int igb_max_channels(struct igb_adapter *adapter) 3374 { 3375 return igb_get_max_rss_queues(adapter); 3376 } 3377 3378 static void igb_get_channels(struct net_device *netdev, 3379 struct ethtool_channels *ch) 3380 { 3381 struct igb_adapter *adapter = netdev_priv(netdev); 3382 3383 /* Report maximum channels */ 3384 ch->max_combined = igb_max_channels(adapter); 3385 3386 /* Report info for other vector */ 3387 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 3388 ch->max_other = NON_Q_VECTORS; 3389 ch->other_count = NON_Q_VECTORS; 3390 } 3391 3392 ch->combined_count = adapter->rss_queues; 3393 } 3394 3395 static int igb_set_channels(struct net_device *netdev, 3396 struct ethtool_channels *ch) 3397 { 3398 struct igb_adapter *adapter = netdev_priv(netdev); 3399 unsigned int count = ch->combined_count; 3400 unsigned int max_combined = 0; 3401 3402 /* Verify they are not requesting separate vectors */ 3403 if (!count || ch->rx_count || ch->tx_count) 3404 return -EINVAL; 3405 3406 /* Verify other_count is valid and has not been changed */ 3407 if (ch->other_count != NON_Q_VECTORS) 3408 return -EINVAL; 3409 3410 /* Verify the number of channels doesn't exceed hw limits */ 3411 max_combined = igb_max_channels(adapter); 3412 if (count > max_combined) 3413 return -EINVAL; 3414 3415 if (count != adapter->rss_queues) { 3416 adapter->rss_queues = count; 3417 igb_set_flag_queue_pairs(adapter, max_combined); 3418 3419 /* Hardware has to reinitialize queues and interrupts to 3420 * match the new configuration. 3421 */ 3422 return igb_reinit_queues(adapter); 3423 } 3424 3425 return 0; 3426 } 3427 3428 static u32 igb_get_priv_flags(struct net_device *netdev) 3429 { 3430 struct igb_adapter *adapter = netdev_priv(netdev); 3431 u32 priv_flags = 0; 3432 3433 if (adapter->flags & IGB_FLAG_RX_LEGACY) 3434 priv_flags |= IGB_PRIV_FLAGS_LEGACY_RX; 3435 3436 return priv_flags; 3437 } 3438 3439 static int igb_set_priv_flags(struct net_device *netdev, u32 priv_flags) 3440 { 3441 struct igb_adapter *adapter = netdev_priv(netdev); 3442 unsigned int flags = adapter->flags; 3443 3444 flags &= ~IGB_FLAG_RX_LEGACY; 3445 if (priv_flags & IGB_PRIV_FLAGS_LEGACY_RX) 3446 flags |= IGB_FLAG_RX_LEGACY; 3447 3448 if (flags != adapter->flags) { 3449 adapter->flags = flags; 3450 3451 /* reset interface to repopulate queues */ 3452 if (netif_running(netdev)) 3453 igb_reinit_locked(adapter); 3454 } 3455 3456 return 0; 3457 } 3458 3459 static const struct ethtool_ops igb_ethtool_ops = { 3460 .supported_coalesce_params = ETHTOOL_COALESCE_USECS, 3461 .get_drvinfo = igb_get_drvinfo, 3462 .get_regs_len = igb_get_regs_len, 3463 .get_regs = igb_get_regs, 3464 .get_wol = igb_get_wol, 3465 .set_wol = igb_set_wol, 3466 .get_msglevel = igb_get_msglevel, 3467 .set_msglevel = igb_set_msglevel, 3468 .nway_reset = igb_nway_reset, 3469 .get_link = igb_get_link, 3470 .get_eeprom_len = igb_get_eeprom_len, 3471 .get_eeprom = igb_get_eeprom, 3472 .set_eeprom = igb_set_eeprom, 3473 .get_ringparam = igb_get_ringparam, 3474 .set_ringparam = igb_set_ringparam, 3475 .get_pauseparam = igb_get_pauseparam, 3476 .set_pauseparam = igb_set_pauseparam, 3477 .self_test = igb_diag_test, 3478 .get_strings = igb_get_strings, 3479 .set_phys_id = igb_set_phys_id, 3480 .get_sset_count = igb_get_sset_count, 3481 .get_ethtool_stats = igb_get_ethtool_stats, 3482 .get_coalesce = igb_get_coalesce, 3483 .set_coalesce = igb_set_coalesce, 3484 .get_ts_info = igb_get_ts_info, 3485 .get_rxnfc = igb_get_rxnfc, 3486 .set_rxnfc = igb_set_rxnfc, 3487 .get_eee = igb_get_eee, 3488 .set_eee = igb_set_eee, 3489 .get_module_info = igb_get_module_info, 3490 .get_module_eeprom = igb_get_module_eeprom, 3491 .get_rxfh_indir_size = igb_get_rxfh_indir_size, 3492 .get_rxfh = igb_get_rxfh, 3493 .set_rxfh = igb_set_rxfh, 3494 .get_channels = igb_get_channels, 3495 .set_channels = igb_set_channels, 3496 .get_priv_flags = igb_get_priv_flags, 3497 .set_priv_flags = igb_set_priv_flags, 3498 .begin = igb_ethtool_begin, 3499 .complete = igb_ethtool_complete, 3500 .get_link_ksettings = igb_get_link_ksettings, 3501 .set_link_ksettings = igb_set_link_ksettings, 3502 }; 3503 3504 void igb_set_ethtool_ops(struct net_device *netdev) 3505 { 3506 netdev->ethtool_ops = &igb_ethtool_ops; 3507 } 3508