1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com 4 * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/device.h> 9 #include <linux/gpio/consumer.h> 10 #include <linux/i2c.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/regmap.h> 14 #include <linux/regulator/consumer.h> 15 #include <linux/slab.h> 16 17 #include <drm/drm_atomic_helper.h> 18 #include <drm/drm_crtc_helper.h> 19 #include <drm/drm_drv.h> 20 #include <drm/drm_mipi_dsi.h> 21 #include <drm/drm_of.h> 22 #include <drm/drm_panel.h> 23 #include <video/mipi_display.h> 24 #include <video/videomode.h> 25 26 /* Global (16-bit addressable) */ 27 #define TC358768_CHIPID 0x0000 28 #define TC358768_SYSCTL 0x0002 29 #define TC358768_CONFCTL 0x0004 30 #define TC358768_VSDLY 0x0006 31 #define TC358768_DATAFMT 0x0008 32 #define TC358768_GPIOEN 0x000E 33 #define TC358768_GPIODIR 0x0010 34 #define TC358768_GPIOIN 0x0012 35 #define TC358768_GPIOOUT 0x0014 36 #define TC358768_PLLCTL0 0x0016 37 #define TC358768_PLLCTL1 0x0018 38 #define TC358768_CMDBYTE 0x0022 39 #define TC358768_PP_MISC 0x0032 40 #define TC358768_DSITX_DT 0x0050 41 #define TC358768_FIFOSTATUS 0x00F8 42 43 /* Debug (16-bit addressable) */ 44 #define TC358768_VBUFCTRL 0x00E0 45 #define TC358768_DBG_WIDTH 0x00E2 46 #define TC358768_DBG_VBLANK 0x00E4 47 #define TC358768_DBG_DATA 0x00E8 48 49 /* TX PHY (32-bit addressable) */ 50 #define TC358768_CLW_DPHYCONTTX 0x0100 51 #define TC358768_D0W_DPHYCONTTX 0x0104 52 #define TC358768_D1W_DPHYCONTTX 0x0108 53 #define TC358768_D2W_DPHYCONTTX 0x010C 54 #define TC358768_D3W_DPHYCONTTX 0x0110 55 #define TC358768_CLW_CNTRL 0x0140 56 #define TC358768_D0W_CNTRL 0x0144 57 #define TC358768_D1W_CNTRL 0x0148 58 #define TC358768_D2W_CNTRL 0x014C 59 #define TC358768_D3W_CNTRL 0x0150 60 61 /* TX PPI (32-bit addressable) */ 62 #define TC358768_STARTCNTRL 0x0204 63 #define TC358768_DSITXSTATUS 0x0208 64 #define TC358768_LINEINITCNT 0x0210 65 #define TC358768_LPTXTIMECNT 0x0214 66 #define TC358768_TCLK_HEADERCNT 0x0218 67 #define TC358768_TCLK_TRAILCNT 0x021C 68 #define TC358768_THS_HEADERCNT 0x0220 69 #define TC358768_TWAKEUP 0x0224 70 #define TC358768_TCLK_POSTCNT 0x0228 71 #define TC358768_THS_TRAILCNT 0x022C 72 #define TC358768_HSTXVREGCNT 0x0230 73 #define TC358768_HSTXVREGEN 0x0234 74 #define TC358768_TXOPTIONCNTRL 0x0238 75 #define TC358768_BTACNTRL1 0x023C 76 77 /* TX CTRL (32-bit addressable) */ 78 #define TC358768_DSI_CONTROL 0x040C 79 #define TC358768_DSI_STATUS 0x0410 80 #define TC358768_DSI_INT 0x0414 81 #define TC358768_DSI_INT_ENA 0x0418 82 #define TC358768_DSICMD_RDFIFO 0x0430 83 #define TC358768_DSI_ACKERR 0x0434 84 #define TC358768_DSI_ACKERR_INTENA 0x0438 85 #define TC358768_DSI_ACKERR_HALT 0x043c 86 #define TC358768_DSI_RXERR 0x0440 87 #define TC358768_DSI_RXERR_INTENA 0x0444 88 #define TC358768_DSI_RXERR_HALT 0x0448 89 #define TC358768_DSI_ERR 0x044C 90 #define TC358768_DSI_ERR_INTENA 0x0450 91 #define TC358768_DSI_ERR_HALT 0x0454 92 #define TC358768_DSI_CONFW 0x0500 93 #define TC358768_DSI_LPCMD 0x0500 94 #define TC358768_DSI_RESET 0x0504 95 #define TC358768_DSI_INT_CLR 0x050C 96 #define TC358768_DSI_START 0x0518 97 98 /* DSITX CTRL (16-bit addressable) */ 99 #define TC358768_DSICMD_TX 0x0600 100 #define TC358768_DSICMD_TYPE 0x0602 101 #define TC358768_DSICMD_WC 0x0604 102 #define TC358768_DSICMD_WD0 0x0610 103 #define TC358768_DSICMD_WD1 0x0612 104 #define TC358768_DSICMD_WD2 0x0614 105 #define TC358768_DSICMD_WD3 0x0616 106 #define TC358768_DSI_EVENT 0x0620 107 #define TC358768_DSI_VSW 0x0622 108 #define TC358768_DSI_VBPR 0x0624 109 #define TC358768_DSI_VACT 0x0626 110 #define TC358768_DSI_HSW 0x0628 111 #define TC358768_DSI_HBPR 0x062A 112 #define TC358768_DSI_HACT 0x062C 113 114 /* TC358768_DSI_CONTROL (0x040C) register */ 115 #define TC358768_DSI_CONTROL_DIS_MODE BIT(15) 116 #define TC358768_DSI_CONTROL_TXMD BIT(7) 117 #define TC358768_DSI_CONTROL_HSCKMD BIT(5) 118 #define TC358768_DSI_CONTROL_EOTDIS BIT(0) 119 120 /* TC358768_DSI_CONFW (0x0500) register */ 121 #define TC358768_DSI_CONFW_MODE_SET (5 << 29) 122 #define TC358768_DSI_CONFW_MODE_CLR (6 << 29) 123 #define TC358768_DSI_CONFW_ADDR_DSI_CONTROL (0x3 << 24) 124 125 static const char * const tc358768_supplies[] = { 126 "vddc", "vddmipi", "vddio" 127 }; 128 129 struct tc358768_dsi_output { 130 struct mipi_dsi_device *dev; 131 struct drm_panel *panel; 132 struct drm_bridge *bridge; 133 }; 134 135 struct tc358768_priv { 136 struct device *dev; 137 struct regmap *regmap; 138 struct gpio_desc *reset_gpio; 139 struct regulator_bulk_data supplies[ARRAY_SIZE(tc358768_supplies)]; 140 struct clk *refclk; 141 int enabled; 142 int error; 143 144 struct mipi_dsi_host dsi_host; 145 struct drm_bridge bridge; 146 struct tc358768_dsi_output output; 147 148 u32 pd_lines; /* number of Parallel Port Input Data Lines */ 149 u32 dsi_lanes; /* number of DSI Lanes */ 150 151 /* Parameters for PLL programming */ 152 u32 fbd; /* PLL feedback divider */ 153 u32 prd; /* PLL input divider */ 154 u32 frs; /* PLL Freqency range for HSCK (post divider) */ 155 156 u32 dsiclk; /* pll_clk / 2 */ 157 }; 158 159 static inline struct tc358768_priv *dsi_host_to_tc358768(struct mipi_dsi_host 160 *host) 161 { 162 return container_of(host, struct tc358768_priv, dsi_host); 163 } 164 165 static inline struct tc358768_priv *bridge_to_tc358768(struct drm_bridge 166 *bridge) 167 { 168 return container_of(bridge, struct tc358768_priv, bridge); 169 } 170 171 static int tc358768_clear_error(struct tc358768_priv *priv) 172 { 173 int ret = priv->error; 174 175 priv->error = 0; 176 return ret; 177 } 178 179 static void tc358768_write(struct tc358768_priv *priv, u32 reg, u32 val) 180 { 181 /* work around https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */ 182 int tmpval = val; 183 size_t count = 2; 184 185 if (priv->error) 186 return; 187 188 /* 16-bit register? */ 189 if (reg < 0x100 || reg >= 0x600) 190 count = 1; 191 192 priv->error = regmap_bulk_write(priv->regmap, reg, &tmpval, count); 193 } 194 195 static void tc358768_read(struct tc358768_priv *priv, u32 reg, u32 *val) 196 { 197 size_t count = 2; 198 199 if (priv->error) 200 return; 201 202 /* 16-bit register? */ 203 if (reg < 0x100 || reg >= 0x600) { 204 *val = 0; 205 count = 1; 206 } 207 208 priv->error = regmap_bulk_read(priv->regmap, reg, val, count); 209 } 210 211 static void tc358768_update_bits(struct tc358768_priv *priv, u32 reg, u32 mask, 212 u32 val) 213 { 214 u32 tmp, orig; 215 216 tc358768_read(priv, reg, &orig); 217 tmp = orig & ~mask; 218 tmp |= val & mask; 219 if (tmp != orig) 220 tc358768_write(priv, reg, tmp); 221 } 222 223 static int tc358768_sw_reset(struct tc358768_priv *priv) 224 { 225 /* Assert Reset */ 226 tc358768_write(priv, TC358768_SYSCTL, 1); 227 /* Release Reset, Exit Sleep */ 228 tc358768_write(priv, TC358768_SYSCTL, 0); 229 230 return tc358768_clear_error(priv); 231 } 232 233 static void tc358768_hw_enable(struct tc358768_priv *priv) 234 { 235 int ret; 236 237 if (priv->enabled) 238 return; 239 240 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies); 241 if (ret < 0) 242 dev_err(priv->dev, "error enabling regulators (%d)\n", ret); 243 244 if (priv->reset_gpio) 245 usleep_range(200, 300); 246 247 /* 248 * The RESX is active low (GPIO_ACTIVE_LOW). 249 * DEASSERT (value = 0) the reset_gpio to enable the chip 250 */ 251 gpiod_set_value_cansleep(priv->reset_gpio, 0); 252 253 /* wait for encoder clocks to stabilize */ 254 usleep_range(1000, 2000); 255 256 priv->enabled = true; 257 } 258 259 static void tc358768_hw_disable(struct tc358768_priv *priv) 260 { 261 int ret; 262 263 if (!priv->enabled) 264 return; 265 266 /* 267 * The RESX is active low (GPIO_ACTIVE_LOW). 268 * ASSERT (value = 1) the reset_gpio to disable the chip 269 */ 270 gpiod_set_value_cansleep(priv->reset_gpio, 1); 271 272 ret = regulator_bulk_disable(ARRAY_SIZE(priv->supplies), 273 priv->supplies); 274 if (ret < 0) 275 dev_err(priv->dev, "error disabling regulators (%d)\n", ret); 276 277 priv->enabled = false; 278 } 279 280 static u32 tc358768_pll_to_pclk(struct tc358768_priv *priv, u32 pll_clk) 281 { 282 return (u32)div_u64((u64)pll_clk * priv->dsi_lanes, priv->pd_lines); 283 } 284 285 static u32 tc358768_pclk_to_pll(struct tc358768_priv *priv, u32 pclk) 286 { 287 return (u32)div_u64((u64)pclk * priv->pd_lines, priv->dsi_lanes); 288 } 289 290 static int tc358768_calc_pll(struct tc358768_priv *priv, 291 const struct drm_display_mode *mode, 292 bool verify_only) 293 { 294 const u32 frs_limits[] = { 295 1000000000, 296 500000000, 297 250000000, 298 125000000, 299 62500000 300 }; 301 unsigned long refclk; 302 u32 prd, target_pll, i, max_pll, min_pll; 303 u32 frs, best_diff, best_pll, best_prd, best_fbd; 304 305 target_pll = tc358768_pclk_to_pll(priv, mode->clock * 1000); 306 307 /* pll_clk = RefClk * [(FBD + 1)/ (PRD + 1)] * [1 / (2^FRS)] */ 308 309 for (i = 0; i < ARRAY_SIZE(frs_limits); i++) 310 if (target_pll >= frs_limits[i]) 311 break; 312 313 if (i == ARRAY_SIZE(frs_limits) || i == 0) 314 return -EINVAL; 315 316 frs = i - 1; 317 max_pll = frs_limits[i - 1]; 318 min_pll = frs_limits[i]; 319 320 refclk = clk_get_rate(priv->refclk); 321 322 best_diff = UINT_MAX; 323 best_pll = 0; 324 best_prd = 0; 325 best_fbd = 0; 326 327 for (prd = 0; prd < 16; ++prd) { 328 u32 divisor = (prd + 1) * (1 << frs); 329 u32 fbd; 330 331 for (fbd = 0; fbd < 512; ++fbd) { 332 u32 pll, diff; 333 334 pll = (u32)div_u64((u64)refclk * (fbd + 1), divisor); 335 336 if (pll >= max_pll || pll < min_pll) 337 continue; 338 339 diff = max(pll, target_pll) - min(pll, target_pll); 340 341 if (diff < best_diff) { 342 best_diff = diff; 343 best_pll = pll; 344 best_prd = prd; 345 best_fbd = fbd; 346 347 if (best_diff == 0) 348 goto found; 349 } 350 } 351 } 352 353 if (best_diff == UINT_MAX) { 354 dev_err(priv->dev, "could not find suitable PLL setup\n"); 355 return -EINVAL; 356 } 357 358 found: 359 if (verify_only) 360 return 0; 361 362 priv->fbd = best_fbd; 363 priv->prd = best_prd; 364 priv->frs = frs; 365 priv->dsiclk = best_pll / 2; 366 367 return 0; 368 } 369 370 static int tc358768_dsi_host_attach(struct mipi_dsi_host *host, 371 struct mipi_dsi_device *dev) 372 { 373 struct tc358768_priv *priv = dsi_host_to_tc358768(host); 374 struct drm_bridge *bridge; 375 struct drm_panel *panel; 376 struct device_node *ep; 377 int ret; 378 379 if (dev->lanes > 4) { 380 dev_err(priv->dev, "unsupported number of data lanes(%u)\n", 381 dev->lanes); 382 return -EINVAL; 383 } 384 385 /* 386 * tc358768 supports both Video and Pulse mode, but the driver only 387 * implements Video (event) mode currently 388 */ 389 if (!(dev->mode_flags & MIPI_DSI_MODE_VIDEO)) { 390 dev_err(priv->dev, "Only MIPI_DSI_MODE_VIDEO is supported\n"); 391 return -ENOTSUPP; 392 } 393 394 /* 395 * tc358768 supports RGB888, RGB666, RGB666_PACKED and RGB565, but only 396 * RGB888 is verified. 397 */ 398 if (dev->format != MIPI_DSI_FMT_RGB888) { 399 dev_warn(priv->dev, "Only MIPI_DSI_FMT_RGB888 tested!\n"); 400 return -ENOTSUPP; 401 } 402 403 ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0, &panel, 404 &bridge); 405 if (ret) 406 return ret; 407 408 if (panel) { 409 bridge = drm_panel_bridge_add_typed(panel, 410 DRM_MODE_CONNECTOR_DSI); 411 if (IS_ERR(bridge)) 412 return PTR_ERR(bridge); 413 } 414 415 priv->output.dev = dev; 416 priv->output.bridge = bridge; 417 priv->output.panel = panel; 418 419 priv->dsi_lanes = dev->lanes; 420 421 /* get input ep (port0/endpoint0) */ 422 ret = -EINVAL; 423 ep = of_graph_get_endpoint_by_regs(host->dev->of_node, 0, 0); 424 if (ep) { 425 ret = of_property_read_u32(ep, "data-lines", &priv->pd_lines); 426 427 of_node_put(ep); 428 } 429 430 if (ret) 431 priv->pd_lines = mipi_dsi_pixel_format_to_bpp(dev->format); 432 433 drm_bridge_add(&priv->bridge); 434 435 return 0; 436 } 437 438 static int tc358768_dsi_host_detach(struct mipi_dsi_host *host, 439 struct mipi_dsi_device *dev) 440 { 441 struct tc358768_priv *priv = dsi_host_to_tc358768(host); 442 443 drm_bridge_remove(&priv->bridge); 444 if (priv->output.panel) 445 drm_panel_bridge_remove(priv->output.bridge); 446 447 return 0; 448 } 449 450 static ssize_t tc358768_dsi_host_transfer(struct mipi_dsi_host *host, 451 const struct mipi_dsi_msg *msg) 452 { 453 struct tc358768_priv *priv = dsi_host_to_tc358768(host); 454 struct mipi_dsi_packet packet; 455 int ret; 456 457 if (!priv->enabled) { 458 dev_err(priv->dev, "Bridge is not enabled\n"); 459 return -ENODEV; 460 } 461 462 if (msg->rx_len) { 463 dev_warn(priv->dev, "MIPI rx is not supported\n"); 464 return -ENOTSUPP; 465 } 466 467 if (msg->tx_len > 8) { 468 dev_warn(priv->dev, "Maximum 8 byte MIPI tx is supported\n"); 469 return -ENOTSUPP; 470 } 471 472 ret = mipi_dsi_create_packet(&packet, msg); 473 if (ret) 474 return ret; 475 476 if (mipi_dsi_packet_format_is_short(msg->type)) { 477 tc358768_write(priv, TC358768_DSICMD_TYPE, 478 (0x10 << 8) | (packet.header[0] & 0x3f)); 479 tc358768_write(priv, TC358768_DSICMD_WC, 0); 480 tc358768_write(priv, TC358768_DSICMD_WD0, 481 (packet.header[2] << 8) | packet.header[1]); 482 } else { 483 int i; 484 485 tc358768_write(priv, TC358768_DSICMD_TYPE, 486 (0x40 << 8) | (packet.header[0] & 0x3f)); 487 tc358768_write(priv, TC358768_DSICMD_WC, packet.payload_length); 488 for (i = 0; i < packet.payload_length; i += 2) { 489 u16 val = packet.payload[i]; 490 491 if (i + 1 < packet.payload_length) 492 val |= packet.payload[i + 1] << 8; 493 494 tc358768_write(priv, TC358768_DSICMD_WD0 + i, val); 495 } 496 } 497 498 /* start transfer */ 499 tc358768_write(priv, TC358768_DSICMD_TX, 1); 500 501 ret = tc358768_clear_error(priv); 502 if (ret) 503 dev_warn(priv->dev, "Software disable failed: %d\n", ret); 504 else 505 ret = packet.size; 506 507 return ret; 508 } 509 510 static const struct mipi_dsi_host_ops tc358768_dsi_host_ops = { 511 .attach = tc358768_dsi_host_attach, 512 .detach = tc358768_dsi_host_detach, 513 .transfer = tc358768_dsi_host_transfer, 514 }; 515 516 static int tc358768_bridge_attach(struct drm_bridge *bridge, 517 enum drm_bridge_attach_flags flags) 518 { 519 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 520 521 if (!drm_core_check_feature(bridge->dev, DRIVER_ATOMIC)) { 522 dev_err(priv->dev, "needs atomic updates support\n"); 523 return -ENOTSUPP; 524 } 525 526 return drm_bridge_attach(bridge->encoder, priv->output.bridge, bridge, 527 flags); 528 } 529 530 static enum drm_mode_status 531 tc358768_bridge_mode_valid(struct drm_bridge *bridge, 532 const struct drm_display_mode *mode) 533 { 534 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 535 536 if (tc358768_calc_pll(priv, mode, true)) 537 return MODE_CLOCK_RANGE; 538 539 return MODE_OK; 540 } 541 542 static void tc358768_bridge_disable(struct drm_bridge *bridge) 543 { 544 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 545 int ret; 546 547 /* set FrmStop */ 548 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(15), BIT(15)); 549 550 /* wait at least for one frame */ 551 msleep(50); 552 553 /* clear PP_en */ 554 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), 0); 555 556 /* set RstPtr */ 557 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(14), BIT(14)); 558 559 ret = tc358768_clear_error(priv); 560 if (ret) 561 dev_warn(priv->dev, "Software disable failed: %d\n", ret); 562 } 563 564 static void tc358768_bridge_post_disable(struct drm_bridge *bridge) 565 { 566 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 567 568 tc358768_hw_disable(priv); 569 } 570 571 static int tc358768_setup_pll(struct tc358768_priv *priv, 572 const struct drm_display_mode *mode) 573 { 574 u32 fbd, prd, frs; 575 int ret; 576 577 ret = tc358768_calc_pll(priv, mode, false); 578 if (ret) { 579 dev_err(priv->dev, "PLL calculation failed: %d\n", ret); 580 return ret; 581 } 582 583 fbd = priv->fbd; 584 prd = priv->prd; 585 frs = priv->frs; 586 587 dev_dbg(priv->dev, "PLL: refclk %lu, fbd %u, prd %u, frs %u\n", 588 clk_get_rate(priv->refclk), fbd, prd, frs); 589 dev_dbg(priv->dev, "PLL: pll_clk: %u, DSIClk %u, DSIByteClk %u\n", 590 priv->dsiclk * 2, priv->dsiclk, priv->dsiclk / 4); 591 dev_dbg(priv->dev, "PLL: pclk %u (panel: %u)\n", 592 tc358768_pll_to_pclk(priv, priv->dsiclk * 2), 593 mode->clock * 1000); 594 595 /* PRD[15:12] FBD[8:0] */ 596 tc358768_write(priv, TC358768_PLLCTL0, (prd << 12) | fbd); 597 598 /* FRS[11:10] LBWS[9:8] CKEN[4] RESETB[1] EN[0] */ 599 tc358768_write(priv, TC358768_PLLCTL1, 600 (frs << 10) | (0x2 << 8) | BIT(1) | BIT(0)); 601 602 /* wait for lock */ 603 usleep_range(1000, 2000); 604 605 /* FRS[11:10] LBWS[9:8] CKEN[4] PLL_CKEN[4] RESETB[1] EN[0] */ 606 tc358768_write(priv, TC358768_PLLCTL1, 607 (frs << 10) | (0x2 << 8) | BIT(4) | BIT(1) | BIT(0)); 608 609 return tc358768_clear_error(priv); 610 } 611 612 #define TC358768_PRECISION 1000 613 static u32 tc358768_ns_to_cnt(u32 ns, u32 period_nsk) 614 { 615 return (ns * TC358768_PRECISION + period_nsk) / period_nsk; 616 } 617 618 static u32 tc358768_to_ns(u32 nsk) 619 { 620 return (nsk / TC358768_PRECISION); 621 } 622 623 static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) 624 { 625 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 626 struct mipi_dsi_device *dsi_dev = priv->output.dev; 627 u32 val, val2, lptxcnt, hact, data_type; 628 const struct drm_display_mode *mode; 629 u32 dsibclk_nsk, dsiclk_nsk, ui_nsk, phy_delay_nsk; 630 u32 dsiclk, dsibclk; 631 int ret, i; 632 633 tc358768_hw_enable(priv); 634 635 ret = tc358768_sw_reset(priv); 636 if (ret) { 637 dev_err(priv->dev, "Software reset failed: %d\n", ret); 638 tc358768_hw_disable(priv); 639 return; 640 } 641 642 mode = &bridge->encoder->crtc->state->adjusted_mode; 643 ret = tc358768_setup_pll(priv, mode); 644 if (ret) { 645 dev_err(priv->dev, "PLL setup failed: %d\n", ret); 646 tc358768_hw_disable(priv); 647 return; 648 } 649 650 dsiclk = priv->dsiclk; 651 dsibclk = dsiclk / 4; 652 653 /* Data Format Control Register */ 654 val = BIT(2) | BIT(1) | BIT(0); /* rdswap_en | dsitx_en | txdt_en */ 655 switch (dsi_dev->format) { 656 case MIPI_DSI_FMT_RGB888: 657 val |= (0x3 << 4); 658 hact = mode->hdisplay * 3; 659 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24; 660 break; 661 case MIPI_DSI_FMT_RGB666: 662 val |= (0x4 << 4); 663 hact = mode->hdisplay * 3; 664 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18; 665 break; 666 667 case MIPI_DSI_FMT_RGB666_PACKED: 668 val |= (0x4 << 4) | BIT(3); 669 hact = mode->hdisplay * 18 / 8; 670 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18; 671 break; 672 673 case MIPI_DSI_FMT_RGB565: 674 val |= (0x5 << 4); 675 hact = mode->hdisplay * 2; 676 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16; 677 break; 678 default: 679 dev_err(priv->dev, "Invalid data format (%u)\n", 680 dsi_dev->format); 681 tc358768_hw_disable(priv); 682 return; 683 } 684 685 /* VSDly[9:0] */ 686 tc358768_write(priv, TC358768_VSDLY, 1); 687 688 tc358768_write(priv, TC358768_DATAFMT, val); 689 tc358768_write(priv, TC358768_DSITX_DT, data_type); 690 691 /* Enable D-PHY (HiZ->LP11) */ 692 tc358768_write(priv, TC358768_CLW_CNTRL, 0x0000); 693 /* Enable lanes */ 694 for (i = 0; i < dsi_dev->lanes; i++) 695 tc358768_write(priv, TC358768_D0W_CNTRL + i * 4, 0x0000); 696 697 /* DSI Timings */ 698 dsibclk_nsk = (u32)div_u64((u64)1000000000 * TC358768_PRECISION, 699 dsibclk); 700 dsiclk_nsk = (u32)div_u64((u64)1000000000 * TC358768_PRECISION, dsiclk); 701 ui_nsk = dsiclk_nsk / 2; 702 phy_delay_nsk = dsibclk_nsk + 2 * dsiclk_nsk; 703 dev_dbg(priv->dev, "dsiclk_nsk: %u\n", dsiclk_nsk); 704 dev_dbg(priv->dev, "ui_nsk: %u\n", ui_nsk); 705 dev_dbg(priv->dev, "dsibclk_nsk: %u\n", dsibclk_nsk); 706 dev_dbg(priv->dev, "phy_delay_nsk: %u\n", phy_delay_nsk); 707 708 /* LP11 > 100us for D-PHY Rx Init */ 709 val = tc358768_ns_to_cnt(100 * 1000, dsibclk_nsk) - 1; 710 dev_dbg(priv->dev, "LINEINITCNT: 0x%x\n", val); 711 tc358768_write(priv, TC358768_LINEINITCNT, val); 712 713 /* LPTimeCnt > 50ns */ 714 val = tc358768_ns_to_cnt(50, dsibclk_nsk) - 1; 715 lptxcnt = val; 716 dev_dbg(priv->dev, "LPTXTIMECNT: 0x%x\n", val); 717 tc358768_write(priv, TC358768_LPTXTIMECNT, val); 718 719 /* 38ns < TCLK_PREPARE < 95ns */ 720 val = tc358768_ns_to_cnt(65, dsibclk_nsk) - 1; 721 /* TCLK_PREPARE > 300ns */ 722 val2 = tc358768_ns_to_cnt(300 + tc358768_to_ns(3 * ui_nsk), 723 dsibclk_nsk); 724 val |= (val2 - tc358768_to_ns(phy_delay_nsk - dsibclk_nsk)) << 8; 725 dev_dbg(priv->dev, "TCLK_HEADERCNT: 0x%x\n", val); 726 tc358768_write(priv, TC358768_TCLK_HEADERCNT, val); 727 728 /* TCLK_TRAIL > 60ns + 3*UI */ 729 val = 60 + tc358768_to_ns(3 * ui_nsk); 730 val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 5; 731 dev_dbg(priv->dev, "TCLK_TRAILCNT: 0x%x\n", val); 732 tc358768_write(priv, TC358768_TCLK_TRAILCNT, val); 733 734 /* 40ns + 4*UI < THS_PREPARE < 85ns + 6*UI */ 735 val = 50 + tc358768_to_ns(4 * ui_nsk); 736 val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 1; 737 /* THS_ZERO > 145ns + 10*UI */ 738 val2 = tc358768_ns_to_cnt(145 - tc358768_to_ns(ui_nsk), dsibclk_nsk); 739 val |= (val2 - tc358768_to_ns(phy_delay_nsk)) << 8; 740 dev_dbg(priv->dev, "THS_HEADERCNT: 0x%x\n", val); 741 tc358768_write(priv, TC358768_THS_HEADERCNT, val); 742 743 /* TWAKEUP > 1ms in lptxcnt steps */ 744 val = tc358768_ns_to_cnt(1020000, dsibclk_nsk); 745 val = val / (lptxcnt + 1) - 1; 746 dev_dbg(priv->dev, "TWAKEUP: 0x%x\n", val); 747 tc358768_write(priv, TC358768_TWAKEUP, val); 748 749 /* TCLK_POSTCNT > 60ns + 52*UI */ 750 val = tc358768_ns_to_cnt(60 + tc358768_to_ns(52 * ui_nsk), 751 dsibclk_nsk) - 3; 752 dev_dbg(priv->dev, "TCLK_POSTCNT: 0x%x\n", val); 753 tc358768_write(priv, TC358768_TCLK_POSTCNT, val); 754 755 /* 60ns + 4*UI < THS_PREPARE < 105ns + 12*UI */ 756 val = tc358768_ns_to_cnt(60 + tc358768_to_ns(15 * ui_nsk), 757 dsibclk_nsk) - 5; 758 dev_dbg(priv->dev, "THS_TRAILCNT: 0x%x\n", val); 759 tc358768_write(priv, TC358768_THS_TRAILCNT, val); 760 761 val = BIT(0); 762 for (i = 0; i < dsi_dev->lanes; i++) 763 val |= BIT(i + 1); 764 tc358768_write(priv, TC358768_HSTXVREGEN, val); 765 766 if (!(dsi_dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) 767 tc358768_write(priv, TC358768_TXOPTIONCNTRL, 0x1); 768 769 /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */ 770 val = tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk * 4); 771 val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 1; 772 val2 = tc358768_ns_to_cnt(tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk), 773 dsibclk_nsk) - 2; 774 val |= val2 << 16; 775 dev_dbg(priv->dev, "BTACNTRL1: 0x%x\n", val); 776 tc358768_write(priv, TC358768_BTACNTRL1, val); 777 778 /* START[0] */ 779 tc358768_write(priv, TC358768_STARTCNTRL, 1); 780 781 /* Set event mode */ 782 tc358768_write(priv, TC358768_DSI_EVENT, 1); 783 784 /* vsw (+ vbp) */ 785 tc358768_write(priv, TC358768_DSI_VSW, 786 mode->vtotal - mode->vsync_start); 787 /* vbp (not used in event mode) */ 788 tc358768_write(priv, TC358768_DSI_VBPR, 0); 789 /* vact */ 790 tc358768_write(priv, TC358768_DSI_VACT, mode->vdisplay); 791 792 /* (hsw + hbp) * byteclk * ndl / pclk */ 793 val = (u32)div_u64((mode->htotal - mode->hsync_start) * 794 ((u64)priv->dsiclk / 4) * priv->dsi_lanes, 795 mode->clock * 1000); 796 tc358768_write(priv, TC358768_DSI_HSW, val); 797 /* hbp (not used in event mode) */ 798 tc358768_write(priv, TC358768_DSI_HBPR, 0); 799 /* hact (bytes) */ 800 tc358768_write(priv, TC358768_DSI_HACT, hact); 801 802 /* VSYNC polarity */ 803 if (!(mode->flags & DRM_MODE_FLAG_NVSYNC)) 804 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(5), BIT(5)); 805 /* HSYNC polarity */ 806 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 807 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(0), BIT(0)); 808 809 /* Start DSI Tx */ 810 tc358768_write(priv, TC358768_DSI_START, 0x1); 811 812 /* Configure DSI_Control register */ 813 val = TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL; 814 val |= TC358768_DSI_CONTROL_TXMD | TC358768_DSI_CONTROL_HSCKMD | 815 0x3 << 1 | TC358768_DSI_CONTROL_EOTDIS; 816 tc358768_write(priv, TC358768_DSI_CONFW, val); 817 818 val = TC358768_DSI_CONFW_MODE_SET | TC358768_DSI_CONFW_ADDR_DSI_CONTROL; 819 val |= (dsi_dev->lanes - 1) << 1; 820 821 if (!(dsi_dev->mode_flags & MIPI_DSI_MODE_LPM)) 822 val |= TC358768_DSI_CONTROL_TXMD; 823 824 if (!(dsi_dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) 825 val |= TC358768_DSI_CONTROL_HSCKMD; 826 827 if (dsi_dev->mode_flags & MIPI_DSI_MODE_EOT_PACKET) 828 val |= TC358768_DSI_CONTROL_EOTDIS; 829 830 tc358768_write(priv, TC358768_DSI_CONFW, val); 831 832 val = TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL; 833 val |= TC358768_DSI_CONTROL_DIS_MODE; /* DSI mode */ 834 tc358768_write(priv, TC358768_DSI_CONFW, val); 835 836 ret = tc358768_clear_error(priv); 837 if (ret) { 838 dev_err(priv->dev, "Bridge pre_enable failed: %d\n", ret); 839 tc358768_bridge_disable(bridge); 840 tc358768_bridge_post_disable(bridge); 841 } 842 } 843 844 static void tc358768_bridge_enable(struct drm_bridge *bridge) 845 { 846 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 847 int ret; 848 849 if (!priv->enabled) { 850 dev_err(priv->dev, "Bridge is not enabled\n"); 851 return; 852 } 853 854 /* clear FrmStop and RstPtr */ 855 tc358768_update_bits(priv, TC358768_PP_MISC, 0x3 << 14, 0); 856 857 /* set PP_en */ 858 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), BIT(6)); 859 860 ret = tc358768_clear_error(priv); 861 if (ret) { 862 dev_err(priv->dev, "Bridge enable failed: %d\n", ret); 863 tc358768_bridge_disable(bridge); 864 tc358768_bridge_post_disable(bridge); 865 } 866 } 867 868 static const struct drm_bridge_funcs tc358768_bridge_funcs = { 869 .attach = tc358768_bridge_attach, 870 .mode_valid = tc358768_bridge_mode_valid, 871 .pre_enable = tc358768_bridge_pre_enable, 872 .enable = tc358768_bridge_enable, 873 .disable = tc358768_bridge_disable, 874 .post_disable = tc358768_bridge_post_disable, 875 }; 876 877 static const struct drm_bridge_timings default_tc358768_timings = { 878 .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 879 | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE 880 | DRM_BUS_FLAG_DE_HIGH, 881 }; 882 883 static bool tc358768_is_reserved_reg(unsigned int reg) 884 { 885 switch (reg) { 886 case 0x114 ... 0x13f: 887 case 0x200: 888 case 0x20c: 889 case 0x400 ... 0x408: 890 case 0x41c ... 0x42f: 891 return true; 892 default: 893 return false; 894 } 895 } 896 897 static bool tc358768_writeable_reg(struct device *dev, unsigned int reg) 898 { 899 if (tc358768_is_reserved_reg(reg)) 900 return false; 901 902 switch (reg) { 903 case TC358768_CHIPID: 904 case TC358768_FIFOSTATUS: 905 case TC358768_DSITXSTATUS ... (TC358768_DSITXSTATUS + 2): 906 case TC358768_DSI_CONTROL ... (TC358768_DSI_INT_ENA + 2): 907 case TC358768_DSICMD_RDFIFO ... (TC358768_DSI_ERR_HALT + 2): 908 return false; 909 default: 910 return true; 911 } 912 } 913 914 static bool tc358768_readable_reg(struct device *dev, unsigned int reg) 915 { 916 if (tc358768_is_reserved_reg(reg)) 917 return false; 918 919 switch (reg) { 920 case TC358768_STARTCNTRL: 921 case TC358768_DSI_CONFW ... (TC358768_DSI_CONFW + 2): 922 case TC358768_DSI_INT_CLR ... (TC358768_DSI_INT_CLR + 2): 923 case TC358768_DSI_START ... (TC358768_DSI_START + 2): 924 case TC358768_DBG_DATA: 925 return false; 926 default: 927 return true; 928 } 929 } 930 931 static const struct regmap_config tc358768_regmap_config = { 932 .name = "tc358768", 933 .reg_bits = 16, 934 .val_bits = 16, 935 .max_register = TC358768_DSI_HACT, 936 .cache_type = REGCACHE_NONE, 937 .writeable_reg = tc358768_writeable_reg, 938 .readable_reg = tc358768_readable_reg, 939 .reg_format_endian = REGMAP_ENDIAN_BIG, 940 .val_format_endian = REGMAP_ENDIAN_BIG, 941 }; 942 943 static const struct i2c_device_id tc358768_i2c_ids[] = { 944 { "tc358768", 0 }, 945 { "tc358778", 0 }, 946 { } 947 }; 948 MODULE_DEVICE_TABLE(i2c, tc358768_i2c_ids); 949 950 static const struct of_device_id tc358768_of_ids[] = { 951 { .compatible = "toshiba,tc358768", }, 952 { .compatible = "toshiba,tc358778", }, 953 { } 954 }; 955 MODULE_DEVICE_TABLE(of, tc358768_of_ids); 956 957 static int tc358768_get_regulators(struct tc358768_priv *priv) 958 { 959 int i, ret; 960 961 for (i = 0; i < ARRAY_SIZE(priv->supplies); ++i) 962 priv->supplies[i].supply = tc358768_supplies[i]; 963 964 ret = devm_regulator_bulk_get(priv->dev, ARRAY_SIZE(priv->supplies), 965 priv->supplies); 966 if (ret < 0) 967 dev_err(priv->dev, "failed to get regulators: %d\n", ret); 968 969 return ret; 970 } 971 972 static int tc358768_i2c_probe(struct i2c_client *client, 973 const struct i2c_device_id *id) 974 { 975 struct tc358768_priv *priv; 976 struct device *dev = &client->dev; 977 struct device_node *np = dev->of_node; 978 int ret; 979 980 if (!np) 981 return -ENODEV; 982 983 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 984 if (!priv) 985 return -ENOMEM; 986 987 dev_set_drvdata(dev, priv); 988 priv->dev = dev; 989 990 ret = tc358768_get_regulators(priv); 991 if (ret) 992 return ret; 993 994 priv->refclk = devm_clk_get(dev, "refclk"); 995 if (IS_ERR(priv->refclk)) 996 return PTR_ERR(priv->refclk); 997 998 /* 999 * RESX is low active, to disable tc358768 initially (keep in reset) 1000 * the gpio line must be LOW. This is the ASSERTED state of 1001 * GPIO_ACTIVE_LOW (GPIOD_OUT_HIGH == ASSERTED). 1002 */ 1003 priv->reset_gpio = devm_gpiod_get_optional(dev, "reset", 1004 GPIOD_OUT_HIGH); 1005 if (IS_ERR(priv->reset_gpio)) 1006 return PTR_ERR(priv->reset_gpio); 1007 1008 priv->regmap = devm_regmap_init_i2c(client, &tc358768_regmap_config); 1009 if (IS_ERR(priv->regmap)) { 1010 dev_err(dev, "Failed to init regmap\n"); 1011 return PTR_ERR(priv->regmap); 1012 } 1013 1014 priv->dsi_host.dev = dev; 1015 priv->dsi_host.ops = &tc358768_dsi_host_ops; 1016 1017 priv->bridge.funcs = &tc358768_bridge_funcs; 1018 priv->bridge.timings = &default_tc358768_timings; 1019 priv->bridge.of_node = np; 1020 1021 i2c_set_clientdata(client, priv); 1022 1023 return mipi_dsi_host_register(&priv->dsi_host); 1024 } 1025 1026 static int tc358768_i2c_remove(struct i2c_client *client) 1027 { 1028 struct tc358768_priv *priv = i2c_get_clientdata(client); 1029 1030 mipi_dsi_host_unregister(&priv->dsi_host); 1031 1032 return 0; 1033 } 1034 1035 static struct i2c_driver tc358768_driver = { 1036 .driver = { 1037 .name = "tc358768", 1038 .of_match_table = tc358768_of_ids, 1039 }, 1040 .id_table = tc358768_i2c_ids, 1041 .probe = tc358768_i2c_probe, 1042 .remove = tc358768_i2c_remove, 1043 }; 1044 module_i2c_driver(tc358768_driver); 1045 1046 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>"); 1047 MODULE_DESCRIPTION("TC358768AXBG/TC358778XBG DSI bridge"); 1048 MODULE_LICENSE("GPL v2"); 1049