1 // SPDX-License-Identifier: GPL-2.0 2 /** 3 * Wrapper driver for SERDES used in J721E 4 * 5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ 6 * Author: Kishon Vijay Abraham I <kishon@ti.com> 7 */ 8 9 #include <dt-bindings/phy/phy.h> 10 #include <linux/clk.h> 11 #include <linux/clk-provider.h> 12 #include <linux/gpio.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/mux/consumer.h> 17 #include <linux/of_address.h> 18 #include <linux/of_platform.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/regmap.h> 22 #include <linux/reset-controller.h> 23 24 #define WIZ_SERDES_CTRL 0x404 25 #define WIZ_SERDES_TOP_CTRL 0x408 26 #define WIZ_SERDES_RST 0x40c 27 #define WIZ_SERDES_TYPEC 0x410 28 #define WIZ_LANECTL(n) (0x480 + (0x40 * (n))) 29 30 #define WIZ_MAX_LANES 4 31 #define WIZ_MUX_NUM_CLOCKS 3 32 #define WIZ_DIV_NUM_CLOCKS_16G 2 33 #define WIZ_DIV_NUM_CLOCKS_10G 1 34 35 #define WIZ_SERDES_TYPEC_LN10_SWAP BIT(30) 36 37 enum wiz_lane_standard_mode { 38 LANE_MODE_GEN1, 39 LANE_MODE_GEN2, 40 LANE_MODE_GEN3, 41 LANE_MODE_GEN4, 42 }; 43 44 enum wiz_refclk_mux_sel { 45 PLL0_REFCLK, 46 PLL1_REFCLK, 47 REFCLK_DIG, 48 }; 49 50 enum wiz_refclk_div_sel { 51 CMN_REFCLK_DIG_DIV, 52 CMN_REFCLK1_DIG_DIV, 53 }; 54 55 static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31); 56 static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31); 57 static const struct reg_field pll1_refclk_mux_sel = 58 REG_FIELD(WIZ_SERDES_RST, 29, 29); 59 static const struct reg_field pll0_refclk_mux_sel = 60 REG_FIELD(WIZ_SERDES_RST, 28, 28); 61 static const struct reg_field refclk_dig_sel_16g = 62 REG_FIELD(WIZ_SERDES_RST, 24, 25); 63 static const struct reg_field refclk_dig_sel_10g = 64 REG_FIELD(WIZ_SERDES_RST, 24, 24); 65 static const struct reg_field pma_cmn_refclk_int_mode = 66 REG_FIELD(WIZ_SERDES_TOP_CTRL, 28, 29); 67 static const struct reg_field pma_cmn_refclk_mode = 68 REG_FIELD(WIZ_SERDES_TOP_CTRL, 30, 31); 69 static const struct reg_field pma_cmn_refclk_dig_div = 70 REG_FIELD(WIZ_SERDES_TOP_CTRL, 26, 27); 71 static const struct reg_field pma_cmn_refclk1_dig_div = 72 REG_FIELD(WIZ_SERDES_TOP_CTRL, 24, 25); 73 74 static const struct reg_field p_enable[WIZ_MAX_LANES] = { 75 REG_FIELD(WIZ_LANECTL(0), 30, 31), 76 REG_FIELD(WIZ_LANECTL(1), 30, 31), 77 REG_FIELD(WIZ_LANECTL(2), 30, 31), 78 REG_FIELD(WIZ_LANECTL(3), 30, 31), 79 }; 80 81 static const struct reg_field p_align[WIZ_MAX_LANES] = { 82 REG_FIELD(WIZ_LANECTL(0), 29, 29), 83 REG_FIELD(WIZ_LANECTL(1), 29, 29), 84 REG_FIELD(WIZ_LANECTL(2), 29, 29), 85 REG_FIELD(WIZ_LANECTL(3), 29, 29), 86 }; 87 88 static const struct reg_field p_raw_auto_start[WIZ_MAX_LANES] = { 89 REG_FIELD(WIZ_LANECTL(0), 28, 28), 90 REG_FIELD(WIZ_LANECTL(1), 28, 28), 91 REG_FIELD(WIZ_LANECTL(2), 28, 28), 92 REG_FIELD(WIZ_LANECTL(3), 28, 28), 93 }; 94 95 static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = { 96 REG_FIELD(WIZ_LANECTL(0), 24, 25), 97 REG_FIELD(WIZ_LANECTL(1), 24, 25), 98 REG_FIELD(WIZ_LANECTL(2), 24, 25), 99 REG_FIELD(WIZ_LANECTL(3), 24, 25), 100 }; 101 102 static const struct reg_field typec_ln10_swap = 103 REG_FIELD(WIZ_SERDES_TYPEC, 30, 30); 104 105 struct wiz_clk_mux { 106 struct clk_hw hw; 107 struct regmap_field *field; 108 u32 *table; 109 struct clk_init_data clk_data; 110 }; 111 112 #define to_wiz_clk_mux(_hw) container_of(_hw, struct wiz_clk_mux, hw) 113 114 struct wiz_clk_divider { 115 struct clk_hw hw; 116 struct regmap_field *field; 117 struct clk_div_table *table; 118 struct clk_init_data clk_data; 119 }; 120 121 #define to_wiz_clk_div(_hw) container_of(_hw, struct wiz_clk_divider, hw) 122 123 struct wiz_clk_mux_sel { 124 struct regmap_field *field; 125 u32 table[4]; 126 const char *node_name; 127 }; 128 129 struct wiz_clk_div_sel { 130 struct regmap_field *field; 131 struct clk_div_table *table; 132 const char *node_name; 133 }; 134 135 static struct wiz_clk_mux_sel clk_mux_sel_16g[] = { 136 { 137 /* 138 * Mux value to be configured for each of the input clocks 139 * in the order populated in device tree 140 */ 141 .table = { 1, 0 }, 142 .node_name = "pll0-refclk", 143 }, 144 { 145 .table = { 1, 0 }, 146 .node_name = "pll1-refclk", 147 }, 148 { 149 .table = { 1, 3, 0, 2 }, 150 .node_name = "refclk-dig", 151 }, 152 }; 153 154 static struct wiz_clk_mux_sel clk_mux_sel_10g[] = { 155 { 156 /* 157 * Mux value to be configured for each of the input clocks 158 * in the order populated in device tree 159 */ 160 .table = { 1, 0 }, 161 .node_name = "pll0-refclk", 162 }, 163 { 164 .table = { 1, 0 }, 165 .node_name = "pll1-refclk", 166 }, 167 { 168 .table = { 1, 0 }, 169 .node_name = "refclk-dig", 170 }, 171 }; 172 173 static struct clk_div_table clk_div_table[] = { 174 { .val = 0, .div = 1, }, 175 { .val = 1, .div = 2, }, 176 { .val = 2, .div = 4, }, 177 { .val = 3, .div = 8, }, 178 }; 179 180 static struct wiz_clk_div_sel clk_div_sel[] = { 181 { 182 .table = clk_div_table, 183 .node_name = "cmn-refclk-dig-div", 184 }, 185 { 186 .table = clk_div_table, 187 .node_name = "cmn-refclk1-dig-div", 188 }, 189 }; 190 191 enum wiz_type { 192 J721E_WIZ_16G, 193 J721E_WIZ_10G, 194 }; 195 196 #define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */ 197 #define WIZ_TYPEC_DIR_DEBOUNCE_MAX 1000 198 199 struct wiz { 200 struct regmap *regmap; 201 enum wiz_type type; 202 struct wiz_clk_mux_sel *clk_mux_sel; 203 struct wiz_clk_div_sel *clk_div_sel; 204 unsigned int clk_div_sel_num; 205 struct regmap_field *por_en; 206 struct regmap_field *phy_reset_n; 207 struct regmap_field *p_enable[WIZ_MAX_LANES]; 208 struct regmap_field *p_align[WIZ_MAX_LANES]; 209 struct regmap_field *p_raw_auto_start[WIZ_MAX_LANES]; 210 struct regmap_field *p_standard_mode[WIZ_MAX_LANES]; 211 struct regmap_field *pma_cmn_refclk_int_mode; 212 struct regmap_field *pma_cmn_refclk_mode; 213 struct regmap_field *pma_cmn_refclk_dig_div; 214 struct regmap_field *pma_cmn_refclk1_dig_div; 215 struct regmap_field *typec_ln10_swap; 216 217 struct device *dev; 218 u32 num_lanes; 219 struct platform_device *serdes_pdev; 220 struct reset_controller_dev wiz_phy_reset_dev; 221 struct gpio_desc *gpio_typec_dir; 222 int typec_dir_delay; 223 }; 224 225 static int wiz_reset(struct wiz *wiz) 226 { 227 int ret; 228 229 ret = regmap_field_write(wiz->por_en, 0x1); 230 if (ret) 231 return ret; 232 233 mdelay(1); 234 235 ret = regmap_field_write(wiz->por_en, 0x0); 236 if (ret) 237 return ret; 238 239 return 0; 240 } 241 242 static int wiz_mode_select(struct wiz *wiz) 243 { 244 u32 num_lanes = wiz->num_lanes; 245 int ret; 246 int i; 247 248 for (i = 0; i < num_lanes; i++) { 249 ret = regmap_field_write(wiz->p_standard_mode[i], 250 LANE_MODE_GEN4); 251 if (ret) 252 return ret; 253 } 254 255 return 0; 256 } 257 258 static int wiz_init_raw_interface(struct wiz *wiz, bool enable) 259 { 260 u32 num_lanes = wiz->num_lanes; 261 int i; 262 int ret; 263 264 for (i = 0; i < num_lanes; i++) { 265 ret = regmap_field_write(wiz->p_align[i], enable); 266 if (ret) 267 return ret; 268 269 ret = regmap_field_write(wiz->p_raw_auto_start[i], enable); 270 if (ret) 271 return ret; 272 } 273 274 return 0; 275 } 276 277 static int wiz_init(struct wiz *wiz) 278 { 279 struct device *dev = wiz->dev; 280 int ret; 281 282 ret = wiz_reset(wiz); 283 if (ret) { 284 dev_err(dev, "WIZ reset failed\n"); 285 return ret; 286 } 287 288 ret = wiz_mode_select(wiz); 289 if (ret) { 290 dev_err(dev, "WIZ mode select failed\n"); 291 return ret; 292 } 293 294 ret = wiz_init_raw_interface(wiz, true); 295 if (ret) { 296 dev_err(dev, "WIZ interface initialization failed\n"); 297 return ret; 298 } 299 300 return 0; 301 } 302 303 static int wiz_regfield_init(struct wiz *wiz) 304 { 305 struct wiz_clk_mux_sel *clk_mux_sel; 306 struct wiz_clk_div_sel *clk_div_sel; 307 struct regmap *regmap = wiz->regmap; 308 int num_lanes = wiz->num_lanes; 309 struct device *dev = wiz->dev; 310 int i; 311 312 wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en); 313 if (IS_ERR(wiz->por_en)) { 314 dev_err(dev, "POR_EN reg field init failed\n"); 315 return PTR_ERR(wiz->por_en); 316 } 317 318 wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap, 319 phy_reset_n); 320 if (IS_ERR(wiz->phy_reset_n)) { 321 dev_err(dev, "PHY_RESET_N reg field init failed\n"); 322 return PTR_ERR(wiz->phy_reset_n); 323 } 324 325 wiz->pma_cmn_refclk_int_mode = 326 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_int_mode); 327 if (IS_ERR(wiz->pma_cmn_refclk_int_mode)) { 328 dev_err(dev, "PMA_CMN_REFCLK_INT_MODE reg field init failed\n"); 329 return PTR_ERR(wiz->pma_cmn_refclk_int_mode); 330 } 331 332 wiz->pma_cmn_refclk_mode = 333 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_mode); 334 if (IS_ERR(wiz->pma_cmn_refclk_mode)) { 335 dev_err(dev, "PMA_CMN_REFCLK_MODE reg field init failed\n"); 336 return PTR_ERR(wiz->pma_cmn_refclk_mode); 337 } 338 339 clk_div_sel = &wiz->clk_div_sel[CMN_REFCLK_DIG_DIV]; 340 clk_div_sel->field = devm_regmap_field_alloc(dev, regmap, 341 pma_cmn_refclk_dig_div); 342 if (IS_ERR(clk_div_sel->field)) { 343 dev_err(dev, "PMA_CMN_REFCLK_DIG_DIV reg field init failed\n"); 344 return PTR_ERR(clk_div_sel->field); 345 } 346 347 if (wiz->type == J721E_WIZ_16G) { 348 clk_div_sel = &wiz->clk_div_sel[CMN_REFCLK1_DIG_DIV]; 349 clk_div_sel->field = 350 devm_regmap_field_alloc(dev, regmap, 351 pma_cmn_refclk1_dig_div); 352 if (IS_ERR(clk_div_sel->field)) { 353 dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init failed\n"); 354 return PTR_ERR(clk_div_sel->field); 355 } 356 } 357 358 clk_mux_sel = &wiz->clk_mux_sel[PLL0_REFCLK]; 359 clk_mux_sel->field = devm_regmap_field_alloc(dev, regmap, 360 pll0_refclk_mux_sel); 361 if (IS_ERR(clk_mux_sel->field)) { 362 dev_err(dev, "PLL0_REFCLK_SEL reg field init failed\n"); 363 return PTR_ERR(clk_mux_sel->field); 364 } 365 366 clk_mux_sel = &wiz->clk_mux_sel[PLL1_REFCLK]; 367 clk_mux_sel->field = devm_regmap_field_alloc(dev, regmap, 368 pll1_refclk_mux_sel); 369 if (IS_ERR(clk_mux_sel->field)) { 370 dev_err(dev, "PLL1_REFCLK_SEL reg field init failed\n"); 371 return PTR_ERR(clk_mux_sel->field); 372 } 373 374 clk_mux_sel = &wiz->clk_mux_sel[REFCLK_DIG]; 375 if (wiz->type == J721E_WIZ_10G) 376 clk_mux_sel->field = 377 devm_regmap_field_alloc(dev, regmap, 378 refclk_dig_sel_10g); 379 else 380 clk_mux_sel->field = 381 devm_regmap_field_alloc(dev, regmap, 382 refclk_dig_sel_16g); 383 384 if (IS_ERR(clk_mux_sel->field)) { 385 dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n"); 386 return PTR_ERR(clk_mux_sel->field); 387 } 388 389 for (i = 0; i < num_lanes; i++) { 390 wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap, 391 p_enable[i]); 392 if (IS_ERR(wiz->p_enable[i])) { 393 dev_err(dev, "P%d_ENABLE reg field init failed\n", i); 394 return PTR_ERR(wiz->p_enable[i]); 395 } 396 397 wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap, 398 p_align[i]); 399 if (IS_ERR(wiz->p_align[i])) { 400 dev_err(dev, "P%d_ALIGN reg field init failed\n", i); 401 return PTR_ERR(wiz->p_align[i]); 402 } 403 404 wiz->p_raw_auto_start[i] = 405 devm_regmap_field_alloc(dev, regmap, p_raw_auto_start[i]); 406 if (IS_ERR(wiz->p_raw_auto_start[i])) { 407 dev_err(dev, "P%d_RAW_AUTO_START reg field init fail\n", 408 i); 409 return PTR_ERR(wiz->p_raw_auto_start[i]); 410 } 411 412 wiz->p_standard_mode[i] = 413 devm_regmap_field_alloc(dev, regmap, p_standard_mode[i]); 414 if (IS_ERR(wiz->p_standard_mode[i])) { 415 dev_err(dev, "P%d_STANDARD_MODE reg field init fail\n", 416 i); 417 return PTR_ERR(wiz->p_standard_mode[i]); 418 } 419 } 420 421 wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap, 422 typec_ln10_swap); 423 if (IS_ERR(wiz->typec_ln10_swap)) { 424 dev_err(dev, "LN10_SWAP reg field init failed\n"); 425 return PTR_ERR(wiz->typec_ln10_swap); 426 } 427 428 return 0; 429 } 430 431 static u8 wiz_clk_mux_get_parent(struct clk_hw *hw) 432 { 433 struct wiz_clk_mux *mux = to_wiz_clk_mux(hw); 434 struct regmap_field *field = mux->field; 435 unsigned int val; 436 437 regmap_field_read(field, &val); 438 return clk_mux_val_to_index(hw, mux->table, 0, val); 439 } 440 441 static int wiz_clk_mux_set_parent(struct clk_hw *hw, u8 index) 442 { 443 struct wiz_clk_mux *mux = to_wiz_clk_mux(hw); 444 struct regmap_field *field = mux->field; 445 int val; 446 447 val = mux->table[index]; 448 return regmap_field_write(field, val); 449 } 450 451 static const struct clk_ops wiz_clk_mux_ops = { 452 .set_parent = wiz_clk_mux_set_parent, 453 .get_parent = wiz_clk_mux_get_parent, 454 }; 455 456 static int wiz_mux_clk_register(struct wiz *wiz, struct device_node *node, 457 struct regmap_field *field, u32 *table) 458 { 459 struct device *dev = wiz->dev; 460 struct clk_init_data *init; 461 const char **parent_names; 462 unsigned int num_parents; 463 struct wiz_clk_mux *mux; 464 char clk_name[100]; 465 struct clk *clk; 466 int ret; 467 468 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); 469 if (!mux) 470 return -ENOMEM; 471 472 num_parents = of_clk_get_parent_count(node); 473 if (num_parents < 2) { 474 dev_err(dev, "SERDES clock must have parents\n"); 475 return -EINVAL; 476 } 477 478 parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), 479 GFP_KERNEL); 480 if (!parent_names) 481 return -ENOMEM; 482 483 of_clk_parent_fill(node, parent_names, num_parents); 484 485 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), 486 node->name); 487 488 init = &mux->clk_data; 489 490 init->ops = &wiz_clk_mux_ops; 491 init->flags = CLK_SET_RATE_NO_REPARENT; 492 init->parent_names = parent_names; 493 init->num_parents = num_parents; 494 init->name = clk_name; 495 496 mux->field = field; 497 mux->table = table; 498 mux->hw.init = init; 499 500 clk = devm_clk_register(dev, &mux->hw); 501 if (IS_ERR(clk)) 502 return PTR_ERR(clk); 503 504 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); 505 if (ret) 506 dev_err(dev, "Failed to add clock provider: %s\n", clk_name); 507 508 return ret; 509 } 510 511 static unsigned long wiz_clk_div_recalc_rate(struct clk_hw *hw, 512 unsigned long parent_rate) 513 { 514 struct wiz_clk_divider *div = to_wiz_clk_div(hw); 515 struct regmap_field *field = div->field; 516 int val; 517 518 regmap_field_read(field, &val); 519 520 return divider_recalc_rate(hw, parent_rate, val, div->table, 0x0, 2); 521 } 522 523 static long wiz_clk_div_round_rate(struct clk_hw *hw, unsigned long rate, 524 unsigned long *prate) 525 { 526 struct wiz_clk_divider *div = to_wiz_clk_div(hw); 527 528 return divider_round_rate(hw, rate, prate, div->table, 2, 0x0); 529 } 530 531 static int wiz_clk_div_set_rate(struct clk_hw *hw, unsigned long rate, 532 unsigned long parent_rate) 533 { 534 struct wiz_clk_divider *div = to_wiz_clk_div(hw); 535 struct regmap_field *field = div->field; 536 int val; 537 538 val = divider_get_val(rate, parent_rate, div->table, 2, 0x0); 539 if (val < 0) 540 return val; 541 542 return regmap_field_write(field, val); 543 } 544 545 static const struct clk_ops wiz_clk_div_ops = { 546 .recalc_rate = wiz_clk_div_recalc_rate, 547 .round_rate = wiz_clk_div_round_rate, 548 .set_rate = wiz_clk_div_set_rate, 549 }; 550 551 static int wiz_div_clk_register(struct wiz *wiz, struct device_node *node, 552 struct regmap_field *field, 553 struct clk_div_table *table) 554 { 555 struct device *dev = wiz->dev; 556 struct wiz_clk_divider *div; 557 struct clk_init_data *init; 558 const char **parent_names; 559 char clk_name[100]; 560 struct clk *clk; 561 int ret; 562 563 div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); 564 if (!div) 565 return -ENOMEM; 566 567 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), 568 node->name); 569 570 parent_names = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL); 571 if (!parent_names) 572 return -ENOMEM; 573 574 of_clk_parent_fill(node, parent_names, 1); 575 576 init = &div->clk_data; 577 578 init->ops = &wiz_clk_div_ops; 579 init->flags = 0; 580 init->parent_names = parent_names; 581 init->num_parents = 1; 582 init->name = clk_name; 583 584 div->field = field; 585 div->table = table; 586 div->hw.init = init; 587 588 clk = devm_clk_register(dev, &div->hw); 589 if (IS_ERR(clk)) 590 return PTR_ERR(clk); 591 592 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); 593 if (ret) 594 dev_err(dev, "Failed to add clock provider: %s\n", clk_name); 595 596 return ret; 597 } 598 599 static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node) 600 { 601 struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; 602 struct device_node *clk_node; 603 int i; 604 605 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) { 606 clk_node = of_get_child_by_name(node, clk_mux_sel[i].node_name); 607 of_clk_del_provider(clk_node); 608 of_node_put(clk_node); 609 } 610 } 611 612 static int wiz_clock_init(struct wiz *wiz, struct device_node *node) 613 { 614 struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; 615 struct device *dev = wiz->dev; 616 struct device_node *clk_node; 617 const char *node_name; 618 unsigned long rate; 619 struct clk *clk; 620 int ret; 621 int i; 622 623 clk = devm_clk_get(dev, "core_ref_clk"); 624 if (IS_ERR(clk)) { 625 dev_err(dev, "core_ref_clk clock not found\n"); 626 ret = PTR_ERR(clk); 627 return ret; 628 } 629 630 rate = clk_get_rate(clk); 631 if (rate >= 100000000) 632 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1); 633 else 634 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3); 635 636 clk = devm_clk_get(dev, "ext_ref_clk"); 637 if (IS_ERR(clk)) { 638 dev_err(dev, "ext_ref_clk clock not found\n"); 639 ret = PTR_ERR(clk); 640 return ret; 641 } 642 643 rate = clk_get_rate(clk); 644 if (rate >= 100000000) 645 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0); 646 else 647 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2); 648 649 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) { 650 node_name = clk_mux_sel[i].node_name; 651 clk_node = of_get_child_by_name(node, node_name); 652 if (!clk_node) { 653 dev_err(dev, "Unable to get %s node\n", node_name); 654 ret = -EINVAL; 655 goto err; 656 } 657 658 ret = wiz_mux_clk_register(wiz, clk_node, clk_mux_sel[i].field, 659 clk_mux_sel[i].table); 660 if (ret) { 661 dev_err(dev, "Failed to register %s clock\n", 662 node_name); 663 of_node_put(clk_node); 664 goto err; 665 } 666 667 of_node_put(clk_node); 668 } 669 670 for (i = 0; i < wiz->clk_div_sel_num; i++) { 671 node_name = clk_div_sel[i].node_name; 672 clk_node = of_get_child_by_name(node, node_name); 673 if (!clk_node) { 674 dev_err(dev, "Unable to get %s node\n", node_name); 675 ret = -EINVAL; 676 goto err; 677 } 678 679 ret = wiz_div_clk_register(wiz, clk_node, clk_div_sel[i].field, 680 clk_div_sel[i].table); 681 if (ret) { 682 dev_err(dev, "Failed to register %s clock\n", 683 node_name); 684 of_node_put(clk_node); 685 goto err; 686 } 687 688 of_node_put(clk_node); 689 } 690 691 return 0; 692 err: 693 wiz_clock_cleanup(wiz, node); 694 695 return ret; 696 } 697 698 static int wiz_phy_reset_assert(struct reset_controller_dev *rcdev, 699 unsigned long id) 700 { 701 struct device *dev = rcdev->dev; 702 struct wiz *wiz = dev_get_drvdata(dev); 703 int ret = 0; 704 705 if (id == 0) { 706 ret = regmap_field_write(wiz->phy_reset_n, false); 707 return ret; 708 } 709 710 ret = regmap_field_write(wiz->p_enable[id - 1], false); 711 return ret; 712 } 713 714 static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev, 715 unsigned long id) 716 { 717 struct device *dev = rcdev->dev; 718 struct wiz *wiz = dev_get_drvdata(dev); 719 int ret; 720 721 /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */ 722 if (id == 0 && wiz->gpio_typec_dir) { 723 if (wiz->typec_dir_delay) 724 msleep_interruptible(wiz->typec_dir_delay); 725 726 if (gpiod_get_value_cansleep(wiz->gpio_typec_dir)) 727 regmap_field_write(wiz->typec_ln10_swap, 1); 728 else 729 regmap_field_write(wiz->typec_ln10_swap, 0); 730 } 731 732 if (id == 0) { 733 ret = regmap_field_write(wiz->phy_reset_n, true); 734 return ret; 735 } 736 737 ret = regmap_field_write(wiz->p_enable[id - 1], true); 738 return ret; 739 } 740 741 static const struct reset_control_ops wiz_phy_reset_ops = { 742 .assert = wiz_phy_reset_assert, 743 .deassert = wiz_phy_reset_deassert, 744 }; 745 746 static struct regmap_config wiz_regmap_config = { 747 .reg_bits = 32, 748 .val_bits = 32, 749 .reg_stride = 4, 750 .fast_io = true, 751 }; 752 753 static const struct of_device_id wiz_id_table[] = { 754 { 755 .compatible = "ti,j721e-wiz-16g", .data = (void *)J721E_WIZ_16G 756 }, 757 { 758 .compatible = "ti,j721e-wiz-10g", .data = (void *)J721E_WIZ_10G 759 }, 760 {} 761 }; 762 MODULE_DEVICE_TABLE(of, wiz_id_table); 763 764 static int wiz_probe(struct platform_device *pdev) 765 { 766 struct reset_controller_dev *phy_reset_dev; 767 struct device *dev = &pdev->dev; 768 struct device_node *node = dev->of_node; 769 struct platform_device *serdes_pdev; 770 struct device_node *child_node; 771 struct regmap *regmap; 772 struct resource res; 773 void __iomem *base; 774 struct wiz *wiz; 775 u32 num_lanes; 776 int ret; 777 778 wiz = devm_kzalloc(dev, sizeof(*wiz), GFP_KERNEL); 779 if (!wiz) 780 return -ENOMEM; 781 782 wiz->type = (enum wiz_type)of_device_get_match_data(dev); 783 784 child_node = of_get_child_by_name(node, "serdes"); 785 if (!child_node) { 786 dev_err(dev, "Failed to get SERDES child DT node\n"); 787 return -ENODEV; 788 } 789 790 ret = of_address_to_resource(child_node, 0, &res); 791 if (ret) { 792 dev_err(dev, "Failed to get memory resource\n"); 793 goto err_addr_to_resource; 794 } 795 796 base = devm_ioremap(dev, res.start, resource_size(&res)); 797 if (!base) 798 goto err_addr_to_resource; 799 800 regmap = devm_regmap_init_mmio(dev, base, &wiz_regmap_config); 801 if (IS_ERR(regmap)) { 802 dev_err(dev, "Failed to initialize regmap\n"); 803 ret = PTR_ERR(regmap); 804 goto err_addr_to_resource; 805 } 806 807 ret = of_property_read_u32(node, "num-lanes", &num_lanes); 808 if (ret) { 809 dev_err(dev, "Failed to read num-lanes property\n"); 810 goto err_addr_to_resource; 811 } 812 813 if (num_lanes > WIZ_MAX_LANES) { 814 dev_err(dev, "Cannot support %d lanes\n", num_lanes); 815 goto err_addr_to_resource; 816 } 817 818 wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir", 819 GPIOD_IN); 820 if (IS_ERR(wiz->gpio_typec_dir)) { 821 ret = PTR_ERR(wiz->gpio_typec_dir); 822 if (ret != -EPROBE_DEFER) 823 dev_err(dev, "Failed to request typec-dir gpio: %d\n", 824 ret); 825 goto err_addr_to_resource; 826 } 827 828 if (wiz->gpio_typec_dir) { 829 ret = of_property_read_u32(node, "typec-dir-debounce-ms", 830 &wiz->typec_dir_delay); 831 if (ret && ret != -EINVAL) { 832 dev_err(dev, "Invalid typec-dir-debounce property\n"); 833 goto err_addr_to_resource; 834 } 835 836 /* use min. debounce from Type-C spec if not provided in DT */ 837 if (ret == -EINVAL) 838 wiz->typec_dir_delay = WIZ_TYPEC_DIR_DEBOUNCE_MIN; 839 840 if (wiz->typec_dir_delay < WIZ_TYPEC_DIR_DEBOUNCE_MIN || 841 wiz->typec_dir_delay > WIZ_TYPEC_DIR_DEBOUNCE_MAX) { 842 dev_err(dev, "Invalid typec-dir-debounce property\n"); 843 goto err_addr_to_resource; 844 } 845 } 846 847 wiz->dev = dev; 848 wiz->regmap = regmap; 849 wiz->num_lanes = num_lanes; 850 if (wiz->type == J721E_WIZ_10G) 851 wiz->clk_mux_sel = clk_mux_sel_10g; 852 else 853 wiz->clk_mux_sel = clk_mux_sel_16g; 854 855 wiz->clk_div_sel = clk_div_sel; 856 857 if (wiz->type == J721E_WIZ_10G) 858 wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G; 859 else 860 wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G; 861 862 platform_set_drvdata(pdev, wiz); 863 864 ret = wiz_regfield_init(wiz); 865 if (ret) { 866 dev_err(dev, "Failed to initialize regfields\n"); 867 goto err_addr_to_resource; 868 } 869 870 phy_reset_dev = &wiz->wiz_phy_reset_dev; 871 phy_reset_dev->dev = dev; 872 phy_reset_dev->ops = &wiz_phy_reset_ops, 873 phy_reset_dev->owner = THIS_MODULE, 874 phy_reset_dev->of_node = node; 875 /* Reset for each of the lane and one for the entire SERDES */ 876 phy_reset_dev->nr_resets = num_lanes + 1; 877 878 ret = devm_reset_controller_register(dev, phy_reset_dev); 879 if (ret < 0) { 880 dev_warn(dev, "Failed to register reset controller\n"); 881 goto err_addr_to_resource; 882 } 883 884 pm_runtime_enable(dev); 885 ret = pm_runtime_get_sync(dev); 886 if (ret < 0) { 887 dev_err(dev, "pm_runtime_get_sync failed\n"); 888 goto err_get_sync; 889 } 890 891 ret = wiz_clock_init(wiz, node); 892 if (ret < 0) { 893 dev_warn(dev, "Failed to initialize clocks\n"); 894 goto err_get_sync; 895 } 896 897 serdes_pdev = of_platform_device_create(child_node, NULL, dev); 898 if (!serdes_pdev) { 899 dev_WARN(dev, "Unable to create SERDES platform device\n"); 900 goto err_pdev_create; 901 } 902 wiz->serdes_pdev = serdes_pdev; 903 904 ret = wiz_init(wiz); 905 if (ret) { 906 dev_err(dev, "WIZ initialization failed\n"); 907 goto err_wiz_init; 908 } 909 910 of_node_put(child_node); 911 return 0; 912 913 err_wiz_init: 914 of_platform_device_destroy(&serdes_pdev->dev, NULL); 915 916 err_pdev_create: 917 wiz_clock_cleanup(wiz, node); 918 919 err_get_sync: 920 pm_runtime_put(dev); 921 pm_runtime_disable(dev); 922 923 err_addr_to_resource: 924 of_node_put(child_node); 925 926 return ret; 927 } 928 929 static int wiz_remove(struct platform_device *pdev) 930 { 931 struct device *dev = &pdev->dev; 932 struct device_node *node = dev->of_node; 933 struct platform_device *serdes_pdev; 934 struct wiz *wiz; 935 936 wiz = dev_get_drvdata(dev); 937 serdes_pdev = wiz->serdes_pdev; 938 939 of_platform_device_destroy(&serdes_pdev->dev, NULL); 940 wiz_clock_cleanup(wiz, node); 941 pm_runtime_put(dev); 942 pm_runtime_disable(dev); 943 944 return 0; 945 } 946 947 static struct platform_driver wiz_driver = { 948 .probe = wiz_probe, 949 .remove = wiz_remove, 950 .driver = { 951 .name = "wiz", 952 .of_match_table = wiz_id_table, 953 }, 954 }; 955 module_platform_driver(wiz_driver); 956 957 MODULE_AUTHOR("Texas Instruments Inc."); 958 MODULE_DESCRIPTION("TI J721E WIZ driver"); 959 MODULE_LICENSE("GPL v2"); 960