1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // rt5682.c -- RT5682 ALSA SoC audio component driver 4 // 5 // Copyright 2018 Realtek Semiconductor Corp. 6 // Author: Bard Liao <bardliao@realtek.com> 7 // 8 9 #include <linux/module.h> 10 #include <linux/moduleparam.h> 11 #include <linux/init.h> 12 #include <linux/delay.h> 13 #include <linux/pm.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/platform_device.h> 16 #include <linux/spi/spi.h> 17 #include <linux/acpi.h> 18 #include <linux/gpio.h> 19 #include <linux/of_gpio.h> 20 #include <linux/mutex.h> 21 #include <sound/core.h> 22 #include <sound/pcm.h> 23 #include <sound/pcm_params.h> 24 #include <sound/jack.h> 25 #include <sound/soc.h> 26 #include <sound/soc-dapm.h> 27 #include <sound/initval.h> 28 #include <sound/tlv.h> 29 #include <sound/rt5682.h> 30 31 #include "rl6231.h" 32 #include "rt5682.h" 33 34 const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = { 35 "AVDD", 36 "MICVDD", 37 "VBAT", 38 }; 39 EXPORT_SYMBOL_GPL(rt5682_supply_names); 40 41 static const struct reg_sequence patch_list[] = { 42 {RT5682_HP_IMP_SENS_CTRL_19, 0x1000}, 43 {RT5682_DAC_ADC_DIG_VOL1, 0xa020}, 44 {RT5682_I2C_CTRL, 0x000f}, 45 {RT5682_PLL2_INTERNAL, 0x8266}, 46 }; 47 48 void rt5682_apply_patch_list(struct rt5682_priv *rt5682, struct device *dev) 49 { 50 int ret; 51 52 ret = regmap_multi_reg_write(rt5682->regmap, patch_list, 53 ARRAY_SIZE(patch_list)); 54 if (ret) 55 dev_warn(dev, "Failed to apply regmap patch: %d\n", ret); 56 } 57 EXPORT_SYMBOL_GPL(rt5682_apply_patch_list); 58 59 const struct reg_default rt5682_reg[RT5682_REG_NUM] = { 60 {0x0002, 0x8080}, 61 {0x0003, 0x8000}, 62 {0x0005, 0x0000}, 63 {0x0006, 0x0000}, 64 {0x0008, 0x800f}, 65 {0x000b, 0x0000}, 66 {0x0010, 0x4040}, 67 {0x0011, 0x0000}, 68 {0x0012, 0x1404}, 69 {0x0013, 0x1000}, 70 {0x0014, 0xa00a}, 71 {0x0015, 0x0404}, 72 {0x0016, 0x0404}, 73 {0x0019, 0xafaf}, 74 {0x001c, 0x2f2f}, 75 {0x001f, 0x0000}, 76 {0x0022, 0x5757}, 77 {0x0023, 0x0039}, 78 {0x0024, 0x000b}, 79 {0x0026, 0xc0c4}, 80 {0x0029, 0x8080}, 81 {0x002a, 0xa0a0}, 82 {0x002b, 0x0300}, 83 {0x0030, 0x0000}, 84 {0x003c, 0x0080}, 85 {0x0044, 0x0c0c}, 86 {0x0049, 0x0000}, 87 {0x0061, 0x0000}, 88 {0x0062, 0x0000}, 89 {0x0063, 0x003f}, 90 {0x0064, 0x0000}, 91 {0x0065, 0x0000}, 92 {0x0066, 0x0030}, 93 {0x0067, 0x0000}, 94 {0x006b, 0x0000}, 95 {0x006c, 0x0000}, 96 {0x006d, 0x2200}, 97 {0x006e, 0x0a10}, 98 {0x0070, 0x8000}, 99 {0x0071, 0x8000}, 100 {0x0073, 0x0000}, 101 {0x0074, 0x0000}, 102 {0x0075, 0x0002}, 103 {0x0076, 0x0001}, 104 {0x0079, 0x0000}, 105 {0x007a, 0x0000}, 106 {0x007b, 0x0000}, 107 {0x007c, 0x0100}, 108 {0x007e, 0x0000}, 109 {0x0080, 0x0000}, 110 {0x0081, 0x0000}, 111 {0x0082, 0x0000}, 112 {0x0083, 0x0000}, 113 {0x0084, 0x0000}, 114 {0x0085, 0x0000}, 115 {0x0086, 0x0005}, 116 {0x0087, 0x0000}, 117 {0x0088, 0x0000}, 118 {0x008c, 0x0003}, 119 {0x008d, 0x0000}, 120 {0x008e, 0x0060}, 121 {0x008f, 0x1000}, 122 {0x0091, 0x0c26}, 123 {0x0092, 0x0073}, 124 {0x0093, 0x0000}, 125 {0x0094, 0x0080}, 126 {0x0098, 0x0000}, 127 {0x009a, 0x0000}, 128 {0x009b, 0x0000}, 129 {0x009c, 0x0000}, 130 {0x009d, 0x0000}, 131 {0x009e, 0x100c}, 132 {0x009f, 0x0000}, 133 {0x00a0, 0x0000}, 134 {0x00a3, 0x0002}, 135 {0x00a4, 0x0001}, 136 {0x00ae, 0x2040}, 137 {0x00af, 0x0000}, 138 {0x00b6, 0x0000}, 139 {0x00b7, 0x0000}, 140 {0x00b8, 0x0000}, 141 {0x00b9, 0x0002}, 142 {0x00be, 0x0000}, 143 {0x00c0, 0x0160}, 144 {0x00c1, 0x82a0}, 145 {0x00c2, 0x0000}, 146 {0x00d0, 0x0000}, 147 {0x00d1, 0x2244}, 148 {0x00d2, 0x3300}, 149 {0x00d3, 0x2200}, 150 {0x00d4, 0x0000}, 151 {0x00d9, 0x0009}, 152 {0x00da, 0x0000}, 153 {0x00db, 0x0000}, 154 {0x00dc, 0x00c0}, 155 {0x00dd, 0x2220}, 156 {0x00de, 0x3131}, 157 {0x00df, 0x3131}, 158 {0x00e0, 0x3131}, 159 {0x00e2, 0x0000}, 160 {0x00e3, 0x4000}, 161 {0x00e4, 0x0aa0}, 162 {0x00e5, 0x3131}, 163 {0x00e6, 0x3131}, 164 {0x00e7, 0x3131}, 165 {0x00e8, 0x3131}, 166 {0x00ea, 0xb320}, 167 {0x00eb, 0x0000}, 168 {0x00f0, 0x0000}, 169 {0x00f1, 0x00d0}, 170 {0x00f2, 0x00d0}, 171 {0x00f6, 0x0000}, 172 {0x00fa, 0x0000}, 173 {0x00fb, 0x0000}, 174 {0x00fc, 0x0000}, 175 {0x00fd, 0x0000}, 176 {0x00fe, 0x10ec}, 177 {0x00ff, 0x6530}, 178 {0x0100, 0xa0a0}, 179 {0x010b, 0x0000}, 180 {0x010c, 0xae00}, 181 {0x010d, 0xaaa0}, 182 {0x010e, 0x8aa2}, 183 {0x010f, 0x02a2}, 184 {0x0110, 0xc000}, 185 {0x0111, 0x04a2}, 186 {0x0112, 0x2800}, 187 {0x0113, 0x0000}, 188 {0x0117, 0x0100}, 189 {0x0125, 0x0410}, 190 {0x0132, 0x6026}, 191 {0x0136, 0x5555}, 192 {0x0138, 0x3700}, 193 {0x013a, 0x2000}, 194 {0x013b, 0x2000}, 195 {0x013c, 0x2005}, 196 {0x013f, 0x0000}, 197 {0x0142, 0x0000}, 198 {0x0145, 0x0002}, 199 {0x0146, 0x0000}, 200 {0x0147, 0x0000}, 201 {0x0148, 0x0000}, 202 {0x0149, 0x0000}, 203 {0x0150, 0x79a1}, 204 {0x0156, 0xaaaa}, 205 {0x0160, 0x4ec0}, 206 {0x0161, 0x0080}, 207 {0x0162, 0x0200}, 208 {0x0163, 0x0800}, 209 {0x0164, 0x0000}, 210 {0x0165, 0x0000}, 211 {0x0166, 0x0000}, 212 {0x0167, 0x000f}, 213 {0x0168, 0x000f}, 214 {0x0169, 0x0021}, 215 {0x0190, 0x413d}, 216 {0x0194, 0x0000}, 217 {0x0195, 0x0000}, 218 {0x0197, 0x0022}, 219 {0x0198, 0x0000}, 220 {0x0199, 0x0000}, 221 {0x01af, 0x0000}, 222 {0x01b0, 0x0400}, 223 {0x01b1, 0x0000}, 224 {0x01b2, 0x0000}, 225 {0x01b3, 0x0000}, 226 {0x01b4, 0x0000}, 227 {0x01b5, 0x0000}, 228 {0x01b6, 0x01c3}, 229 {0x01b7, 0x02a0}, 230 {0x01b8, 0x03e9}, 231 {0x01b9, 0x1389}, 232 {0x01ba, 0xc351}, 233 {0x01bb, 0x0009}, 234 {0x01bc, 0x0018}, 235 {0x01bd, 0x002a}, 236 {0x01be, 0x004c}, 237 {0x01bf, 0x0097}, 238 {0x01c0, 0x433d}, 239 {0x01c2, 0x0000}, 240 {0x01c3, 0x0000}, 241 {0x01c4, 0x0000}, 242 {0x01c5, 0x0000}, 243 {0x01c6, 0x0000}, 244 {0x01c7, 0x0000}, 245 {0x01c8, 0x40af}, 246 {0x01c9, 0x0702}, 247 {0x01ca, 0x0000}, 248 {0x01cb, 0x0000}, 249 {0x01cc, 0x5757}, 250 {0x01cd, 0x5757}, 251 {0x01ce, 0x5757}, 252 {0x01cf, 0x5757}, 253 {0x01d0, 0x5757}, 254 {0x01d1, 0x5757}, 255 {0x01d2, 0x5757}, 256 {0x01d3, 0x5757}, 257 {0x01d4, 0x5757}, 258 {0x01d5, 0x5757}, 259 {0x01d6, 0x0000}, 260 {0x01d7, 0x0008}, 261 {0x01d8, 0x0029}, 262 {0x01d9, 0x3333}, 263 {0x01da, 0x0000}, 264 {0x01db, 0x0004}, 265 {0x01dc, 0x0000}, 266 {0x01de, 0x7c00}, 267 {0x01df, 0x0320}, 268 {0x01e0, 0x06a1}, 269 {0x01e1, 0x0000}, 270 {0x01e2, 0x0000}, 271 {0x01e3, 0x0000}, 272 {0x01e4, 0x0000}, 273 {0x01e6, 0x0001}, 274 {0x01e7, 0x0000}, 275 {0x01e8, 0x0000}, 276 {0x01ea, 0x0000}, 277 {0x01eb, 0x0000}, 278 {0x01ec, 0x0000}, 279 {0x01ed, 0x0000}, 280 {0x01ee, 0x0000}, 281 {0x01ef, 0x0000}, 282 {0x01f0, 0x0000}, 283 {0x01f1, 0x0000}, 284 {0x01f2, 0x0000}, 285 {0x01f3, 0x0000}, 286 {0x01f4, 0x0000}, 287 {0x0210, 0x6297}, 288 {0x0211, 0xa005}, 289 {0x0212, 0x824c}, 290 {0x0213, 0xf7ff}, 291 {0x0214, 0xf24c}, 292 {0x0215, 0x0102}, 293 {0x0216, 0x00a3}, 294 {0x0217, 0x0048}, 295 {0x0218, 0xa2c0}, 296 {0x0219, 0x0400}, 297 {0x021a, 0x00c8}, 298 {0x021b, 0x00c0}, 299 {0x021c, 0x0000}, 300 {0x0250, 0x4500}, 301 {0x0251, 0x40b3}, 302 {0x0252, 0x0000}, 303 {0x0253, 0x0000}, 304 {0x0254, 0x0000}, 305 {0x0255, 0x0000}, 306 {0x0256, 0x0000}, 307 {0x0257, 0x0000}, 308 {0x0258, 0x0000}, 309 {0x0259, 0x0000}, 310 {0x025a, 0x0005}, 311 {0x0270, 0x0000}, 312 {0x02ff, 0x0110}, 313 {0x0300, 0x001f}, 314 {0x0301, 0x032c}, 315 {0x0302, 0x5f21}, 316 {0x0303, 0x4000}, 317 {0x0304, 0x4000}, 318 {0x0305, 0x06d5}, 319 {0x0306, 0x8000}, 320 {0x0307, 0x0700}, 321 {0x0310, 0x4560}, 322 {0x0311, 0xa4a8}, 323 {0x0312, 0x7418}, 324 {0x0313, 0x0000}, 325 {0x0314, 0x0006}, 326 {0x0315, 0xffff}, 327 {0x0316, 0xc400}, 328 {0x0317, 0x0000}, 329 {0x03c0, 0x7e00}, 330 {0x03c1, 0x8000}, 331 {0x03c2, 0x8000}, 332 {0x03c3, 0x8000}, 333 {0x03c4, 0x8000}, 334 {0x03c5, 0x8000}, 335 {0x03c6, 0x8000}, 336 {0x03c7, 0x8000}, 337 {0x03c8, 0x8000}, 338 {0x03c9, 0x8000}, 339 {0x03ca, 0x8000}, 340 {0x03cb, 0x8000}, 341 {0x03cc, 0x8000}, 342 {0x03d0, 0x0000}, 343 {0x03d1, 0x0000}, 344 {0x03d2, 0x0000}, 345 {0x03d3, 0x0000}, 346 {0x03d4, 0x2000}, 347 {0x03d5, 0x2000}, 348 {0x03d6, 0x0000}, 349 {0x03d7, 0x0000}, 350 {0x03d8, 0x2000}, 351 {0x03d9, 0x2000}, 352 {0x03da, 0x2000}, 353 {0x03db, 0x2000}, 354 {0x03dc, 0x0000}, 355 {0x03dd, 0x0000}, 356 {0x03de, 0x0000}, 357 {0x03df, 0x2000}, 358 {0x03e0, 0x0000}, 359 {0x03e1, 0x0000}, 360 {0x03e2, 0x0000}, 361 {0x03e3, 0x0000}, 362 {0x03e4, 0x0000}, 363 {0x03e5, 0x0000}, 364 {0x03e6, 0x0000}, 365 {0x03e7, 0x0000}, 366 {0x03e8, 0x0000}, 367 {0x03e9, 0x0000}, 368 {0x03ea, 0x0000}, 369 {0x03eb, 0x0000}, 370 {0x03ec, 0x0000}, 371 {0x03ed, 0x0000}, 372 {0x03ee, 0x0000}, 373 {0x03ef, 0x0000}, 374 {0x03f0, 0x0800}, 375 {0x03f1, 0x0800}, 376 {0x03f2, 0x0800}, 377 {0x03f3, 0x0800}, 378 }; 379 EXPORT_SYMBOL_GPL(rt5682_reg); 380 381 bool rt5682_volatile_register(struct device *dev, unsigned int reg) 382 { 383 switch (reg) { 384 case RT5682_RESET: 385 case RT5682_CBJ_CTRL_2: 386 case RT5682_INT_ST_1: 387 case RT5682_4BTN_IL_CMD_1: 388 case RT5682_AJD1_CTRL: 389 case RT5682_HP_CALIB_CTRL_1: 390 case RT5682_DEVICE_ID: 391 case RT5682_I2C_MODE: 392 case RT5682_HP_CALIB_CTRL_10: 393 case RT5682_EFUSE_CTRL_2: 394 case RT5682_JD_TOP_VC_VTRL: 395 case RT5682_HP_IMP_SENS_CTRL_19: 396 case RT5682_IL_CMD_1: 397 case RT5682_SAR_IL_CMD_2: 398 case RT5682_SAR_IL_CMD_4: 399 case RT5682_SAR_IL_CMD_10: 400 case RT5682_SAR_IL_CMD_11: 401 case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11: 402 case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11: 403 return true; 404 default: 405 return false; 406 } 407 } 408 EXPORT_SYMBOL_GPL(rt5682_volatile_register); 409 410 bool rt5682_readable_register(struct device *dev, unsigned int reg) 411 { 412 switch (reg) { 413 case RT5682_RESET: 414 case RT5682_VERSION_ID: 415 case RT5682_VENDOR_ID: 416 case RT5682_DEVICE_ID: 417 case RT5682_HP_CTRL_1: 418 case RT5682_HP_CTRL_2: 419 case RT5682_HPL_GAIN: 420 case RT5682_HPR_GAIN: 421 case RT5682_I2C_CTRL: 422 case RT5682_CBJ_BST_CTRL: 423 case RT5682_CBJ_CTRL_1: 424 case RT5682_CBJ_CTRL_2: 425 case RT5682_CBJ_CTRL_3: 426 case RT5682_CBJ_CTRL_4: 427 case RT5682_CBJ_CTRL_5: 428 case RT5682_CBJ_CTRL_6: 429 case RT5682_CBJ_CTRL_7: 430 case RT5682_DAC1_DIG_VOL: 431 case RT5682_STO1_ADC_DIG_VOL: 432 case RT5682_STO1_ADC_BOOST: 433 case RT5682_HP_IMP_GAIN_1: 434 case RT5682_HP_IMP_GAIN_2: 435 case RT5682_SIDETONE_CTRL: 436 case RT5682_STO1_ADC_MIXER: 437 case RT5682_AD_DA_MIXER: 438 case RT5682_STO1_DAC_MIXER: 439 case RT5682_A_DAC1_MUX: 440 case RT5682_DIG_INF2_DATA: 441 case RT5682_REC_MIXER: 442 case RT5682_CAL_REC: 443 case RT5682_ALC_BACK_GAIN: 444 case RT5682_PWR_DIG_1: 445 case RT5682_PWR_DIG_2: 446 case RT5682_PWR_ANLG_1: 447 case RT5682_PWR_ANLG_2: 448 case RT5682_PWR_ANLG_3: 449 case RT5682_PWR_MIXER: 450 case RT5682_PWR_VOL: 451 case RT5682_CLK_DET: 452 case RT5682_RESET_LPF_CTRL: 453 case RT5682_RESET_HPF_CTRL: 454 case RT5682_DMIC_CTRL_1: 455 case RT5682_I2S1_SDP: 456 case RT5682_I2S2_SDP: 457 case RT5682_ADDA_CLK_1: 458 case RT5682_ADDA_CLK_2: 459 case RT5682_I2S1_F_DIV_CTRL_1: 460 case RT5682_I2S1_F_DIV_CTRL_2: 461 case RT5682_TDM_CTRL: 462 case RT5682_TDM_ADDA_CTRL_1: 463 case RT5682_TDM_ADDA_CTRL_2: 464 case RT5682_DATA_SEL_CTRL_1: 465 case RT5682_TDM_TCON_CTRL: 466 case RT5682_GLB_CLK: 467 case RT5682_PLL_CTRL_1: 468 case RT5682_PLL_CTRL_2: 469 case RT5682_PLL_TRACK_1: 470 case RT5682_PLL_TRACK_2: 471 case RT5682_PLL_TRACK_3: 472 case RT5682_PLL_TRACK_4: 473 case RT5682_PLL_TRACK_5: 474 case RT5682_PLL_TRACK_6: 475 case RT5682_PLL_TRACK_11: 476 case RT5682_SDW_REF_CLK: 477 case RT5682_DEPOP_1: 478 case RT5682_DEPOP_2: 479 case RT5682_HP_CHARGE_PUMP_1: 480 case RT5682_HP_CHARGE_PUMP_2: 481 case RT5682_MICBIAS_1: 482 case RT5682_MICBIAS_2: 483 case RT5682_PLL_TRACK_12: 484 case RT5682_PLL_TRACK_14: 485 case RT5682_PLL2_CTRL_1: 486 case RT5682_PLL2_CTRL_2: 487 case RT5682_PLL2_CTRL_3: 488 case RT5682_PLL2_CTRL_4: 489 case RT5682_RC_CLK_CTRL: 490 case RT5682_I2S_M_CLK_CTRL_1: 491 case RT5682_I2S2_F_DIV_CTRL_1: 492 case RT5682_I2S2_F_DIV_CTRL_2: 493 case RT5682_EQ_CTRL_1: 494 case RT5682_EQ_CTRL_2: 495 case RT5682_IRQ_CTRL_1: 496 case RT5682_IRQ_CTRL_2: 497 case RT5682_IRQ_CTRL_3: 498 case RT5682_IRQ_CTRL_4: 499 case RT5682_INT_ST_1: 500 case RT5682_GPIO_CTRL_1: 501 case RT5682_GPIO_CTRL_2: 502 case RT5682_GPIO_CTRL_3: 503 case RT5682_HP_AMP_DET_CTRL_1: 504 case RT5682_HP_AMP_DET_CTRL_2: 505 case RT5682_MID_HP_AMP_DET: 506 case RT5682_LOW_HP_AMP_DET: 507 case RT5682_DELAY_BUF_CTRL: 508 case RT5682_SV_ZCD_1: 509 case RT5682_SV_ZCD_2: 510 case RT5682_IL_CMD_1: 511 case RT5682_IL_CMD_2: 512 case RT5682_IL_CMD_3: 513 case RT5682_IL_CMD_4: 514 case RT5682_IL_CMD_5: 515 case RT5682_IL_CMD_6: 516 case RT5682_4BTN_IL_CMD_1: 517 case RT5682_4BTN_IL_CMD_2: 518 case RT5682_4BTN_IL_CMD_3: 519 case RT5682_4BTN_IL_CMD_4: 520 case RT5682_4BTN_IL_CMD_5: 521 case RT5682_4BTN_IL_CMD_6: 522 case RT5682_4BTN_IL_CMD_7: 523 case RT5682_ADC_STO1_HP_CTRL_1: 524 case RT5682_ADC_STO1_HP_CTRL_2: 525 case RT5682_AJD1_CTRL: 526 case RT5682_JD1_THD: 527 case RT5682_JD2_THD: 528 case RT5682_JD_CTRL_1: 529 case RT5682_DUMMY_1: 530 case RT5682_DUMMY_2: 531 case RT5682_DUMMY_3: 532 case RT5682_DAC_ADC_DIG_VOL1: 533 case RT5682_BIAS_CUR_CTRL_2: 534 case RT5682_BIAS_CUR_CTRL_3: 535 case RT5682_BIAS_CUR_CTRL_4: 536 case RT5682_BIAS_CUR_CTRL_5: 537 case RT5682_BIAS_CUR_CTRL_6: 538 case RT5682_BIAS_CUR_CTRL_7: 539 case RT5682_BIAS_CUR_CTRL_8: 540 case RT5682_BIAS_CUR_CTRL_9: 541 case RT5682_BIAS_CUR_CTRL_10: 542 case RT5682_VREF_REC_OP_FB_CAP_CTRL: 543 case RT5682_CHARGE_PUMP_1: 544 case RT5682_DIG_IN_CTRL_1: 545 case RT5682_PAD_DRIVING_CTRL: 546 case RT5682_SOFT_RAMP_DEPOP: 547 case RT5682_CHOP_DAC: 548 case RT5682_CHOP_ADC: 549 case RT5682_CALIB_ADC_CTRL: 550 case RT5682_VOL_TEST: 551 case RT5682_SPKVDD_DET_STA: 552 case RT5682_TEST_MODE_CTRL_1: 553 case RT5682_TEST_MODE_CTRL_2: 554 case RT5682_TEST_MODE_CTRL_3: 555 case RT5682_TEST_MODE_CTRL_4: 556 case RT5682_TEST_MODE_CTRL_5: 557 case RT5682_PLL1_INTERNAL: 558 case RT5682_PLL2_INTERNAL: 559 case RT5682_STO_NG2_CTRL_1: 560 case RT5682_STO_NG2_CTRL_2: 561 case RT5682_STO_NG2_CTRL_3: 562 case RT5682_STO_NG2_CTRL_4: 563 case RT5682_STO_NG2_CTRL_5: 564 case RT5682_STO_NG2_CTRL_6: 565 case RT5682_STO_NG2_CTRL_7: 566 case RT5682_STO_NG2_CTRL_8: 567 case RT5682_STO_NG2_CTRL_9: 568 case RT5682_STO_NG2_CTRL_10: 569 case RT5682_STO1_DAC_SIL_DET: 570 case RT5682_SIL_PSV_CTRL1: 571 case RT5682_SIL_PSV_CTRL2: 572 case RT5682_SIL_PSV_CTRL3: 573 case RT5682_SIL_PSV_CTRL4: 574 case RT5682_SIL_PSV_CTRL5: 575 case RT5682_HP_IMP_SENS_CTRL_01: 576 case RT5682_HP_IMP_SENS_CTRL_02: 577 case RT5682_HP_IMP_SENS_CTRL_03: 578 case RT5682_HP_IMP_SENS_CTRL_04: 579 case RT5682_HP_IMP_SENS_CTRL_05: 580 case RT5682_HP_IMP_SENS_CTRL_06: 581 case RT5682_HP_IMP_SENS_CTRL_07: 582 case RT5682_HP_IMP_SENS_CTRL_08: 583 case RT5682_HP_IMP_SENS_CTRL_09: 584 case RT5682_HP_IMP_SENS_CTRL_10: 585 case RT5682_HP_IMP_SENS_CTRL_11: 586 case RT5682_HP_IMP_SENS_CTRL_12: 587 case RT5682_HP_IMP_SENS_CTRL_13: 588 case RT5682_HP_IMP_SENS_CTRL_14: 589 case RT5682_HP_IMP_SENS_CTRL_15: 590 case RT5682_HP_IMP_SENS_CTRL_16: 591 case RT5682_HP_IMP_SENS_CTRL_17: 592 case RT5682_HP_IMP_SENS_CTRL_18: 593 case RT5682_HP_IMP_SENS_CTRL_19: 594 case RT5682_HP_IMP_SENS_CTRL_20: 595 case RT5682_HP_IMP_SENS_CTRL_21: 596 case RT5682_HP_IMP_SENS_CTRL_22: 597 case RT5682_HP_IMP_SENS_CTRL_23: 598 case RT5682_HP_IMP_SENS_CTRL_24: 599 case RT5682_HP_IMP_SENS_CTRL_25: 600 case RT5682_HP_IMP_SENS_CTRL_26: 601 case RT5682_HP_IMP_SENS_CTRL_27: 602 case RT5682_HP_IMP_SENS_CTRL_28: 603 case RT5682_HP_IMP_SENS_CTRL_29: 604 case RT5682_HP_IMP_SENS_CTRL_30: 605 case RT5682_HP_IMP_SENS_CTRL_31: 606 case RT5682_HP_IMP_SENS_CTRL_32: 607 case RT5682_HP_IMP_SENS_CTRL_33: 608 case RT5682_HP_IMP_SENS_CTRL_34: 609 case RT5682_HP_IMP_SENS_CTRL_35: 610 case RT5682_HP_IMP_SENS_CTRL_36: 611 case RT5682_HP_IMP_SENS_CTRL_37: 612 case RT5682_HP_IMP_SENS_CTRL_38: 613 case RT5682_HP_IMP_SENS_CTRL_39: 614 case RT5682_HP_IMP_SENS_CTRL_40: 615 case RT5682_HP_IMP_SENS_CTRL_41: 616 case RT5682_HP_IMP_SENS_CTRL_42: 617 case RT5682_HP_IMP_SENS_CTRL_43: 618 case RT5682_HP_LOGIC_CTRL_1: 619 case RT5682_HP_LOGIC_CTRL_2: 620 case RT5682_HP_LOGIC_CTRL_3: 621 case RT5682_HP_CALIB_CTRL_1: 622 case RT5682_HP_CALIB_CTRL_2: 623 case RT5682_HP_CALIB_CTRL_3: 624 case RT5682_HP_CALIB_CTRL_4: 625 case RT5682_HP_CALIB_CTRL_5: 626 case RT5682_HP_CALIB_CTRL_6: 627 case RT5682_HP_CALIB_CTRL_7: 628 case RT5682_HP_CALIB_CTRL_9: 629 case RT5682_HP_CALIB_CTRL_10: 630 case RT5682_HP_CALIB_CTRL_11: 631 case RT5682_HP_CALIB_STA_1: 632 case RT5682_HP_CALIB_STA_2: 633 case RT5682_HP_CALIB_STA_3: 634 case RT5682_HP_CALIB_STA_4: 635 case RT5682_HP_CALIB_STA_5: 636 case RT5682_HP_CALIB_STA_6: 637 case RT5682_HP_CALIB_STA_7: 638 case RT5682_HP_CALIB_STA_8: 639 case RT5682_HP_CALIB_STA_9: 640 case RT5682_HP_CALIB_STA_10: 641 case RT5682_HP_CALIB_STA_11: 642 case RT5682_SAR_IL_CMD_1: 643 case RT5682_SAR_IL_CMD_2: 644 case RT5682_SAR_IL_CMD_3: 645 case RT5682_SAR_IL_CMD_4: 646 case RT5682_SAR_IL_CMD_5: 647 case RT5682_SAR_IL_CMD_6: 648 case RT5682_SAR_IL_CMD_7: 649 case RT5682_SAR_IL_CMD_8: 650 case RT5682_SAR_IL_CMD_9: 651 case RT5682_SAR_IL_CMD_10: 652 case RT5682_SAR_IL_CMD_11: 653 case RT5682_SAR_IL_CMD_12: 654 case RT5682_SAR_IL_CMD_13: 655 case RT5682_EFUSE_CTRL_1: 656 case RT5682_EFUSE_CTRL_2: 657 case RT5682_EFUSE_CTRL_3: 658 case RT5682_EFUSE_CTRL_4: 659 case RT5682_EFUSE_CTRL_5: 660 case RT5682_EFUSE_CTRL_6: 661 case RT5682_EFUSE_CTRL_7: 662 case RT5682_EFUSE_CTRL_8: 663 case RT5682_EFUSE_CTRL_9: 664 case RT5682_EFUSE_CTRL_10: 665 case RT5682_EFUSE_CTRL_11: 666 case RT5682_JD_TOP_VC_VTRL: 667 case RT5682_DRC1_CTRL_0: 668 case RT5682_DRC1_CTRL_1: 669 case RT5682_DRC1_CTRL_2: 670 case RT5682_DRC1_CTRL_3: 671 case RT5682_DRC1_CTRL_4: 672 case RT5682_DRC1_CTRL_5: 673 case RT5682_DRC1_CTRL_6: 674 case RT5682_DRC1_HARD_LMT_CTRL_1: 675 case RT5682_DRC1_HARD_LMT_CTRL_2: 676 case RT5682_DRC1_PRIV_1: 677 case RT5682_DRC1_PRIV_2: 678 case RT5682_DRC1_PRIV_3: 679 case RT5682_DRC1_PRIV_4: 680 case RT5682_DRC1_PRIV_5: 681 case RT5682_DRC1_PRIV_6: 682 case RT5682_DRC1_PRIV_7: 683 case RT5682_DRC1_PRIV_8: 684 case RT5682_EQ_AUTO_RCV_CTRL1: 685 case RT5682_EQ_AUTO_RCV_CTRL2: 686 case RT5682_EQ_AUTO_RCV_CTRL3: 687 case RT5682_EQ_AUTO_RCV_CTRL4: 688 case RT5682_EQ_AUTO_RCV_CTRL5: 689 case RT5682_EQ_AUTO_RCV_CTRL6: 690 case RT5682_EQ_AUTO_RCV_CTRL7: 691 case RT5682_EQ_AUTO_RCV_CTRL8: 692 case RT5682_EQ_AUTO_RCV_CTRL9: 693 case RT5682_EQ_AUTO_RCV_CTRL10: 694 case RT5682_EQ_AUTO_RCV_CTRL11: 695 case RT5682_EQ_AUTO_RCV_CTRL12: 696 case RT5682_EQ_AUTO_RCV_CTRL13: 697 case RT5682_ADC_L_EQ_LPF1_A1: 698 case RT5682_R_EQ_LPF1_A1: 699 case RT5682_L_EQ_LPF1_H0: 700 case RT5682_R_EQ_LPF1_H0: 701 case RT5682_L_EQ_BPF1_A1: 702 case RT5682_R_EQ_BPF1_A1: 703 case RT5682_L_EQ_BPF1_A2: 704 case RT5682_R_EQ_BPF1_A2: 705 case RT5682_L_EQ_BPF1_H0: 706 case RT5682_R_EQ_BPF1_H0: 707 case RT5682_L_EQ_BPF2_A1: 708 case RT5682_R_EQ_BPF2_A1: 709 case RT5682_L_EQ_BPF2_A2: 710 case RT5682_R_EQ_BPF2_A2: 711 case RT5682_L_EQ_BPF2_H0: 712 case RT5682_R_EQ_BPF2_H0: 713 case RT5682_L_EQ_BPF3_A1: 714 case RT5682_R_EQ_BPF3_A1: 715 case RT5682_L_EQ_BPF3_A2: 716 case RT5682_R_EQ_BPF3_A2: 717 case RT5682_L_EQ_BPF3_H0: 718 case RT5682_R_EQ_BPF3_H0: 719 case RT5682_L_EQ_BPF4_A1: 720 case RT5682_R_EQ_BPF4_A1: 721 case RT5682_L_EQ_BPF4_A2: 722 case RT5682_R_EQ_BPF4_A2: 723 case RT5682_L_EQ_BPF4_H0: 724 case RT5682_R_EQ_BPF4_H0: 725 case RT5682_L_EQ_HPF1_A1: 726 case RT5682_R_EQ_HPF1_A1: 727 case RT5682_L_EQ_HPF1_H0: 728 case RT5682_R_EQ_HPF1_H0: 729 case RT5682_L_EQ_PRE_VOL: 730 case RT5682_R_EQ_PRE_VOL: 731 case RT5682_L_EQ_POST_VOL: 732 case RT5682_R_EQ_POST_VOL: 733 case RT5682_I2C_MODE: 734 return true; 735 default: 736 return false; 737 } 738 } 739 EXPORT_SYMBOL_GPL(rt5682_readable_register); 740 741 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); 742 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); 743 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); 744 745 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ 746 static const DECLARE_TLV_DB_RANGE(bst_tlv, 747 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), 748 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), 749 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 750 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), 751 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), 752 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), 753 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) 754 ); 755 756 /* Interface data select */ 757 static const char * const rt5682_data_select[] = { 758 "L/R", "R/L", "L/L", "R/R" 759 }; 760 761 static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum, 762 RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select); 763 764 static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum, 765 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select); 766 767 static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum, 768 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select); 769 770 static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum, 771 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select); 772 773 static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum, 774 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select); 775 776 static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux = 777 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum); 778 779 static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux = 780 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum); 781 782 static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux = 783 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum); 784 785 static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux = 786 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum); 787 788 static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux = 789 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum); 790 791 static const char * const rt5682_dac_select[] = { 792 "IF1", "SOUND" 793 }; 794 795 static SOC_ENUM_SINGLE_DECL(rt5682_dacl_enum, 796 RT5682_AD_DA_MIXER, RT5682_DAC1_L_SEL_SFT, rt5682_dac_select); 797 798 static const struct snd_kcontrol_new rt5682_dac_l_mux = 799 SOC_DAPM_ENUM("DAC L Mux", rt5682_dacl_enum); 800 801 static SOC_ENUM_SINGLE_DECL(rt5682_dacr_enum, 802 RT5682_AD_DA_MIXER, RT5682_DAC1_R_SEL_SFT, rt5682_dac_select); 803 804 static const struct snd_kcontrol_new rt5682_dac_r_mux = 805 SOC_DAPM_ENUM("DAC R Mux", rt5682_dacr_enum); 806 807 void rt5682_reset(struct rt5682_priv *rt5682) 808 { 809 regmap_write(rt5682->regmap, RT5682_RESET, 0); 810 if (!rt5682->is_sdw) 811 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 1); 812 } 813 EXPORT_SYMBOL_GPL(rt5682_reset); 814 815 /** 816 * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters 817 * @component: SoC audio component device. 818 * @filter_mask: mask of filters. 819 * @clk_src: clock source 820 * 821 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can 822 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to 823 * support special i2s clock format such as Intel's 100fs(100 * sampling rate). 824 * ASRC function will track i2s clock and generate a corresponding system clock 825 * for codec. This function provides an API to select the clock source for a 826 * set of filters specified by the mask. And the component driver will turn on 827 * ASRC for these filters if ASRC is selected as their clock source. 828 */ 829 int rt5682_sel_asrc_clk_src(struct snd_soc_component *component, 830 unsigned int filter_mask, unsigned int clk_src) 831 { 832 switch (clk_src) { 833 case RT5682_CLK_SEL_SYS: 834 case RT5682_CLK_SEL_I2S1_ASRC: 835 case RT5682_CLK_SEL_I2S2_ASRC: 836 break; 837 838 default: 839 return -EINVAL; 840 } 841 842 if (filter_mask & RT5682_DA_STEREO1_FILTER) { 843 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2, 844 RT5682_FILTER_CLK_SEL_MASK, 845 clk_src << RT5682_FILTER_CLK_SEL_SFT); 846 } 847 848 if (filter_mask & RT5682_AD_STEREO1_FILTER) { 849 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3, 850 RT5682_FILTER_CLK_SEL_MASK, 851 clk_src << RT5682_FILTER_CLK_SEL_SFT); 852 } 853 854 return 0; 855 } 856 EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src); 857 858 static int rt5682_button_detect(struct snd_soc_component *component) 859 { 860 int btn_type, val; 861 862 val = snd_soc_component_read(component, RT5682_4BTN_IL_CMD_1); 863 btn_type = val & 0xfff0; 864 snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val); 865 dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type); 866 snd_soc_component_update_bits(component, 867 RT5682_SAR_IL_CMD_2, 0x10, 0x10); 868 869 return btn_type; 870 } 871 872 static void rt5682_enable_push_button_irq(struct snd_soc_component *component, 873 bool enable) 874 { 875 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 876 877 if (enable) { 878 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 879 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN); 880 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13, 881 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN); 882 snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040); 883 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 884 RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK, 885 RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR); 886 if (rt5682->is_sdw) 887 snd_soc_component_update_bits(component, 888 RT5682_IRQ_CTRL_3, 889 RT5682_IL_IRQ_MASK | RT5682_IL_IRQ_TYPE_MASK, 890 RT5682_IL_IRQ_EN | RT5682_IL_IRQ_PUL); 891 else 892 snd_soc_component_update_bits(component, 893 RT5682_IRQ_CTRL_3, RT5682_IL_IRQ_MASK, 894 RT5682_IL_IRQ_EN); 895 } else { 896 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3, 897 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS); 898 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1, 899 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS); 900 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 901 RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS); 902 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2, 903 RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST); 904 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13, 905 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE); 906 } 907 } 908 909 /** 910 * rt5682_headset_detect - Detect headset. 911 * @component: SoC audio component device. 912 * @jack_insert: Jack insert or not. 913 * 914 * Detect whether is headset or not when jack inserted. 915 * 916 * Returns detect status. 917 */ 918 int rt5682_headset_detect(struct snd_soc_component *component, int jack_insert) 919 { 920 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 921 struct snd_soc_dapm_context *dapm = &component->dapm; 922 unsigned int val, count; 923 924 if (jack_insert) { 925 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 926 RT5682_PWR_VREF2 | RT5682_PWR_MB, 927 RT5682_PWR_VREF2 | RT5682_PWR_MB); 928 snd_soc_component_update_bits(component, 929 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0); 930 usleep_range(15000, 20000); 931 snd_soc_component_update_bits(component, 932 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2); 933 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3, 934 RT5682_PWR_CBJ, RT5682_PWR_CBJ); 935 snd_soc_component_update_bits(component, 936 RT5682_HP_CHARGE_PUMP_1, 937 RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 0); 938 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 939 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH); 940 941 count = 0; 942 val = snd_soc_component_read(component, RT5682_CBJ_CTRL_2) 943 & RT5682_JACK_TYPE_MASK; 944 while (val == 0 && count < 50) { 945 usleep_range(10000, 15000); 946 val = snd_soc_component_read(component, 947 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK; 948 count++; 949 } 950 951 switch (val) { 952 case 0x1: 953 case 0x2: 954 rt5682->jack_type = SND_JACK_HEADSET; 955 rt5682_enable_push_button_irq(component, true); 956 break; 957 default: 958 rt5682->jack_type = SND_JACK_HEADPHONE; 959 break; 960 } 961 962 snd_soc_component_update_bits(component, 963 RT5682_HP_CHARGE_PUMP_1, 964 RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 965 RT5682_OSW_L_EN | RT5682_OSW_R_EN); 966 snd_soc_component_update_bits(component, RT5682_MICBIAS_2, 967 RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK, 968 RT5682_PWR_CLK25M_PU | RT5682_PWR_CLK1M_PU); 969 } else { 970 rt5682_enable_push_button_irq(component, false); 971 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1, 972 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW); 973 if (!snd_soc_dapm_get_pin_status(dapm, "MICBIAS")) 974 snd_soc_component_update_bits(component, 975 RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0); 976 if (!snd_soc_dapm_get_pin_status(dapm, "Vref2")) 977 snd_soc_component_update_bits(component, 978 RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0); 979 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3, 980 RT5682_PWR_CBJ, 0); 981 snd_soc_component_update_bits(component, RT5682_MICBIAS_2, 982 RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK, 983 RT5682_PWR_CLK25M_PD | RT5682_PWR_CLK1M_PD); 984 985 rt5682->jack_type = 0; 986 } 987 988 dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type); 989 return rt5682->jack_type; 990 } 991 EXPORT_SYMBOL_GPL(rt5682_headset_detect); 992 993 static int rt5682_set_jack_detect(struct snd_soc_component *component, 994 struct snd_soc_jack *hs_jack, void *data) 995 { 996 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 997 998 rt5682->hs_jack = hs_jack; 999 1000 if (!hs_jack) { 1001 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1002 RT5682_JD1_EN_MASK, RT5682_JD1_DIS); 1003 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 1004 RT5682_POW_JDH | RT5682_POW_JDL, 0); 1005 cancel_delayed_work_sync(&rt5682->jack_detect_work); 1006 1007 return 0; 1008 } 1009 1010 if (!rt5682->is_sdw) { 1011 switch (rt5682->pdata.jd_src) { 1012 case RT5682_JD1: 1013 snd_soc_component_update_bits(component, 1014 RT5682_CBJ_CTRL_2, RT5682_EXT_JD_SRC, 1015 RT5682_EXT_JD_SRC_MANUAL); 1016 snd_soc_component_write(component, RT5682_CBJ_CTRL_1, 1017 0xd042); 1018 snd_soc_component_update_bits(component, 1019 RT5682_CBJ_CTRL_3, RT5682_CBJ_IN_BUF_EN, 1020 RT5682_CBJ_IN_BUF_EN); 1021 snd_soc_component_update_bits(component, 1022 RT5682_SAR_IL_CMD_1, RT5682_SAR_POW_MASK, 1023 RT5682_SAR_POW_EN); 1024 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, 1025 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ); 1026 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 1027 RT5682_POW_IRQ | RT5682_POW_JDH | 1028 RT5682_POW_ANA, RT5682_POW_IRQ | 1029 RT5682_POW_JDH | RT5682_POW_ANA); 1030 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2, 1031 RT5682_PWR_JDH, RT5682_PWR_JDH); 1032 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1033 RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK, 1034 RT5682_JD1_EN | RT5682_JD1_POL_NOR); 1035 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_4, 1036 0x7f7f, (rt5682->pdata.btndet_delay << 8 | 1037 rt5682->pdata.btndet_delay)); 1038 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_5, 1039 0x7f7f, (rt5682->pdata.btndet_delay << 8 | 1040 rt5682->pdata.btndet_delay)); 1041 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_6, 1042 0x7f7f, (rt5682->pdata.btndet_delay << 8 | 1043 rt5682->pdata.btndet_delay)); 1044 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_7, 1045 0x7f7f, (rt5682->pdata.btndet_delay << 8 | 1046 rt5682->pdata.btndet_delay)); 1047 mod_delayed_work(system_power_efficient_wq, 1048 &rt5682->jack_detect_work, 1049 msecs_to_jiffies(250)); 1050 break; 1051 1052 case RT5682_JD_NULL: 1053 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, 1054 RT5682_JD1_EN_MASK, RT5682_JD1_DIS); 1055 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, 1056 RT5682_POW_JDH | RT5682_POW_JDL, 0); 1057 break; 1058 1059 default: 1060 dev_warn(component->dev, "Wrong JD source\n"); 1061 break; 1062 } 1063 } 1064 1065 return 0; 1066 } 1067 1068 void rt5682_jack_detect_handler(struct work_struct *work) 1069 { 1070 struct rt5682_priv *rt5682 = 1071 container_of(work, struct rt5682_priv, jack_detect_work.work); 1072 int val, btn_type; 1073 1074 while (!rt5682->component) 1075 usleep_range(10000, 15000); 1076 1077 while (!rt5682->component->card->instantiated) 1078 usleep_range(10000, 15000); 1079 1080 mutex_lock(&rt5682->calibrate_mutex); 1081 1082 val = snd_soc_component_read(rt5682->component, RT5682_AJD1_CTRL) 1083 & RT5682_JDH_RS_MASK; 1084 if (!val) { 1085 /* jack in */ 1086 if (rt5682->jack_type == 0) { 1087 /* jack was out, report jack type */ 1088 rt5682->jack_type = 1089 rt5682_headset_detect(rt5682->component, 1); 1090 } else if ((rt5682->jack_type & SND_JACK_HEADSET) == 1091 SND_JACK_HEADSET) { 1092 /* jack is already in, report button event */ 1093 rt5682->jack_type = SND_JACK_HEADSET; 1094 btn_type = rt5682_button_detect(rt5682->component); 1095 /** 1096 * rt5682 can report three kinds of button behavior, 1097 * one click, double click and hold. However, 1098 * currently we will report button pressed/released 1099 * event. So all the three button behaviors are 1100 * treated as button pressed. 1101 */ 1102 switch (btn_type) { 1103 case 0x8000: 1104 case 0x4000: 1105 case 0x2000: 1106 rt5682->jack_type |= SND_JACK_BTN_0; 1107 break; 1108 case 0x1000: 1109 case 0x0800: 1110 case 0x0400: 1111 rt5682->jack_type |= SND_JACK_BTN_1; 1112 break; 1113 case 0x0200: 1114 case 0x0100: 1115 case 0x0080: 1116 rt5682->jack_type |= SND_JACK_BTN_2; 1117 break; 1118 case 0x0040: 1119 case 0x0020: 1120 case 0x0010: 1121 rt5682->jack_type |= SND_JACK_BTN_3; 1122 break; 1123 case 0x0000: /* unpressed */ 1124 break; 1125 default: 1126 dev_err(rt5682->component->dev, 1127 "Unexpected button code 0x%04x\n", 1128 btn_type); 1129 break; 1130 } 1131 } 1132 } else { 1133 /* jack out */ 1134 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0); 1135 } 1136 1137 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type, 1138 SND_JACK_HEADSET | 1139 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1140 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1141 1142 if (!rt5682->is_sdw) { 1143 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1144 SND_JACK_BTN_2 | SND_JACK_BTN_3)) 1145 schedule_delayed_work(&rt5682->jd_check_work, 0); 1146 else 1147 cancel_delayed_work_sync(&rt5682->jd_check_work); 1148 } 1149 1150 mutex_unlock(&rt5682->calibrate_mutex); 1151 } 1152 EXPORT_SYMBOL_GPL(rt5682_jack_detect_handler); 1153 1154 static const struct snd_kcontrol_new rt5682_snd_controls[] = { 1155 /* DAC Digital Volume */ 1156 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL, 1157 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 87, 0, dac_vol_tlv), 1158 1159 /* IN Boost Volume */ 1160 SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL, 1161 RT5682_BST_CBJ_SFT, 8, 0, bst_tlv), 1162 1163 /* ADC Digital Volume Control */ 1164 SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL, 1165 RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1), 1166 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL, 1167 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv), 1168 1169 /* ADC Boost Volume Control */ 1170 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST, 1171 RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT, 1172 3, 0, adc_bst_tlv), 1173 }; 1174 1175 static int rt5682_div_sel(struct rt5682_priv *rt5682, 1176 int target, const int div[], int size) 1177 { 1178 int i; 1179 1180 if (rt5682->sysclk < target) { 1181 dev_err(rt5682->component->dev, 1182 "sysclk rate %d is too low\n", rt5682->sysclk); 1183 return 0; 1184 } 1185 1186 for (i = 0; i < size - 1; i++) { 1187 dev_dbg(rt5682->component->dev, "div[%d]=%d\n", i, div[i]); 1188 if (target * div[i] == rt5682->sysclk) 1189 return i; 1190 if (target * div[i + 1] > rt5682->sysclk) { 1191 dev_dbg(rt5682->component->dev, 1192 "can't find div for sysclk %d\n", 1193 rt5682->sysclk); 1194 return i; 1195 } 1196 } 1197 1198 if (target * div[i] < rt5682->sysclk) 1199 dev_err(rt5682->component->dev, 1200 "sysclk rate %d is too high\n", rt5682->sysclk); 1201 1202 return size - 1; 1203 } 1204 1205 /** 1206 * set_dmic_clk - Set parameter of dmic. 1207 * 1208 * @w: DAPM widget. 1209 * @kcontrol: The kcontrol of this widget. 1210 * @event: Event id. 1211 * 1212 * Choose dmic clock between 1MHz and 3MHz. 1213 * It is better for clock to approximate 3MHz. 1214 */ 1215 static int set_dmic_clk(struct snd_soc_dapm_widget *w, 1216 struct snd_kcontrol *kcontrol, int event) 1217 { 1218 struct snd_soc_component *component = 1219 snd_soc_dapm_to_component(w->dapm); 1220 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1221 int idx = -EINVAL, dmic_clk_rate = 3072000; 1222 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128}; 1223 1224 if (rt5682->pdata.dmic_clk_rate) 1225 dmic_clk_rate = rt5682->pdata.dmic_clk_rate; 1226 1227 idx = rt5682_div_sel(rt5682, dmic_clk_rate, div, ARRAY_SIZE(div)); 1228 1229 snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1, 1230 RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT); 1231 1232 return 0; 1233 } 1234 1235 static int set_filter_clk(struct snd_soc_dapm_widget *w, 1236 struct snd_kcontrol *kcontrol, int event) 1237 { 1238 struct snd_soc_component *component = 1239 snd_soc_dapm_to_component(w->dapm); 1240 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1241 int ref, val, reg, idx = -EINVAL; 1242 static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48}; 1243 static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48}; 1244 1245 if (rt5682->is_sdw) 1246 return 0; 1247 1248 val = snd_soc_component_read(component, RT5682_GPIO_CTRL_1) & 1249 RT5682_GP4_PIN_MASK; 1250 if (w->shift == RT5682_PWR_ADC_S1F_BIT && 1251 val == RT5682_GP4_PIN_ADCDAT2) 1252 ref = 256 * rt5682->lrck[RT5682_AIF2]; 1253 else 1254 ref = 256 * rt5682->lrck[RT5682_AIF1]; 1255 1256 idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f)); 1257 1258 if (w->shift == RT5682_PWR_ADC_S1F_BIT) 1259 reg = RT5682_PLL_TRACK_3; 1260 else 1261 reg = RT5682_PLL_TRACK_2; 1262 1263 snd_soc_component_update_bits(component, reg, 1264 RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT); 1265 1266 /* select over sample rate */ 1267 for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) { 1268 if (rt5682->sysclk <= 12288000 * div_o[idx]) 1269 break; 1270 } 1271 1272 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1, 1273 RT5682_ADC_OSR_MASK | RT5682_DAC_OSR_MASK, 1274 (idx << RT5682_ADC_OSR_SFT) | (idx << RT5682_DAC_OSR_SFT)); 1275 1276 return 0; 1277 } 1278 1279 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w, 1280 struct snd_soc_dapm_widget *sink) 1281 { 1282 unsigned int val; 1283 struct snd_soc_component *component = 1284 snd_soc_dapm_to_component(w->dapm); 1285 1286 val = snd_soc_component_read(component, RT5682_GLB_CLK); 1287 val &= RT5682_SCLK_SRC_MASK; 1288 if (val == RT5682_SCLK_SRC_PLL1) 1289 return 1; 1290 else 1291 return 0; 1292 } 1293 1294 static int is_sys_clk_from_pll2(struct snd_soc_dapm_widget *w, 1295 struct snd_soc_dapm_widget *sink) 1296 { 1297 unsigned int val; 1298 struct snd_soc_component *component = 1299 snd_soc_dapm_to_component(w->dapm); 1300 1301 val = snd_soc_component_read(component, RT5682_GLB_CLK); 1302 val &= RT5682_SCLK_SRC_MASK; 1303 if (val == RT5682_SCLK_SRC_PLL2) 1304 return 1; 1305 else 1306 return 0; 1307 } 1308 1309 static int is_using_asrc(struct snd_soc_dapm_widget *w, 1310 struct snd_soc_dapm_widget *sink) 1311 { 1312 unsigned int reg, shift, val; 1313 struct snd_soc_component *component = 1314 snd_soc_dapm_to_component(w->dapm); 1315 1316 switch (w->shift) { 1317 case RT5682_ADC_STO1_ASRC_SFT: 1318 reg = RT5682_PLL_TRACK_3; 1319 shift = RT5682_FILTER_CLK_SEL_SFT; 1320 break; 1321 case RT5682_DAC_STO1_ASRC_SFT: 1322 reg = RT5682_PLL_TRACK_2; 1323 shift = RT5682_FILTER_CLK_SEL_SFT; 1324 break; 1325 default: 1326 return 0; 1327 } 1328 1329 val = (snd_soc_component_read(component, reg) >> shift) & 0xf; 1330 switch (val) { 1331 case RT5682_CLK_SEL_I2S1_ASRC: 1332 case RT5682_CLK_SEL_I2S2_ASRC: 1333 return 1; 1334 default: 1335 return 0; 1336 } 1337 } 1338 1339 /* Digital Mixer */ 1340 static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = { 1341 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER, 1342 RT5682_M_STO1_ADC_L1_SFT, 1, 1), 1343 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER, 1344 RT5682_M_STO1_ADC_L2_SFT, 1, 1), 1345 }; 1346 1347 static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = { 1348 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER, 1349 RT5682_M_STO1_ADC_R1_SFT, 1, 1), 1350 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER, 1351 RT5682_M_STO1_ADC_R2_SFT, 1, 1), 1352 }; 1353 1354 static const struct snd_kcontrol_new rt5682_dac_l_mix[] = { 1355 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER, 1356 RT5682_M_ADCMIX_L_SFT, 1, 1), 1357 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER, 1358 RT5682_M_DAC1_L_SFT, 1, 1), 1359 }; 1360 1361 static const struct snd_kcontrol_new rt5682_dac_r_mix[] = { 1362 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER, 1363 RT5682_M_ADCMIX_R_SFT, 1, 1), 1364 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER, 1365 RT5682_M_DAC1_R_SFT, 1, 1), 1366 }; 1367 1368 static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = { 1369 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER, 1370 RT5682_M_DAC_L1_STO_L_SFT, 1, 1), 1371 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER, 1372 RT5682_M_DAC_R1_STO_L_SFT, 1, 1), 1373 }; 1374 1375 static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = { 1376 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER, 1377 RT5682_M_DAC_L1_STO_R_SFT, 1, 1), 1378 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER, 1379 RT5682_M_DAC_R1_STO_R_SFT, 1, 1), 1380 }; 1381 1382 /* Analog Input Mixer */ 1383 static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = { 1384 SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER, 1385 RT5682_M_CBJ_RM1_L_SFT, 1, 1), 1386 }; 1387 1388 /* STO1 ADC1 Source */ 1389 /* MX-26 [13] [5] */ 1390 static const char * const rt5682_sto1_adc1_src[] = { 1391 "DAC MIX", "ADC" 1392 }; 1393 1394 static SOC_ENUM_SINGLE_DECL( 1395 rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER, 1396 RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src); 1397 1398 static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux = 1399 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum); 1400 1401 static SOC_ENUM_SINGLE_DECL( 1402 rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER, 1403 RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src); 1404 1405 static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux = 1406 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum); 1407 1408 /* STO1 ADC Source */ 1409 /* MX-26 [11:10] [3:2] */ 1410 static const char * const rt5682_sto1_adc_src[] = { 1411 "ADC1 L", "ADC1 R" 1412 }; 1413 1414 static SOC_ENUM_SINGLE_DECL( 1415 rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER, 1416 RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src); 1417 1418 static const struct snd_kcontrol_new rt5682_sto1_adcl_mux = 1419 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum); 1420 1421 static SOC_ENUM_SINGLE_DECL( 1422 rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER, 1423 RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src); 1424 1425 static const struct snd_kcontrol_new rt5682_sto1_adcr_mux = 1426 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum); 1427 1428 /* STO1 ADC2 Source */ 1429 /* MX-26 [12] [4] */ 1430 static const char * const rt5682_sto1_adc2_src[] = { 1431 "DAC MIX", "DMIC" 1432 }; 1433 1434 static SOC_ENUM_SINGLE_DECL( 1435 rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER, 1436 RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src); 1437 1438 static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux = 1439 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum); 1440 1441 static SOC_ENUM_SINGLE_DECL( 1442 rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER, 1443 RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src); 1444 1445 static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux = 1446 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum); 1447 1448 /* MX-79 [6:4] I2S1 ADC data location */ 1449 static const unsigned int rt5682_if1_adc_slot_values[] = { 1450 0, 1451 2, 1452 4, 1453 6, 1454 }; 1455 1456 static const char * const rt5682_if1_adc_slot_src[] = { 1457 "Slot 0", "Slot 2", "Slot 4", "Slot 6" 1458 }; 1459 1460 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum, 1461 RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK, 1462 rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values); 1463 1464 static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux = 1465 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum); 1466 1467 /* Analog DAC L1 Source, Analog DAC R1 Source*/ 1468 /* MX-2B [4], MX-2B [0]*/ 1469 static const char * const rt5682_alg_dac1_src[] = { 1470 "Stereo1 DAC Mixer", "DAC1" 1471 }; 1472 1473 static SOC_ENUM_SINGLE_DECL( 1474 rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX, 1475 RT5682_A_DACL1_SFT, rt5682_alg_dac1_src); 1476 1477 static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux = 1478 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum); 1479 1480 static SOC_ENUM_SINGLE_DECL( 1481 rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX, 1482 RT5682_A_DACR1_SFT, rt5682_alg_dac1_src); 1483 1484 static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux = 1485 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum); 1486 1487 /* Out Switch */ 1488 static const struct snd_kcontrol_new hpol_switch = 1489 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1, 1490 RT5682_L_MUTE_SFT, 1, 1); 1491 static const struct snd_kcontrol_new hpor_switch = 1492 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1, 1493 RT5682_R_MUTE_SFT, 1, 1); 1494 1495 static int rt5682_hp_event(struct snd_soc_dapm_widget *w, 1496 struct snd_kcontrol *kcontrol, int event) 1497 { 1498 struct snd_soc_component *component = 1499 snd_soc_dapm_to_component(w->dapm); 1500 1501 switch (event) { 1502 case SND_SOC_DAPM_PRE_PMU: 1503 snd_soc_component_write(component, 1504 RT5682_HP_LOGIC_CTRL_2, 0x0012); 1505 snd_soc_component_write(component, 1506 RT5682_HP_CTRL_2, 0x6000); 1507 snd_soc_component_update_bits(component, 1508 RT5682_DEPOP_1, 0x60, 0x60); 1509 snd_soc_component_update_bits(component, 1510 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0080); 1511 break; 1512 1513 case SND_SOC_DAPM_POST_PMD: 1514 snd_soc_component_update_bits(component, 1515 RT5682_DEPOP_1, 0x60, 0x0); 1516 snd_soc_component_write(component, 1517 RT5682_HP_CTRL_2, 0x0000); 1518 snd_soc_component_update_bits(component, 1519 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0000); 1520 break; 1521 } 1522 1523 return 0; 1524 } 1525 1526 static int set_dmic_power(struct snd_soc_dapm_widget *w, 1527 struct snd_kcontrol *kcontrol, int event) 1528 { 1529 struct snd_soc_component *component = 1530 snd_soc_dapm_to_component(w->dapm); 1531 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 1532 unsigned int delay = 50; 1533 1534 if (rt5682->pdata.dmic_delay) 1535 delay = rt5682->pdata.dmic_delay; 1536 1537 switch (event) { 1538 case SND_SOC_DAPM_POST_PMU: 1539 /*Add delay to avoid pop noise*/ 1540 msleep(delay); 1541 break; 1542 } 1543 1544 return 0; 1545 } 1546 1547 static int rt5682_set_verf(struct snd_soc_dapm_widget *w, 1548 struct snd_kcontrol *kcontrol, int event) 1549 { 1550 struct snd_soc_component *component = 1551 snd_soc_dapm_to_component(w->dapm); 1552 1553 switch (event) { 1554 case SND_SOC_DAPM_PRE_PMU: 1555 switch (w->shift) { 1556 case RT5682_PWR_VREF1_BIT: 1557 snd_soc_component_update_bits(component, 1558 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0); 1559 break; 1560 1561 case RT5682_PWR_VREF2_BIT: 1562 snd_soc_component_update_bits(component, 1563 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0); 1564 break; 1565 } 1566 break; 1567 1568 case SND_SOC_DAPM_POST_PMU: 1569 usleep_range(15000, 20000); 1570 switch (w->shift) { 1571 case RT5682_PWR_VREF1_BIT: 1572 snd_soc_component_update_bits(component, 1573 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 1574 RT5682_PWR_FV1); 1575 break; 1576 1577 case RT5682_PWR_VREF2_BIT: 1578 snd_soc_component_update_bits(component, 1579 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 1580 RT5682_PWR_FV2); 1581 break; 1582 } 1583 break; 1584 } 1585 1586 return 0; 1587 } 1588 1589 static const unsigned int rt5682_adcdat_pin_values[] = { 1590 1, 1591 3, 1592 }; 1593 1594 static const char * const rt5682_adcdat_pin_select[] = { 1595 "ADCDAT1", 1596 "ADCDAT2", 1597 }; 1598 1599 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum, 1600 RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK, 1601 rt5682_adcdat_pin_select, rt5682_adcdat_pin_values); 1602 1603 static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl = 1604 SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum); 1605 1606 static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = { 1607 SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT, 1608 0, NULL, 0), 1609 SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT, 1610 0, NULL, 0), 1611 SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT, 1612 0, NULL, 0), 1613 SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT, 1614 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU), 1615 SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0, 1616 rt5682_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1617 SND_SOC_DAPM_SUPPLY("Vref2", SND_SOC_NOPM, 0, 0, NULL, 0), 1618 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, NULL, 0), 1619 1620 /* ASRC */ 1621 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1, 1622 RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0), 1623 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1, 1624 RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0), 1625 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1, 1626 RT5682_AD_ASRC_SFT, 0, NULL, 0), 1627 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1, 1628 RT5682_DA_ASRC_SFT, 0, NULL, 0), 1629 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1, 1630 RT5682_DMIC_ASRC_SFT, 0, NULL, 0), 1631 1632 /* Input Side */ 1633 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT, 1634 0, NULL, 0), 1635 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT, 1636 0, NULL, 0), 1637 1638 /* Input Lines */ 1639 SND_SOC_DAPM_INPUT("DMIC L1"), 1640 SND_SOC_DAPM_INPUT("DMIC R1"), 1641 1642 SND_SOC_DAPM_INPUT("IN1P"), 1643 1644 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 1645 set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 1646 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1, 1647 RT5682_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU), 1648 1649 /* Boost */ 1650 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 1651 0, 0, NULL, 0), 1652 1653 /* REC Mixer */ 1654 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix, 1655 ARRAY_SIZE(rt5682_rec1_l_mix)), 1656 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2, 1657 RT5682_PWR_RM1_L_BIT, 0, NULL, 0), 1658 1659 /* ADCs */ 1660 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0), 1661 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0), 1662 1663 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1, 1664 RT5682_PWR_ADC_L1_BIT, 0, NULL, 0), 1665 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1, 1666 RT5682_PWR_ADC_R1_BIT, 0, NULL, 0), 1667 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC, 1668 RT5682_CKGEN_ADC1_SFT, 0, NULL, 0), 1669 1670 /* ADC Mux */ 1671 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0, 1672 &rt5682_sto1_adc1l_mux), 1673 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0, 1674 &rt5682_sto1_adc1r_mux), 1675 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0, 1676 &rt5682_sto1_adc2l_mux), 1677 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0, 1678 &rt5682_sto1_adc2r_mux), 1679 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0, 1680 &rt5682_sto1_adcl_mux), 1681 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0, 1682 &rt5682_sto1_adcr_mux), 1683 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0, 1684 &rt5682_if1_adc_slot_mux), 1685 1686 /* ADC Mixer */ 1687 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2, 1688 RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk, 1689 SND_SOC_DAPM_PRE_PMU), 1690 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL, 1691 RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix, 1692 ARRAY_SIZE(rt5682_sto1_adc_l_mix)), 1693 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL, 1694 RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix, 1695 ARRAY_SIZE(rt5682_sto1_adc_r_mix)), 1696 SND_SOC_DAPM_SUPPLY("BTN Detection Mode", RT5682_SAR_IL_CMD_1, 1697 14, 1, NULL, 0), 1698 1699 /* ADC PGA */ 1700 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 1701 1702 /* Digital Interface */ 1703 SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT, 1704 0, NULL, 0), 1705 SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT, 1706 0, NULL, 0), 1707 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), 1708 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0), 1709 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0), 1710 SND_SOC_DAPM_PGA("SOUND DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), 1711 SND_SOC_DAPM_PGA("SOUND DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), 1712 1713 /* Digital Interface Select */ 1714 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1715 &rt5682_if1_01_adc_swap_mux), 1716 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1717 &rt5682_if1_23_adc_swap_mux), 1718 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1719 &rt5682_if1_45_adc_swap_mux), 1720 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1721 &rt5682_if1_67_adc_swap_mux), 1722 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0, 1723 &rt5682_if2_adc_swap_mux), 1724 1725 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0, 1726 &rt5682_adcdat_pin_ctrl), 1727 1728 SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0, 1729 &rt5682_dac_l_mux), 1730 SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0, 1731 &rt5682_dac_r_mux), 1732 1733 /* Audio Interface */ 1734 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, 1735 RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1), 1736 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, 1737 RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1), 1738 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 1739 SND_SOC_DAPM_AIF_IN("SDWRX", "SDW Playback", 0, SND_SOC_NOPM, 0, 0), 1740 SND_SOC_DAPM_AIF_OUT("SDWTX", "SDW Capture", 0, SND_SOC_NOPM, 0, 0), 1741 1742 /* Output Side */ 1743 /* DAC mixer before sound effect */ 1744 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, 1745 rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)), 1746 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, 1747 rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)), 1748 1749 /* DAC channel Mux */ 1750 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0, 1751 &rt5682_alg_dac_l1_mux), 1752 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0, 1753 &rt5682_alg_dac_r1_mux), 1754 1755 /* DAC Mixer */ 1756 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2, 1757 RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk, 1758 SND_SOC_DAPM_PRE_PMU), 1759 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0, 1760 rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)), 1761 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0, 1762 rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)), 1763 1764 /* DACs */ 1765 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1, 1766 RT5682_PWR_DAC_L1_BIT, 0), 1767 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1, 1768 RT5682_PWR_DAC_R1_BIT, 0), 1769 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC, 1770 RT5682_CKGEN_DAC1_SFT, 0, NULL, 0), 1771 1772 /* HPO */ 1773 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event, 1774 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU), 1775 1776 SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1, 1777 RT5682_PWR_HA_L_BIT, 0, NULL, 0), 1778 SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1, 1779 RT5682_PWR_HA_R_BIT, 0, NULL, 0), 1780 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1, 1781 RT5682_PUMP_EN_SFT, 0, NULL, 0), 1782 SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1, 1783 RT5682_CAPLESS_EN_SFT, 0, NULL, 0), 1784 1785 SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0, 1786 &hpol_switch), 1787 SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0, 1788 &hpor_switch), 1789 1790 /* CLK DET */ 1791 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET, 1792 RT5682_SYS_CLK_DET_SFT, 0, NULL, 0), 1793 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET, 1794 RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0), 1795 SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET, 1796 RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0), 1797 SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET, 1798 RT5682_POW_CLK_DET_SFT, 0, NULL, 0), 1799 1800 /* Output Lines */ 1801 SND_SOC_DAPM_OUTPUT("HPOL"), 1802 SND_SOC_DAPM_OUTPUT("HPOR"), 1803 }; 1804 1805 static const struct snd_soc_dapm_route rt5682_dapm_routes[] = { 1806 /*PLL*/ 1807 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1}, 1808 {"ADC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2}, 1809 {"ADC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2}, 1810 {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1}, 1811 {"DAC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2}, 1812 {"DAC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2}, 1813 1814 /*ASRC*/ 1815 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc}, 1816 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc}, 1817 {"ADC STO1 ASRC", NULL, "AD ASRC"}, 1818 {"ADC STO1 ASRC", NULL, "DA ASRC"}, 1819 {"ADC STO1 ASRC", NULL, "CLKDET"}, 1820 {"DAC STO1 ASRC", NULL, "AD ASRC"}, 1821 {"DAC STO1 ASRC", NULL, "DA ASRC"}, 1822 {"DAC STO1 ASRC", NULL, "CLKDET"}, 1823 1824 /*Vref*/ 1825 {"MICBIAS1", NULL, "Vref1"}, 1826 {"MICBIAS2", NULL, "Vref1"}, 1827 1828 {"CLKDET SYS", NULL, "CLKDET"}, 1829 1830 {"IN1P", NULL, "LDO2"}, 1831 1832 {"BST1 CBJ", NULL, "IN1P"}, 1833 1834 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"}, 1835 {"RECMIX1L", NULL, "RECMIX1L Power"}, 1836 1837 {"ADC1 L", NULL, "RECMIX1L"}, 1838 {"ADC1 L", NULL, "ADC1 L Power"}, 1839 {"ADC1 L", NULL, "ADC1 clock"}, 1840 1841 {"DMIC L1", NULL, "DMIC CLK"}, 1842 {"DMIC L1", NULL, "DMIC1 Power"}, 1843 {"DMIC R1", NULL, "DMIC CLK"}, 1844 {"DMIC R1", NULL, "DMIC1 Power"}, 1845 {"DMIC CLK", NULL, "DMIC ASRC"}, 1846 1847 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"}, 1848 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"}, 1849 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"}, 1850 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"}, 1851 1852 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"}, 1853 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1854 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"}, 1855 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"}, 1856 1857 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"}, 1858 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1859 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"}, 1860 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"}, 1861 1862 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"}, 1863 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"}, 1864 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"}, 1865 1866 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"}, 1867 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"}, 1868 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"}, 1869 1870 {"ADC Stereo1 Filter", NULL, "BTN Detection Mode"}, 1871 1872 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"}, 1873 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"}, 1874 1875 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1876 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1877 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1878 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1879 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1880 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1881 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1882 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1883 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1884 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1885 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1886 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1887 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1888 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1889 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1890 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1891 1892 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"}, 1893 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"}, 1894 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"}, 1895 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"}, 1896 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"}, 1897 {"AIF1TX", NULL, "I2S1"}, 1898 {"AIF1TX", NULL, "ADCDAT Mux"}, 1899 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"}, 1900 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"}, 1901 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"}, 1902 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"}, 1903 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"}, 1904 {"AIF2TX", NULL, "ADCDAT Mux"}, 1905 1906 {"SDWTX", NULL, "PLL2B"}, 1907 {"SDWTX", NULL, "PLL2F"}, 1908 {"SDWTX", NULL, "ADCDAT Mux"}, 1909 1910 {"IF1 DAC1 L", NULL, "AIF1RX"}, 1911 {"IF1 DAC1 L", NULL, "I2S1"}, 1912 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"}, 1913 {"IF1 DAC1 R", NULL, "AIF1RX"}, 1914 {"IF1 DAC1 R", NULL, "I2S1"}, 1915 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"}, 1916 1917 {"SOUND DAC L", NULL, "SDWRX"}, 1918 {"SOUND DAC L", NULL, "DAC Stereo1 Filter"}, 1919 {"SOUND DAC L", NULL, "PLL2B"}, 1920 {"SOUND DAC L", NULL, "PLL2F"}, 1921 {"SOUND DAC R", NULL, "SDWRX"}, 1922 {"SOUND DAC R", NULL, "DAC Stereo1 Filter"}, 1923 {"SOUND DAC R", NULL, "PLL2B"}, 1924 {"SOUND DAC R", NULL, "PLL2F"}, 1925 1926 {"DAC L Mux", "IF1", "IF1 DAC1 L"}, 1927 {"DAC L Mux", "SOUND", "SOUND DAC L"}, 1928 {"DAC R Mux", "IF1", "IF1 DAC1 R"}, 1929 {"DAC R Mux", "SOUND", "SOUND DAC R"}, 1930 1931 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"}, 1932 {"DAC1 MIXL", "DAC1 Switch", "DAC L Mux"}, 1933 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"}, 1934 {"DAC1 MIXR", "DAC1 Switch", "DAC R Mux"}, 1935 1936 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"}, 1937 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"}, 1938 1939 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"}, 1940 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"}, 1941 1942 {"DAC L1 Source", "DAC1", "DAC1 MIXL"}, 1943 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"}, 1944 {"DAC R1 Source", "DAC1", "DAC1 MIXR"}, 1945 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"}, 1946 1947 {"DAC L1", NULL, "DAC L1 Source"}, 1948 {"DAC R1", NULL, "DAC R1 Source"}, 1949 1950 {"DAC L1", NULL, "DAC 1 Clock"}, 1951 {"DAC R1", NULL, "DAC 1 Clock"}, 1952 1953 {"HP Amp", NULL, "DAC L1"}, 1954 {"HP Amp", NULL, "DAC R1"}, 1955 {"HP Amp", NULL, "HP Amp L"}, 1956 {"HP Amp", NULL, "HP Amp R"}, 1957 {"HP Amp", NULL, "Capless"}, 1958 {"HP Amp", NULL, "Charge Pump"}, 1959 {"HP Amp", NULL, "CLKDET SYS"}, 1960 {"HP Amp", NULL, "Vref1"}, 1961 {"HPOL Playback", "Switch", "HP Amp"}, 1962 {"HPOR Playback", "Switch", "HP Amp"}, 1963 {"HPOL", NULL, "HPOL Playback"}, 1964 {"HPOR", NULL, "HPOR Playback"}, 1965 }; 1966 1967 static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 1968 unsigned int rx_mask, int slots, int slot_width) 1969 { 1970 struct snd_soc_component *component = dai->component; 1971 unsigned int cl, val = 0; 1972 1973 if (tx_mask || rx_mask) 1974 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2, 1975 RT5682_TDM_EN, RT5682_TDM_EN); 1976 else 1977 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2, 1978 RT5682_TDM_EN, 0); 1979 1980 switch (slots) { 1981 case 4: 1982 val |= RT5682_TDM_TX_CH_4; 1983 val |= RT5682_TDM_RX_CH_4; 1984 break; 1985 case 6: 1986 val |= RT5682_TDM_TX_CH_6; 1987 val |= RT5682_TDM_RX_CH_6; 1988 break; 1989 case 8: 1990 val |= RT5682_TDM_TX_CH_8; 1991 val |= RT5682_TDM_RX_CH_8; 1992 break; 1993 case 2: 1994 break; 1995 default: 1996 return -EINVAL; 1997 } 1998 1999 snd_soc_component_update_bits(component, RT5682_TDM_CTRL, 2000 RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val); 2001 2002 switch (slot_width) { 2003 case 8: 2004 if (tx_mask || rx_mask) 2005 return -EINVAL; 2006 cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8; 2007 break; 2008 case 16: 2009 val = RT5682_TDM_CL_16; 2010 cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16; 2011 break; 2012 case 20: 2013 val = RT5682_TDM_CL_20; 2014 cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20; 2015 break; 2016 case 24: 2017 val = RT5682_TDM_CL_24; 2018 cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24; 2019 break; 2020 case 32: 2021 val = RT5682_TDM_CL_32; 2022 cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32; 2023 break; 2024 default: 2025 return -EINVAL; 2026 } 2027 2028 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2029 RT5682_TDM_CL_MASK, val); 2030 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2031 RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl); 2032 2033 return 0; 2034 } 2035 2036 static int rt5682_hw_params(struct snd_pcm_substream *substream, 2037 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 2038 { 2039 struct snd_soc_component *component = dai->component; 2040 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2041 unsigned int len_1 = 0, len_2 = 0; 2042 int pre_div, frame_size; 2043 2044 rt5682->lrck[dai->id] = params_rate(params); 2045 pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]); 2046 2047 frame_size = snd_soc_params_to_frame_size(params); 2048 if (frame_size < 0) { 2049 dev_err(component->dev, "Unsupported frame size: %d\n", 2050 frame_size); 2051 return -EINVAL; 2052 } 2053 2054 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n", 2055 rt5682->lrck[dai->id], pre_div, dai->id); 2056 2057 switch (params_width(params)) { 2058 case 16: 2059 break; 2060 case 20: 2061 len_1 |= RT5682_I2S1_DL_20; 2062 len_2 |= RT5682_I2S2_DL_20; 2063 break; 2064 case 24: 2065 len_1 |= RT5682_I2S1_DL_24; 2066 len_2 |= RT5682_I2S2_DL_24; 2067 break; 2068 case 32: 2069 len_1 |= RT5682_I2S1_DL_32; 2070 len_2 |= RT5682_I2S2_DL_24; 2071 break; 2072 case 8: 2073 len_1 |= RT5682_I2S2_DL_8; 2074 len_2 |= RT5682_I2S2_DL_8; 2075 break; 2076 default: 2077 return -EINVAL; 2078 } 2079 2080 switch (dai->id) { 2081 case RT5682_AIF1: 2082 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2083 RT5682_I2S1_DL_MASK, len_1); 2084 if (rt5682->master[RT5682_AIF1]) { 2085 snd_soc_component_update_bits(component, 2086 RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK | 2087 RT5682_I2S_CLK_SRC_MASK, 2088 pre_div << RT5682_I2S_M_DIV_SFT | 2089 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT); 2090 } 2091 if (params_channels(params) == 1) /* mono mode */ 2092 snd_soc_component_update_bits(component, 2093 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK, 2094 RT5682_I2S1_MONO_EN); 2095 else 2096 snd_soc_component_update_bits(component, 2097 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK, 2098 RT5682_I2S1_MONO_DIS); 2099 break; 2100 case RT5682_AIF2: 2101 snd_soc_component_update_bits(component, RT5682_I2S2_SDP, 2102 RT5682_I2S2_DL_MASK, len_2); 2103 if (rt5682->master[RT5682_AIF2]) { 2104 snd_soc_component_update_bits(component, 2105 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK, 2106 pre_div << RT5682_I2S2_M_PD_SFT); 2107 } 2108 if (params_channels(params) == 1) /* mono mode */ 2109 snd_soc_component_update_bits(component, 2110 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK, 2111 RT5682_I2S2_MONO_EN); 2112 else 2113 snd_soc_component_update_bits(component, 2114 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK, 2115 RT5682_I2S2_MONO_DIS); 2116 break; 2117 default: 2118 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2119 return -EINVAL; 2120 } 2121 2122 return 0; 2123 } 2124 2125 static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2126 { 2127 struct snd_soc_component *component = dai->component; 2128 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2129 unsigned int reg_val = 0, tdm_ctrl = 0; 2130 2131 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2132 case SND_SOC_DAIFMT_CBM_CFM: 2133 rt5682->master[dai->id] = 1; 2134 break; 2135 case SND_SOC_DAIFMT_CBS_CFS: 2136 rt5682->master[dai->id] = 0; 2137 break; 2138 default: 2139 return -EINVAL; 2140 } 2141 2142 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2143 case SND_SOC_DAIFMT_NB_NF: 2144 break; 2145 case SND_SOC_DAIFMT_IB_NF: 2146 reg_val |= RT5682_I2S_BP_INV; 2147 tdm_ctrl |= RT5682_TDM_S_BP_INV; 2148 break; 2149 case SND_SOC_DAIFMT_NB_IF: 2150 if (dai->id == RT5682_AIF1) 2151 tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV; 2152 else 2153 return -EINVAL; 2154 break; 2155 case SND_SOC_DAIFMT_IB_IF: 2156 if (dai->id == RT5682_AIF1) 2157 tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV | 2158 RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV; 2159 else 2160 return -EINVAL; 2161 break; 2162 default: 2163 return -EINVAL; 2164 } 2165 2166 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2167 case SND_SOC_DAIFMT_I2S: 2168 break; 2169 case SND_SOC_DAIFMT_LEFT_J: 2170 reg_val |= RT5682_I2S_DF_LEFT; 2171 tdm_ctrl |= RT5682_TDM_DF_LEFT; 2172 break; 2173 case SND_SOC_DAIFMT_DSP_A: 2174 reg_val |= RT5682_I2S_DF_PCM_A; 2175 tdm_ctrl |= RT5682_TDM_DF_PCM_A; 2176 break; 2177 case SND_SOC_DAIFMT_DSP_B: 2178 reg_val |= RT5682_I2S_DF_PCM_B; 2179 tdm_ctrl |= RT5682_TDM_DF_PCM_B; 2180 break; 2181 default: 2182 return -EINVAL; 2183 } 2184 2185 switch (dai->id) { 2186 case RT5682_AIF1: 2187 snd_soc_component_update_bits(component, RT5682_I2S1_SDP, 2188 RT5682_I2S_DF_MASK, reg_val); 2189 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2190 RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK | 2191 RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK | 2192 RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK, 2193 tdm_ctrl | rt5682->master[dai->id]); 2194 break; 2195 case RT5682_AIF2: 2196 if (rt5682->master[dai->id] == 0) 2197 reg_val |= RT5682_I2S2_MS_S; 2198 snd_soc_component_update_bits(component, RT5682_I2S2_SDP, 2199 RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK | 2200 RT5682_I2S_DF_MASK, reg_val); 2201 break; 2202 default: 2203 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); 2204 return -EINVAL; 2205 } 2206 return 0; 2207 } 2208 2209 static int rt5682_set_component_sysclk(struct snd_soc_component *component, 2210 int clk_id, int source, unsigned int freq, int dir) 2211 { 2212 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2213 unsigned int reg_val = 0, src = 0; 2214 2215 if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src) 2216 return 0; 2217 2218 switch (clk_id) { 2219 case RT5682_SCLK_S_MCLK: 2220 reg_val |= RT5682_SCLK_SRC_MCLK; 2221 src = RT5682_CLK_SRC_MCLK; 2222 break; 2223 case RT5682_SCLK_S_PLL1: 2224 reg_val |= RT5682_SCLK_SRC_PLL1; 2225 src = RT5682_CLK_SRC_PLL1; 2226 break; 2227 case RT5682_SCLK_S_PLL2: 2228 reg_val |= RT5682_SCLK_SRC_PLL2; 2229 src = RT5682_CLK_SRC_PLL2; 2230 break; 2231 case RT5682_SCLK_S_RCCLK: 2232 reg_val |= RT5682_SCLK_SRC_RCCLK; 2233 src = RT5682_CLK_SRC_RCCLK; 2234 break; 2235 default: 2236 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); 2237 return -EINVAL; 2238 } 2239 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2240 RT5682_SCLK_SRC_MASK, reg_val); 2241 2242 if (rt5682->master[RT5682_AIF2]) { 2243 snd_soc_component_update_bits(component, 2244 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK, 2245 src << RT5682_I2S2_SRC_SFT); 2246 } 2247 2248 rt5682->sysclk = freq; 2249 rt5682->sysclk_src = clk_id; 2250 2251 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", 2252 freq, clk_id); 2253 2254 return 0; 2255 } 2256 2257 static int rt5682_set_component_pll(struct snd_soc_component *component, 2258 int pll_id, int source, unsigned int freq_in, 2259 unsigned int freq_out) 2260 { 2261 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2262 struct rl6231_pll_code pll_code, pll2f_code, pll2b_code; 2263 unsigned int pll2_fout1, pll2_ps_val; 2264 int ret; 2265 2266 if (source == rt5682->pll_src[pll_id] && 2267 freq_in == rt5682->pll_in[pll_id] && 2268 freq_out == rt5682->pll_out[pll_id]) 2269 return 0; 2270 2271 if (!freq_in || !freq_out) { 2272 dev_dbg(component->dev, "PLL disabled\n"); 2273 2274 rt5682->pll_in[pll_id] = 0; 2275 rt5682->pll_out[pll_id] = 0; 2276 snd_soc_component_update_bits(component, RT5682_GLB_CLK, 2277 RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK); 2278 return 0; 2279 } 2280 2281 if (pll_id == RT5682_PLL2) { 2282 switch (source) { 2283 case RT5682_PLL2_S_MCLK: 2284 snd_soc_component_update_bits(component, 2285 RT5682_GLB_CLK, RT5682_PLL2_SRC_MASK, 2286 RT5682_PLL2_SRC_MCLK); 2287 break; 2288 default: 2289 dev_err(component->dev, "Unknown PLL2 Source %d\n", 2290 source); 2291 return -EINVAL; 2292 } 2293 2294 /** 2295 * PLL2 concatenates 2 PLL units. 2296 * We suggest the Fout of the front PLL is 3.84MHz. 2297 */ 2298 pll2_fout1 = 3840000; 2299 ret = rl6231_pll_calc(freq_in, pll2_fout1, &pll2f_code); 2300 if (ret < 0) { 2301 dev_err(component->dev, "Unsupport input clock %d\n", 2302 freq_in); 2303 return ret; 2304 } 2305 dev_dbg(component->dev, "PLL2F: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n", 2306 freq_in, pll2_fout1, 2307 pll2f_code.m_bp, 2308 (pll2f_code.m_bp ? 0 : pll2f_code.m_code), 2309 pll2f_code.n_code, pll2f_code.k_code); 2310 2311 ret = rl6231_pll_calc(pll2_fout1, freq_out, &pll2b_code); 2312 if (ret < 0) { 2313 dev_err(component->dev, "Unsupport input clock %d\n", 2314 pll2_fout1); 2315 return ret; 2316 } 2317 dev_dbg(component->dev, "PLL2B: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n", 2318 pll2_fout1, freq_out, 2319 pll2b_code.m_bp, 2320 (pll2b_code.m_bp ? 0 : pll2b_code.m_code), 2321 pll2b_code.n_code, pll2b_code.k_code); 2322 2323 snd_soc_component_write(component, RT5682_PLL2_CTRL_1, 2324 pll2f_code.k_code << RT5682_PLL2F_K_SFT | 2325 pll2b_code.k_code << RT5682_PLL2B_K_SFT | 2326 pll2b_code.m_code); 2327 snd_soc_component_write(component, RT5682_PLL2_CTRL_2, 2328 pll2f_code.m_code << RT5682_PLL2F_M_SFT | 2329 pll2b_code.n_code); 2330 snd_soc_component_write(component, RT5682_PLL2_CTRL_3, 2331 pll2f_code.n_code << RT5682_PLL2F_N_SFT); 2332 2333 if (freq_out == 22579200) 2334 pll2_ps_val = 1 << RT5682_PLL2B_SEL_PS_SFT; 2335 else 2336 pll2_ps_val = 1 << RT5682_PLL2B_PS_BYP_SFT; 2337 snd_soc_component_update_bits(component, RT5682_PLL2_CTRL_4, 2338 RT5682_PLL2B_SEL_PS_MASK | RT5682_PLL2B_PS_BYP_MASK | 2339 RT5682_PLL2B_M_BP_MASK | RT5682_PLL2F_M_BP_MASK | 0xf, 2340 pll2_ps_val | 2341 (pll2b_code.m_bp ? 1 : 0) << RT5682_PLL2B_M_BP_SFT | 2342 (pll2f_code.m_bp ? 1 : 0) << RT5682_PLL2F_M_BP_SFT | 2343 0xf); 2344 } else { 2345 switch (source) { 2346 case RT5682_PLL1_S_MCLK: 2347 snd_soc_component_update_bits(component, 2348 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK, 2349 RT5682_PLL1_SRC_MCLK); 2350 break; 2351 case RT5682_PLL1_S_BCLK1: 2352 snd_soc_component_update_bits(component, 2353 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK, 2354 RT5682_PLL1_SRC_BCLK1); 2355 break; 2356 default: 2357 dev_err(component->dev, "Unknown PLL1 Source %d\n", 2358 source); 2359 return -EINVAL; 2360 } 2361 2362 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); 2363 if (ret < 0) { 2364 dev_err(component->dev, "Unsupport input clock %d\n", 2365 freq_in); 2366 return ret; 2367 } 2368 2369 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", 2370 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), 2371 pll_code.n_code, pll_code.k_code); 2372 2373 snd_soc_component_write(component, RT5682_PLL_CTRL_1, 2374 pll_code.n_code << RT5682_PLL_N_SFT | pll_code.k_code); 2375 snd_soc_component_write(component, RT5682_PLL_CTRL_2, 2376 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT | 2377 pll_code.m_bp << RT5682_PLL_M_BP_SFT | RT5682_PLL_RST); 2378 } 2379 2380 rt5682->pll_in[pll_id] = freq_in; 2381 rt5682->pll_out[pll_id] = freq_out; 2382 rt5682->pll_src[pll_id] = source; 2383 2384 return 0; 2385 } 2386 2387 static int rt5682_set_bclk1_ratio(struct snd_soc_dai *dai, unsigned int ratio) 2388 { 2389 struct snd_soc_component *component = dai->component; 2390 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2391 2392 rt5682->bclk[dai->id] = ratio; 2393 2394 switch (ratio) { 2395 case 256: 2396 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2397 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_256); 2398 break; 2399 case 128: 2400 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2401 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_128); 2402 break; 2403 case 64: 2404 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2405 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_64); 2406 break; 2407 case 32: 2408 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL, 2409 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_32); 2410 break; 2411 default: 2412 dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio); 2413 return -EINVAL; 2414 } 2415 2416 return 0; 2417 } 2418 2419 static int rt5682_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio) 2420 { 2421 struct snd_soc_component *component = dai->component; 2422 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2423 2424 rt5682->bclk[dai->id] = ratio; 2425 2426 switch (ratio) { 2427 case 64: 2428 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2, 2429 RT5682_I2S2_BCLK_MS2_MASK, 2430 RT5682_I2S2_BCLK_MS2_64); 2431 break; 2432 case 32: 2433 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2, 2434 RT5682_I2S2_BCLK_MS2_MASK, 2435 RT5682_I2S2_BCLK_MS2_32); 2436 break; 2437 default: 2438 dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio); 2439 return -EINVAL; 2440 } 2441 2442 return 0; 2443 } 2444 2445 static int rt5682_set_bias_level(struct snd_soc_component *component, 2446 enum snd_soc_bias_level level) 2447 { 2448 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2449 2450 switch (level) { 2451 case SND_SOC_BIAS_PREPARE: 2452 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 2453 RT5682_PWR_BG, RT5682_PWR_BG); 2454 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2455 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 2456 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO); 2457 break; 2458 2459 case SND_SOC_BIAS_STANDBY: 2460 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2461 RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL); 2462 break; 2463 case SND_SOC_BIAS_OFF: 2464 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, 2465 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0); 2466 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, 2467 RT5682_PWR_BG, 0); 2468 break; 2469 case SND_SOC_BIAS_ON: 2470 break; 2471 } 2472 2473 return 0; 2474 } 2475 2476 #ifdef CONFIG_COMMON_CLK 2477 #define CLK_PLL2_FIN 48000000 2478 #define CLK_48 48000 2479 #define CLK_44 44100 2480 2481 static bool rt5682_clk_check(struct rt5682_priv *rt5682) 2482 { 2483 if (!rt5682->master[RT5682_AIF1]) { 2484 dev_err(rt5682->component->dev, "sysclk/dai not set correctly\n"); 2485 return false; 2486 } 2487 return true; 2488 } 2489 2490 static int rt5682_wclk_prepare(struct clk_hw *hw) 2491 { 2492 struct rt5682_priv *rt5682 = 2493 container_of(hw, struct rt5682_priv, 2494 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2495 struct snd_soc_component *component = rt5682->component; 2496 struct snd_soc_dapm_context *dapm = 2497 snd_soc_component_get_dapm(component); 2498 2499 if (!rt5682_clk_check(rt5682)) 2500 return -EINVAL; 2501 2502 snd_soc_dapm_mutex_lock(dapm); 2503 2504 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS"); 2505 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 2506 RT5682_PWR_MB, RT5682_PWR_MB); 2507 2508 snd_soc_dapm_force_enable_pin_unlocked(dapm, "Vref2"); 2509 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 2510 RT5682_PWR_VREF2 | RT5682_PWR_FV2, 2511 RT5682_PWR_VREF2); 2512 usleep_range(55000, 60000); 2513 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 2514 RT5682_PWR_FV2, RT5682_PWR_FV2); 2515 2516 snd_soc_dapm_force_enable_pin_unlocked(dapm, "I2S1"); 2517 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2F"); 2518 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2B"); 2519 snd_soc_dapm_sync_unlocked(dapm); 2520 2521 snd_soc_dapm_mutex_unlock(dapm); 2522 2523 return 0; 2524 } 2525 2526 static void rt5682_wclk_unprepare(struct clk_hw *hw) 2527 { 2528 struct rt5682_priv *rt5682 = 2529 container_of(hw, struct rt5682_priv, 2530 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2531 struct snd_soc_component *component = rt5682->component; 2532 struct snd_soc_dapm_context *dapm = 2533 snd_soc_component_get_dapm(component); 2534 2535 if (!rt5682_clk_check(rt5682)) 2536 return; 2537 2538 snd_soc_dapm_mutex_lock(dapm); 2539 2540 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS"); 2541 snd_soc_dapm_disable_pin_unlocked(dapm, "Vref2"); 2542 if (!rt5682->jack_type) 2543 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1, 2544 RT5682_PWR_VREF2 | RT5682_PWR_FV2 | 2545 RT5682_PWR_MB, 0); 2546 2547 snd_soc_dapm_disable_pin_unlocked(dapm, "I2S1"); 2548 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2F"); 2549 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2B"); 2550 snd_soc_dapm_sync_unlocked(dapm); 2551 2552 snd_soc_dapm_mutex_unlock(dapm); 2553 } 2554 2555 static unsigned long rt5682_wclk_recalc_rate(struct clk_hw *hw, 2556 unsigned long parent_rate) 2557 { 2558 struct rt5682_priv *rt5682 = 2559 container_of(hw, struct rt5682_priv, 2560 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2561 struct snd_soc_component *component = rt5682->component; 2562 const char * const clk_name = __clk_get_name(hw->clk); 2563 2564 if (!rt5682_clk_check(rt5682)) 2565 return 0; 2566 /* 2567 * Only accept to set wclk rate to 44.1k or 48kHz. 2568 */ 2569 if (rt5682->lrck[RT5682_AIF1] != CLK_48 && 2570 rt5682->lrck[RT5682_AIF1] != CLK_44) { 2571 dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n", 2572 __func__, clk_name, CLK_44, CLK_48); 2573 return 0; 2574 } 2575 2576 return rt5682->lrck[RT5682_AIF1]; 2577 } 2578 2579 static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate, 2580 unsigned long *parent_rate) 2581 { 2582 struct rt5682_priv *rt5682 = 2583 container_of(hw, struct rt5682_priv, 2584 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2585 struct snd_soc_component *component = rt5682->component; 2586 const char * const clk_name = __clk_get_name(hw->clk); 2587 2588 if (!rt5682_clk_check(rt5682)) 2589 return -EINVAL; 2590 /* 2591 * Only accept to set wclk rate to 44.1k or 48kHz. 2592 * It will force to 48kHz if not both. 2593 */ 2594 if (rate != CLK_48 && rate != CLK_44) { 2595 dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n", 2596 __func__, clk_name, CLK_44, CLK_48); 2597 rate = CLK_48; 2598 } 2599 2600 return rate; 2601 } 2602 2603 static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate, 2604 unsigned long parent_rate) 2605 { 2606 struct rt5682_priv *rt5682 = 2607 container_of(hw, struct rt5682_priv, 2608 dai_clks_hw[RT5682_DAI_WCLK_IDX]); 2609 struct snd_soc_component *component = rt5682->component; 2610 struct clk *parent_clk; 2611 const char * const clk_name = __clk_get_name(hw->clk); 2612 int pre_div; 2613 unsigned int clk_pll2_out; 2614 2615 if (!rt5682_clk_check(rt5682)) 2616 return -EINVAL; 2617 2618 /* 2619 * Whether the wclk's parent clk (mclk) exists or not, please ensure 2620 * it is fixed or set to 48MHz before setting wclk rate. It's a 2621 * temporary limitation. Only accept 48MHz clk as the clk provider. 2622 * 2623 * It will set the codec anyway by assuming mclk is 48MHz. 2624 */ 2625 parent_clk = clk_get_parent(hw->clk); 2626 if (!parent_clk) 2627 dev_warn(component->dev, 2628 "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n", 2629 CLK_PLL2_FIN); 2630 2631 if (parent_rate != CLK_PLL2_FIN) 2632 dev_warn(component->dev, "clk %s only support %d Hz input\n", 2633 clk_name, CLK_PLL2_FIN); 2634 2635 /* 2636 * To achieve the rate conversion from 48MHz to 44.1k or 48kHz, 2637 * PLL2 is needed. 2638 */ 2639 clk_pll2_out = rate * 512; 2640 rt5682_set_component_pll(component, RT5682_PLL2, RT5682_PLL2_S_MCLK, 2641 CLK_PLL2_FIN, clk_pll2_out); 2642 2643 rt5682_set_component_sysclk(component, RT5682_SCLK_S_PLL2, 0, 2644 clk_pll2_out, SND_SOC_CLOCK_IN); 2645 2646 rt5682->lrck[RT5682_AIF1] = rate; 2647 2648 pre_div = rl6231_get_clk_info(rt5682->sysclk, rate); 2649 2650 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1, 2651 RT5682_I2S_M_DIV_MASK | RT5682_I2S_CLK_SRC_MASK, 2652 pre_div << RT5682_I2S_M_DIV_SFT | 2653 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT); 2654 2655 return 0; 2656 } 2657 2658 static unsigned long rt5682_bclk_recalc_rate(struct clk_hw *hw, 2659 unsigned long parent_rate) 2660 { 2661 struct rt5682_priv *rt5682 = 2662 container_of(hw, struct rt5682_priv, 2663 dai_clks_hw[RT5682_DAI_BCLK_IDX]); 2664 struct snd_soc_component *component = rt5682->component; 2665 unsigned int bclks_per_wclk; 2666 2667 bclks_per_wclk = snd_soc_component_read(component, RT5682_TDM_TCON_CTRL); 2668 2669 switch (bclks_per_wclk & RT5682_TDM_BCLK_MS1_MASK) { 2670 case RT5682_TDM_BCLK_MS1_256: 2671 return parent_rate * 256; 2672 case RT5682_TDM_BCLK_MS1_128: 2673 return parent_rate * 128; 2674 case RT5682_TDM_BCLK_MS1_64: 2675 return parent_rate * 64; 2676 case RT5682_TDM_BCLK_MS1_32: 2677 return parent_rate * 32; 2678 default: 2679 return 0; 2680 } 2681 } 2682 2683 static unsigned long rt5682_bclk_get_factor(unsigned long rate, 2684 unsigned long parent_rate) 2685 { 2686 unsigned long factor; 2687 2688 factor = rate / parent_rate; 2689 if (factor < 64) 2690 return 32; 2691 else if (factor < 128) 2692 return 64; 2693 else if (factor < 256) 2694 return 128; 2695 else 2696 return 256; 2697 } 2698 2699 static long rt5682_bclk_round_rate(struct clk_hw *hw, unsigned long rate, 2700 unsigned long *parent_rate) 2701 { 2702 struct rt5682_priv *rt5682 = 2703 container_of(hw, struct rt5682_priv, 2704 dai_clks_hw[RT5682_DAI_BCLK_IDX]); 2705 unsigned long factor; 2706 2707 if (!*parent_rate || !rt5682_clk_check(rt5682)) 2708 return -EINVAL; 2709 2710 /* 2711 * BCLK rates are set as a multiplier of WCLK in HW. 2712 * We don't allow changing the parent WCLK. We just do 2713 * some rounding down based on the parent WCLK rate 2714 * and find the appropriate multiplier of BCLK to 2715 * get the rounded down BCLK value. 2716 */ 2717 factor = rt5682_bclk_get_factor(rate, *parent_rate); 2718 2719 return *parent_rate * factor; 2720 } 2721 2722 static int rt5682_bclk_set_rate(struct clk_hw *hw, unsigned long rate, 2723 unsigned long parent_rate) 2724 { 2725 struct rt5682_priv *rt5682 = 2726 container_of(hw, struct rt5682_priv, 2727 dai_clks_hw[RT5682_DAI_BCLK_IDX]); 2728 struct snd_soc_component *component = rt5682->component; 2729 struct snd_soc_dai *dai = NULL; 2730 unsigned long factor; 2731 2732 if (!rt5682_clk_check(rt5682)) 2733 return -EINVAL; 2734 2735 factor = rt5682_bclk_get_factor(rate, parent_rate); 2736 2737 for_each_component_dais(component, dai) 2738 if (dai->id == RT5682_AIF1) 2739 break; 2740 if (!dai) { 2741 dev_err(component->dev, "dai %d not found in component\n", 2742 RT5682_AIF1); 2743 return -ENODEV; 2744 } 2745 2746 return rt5682_set_bclk1_ratio(dai, factor); 2747 } 2748 2749 static const struct clk_ops rt5682_dai_clk_ops[RT5682_DAI_NUM_CLKS] = { 2750 [RT5682_DAI_WCLK_IDX] = { 2751 .prepare = rt5682_wclk_prepare, 2752 .unprepare = rt5682_wclk_unprepare, 2753 .recalc_rate = rt5682_wclk_recalc_rate, 2754 .round_rate = rt5682_wclk_round_rate, 2755 .set_rate = rt5682_wclk_set_rate, 2756 }, 2757 [RT5682_DAI_BCLK_IDX] = { 2758 .recalc_rate = rt5682_bclk_recalc_rate, 2759 .round_rate = rt5682_bclk_round_rate, 2760 .set_rate = rt5682_bclk_set_rate, 2761 }, 2762 }; 2763 2764 static int rt5682_register_dai_clks(struct snd_soc_component *component) 2765 { 2766 struct device *dev = component->dev; 2767 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2768 struct rt5682_platform_data *pdata = &rt5682->pdata; 2769 struct clk_init_data init; 2770 struct clk *dai_clk; 2771 struct clk_lookup *dai_clk_lookup; 2772 struct clk_hw *dai_clk_hw; 2773 const char *parent_name; 2774 int i, ret; 2775 2776 for (i = 0; i < RT5682_DAI_NUM_CLKS; ++i) { 2777 dai_clk_hw = &rt5682->dai_clks_hw[i]; 2778 2779 switch (i) { 2780 case RT5682_DAI_WCLK_IDX: 2781 /* Make MCLK the parent of WCLK */ 2782 if (rt5682->mclk) { 2783 parent_name = __clk_get_name(rt5682->mclk); 2784 init.parent_names = &parent_name; 2785 init.num_parents = 1; 2786 } else { 2787 init.parent_names = NULL; 2788 init.num_parents = 0; 2789 } 2790 break; 2791 case RT5682_DAI_BCLK_IDX: 2792 /* Make WCLK the parent of BCLK */ 2793 parent_name = __clk_get_name( 2794 rt5682->dai_clks[RT5682_DAI_WCLK_IDX]); 2795 init.parent_names = &parent_name; 2796 init.num_parents = 1; 2797 break; 2798 default: 2799 dev_err(dev, "Invalid clock index\n"); 2800 ret = -EINVAL; 2801 goto err; 2802 } 2803 2804 init.name = pdata->dai_clk_names[i]; 2805 init.ops = &rt5682_dai_clk_ops[i]; 2806 init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE; 2807 dai_clk_hw->init = &init; 2808 2809 dai_clk = devm_clk_register(dev, dai_clk_hw); 2810 if (IS_ERR(dai_clk)) { 2811 dev_warn(dev, "Failed to register %s: %ld\n", 2812 init.name, PTR_ERR(dai_clk)); 2813 ret = PTR_ERR(dai_clk); 2814 goto err; 2815 } 2816 rt5682->dai_clks[i] = dai_clk; 2817 2818 if (dev->of_node) { 2819 devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 2820 dai_clk_hw); 2821 } else { 2822 dai_clk_lookup = clkdev_create(dai_clk, init.name, 2823 "%s", dev_name(dev)); 2824 if (!dai_clk_lookup) { 2825 ret = -ENOMEM; 2826 goto err; 2827 } else { 2828 rt5682->dai_clks_lookup[i] = dai_clk_lookup; 2829 } 2830 } 2831 } 2832 2833 return 0; 2834 2835 err: 2836 do { 2837 if (rt5682->dai_clks_lookup[i]) 2838 clkdev_drop(rt5682->dai_clks_lookup[i]); 2839 } while (i-- > 0); 2840 2841 return ret; 2842 } 2843 #endif /* CONFIG_COMMON_CLK */ 2844 2845 static int rt5682_probe(struct snd_soc_component *component) 2846 { 2847 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2848 struct sdw_slave *slave; 2849 unsigned long time; 2850 struct snd_soc_dapm_context *dapm = &component->dapm; 2851 2852 #ifdef CONFIG_COMMON_CLK 2853 int ret; 2854 #endif 2855 rt5682->component = component; 2856 2857 if (rt5682->is_sdw) { 2858 slave = rt5682->slave; 2859 time = wait_for_completion_timeout( 2860 &slave->initialization_complete, 2861 msecs_to_jiffies(RT5682_PROBE_TIMEOUT)); 2862 if (!time) { 2863 dev_err(&slave->dev, "Initialization not complete, timed out\n"); 2864 return -ETIMEDOUT; 2865 } 2866 } else { 2867 #ifdef CONFIG_COMMON_CLK 2868 /* Check if MCLK provided */ 2869 rt5682->mclk = devm_clk_get(component->dev, "mclk"); 2870 if (IS_ERR(rt5682->mclk)) { 2871 if (PTR_ERR(rt5682->mclk) != -ENOENT) { 2872 ret = PTR_ERR(rt5682->mclk); 2873 return ret; 2874 } 2875 rt5682->mclk = NULL; 2876 } 2877 2878 /* Register CCF DAI clock control */ 2879 ret = rt5682_register_dai_clks(component); 2880 if (ret) 2881 return ret; 2882 2883 /* Initial setup for CCF */ 2884 rt5682->lrck[RT5682_AIF1] = CLK_48; 2885 #endif 2886 } 2887 2888 snd_soc_dapm_disable_pin(dapm, "MICBIAS"); 2889 snd_soc_dapm_disable_pin(dapm, "Vref2"); 2890 snd_soc_dapm_sync(dapm); 2891 return 0; 2892 } 2893 2894 static void rt5682_remove(struct snd_soc_component *component) 2895 { 2896 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2897 2898 #ifdef CONFIG_COMMON_CLK 2899 int i; 2900 2901 for (i = RT5682_DAI_NUM_CLKS - 1; i >= 0; --i) { 2902 if (rt5682->dai_clks_lookup[i]) 2903 clkdev_drop(rt5682->dai_clks_lookup[i]); 2904 } 2905 #endif 2906 2907 rt5682_reset(rt5682); 2908 } 2909 2910 #ifdef CONFIG_PM 2911 static int rt5682_suspend(struct snd_soc_component *component) 2912 { 2913 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2914 2915 regcache_cache_only(rt5682->regmap, true); 2916 regcache_mark_dirty(rt5682->regmap); 2917 return 0; 2918 } 2919 2920 static int rt5682_resume(struct snd_soc_component *component) 2921 { 2922 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component); 2923 2924 regcache_cache_only(rt5682->regmap, false); 2925 regcache_sync(rt5682->regmap); 2926 2927 mod_delayed_work(system_power_efficient_wq, 2928 &rt5682->jack_detect_work, msecs_to_jiffies(250)); 2929 2930 return 0; 2931 } 2932 #else 2933 #define rt5682_suspend NULL 2934 #define rt5682_resume NULL 2935 #endif 2936 2937 const struct snd_soc_dai_ops rt5682_aif1_dai_ops = { 2938 .hw_params = rt5682_hw_params, 2939 .set_fmt = rt5682_set_dai_fmt, 2940 .set_tdm_slot = rt5682_set_tdm_slot, 2941 .set_bclk_ratio = rt5682_set_bclk1_ratio, 2942 }; 2943 EXPORT_SYMBOL_GPL(rt5682_aif1_dai_ops); 2944 2945 const struct snd_soc_dai_ops rt5682_aif2_dai_ops = { 2946 .hw_params = rt5682_hw_params, 2947 .set_fmt = rt5682_set_dai_fmt, 2948 .set_bclk_ratio = rt5682_set_bclk2_ratio, 2949 }; 2950 EXPORT_SYMBOL_GPL(rt5682_aif2_dai_ops); 2951 2952 const struct snd_soc_component_driver rt5682_soc_component_dev = { 2953 .probe = rt5682_probe, 2954 .remove = rt5682_remove, 2955 .suspend = rt5682_suspend, 2956 .resume = rt5682_resume, 2957 .set_bias_level = rt5682_set_bias_level, 2958 .controls = rt5682_snd_controls, 2959 .num_controls = ARRAY_SIZE(rt5682_snd_controls), 2960 .dapm_widgets = rt5682_dapm_widgets, 2961 .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets), 2962 .dapm_routes = rt5682_dapm_routes, 2963 .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes), 2964 .set_sysclk = rt5682_set_component_sysclk, 2965 .set_pll = rt5682_set_component_pll, 2966 .set_jack = rt5682_set_jack_detect, 2967 .use_pmdown_time = 1, 2968 .endianness = 1, 2969 .non_legacy_dai_naming = 1, 2970 }; 2971 EXPORT_SYMBOL_GPL(rt5682_soc_component_dev); 2972 2973 int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev) 2974 { 2975 2976 device_property_read_u32(dev, "realtek,dmic1-data-pin", 2977 &rt5682->pdata.dmic1_data_pin); 2978 device_property_read_u32(dev, "realtek,dmic1-clk-pin", 2979 &rt5682->pdata.dmic1_clk_pin); 2980 device_property_read_u32(dev, "realtek,jd-src", 2981 &rt5682->pdata.jd_src); 2982 device_property_read_u32(dev, "realtek,btndet-delay", 2983 &rt5682->pdata.btndet_delay); 2984 device_property_read_u32(dev, "realtek,dmic-clk-rate-hz", 2985 &rt5682->pdata.dmic_clk_rate); 2986 device_property_read_u32(dev, "realtek,dmic-delay-ms", 2987 &rt5682->pdata.dmic_delay); 2988 2989 rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node, 2990 "realtek,ldo1-en-gpios", 0); 2991 2992 if (device_property_read_string_array(dev, "clock-output-names", 2993 rt5682->pdata.dai_clk_names, 2994 RT5682_DAI_NUM_CLKS) < 0) 2995 dev_warn(dev, "Using default DAI clk names: %s, %s\n", 2996 rt5682->pdata.dai_clk_names[RT5682_DAI_WCLK_IDX], 2997 rt5682->pdata.dai_clk_names[RT5682_DAI_BCLK_IDX]); 2998 2999 return 0; 3000 } 3001 EXPORT_SYMBOL_GPL(rt5682_parse_dt); 3002 3003 void rt5682_calibrate(struct rt5682_priv *rt5682) 3004 { 3005 int value, count; 3006 3007 mutex_lock(&rt5682->calibrate_mutex); 3008 3009 rt5682_reset(rt5682); 3010 regmap_write(rt5682->regmap, RT5682_I2C_CTRL, 0x000f); 3011 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af); 3012 usleep_range(15000, 20000); 3013 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af); 3014 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300); 3015 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000); 3016 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100); 3017 regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800); 3018 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000); 3019 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005); 3020 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c); 3021 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d); 3022 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321); 3023 regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004); 3024 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); 3025 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1); 3026 regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311); 3027 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); 3028 3029 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00); 3030 3031 for (count = 0; count < 60; count++) { 3032 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value); 3033 if (!(value & 0x8000)) 3034 break; 3035 3036 usleep_range(10000, 10005); 3037 } 3038 3039 if (count >= 60) 3040 dev_err(rt5682->component->dev, "HP Calibration Failure\n"); 3041 3042 /* restore settings */ 3043 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x002f); 3044 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080); 3045 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000); 3046 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000); 3047 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000); 3048 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005); 3049 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4); 3050 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0c0c); 3051 3052 mutex_unlock(&rt5682->calibrate_mutex); 3053 } 3054 EXPORT_SYMBOL_GPL(rt5682_calibrate); 3055 3056 MODULE_DESCRIPTION("ASoC RT5682 driver"); 3057 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); 3058 MODULE_LICENSE("GPL v2"); 3059