1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/jz4780-cgu.h>
3#include <dt-bindings/dma/jz4780-dma.h>
4
5/ {
6	#address-cells = <1>;
7	#size-cells = <1>;
8	compatible = "ingenic,jz4780";
9
10	cpuintc: interrupt-controller {
11		#address-cells = <0>;
12		#interrupt-cells = <1>;
13		interrupt-controller;
14		compatible = "mti,cpu-interrupt-controller";
15	};
16
17	intc: interrupt-controller@10001000 {
18		compatible = "ingenic,jz4780-intc";
19		reg = <0x10001000 0x50>;
20
21		interrupt-controller;
22		#interrupt-cells = <1>;
23
24		interrupt-parent = <&cpuintc>;
25		interrupts = <2>;
26	};
27
28	ext: ext {
29		compatible = "fixed-clock";
30		#clock-cells = <0>;
31	};
32
33	rtc: rtc {
34		compatible = "fixed-clock";
35		#clock-cells = <0>;
36		clock-frequency = <32768>;
37	};
38
39	cgu: jz4780-cgu@10000000 {
40		compatible = "ingenic,jz4780-cgu";
41		reg = <0x10000000 0x100>;
42
43		clocks = <&ext>, <&rtc>;
44		clock-names = "ext", "rtc";
45
46		#clock-cells = <1>;
47	};
48
49	tcu: timer@10002000 {
50		compatible = "ingenic,jz4780-tcu",
51			     "ingenic,jz4770-tcu",
52			     "simple-mfd";
53		reg = <0x10002000 0x1000>;
54		#address-cells = <1>;
55		#size-cells = <1>;
56		ranges = <0x0 0x10002000 0x1000>;
57
58		#clock-cells = <1>;
59
60		clocks = <&cgu JZ4780_CLK_RTCLK
61			  &cgu JZ4780_CLK_EXCLK
62			  &cgu JZ4780_CLK_PCLK>;
63		clock-names = "rtc", "ext", "pclk";
64
65		interrupt-controller;
66		#interrupt-cells = <1>;
67
68		interrupt-parent = <&intc>;
69		interrupts = <27 26 25>;
70	};
71
72	rtc_dev: rtc@10003000 {
73		compatible = "ingenic,jz4780-rtc";
74		reg = <0x10003000 0x4c>;
75
76		interrupt-parent = <&intc>;
77		interrupts = <32>;
78
79		clocks = <&cgu JZ4780_CLK_RTCLK>;
80		clock-names = "rtc";
81	};
82
83	pinctrl: pin-controller@10010000 {
84		compatible = "ingenic,jz4780-pinctrl";
85		reg = <0x10010000 0x600>;
86
87		#address-cells = <1>;
88		#size-cells = <0>;
89
90		gpa: gpio@0 {
91			compatible = "ingenic,jz4780-gpio";
92			reg = <0>;
93
94			gpio-controller;
95			gpio-ranges = <&pinctrl 0 0 32>;
96			#gpio-cells = <2>;
97
98			interrupt-controller;
99			#interrupt-cells = <2>;
100
101			interrupt-parent = <&intc>;
102			interrupts = <17>;
103		};
104
105		gpb: gpio@1 {
106			compatible = "ingenic,jz4780-gpio";
107			reg = <1>;
108
109			gpio-controller;
110			gpio-ranges = <&pinctrl 0 32 32>;
111			#gpio-cells = <2>;
112
113			interrupt-controller;
114			#interrupt-cells = <2>;
115
116			interrupt-parent = <&intc>;
117			interrupts = <16>;
118		};
119
120		gpc: gpio@2 {
121			compatible = "ingenic,jz4780-gpio";
122			reg = <2>;
123
124			gpio-controller;
125			gpio-ranges = <&pinctrl 0 64 32>;
126			#gpio-cells = <2>;
127
128			interrupt-controller;
129			#interrupt-cells = <2>;
130
131			interrupt-parent = <&intc>;
132			interrupts = <15>;
133		};
134
135		gpd: gpio@3 {
136			compatible = "ingenic,jz4780-gpio";
137			reg = <3>;
138
139			gpio-controller;
140			gpio-ranges = <&pinctrl 0 96 32>;
141			#gpio-cells = <2>;
142
143			interrupt-controller;
144			#interrupt-cells = <2>;
145
146			interrupt-parent = <&intc>;
147			interrupts = <14>;
148		};
149
150		gpe: gpio@4 {
151			compatible = "ingenic,jz4780-gpio";
152			reg = <4>;
153
154			gpio-controller;
155			gpio-ranges = <&pinctrl 0 128 32>;
156			#gpio-cells = <2>;
157
158			interrupt-controller;
159			#interrupt-cells = <2>;
160
161			interrupt-parent = <&intc>;
162			interrupts = <13>;
163		};
164
165		gpf: gpio@5 {
166			compatible = "ingenic,jz4780-gpio";
167			reg = <5>;
168
169			gpio-controller;
170			gpio-ranges = <&pinctrl 0 160 32>;
171			#gpio-cells = <2>;
172
173			interrupt-controller;
174			#interrupt-cells = <2>;
175
176			interrupt-parent = <&intc>;
177			interrupts = <12>;
178		};
179	};
180
181	spi_gpio {
182		compatible = "spi-gpio";
183		#address-cells = <1>;
184		#size-cells = <0>;
185		num-chipselects = <2>;
186
187		gpio-miso = <&gpe 14 0>;
188		gpio-sck = <&gpe 15 0>;
189		gpio-mosi = <&gpe 17 0>;
190		cs-gpios = <&gpe 16 0
191			    &gpe 18 0>;
192
193		spidev@0 {
194			compatible = "spidev";
195			reg = <0>;
196			spi-max-frequency = <1000000>;
197		};
198	};
199
200	uart0: serial@10030000 {
201		compatible = "ingenic,jz4780-uart";
202		reg = <0x10030000 0x100>;
203
204		interrupt-parent = <&intc>;
205		interrupts = <51>;
206
207		clocks = <&ext>, <&cgu JZ4780_CLK_UART0>;
208		clock-names = "baud", "module";
209
210		status = "disabled";
211	};
212
213	uart1: serial@10031000 {
214		compatible = "ingenic,jz4780-uart";
215		reg = <0x10031000 0x100>;
216
217		interrupt-parent = <&intc>;
218		interrupts = <50>;
219
220		clocks = <&ext>, <&cgu JZ4780_CLK_UART1>;
221		clock-names = "baud", "module";
222
223		status = "disabled";
224	};
225
226	uart2: serial@10032000 {
227		compatible = "ingenic,jz4780-uart";
228		reg = <0x10032000 0x100>;
229
230		interrupt-parent = <&intc>;
231		interrupts = <49>;
232
233		clocks = <&ext>, <&cgu JZ4780_CLK_UART2>;
234		clock-names = "baud", "module";
235
236		status = "disabled";
237	};
238
239	uart3: serial@10033000 {
240		compatible = "ingenic,jz4780-uart";
241		reg = <0x10033000 0x100>;
242
243		interrupt-parent = <&intc>;
244		interrupts = <48>;
245
246		clocks = <&ext>, <&cgu JZ4780_CLK_UART3>;
247		clock-names = "baud", "module";
248
249		status = "disabled";
250	};
251
252	uart4: serial@10034000 {
253		compatible = "ingenic,jz4780-uart";
254		reg = <0x10034000 0x100>;
255
256		interrupt-parent = <&intc>;
257		interrupts = <34>;
258
259		clocks = <&ext>, <&cgu JZ4780_CLK_UART4>;
260		clock-names = "baud", "module";
261
262		status = "disabled";
263	};
264
265	i2c0: i2c@10050000 {
266		compatible = "ingenic,jz4780-i2c";
267		#address-cells = <1>;
268		#size-cells = <0>;
269
270		reg = <0x10050000 0x1000>;
271
272		interrupt-parent = <&intc>;
273		interrupts = <60>;
274
275		clocks = <&cgu JZ4780_CLK_SMB0>;
276		clock-frequency = <100000>;
277		pinctrl-names = "default";
278		pinctrl-0 = <&pins_i2c0_data>;
279
280		status = "disabled";
281	};
282
283	i2c1: i2c@10051000 {
284		compatible = "ingenic,jz4780-i2c";
285		#address-cells = <1>;
286		#size-cells = <0>;
287		reg = <0x10051000 0x1000>;
288
289		interrupt-parent = <&intc>;
290		interrupts = <59>;
291
292		clocks = <&cgu JZ4780_CLK_SMB1>;
293		clock-frequency = <100000>;
294		pinctrl-names = "default";
295		pinctrl-0 = <&pins_i2c1_data>;
296
297		status = "disabled";
298	};
299
300	i2c2: i2c@10052000 {
301		compatible = "ingenic,jz4780-i2c";
302		#address-cells = <1>;
303		#size-cells = <0>;
304		reg = <0x10052000 0x1000>;
305
306		interrupt-parent = <&intc>;
307		interrupts = <58>;
308
309		clocks = <&cgu JZ4780_CLK_SMB2>;
310		clock-frequency = <100000>;
311		pinctrl-names = "default";
312		pinctrl-0 = <&pins_i2c2_data>;
313
314		status = "disabled";
315	};
316
317	i2c3: i2c@10053000 {
318		compatible = "ingenic,jz4780-i2c";
319		#address-cells = <1>;
320		#size-cells = <0>;
321		reg = <0x10053000 0x1000>;
322
323		interrupt-parent = <&intc>;
324		interrupts = <57>;
325
326		clocks = <&cgu JZ4780_CLK_SMB3>;
327		clock-frequency = <100000>;
328		pinctrl-names = "default";
329		pinctrl-0 = <&pins_i2c3_data>;
330
331		status = "disabled";
332	};
333
334	i2c4: i2c@10054000 {
335		compatible = "ingenic,jz4780-i2c";
336		#address-cells = <1>;
337		#size-cells = <0>;
338		reg = <0x10054000 0x1000>;
339
340		interrupt-parent = <&intc>;
341		interrupts = <56>;
342
343		clocks = <&cgu JZ4780_CLK_SMB4>;
344		clock-frequency = <100000>;
345		pinctrl-names = "default";
346		pinctrl-0 = <&pins_i2c4_data>;
347
348		status = "disabled";
349	};
350
351	watchdog: watchdog@10002000 {
352		compatible = "ingenic,jz4780-watchdog";
353		reg = <0x10002000 0x10>;
354
355		clocks = <&cgu JZ4780_CLK_RTCLK>;
356		clock-names = "rtc";
357	};
358
359	nemc: nemc@13410000 {
360		compatible = "ingenic,jz4780-nemc";
361		reg = <0x13410000 0x10000>;
362		#address-cells = <2>;
363		#size-cells = <1>;
364		ranges = <1 0 0x1b000000 0x1000000
365			  2 0 0x1a000000 0x1000000
366			  3 0 0x19000000 0x1000000
367			  4 0 0x18000000 0x1000000
368			  5 0 0x17000000 0x1000000
369			  6 0 0x16000000 0x1000000>;
370
371		clocks = <&cgu JZ4780_CLK_NEMC>;
372
373		status = "disabled";
374	};
375
376	dma: dma@13420000 {
377		compatible = "ingenic,jz4780-dma";
378		reg = <0x13420000 0x400
379		       0x13421000 0x40>;
380		#dma-cells = <2>;
381
382		interrupt-parent = <&intc>;
383		interrupts = <10>;
384
385		clocks = <&cgu JZ4780_CLK_PDMA>;
386	};
387
388	mmc0: mmc@13450000 {
389		compatible = "ingenic,jz4780-mmc";
390		reg = <0x13450000 0x1000>;
391
392		interrupt-parent = <&intc>;
393		interrupts = <37>;
394
395		clocks = <&cgu JZ4780_CLK_MSC0>;
396		clock-names = "mmc";
397
398		cap-sd-highspeed;
399		cap-mmc-highspeed;
400		cap-sdio-irq;
401		dmas = <&dma JZ4780_DMA_MSC0_RX 0xffffffff>,
402		       <&dma JZ4780_DMA_MSC0_TX 0xffffffff>;
403		dma-names = "rx", "tx";
404
405		status = "disabled";
406	};
407
408	mmc1: mmc@13460000 {
409		compatible = "ingenic,jz4780-mmc";
410		reg = <0x13460000 0x1000>;
411
412		interrupt-parent = <&intc>;
413		interrupts = <36>;
414
415		clocks = <&cgu JZ4780_CLK_MSC1>;
416		clock-names = "mmc";
417
418		cap-sd-highspeed;
419		cap-mmc-highspeed;
420		cap-sdio-irq;
421		dmas = <&dma JZ4780_DMA_MSC1_RX 0xffffffff>,
422		       <&dma JZ4780_DMA_MSC1_TX 0xffffffff>;
423		dma-names = "rx", "tx";
424
425		status = "disabled";
426	};
427
428	bch: bch@134d0000 {
429		compatible = "ingenic,jz4780-bch";
430		reg = <0x134d0000 0x10000>;
431
432		clocks = <&cgu JZ4780_CLK_BCH>;
433
434		status = "disabled";
435	};
436};
437