1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel Lynxpoint PCH pinctrl/GPIO driver 4 * 5 * Copyright (c) 2012, 2019, Intel Corporation 6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> 7 * Andy Shevchenko <andriy.shevchenko@linux.intel.com> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/bitops.h> 12 #include <linux/gpio/driver.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/slab.h> 20 #include <linux/types.h> 21 22 #include <linux/pinctrl/pinctrl.h> 23 #include <linux/pinctrl/pinmux.h> 24 #include <linux/pinctrl/pinconf.h> 25 #include <linux/pinctrl/pinconf-generic.h> 26 27 #include "pinctrl-intel.h" 28 29 #define COMMUNITY(p, n) \ 30 { \ 31 .pin_base = (p), \ 32 .npins = (n), \ 33 } 34 35 static const struct pinctrl_pin_desc lptlp_pins[] = { 36 PINCTRL_PIN(0, "GP0_UART1_RXD"), 37 PINCTRL_PIN(1, "GP1_UART1_TXD"), 38 PINCTRL_PIN(2, "GP2_UART1_RTSB"), 39 PINCTRL_PIN(3, "GP3_UART1_CTSB"), 40 PINCTRL_PIN(4, "GP4_I2C0_SDA"), 41 PINCTRL_PIN(5, "GP5_I2C0_SCL"), 42 PINCTRL_PIN(6, "GP6_I2C1_SDA"), 43 PINCTRL_PIN(7, "GP7_I2C1_SCL"), 44 PINCTRL_PIN(8, "GP8"), 45 PINCTRL_PIN(9, "GP9"), 46 PINCTRL_PIN(10, "GP10"), 47 PINCTRL_PIN(11, "GP11_SMBALERTB"), 48 PINCTRL_PIN(12, "GP12_LANPHYPC"), 49 PINCTRL_PIN(13, "GP13"), 50 PINCTRL_PIN(14, "GP14"), 51 PINCTRL_PIN(15, "GP15"), 52 PINCTRL_PIN(16, "GP16_MGPIO9"), 53 PINCTRL_PIN(17, "GP17_MGPIO10"), 54 PINCTRL_PIN(18, "GP18_SRC0CLKRQB"), 55 PINCTRL_PIN(19, "GP19_SRC1CLKRQB"), 56 PINCTRL_PIN(20, "GP20_SRC2CLKRQB"), 57 PINCTRL_PIN(21, "GP21_SRC3CLKRQB"), 58 PINCTRL_PIN(22, "GP22_SRC4CLKRQB_TRST2"), 59 PINCTRL_PIN(23, "GP23_SRC5CLKRQB_TDI2"), 60 PINCTRL_PIN(24, "GP24_MGPIO0"), 61 PINCTRL_PIN(25, "GP25_USBWAKEOUTB"), 62 PINCTRL_PIN(26, "GP26_MGPIO5"), 63 PINCTRL_PIN(27, "GP27_MGPIO6"), 64 PINCTRL_PIN(28, "GP28_MGPIO7"), 65 PINCTRL_PIN(29, "GP29_SLP_WLANB_MGPIO3"), 66 PINCTRL_PIN(30, "GP30_SUSWARNB_SUSPWRDNACK_MGPIO1"), 67 PINCTRL_PIN(31, "GP31_ACPRESENT_MGPIO2"), 68 PINCTRL_PIN(32, "GP32_CLKRUNB"), 69 PINCTRL_PIN(33, "GP33_DEVSLP0"), 70 PINCTRL_PIN(34, "GP34_SATA0XPCIE6L3B_SATA0GP"), 71 PINCTRL_PIN(35, "GP35_SATA1XPCIE6L2B_SATA1GP"), 72 PINCTRL_PIN(36, "GP36_SATA2XPCIE6L1B_SATA2GP"), 73 PINCTRL_PIN(37, "GP37_SATA3XPCIE6L0B_SATA3GP"), 74 PINCTRL_PIN(38, "GP38_DEVSLP1"), 75 PINCTRL_PIN(39, "GP39_DEVSLP2"), 76 PINCTRL_PIN(40, "GP40_OC0B"), 77 PINCTRL_PIN(41, "GP41_OC1B"), 78 PINCTRL_PIN(42, "GP42_OC2B"), 79 PINCTRL_PIN(43, "GP43_OC3B"), 80 PINCTRL_PIN(44, "GP44"), 81 PINCTRL_PIN(45, "GP45_TMS2"), 82 PINCTRL_PIN(46, "GP46_TDO2"), 83 PINCTRL_PIN(47, "GP47"), 84 PINCTRL_PIN(48, "GP48"), 85 PINCTRL_PIN(49, "GP49"), 86 PINCTRL_PIN(50, "GP50"), 87 PINCTRL_PIN(51, "GP51_GSXDOUT"), 88 PINCTRL_PIN(52, "GP52_GSXSLOAD"), 89 PINCTRL_PIN(53, "GP53_GSXDIN"), 90 PINCTRL_PIN(54, "GP54_GSXSRESETB"), 91 PINCTRL_PIN(55, "GP55_GSXCLK"), 92 PINCTRL_PIN(56, "GP56"), 93 PINCTRL_PIN(57, "GP57"), 94 PINCTRL_PIN(58, "GP58"), 95 PINCTRL_PIN(59, "GP59"), 96 PINCTRL_PIN(60, "GP60_SML0ALERTB_MGPIO4"), 97 PINCTRL_PIN(61, "GP61_SUS_STATB"), 98 PINCTRL_PIN(62, "GP62_SUSCLK"), 99 PINCTRL_PIN(63, "GP63_SLP_S5B"), 100 PINCTRL_PIN(64, "GP64_SDIO_CLK"), 101 PINCTRL_PIN(65, "GP65_SDIO_CMD"), 102 PINCTRL_PIN(66, "GP66_SDIO_D0"), 103 PINCTRL_PIN(67, "GP67_SDIO_D1"), 104 PINCTRL_PIN(68, "GP68_SDIO_D2"), 105 PINCTRL_PIN(69, "GP69_SDIO_D3"), 106 PINCTRL_PIN(70, "GP70_SDIO_POWER_EN"), 107 PINCTRL_PIN(71, "GP71_MPHYPC"), 108 PINCTRL_PIN(72, "GP72_BATLOWB"), 109 PINCTRL_PIN(73, "GP73_SML1ALERTB_PCHHOTB_MGPIO8"), 110 PINCTRL_PIN(74, "GP74_SML1DATA_MGPIO12"), 111 PINCTRL_PIN(75, "GP75_SML1CLK_MGPIO11"), 112 PINCTRL_PIN(76, "GP76_BMBUSYB"), 113 PINCTRL_PIN(77, "GP77_PIRQAB"), 114 PINCTRL_PIN(78, "GP78_PIRQBB"), 115 PINCTRL_PIN(79, "GP79_PIRQCB"), 116 PINCTRL_PIN(80, "GP80_PIRQDB"), 117 PINCTRL_PIN(81, "GP81_SPKR"), 118 PINCTRL_PIN(82, "GP82_RCINB"), 119 PINCTRL_PIN(83, "GP83_GSPI0_CSB"), 120 PINCTRL_PIN(84, "GP84_GSPI0_CLK"), 121 PINCTRL_PIN(85, "GP85_GSPI0_MISO"), 122 PINCTRL_PIN(86, "GP86_GSPI0_MOSI"), 123 PINCTRL_PIN(87, "GP87_GSPI1_CSB"), 124 PINCTRL_PIN(88, "GP88_GSPI1_CLK"), 125 PINCTRL_PIN(89, "GP89_GSPI1_MISO"), 126 PINCTRL_PIN(90, "GP90_GSPI1_MOSI"), 127 PINCTRL_PIN(91, "GP91_UART0_RXD"), 128 PINCTRL_PIN(92, "GP92_UART0_TXD"), 129 PINCTRL_PIN(93, "GP93_UART0_RTSB"), 130 PINCTRL_PIN(94, "GP94_UART0_CTSB"), 131 }; 132 133 static const struct intel_community lptlp_communities[] = { 134 COMMUNITY(0, 95), 135 }; 136 137 static const struct intel_pinctrl_soc_data lptlp_soc_data = { 138 .pins = lptlp_pins, 139 .npins = ARRAY_SIZE(lptlp_pins), 140 .communities = lptlp_communities, 141 .ncommunities = ARRAY_SIZE(lptlp_communities), 142 }; 143 144 /* LynxPoint chipset has support for 95 GPIO pins */ 145 146 #define LP_NUM_GPIO 95 147 148 /* Bitmapped register offsets */ 149 #define LP_ACPI_OWNED 0x00 /* Bitmap, set by bios, 0: pin reserved for ACPI */ 150 #define LP_IRQ2IOXAPIC 0x10 /* Bitmap, set by bios, 1: pin routed to IOxAPIC */ 151 #define LP_GC 0x7C /* set APIC IRQ to IRQ14 or IRQ15 for all pins */ 152 #define LP_INT_STAT 0x80 153 #define LP_INT_ENABLE 0x90 154 155 /* Each pin has two 32 bit config registers, starting at 0x100 */ 156 #define LP_CONFIG1 0x100 157 #define LP_CONFIG2 0x104 158 159 /* LP_CONFIG1 reg bits */ 160 #define OUT_LVL_BIT BIT(31) 161 #define IN_LVL_BIT BIT(30) 162 #define TRIG_SEL_BIT BIT(4) /* 0: Edge, 1: Level */ 163 #define INT_INV_BIT BIT(3) /* Invert interrupt triggering */ 164 #define DIR_BIT BIT(2) /* 0: Output, 1: Input */ 165 #define USE_SEL_MASK GENMASK(1, 0) /* 0: Native, 1: GPIO, ... */ 166 #define USE_SEL_NATIVE (0 << 0) 167 #define USE_SEL_GPIO (1 << 0) 168 169 /* LP_CONFIG2 reg bits */ 170 #define GPINDIS_BIT BIT(2) /* disable input sensing */ 171 #define GPIWP_MASK GENMASK(1, 0) /* weak pull options */ 172 #define GPIWP_NONE 0 /* none */ 173 #define GPIWP_DOWN 1 /* weak pull down */ 174 #define GPIWP_UP 2 /* weak pull up */ 175 176 /* 177 * Lynxpoint gpios are controlled through both bitmapped registers and 178 * per gpio specific registers. The bitmapped registers are in chunks of 179 * 3 x 32bit registers to cover all 95 GPIOs 180 * 181 * per gpio specific registers consist of two 32bit registers per gpio 182 * (LP_CONFIG1 and LP_CONFIG2), with 95 GPIOs there's a total of 183 * 190 config registers. 184 * 185 * A simplified view of the register layout look like this: 186 * 187 * LP_ACPI_OWNED[31:0] gpio ownerships for gpios 0-31 (bitmapped registers) 188 * LP_ACPI_OWNED[63:32] gpio ownerships for gpios 32-63 189 * LP_ACPI_OWNED[94:64] gpio ownerships for gpios 63-94 190 * ... 191 * LP_INT_ENABLE[31:0] ... 192 * LP_INT_ENABLE[63:32] ... 193 * LP_INT_ENABLE[94:64] ... 194 * LP0_CONFIG1 (gpio 0) config1 reg for gpio 0 (per gpio registers) 195 * LP0_CONFIG2 (gpio 0) config2 reg for gpio 0 196 * LP1_CONFIG1 (gpio 1) config1 reg for gpio 1 197 * LP1_CONFIG2 (gpio 1) config2 reg for gpio 1 198 * LP2_CONFIG1 (gpio 2) ... 199 * LP2_CONFIG2 (gpio 2) ... 200 * ... 201 * LP94_CONFIG1 (gpio 94) ... 202 * LP94_CONFIG2 (gpio 94) ... 203 * 204 * IOxAPIC redirection map applies only for gpio 8-10, 13-14, 45-55. 205 */ 206 207 static struct intel_community *lp_get_community(struct intel_pinctrl *lg, 208 unsigned int pin) 209 { 210 struct intel_community *comm; 211 int i; 212 213 for (i = 0; i < lg->ncommunities; i++) { 214 comm = &lg->communities[i]; 215 if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base) 216 return comm; 217 } 218 219 return NULL; 220 } 221 222 static void __iomem *lp_gpio_reg(struct gpio_chip *chip, unsigned int offset, 223 int reg) 224 { 225 struct intel_pinctrl *lg = gpiochip_get_data(chip); 226 struct intel_community *comm; 227 int reg_offset; 228 229 comm = lp_get_community(lg, offset); 230 if (!comm) 231 return NULL; 232 233 offset -= comm->pin_base; 234 235 if (reg == LP_CONFIG1 || reg == LP_CONFIG2) 236 /* per gpio specific config registers */ 237 reg_offset = offset * 8; 238 else 239 /* bitmapped registers */ 240 reg_offset = (offset / 32) * 4; 241 242 return comm->regs + reg_offset + reg; 243 } 244 245 static bool lp_gpio_acpi_use(struct intel_pinctrl *lg, unsigned int pin) 246 { 247 void __iomem *acpi_use; 248 249 acpi_use = lp_gpio_reg(&lg->chip, pin, LP_ACPI_OWNED); 250 if (!acpi_use) 251 return true; 252 253 return !(ioread32(acpi_use) & BIT(pin % 32)); 254 } 255 256 static bool lp_gpio_ioxapic_use(struct gpio_chip *chip, unsigned int offset) 257 { 258 void __iomem *ioxapic_use = lp_gpio_reg(chip, offset, LP_IRQ2IOXAPIC); 259 u32 value; 260 261 value = ioread32(ioxapic_use); 262 263 if (offset >= 8 && offset <= 10) 264 return !!(value & BIT(offset - 8 + 0)); 265 if (offset >= 13 && offset <= 14) 266 return !!(value & BIT(offset - 13 + 3)); 267 if (offset >= 45 && offset <= 55) 268 return !!(value & BIT(offset - 45 + 5)); 269 270 return false; 271 } 272 273 static int lp_get_groups_count(struct pinctrl_dev *pctldev) 274 { 275 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 276 277 return lg->soc->ngroups; 278 } 279 280 static const char *lp_get_group_name(struct pinctrl_dev *pctldev, 281 unsigned int selector) 282 { 283 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 284 285 return lg->soc->groups[selector].name; 286 } 287 288 static int lp_get_group_pins(struct pinctrl_dev *pctldev, 289 unsigned int selector, 290 const unsigned int **pins, 291 unsigned int *num_pins) 292 { 293 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 294 295 *pins = lg->soc->groups[selector].pins; 296 *num_pins = lg->soc->groups[selector].npins; 297 298 return 0; 299 } 300 301 static void lp_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 302 unsigned int pin) 303 { 304 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 305 void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1); 306 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); 307 u32 value, mode; 308 309 value = ioread32(reg); 310 311 mode = value & USE_SEL_MASK; 312 if (mode == USE_SEL_GPIO) 313 seq_puts(s, "GPIO "); 314 else 315 seq_printf(s, "mode %d ", mode); 316 317 seq_printf(s, "0x%08x 0x%08x", value, ioread32(conf2)); 318 319 if (lp_gpio_acpi_use(lg, pin)) 320 seq_puts(s, " [ACPI]"); 321 } 322 323 static const struct pinctrl_ops lptlp_pinctrl_ops = { 324 .get_groups_count = lp_get_groups_count, 325 .get_group_name = lp_get_group_name, 326 .get_group_pins = lp_get_group_pins, 327 .pin_dbg_show = lp_pin_dbg_show, 328 }; 329 330 static int lp_get_functions_count(struct pinctrl_dev *pctldev) 331 { 332 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 333 334 return lg->soc->nfunctions; 335 } 336 337 static const char *lp_get_function_name(struct pinctrl_dev *pctldev, 338 unsigned int selector) 339 { 340 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 341 342 return lg->soc->functions[selector].name; 343 } 344 345 static int lp_get_function_groups(struct pinctrl_dev *pctldev, 346 unsigned int selector, 347 const char * const **groups, 348 unsigned int *num_groups) 349 { 350 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 351 352 *groups = lg->soc->functions[selector].groups; 353 *num_groups = lg->soc->functions[selector].ngroups; 354 355 return 0; 356 } 357 358 static int lp_pinmux_set_mux(struct pinctrl_dev *pctldev, 359 unsigned int function, unsigned int group) 360 { 361 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 362 const struct intel_pingroup *grp = &lg->soc->groups[group]; 363 unsigned long flags; 364 int i; 365 366 raw_spin_lock_irqsave(&lg->lock, flags); 367 368 /* Now enable the mux setting for each pin in the group */ 369 for (i = 0; i < grp->npins; i++) { 370 void __iomem *reg = lp_gpio_reg(&lg->chip, grp->pins[i], LP_CONFIG1); 371 u32 value; 372 373 value = ioread32(reg); 374 375 value &= ~USE_SEL_MASK; 376 if (grp->modes) 377 value |= grp->modes[i]; 378 else 379 value |= grp->mode; 380 381 iowrite32(value, reg); 382 } 383 384 raw_spin_unlock_irqrestore(&lg->lock, flags); 385 386 return 0; 387 } 388 389 static int lp_gpio_request_enable(struct pinctrl_dev *pctldev, 390 struct pinctrl_gpio_range *range, 391 unsigned int pin) 392 { 393 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 394 void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1); 395 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); 396 unsigned long flags; 397 u32 value; 398 399 pm_runtime_get(lg->dev); 400 401 raw_spin_lock_irqsave(&lg->lock, flags); 402 403 /* 404 * Reconfigure pin to GPIO mode if needed and issue a warning, 405 * since we expect firmware to configure it properly. 406 */ 407 value = ioread32(reg); 408 if ((value & USE_SEL_MASK) != USE_SEL_GPIO) { 409 iowrite32((value & USE_SEL_MASK) | USE_SEL_GPIO, reg); 410 dev_warn(lg->dev, FW_BUG "pin %u forcibly reconfigured as GPIO\n", pin); 411 } 412 413 /* Enable input sensing */ 414 iowrite32(ioread32(conf2) & ~GPINDIS_BIT, conf2); 415 416 raw_spin_unlock_irqrestore(&lg->lock, flags); 417 418 return 0; 419 } 420 421 static void lp_gpio_disable_free(struct pinctrl_dev *pctldev, 422 struct pinctrl_gpio_range *range, 423 unsigned int pin) 424 { 425 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 426 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); 427 unsigned long flags; 428 429 raw_spin_lock_irqsave(&lg->lock, flags); 430 431 /* Disable input sensing */ 432 iowrite32(ioread32(conf2) | GPINDIS_BIT, conf2); 433 434 raw_spin_unlock_irqrestore(&lg->lock, flags); 435 436 pm_runtime_put(lg->dev); 437 } 438 439 static int lp_gpio_set_direction(struct pinctrl_dev *pctldev, 440 struct pinctrl_gpio_range *range, 441 unsigned int pin, bool input) 442 { 443 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 444 void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1); 445 unsigned long flags; 446 u32 value; 447 448 raw_spin_lock_irqsave(&lg->lock, flags); 449 450 value = ioread32(reg); 451 value &= ~DIR_BIT; 452 if (input) { 453 value |= DIR_BIT; 454 } else { 455 /* 456 * Before making any direction modifications, do a check if GPIO 457 * is set for direct IRQ. On Lynxpoint, setting GPIO to output 458 * does not make sense, so let's at least warn the caller before 459 * they shoot themselves in the foot. 460 */ 461 WARN(lp_gpio_ioxapic_use(&lg->chip, pin), 462 "Potential Error: Setting GPIO to output with IOxAPIC redirection"); 463 } 464 iowrite32(value, reg); 465 466 raw_spin_unlock_irqrestore(&lg->lock, flags); 467 468 return 0; 469 } 470 471 static const struct pinmux_ops lptlp_pinmux_ops = { 472 .get_functions_count = lp_get_functions_count, 473 .get_function_name = lp_get_function_name, 474 .get_function_groups = lp_get_function_groups, 475 .set_mux = lp_pinmux_set_mux, 476 .gpio_request_enable = lp_gpio_request_enable, 477 .gpio_disable_free = lp_gpio_disable_free, 478 .gpio_set_direction = lp_gpio_set_direction, 479 }; 480 481 static int lp_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 482 unsigned long *config) 483 { 484 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 485 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); 486 enum pin_config_param param = pinconf_to_config_param(*config); 487 unsigned long flags; 488 u32 value, pull; 489 u16 arg = 0; 490 491 raw_spin_lock_irqsave(&lg->lock, flags); 492 value = ioread32(conf2); 493 raw_spin_unlock_irqrestore(&lg->lock, flags); 494 495 pull = value & GPIWP_MASK; 496 497 switch (param) { 498 case PIN_CONFIG_BIAS_DISABLE: 499 if (pull) 500 return -EINVAL; 501 break; 502 case PIN_CONFIG_BIAS_PULL_DOWN: 503 if (pull != GPIWP_DOWN) 504 return -EINVAL; 505 506 arg = 1; 507 break; 508 case PIN_CONFIG_BIAS_PULL_UP: 509 if (pull != GPIWP_UP) 510 return -EINVAL; 511 512 arg = 1; 513 break; 514 default: 515 return -ENOTSUPP; 516 } 517 518 *config = pinconf_to_config_packed(param, arg); 519 520 return 0; 521 } 522 523 static int lp_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 524 unsigned long *configs, unsigned int num_configs) 525 { 526 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); 527 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); 528 enum pin_config_param param; 529 unsigned long flags; 530 int i, ret = 0; 531 u32 value; 532 533 raw_spin_lock_irqsave(&lg->lock, flags); 534 535 value = ioread32(conf2); 536 537 for (i = 0; i < num_configs; i++) { 538 param = pinconf_to_config_param(configs[i]); 539 540 switch (param) { 541 case PIN_CONFIG_BIAS_DISABLE: 542 value &= ~GPIWP_MASK; 543 break; 544 case PIN_CONFIG_BIAS_PULL_DOWN: 545 value &= ~GPIWP_MASK; 546 value |= GPIWP_DOWN; 547 break; 548 case PIN_CONFIG_BIAS_PULL_UP: 549 value &= ~GPIWP_MASK; 550 value |= GPIWP_UP; 551 break; 552 default: 553 ret = -ENOTSUPP; 554 } 555 556 if (ret) 557 break; 558 } 559 560 if (!ret) 561 iowrite32(value, conf2); 562 563 raw_spin_unlock_irqrestore(&lg->lock, flags); 564 565 return ret; 566 } 567 568 static const struct pinconf_ops lptlp_pinconf_ops = { 569 .is_generic = true, 570 .pin_config_get = lp_pin_config_get, 571 .pin_config_set = lp_pin_config_set, 572 }; 573 574 static const struct pinctrl_desc lptlp_pinctrl_desc = { 575 .pctlops = &lptlp_pinctrl_ops, 576 .pmxops = &lptlp_pinmux_ops, 577 .confops = &lptlp_pinconf_ops, 578 .owner = THIS_MODULE, 579 }; 580 581 static int lp_gpio_get(struct gpio_chip *chip, unsigned int offset) 582 { 583 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 584 return !!(ioread32(reg) & IN_LVL_BIT); 585 } 586 587 static void lp_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 588 { 589 struct intel_pinctrl *lg = gpiochip_get_data(chip); 590 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 591 unsigned long flags; 592 593 raw_spin_lock_irqsave(&lg->lock, flags); 594 595 if (value) 596 iowrite32(ioread32(reg) | OUT_LVL_BIT, reg); 597 else 598 iowrite32(ioread32(reg) & ~OUT_LVL_BIT, reg); 599 600 raw_spin_unlock_irqrestore(&lg->lock, flags); 601 } 602 603 static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 604 { 605 return pinctrl_gpio_direction_input(chip->base + offset); 606 } 607 608 static int lp_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, 609 int value) 610 { 611 lp_gpio_set(chip, offset, value); 612 613 return pinctrl_gpio_direction_output(chip->base + offset); 614 } 615 616 static int lp_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 617 { 618 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); 619 620 if (ioread32(reg) & DIR_BIT) 621 return GPIO_LINE_DIRECTION_IN; 622 623 return GPIO_LINE_DIRECTION_OUT; 624 } 625 626 static void lp_gpio_irq_handler(struct irq_desc *desc) 627 { 628 struct irq_data *data = irq_desc_get_irq_data(desc); 629 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 630 struct intel_pinctrl *lg = gpiochip_get_data(gc); 631 struct irq_chip *chip = irq_data_get_irq_chip(data); 632 void __iomem *reg, *ena; 633 unsigned long pending; 634 u32 base, pin; 635 636 /* check from GPIO controller which pin triggered the interrupt */ 637 for (base = 0; base < lg->chip.ngpio; base += 32) { 638 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT); 639 ena = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE); 640 641 /* Only interrupts that are enabled */ 642 pending = ioread32(reg) & ioread32(ena); 643 644 for_each_set_bit(pin, &pending, 32) { 645 unsigned int irq; 646 647 irq = irq_find_mapping(lg->chip.irq.domain, base + pin); 648 generic_handle_irq(irq); 649 } 650 } 651 chip->irq_eoi(data); 652 } 653 654 static void lp_irq_ack(struct irq_data *d) 655 { 656 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 657 struct intel_pinctrl *lg = gpiochip_get_data(gc); 658 u32 hwirq = irqd_to_hwirq(d); 659 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_STAT); 660 unsigned long flags; 661 662 raw_spin_lock_irqsave(&lg->lock, flags); 663 iowrite32(BIT(hwirq % 32), reg); 664 raw_spin_unlock_irqrestore(&lg->lock, flags); 665 } 666 667 static void lp_irq_unmask(struct irq_data *d) 668 { 669 } 670 671 static void lp_irq_mask(struct irq_data *d) 672 { 673 } 674 675 static void lp_irq_enable(struct irq_data *d) 676 { 677 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 678 struct intel_pinctrl *lg = gpiochip_get_data(gc); 679 u32 hwirq = irqd_to_hwirq(d); 680 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); 681 unsigned long flags; 682 683 raw_spin_lock_irqsave(&lg->lock, flags); 684 iowrite32(ioread32(reg) | BIT(hwirq % 32), reg); 685 raw_spin_unlock_irqrestore(&lg->lock, flags); 686 } 687 688 static void lp_irq_disable(struct irq_data *d) 689 { 690 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 691 struct intel_pinctrl *lg = gpiochip_get_data(gc); 692 u32 hwirq = irqd_to_hwirq(d); 693 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); 694 unsigned long flags; 695 696 raw_spin_lock_irqsave(&lg->lock, flags); 697 iowrite32(ioread32(reg) & ~BIT(hwirq % 32), reg); 698 raw_spin_unlock_irqrestore(&lg->lock, flags); 699 } 700 701 static int lp_irq_set_type(struct irq_data *d, unsigned int type) 702 { 703 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 704 struct intel_pinctrl *lg = gpiochip_get_data(gc); 705 u32 hwirq = irqd_to_hwirq(d); 706 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1); 707 unsigned long flags; 708 u32 value; 709 710 if (hwirq >= lg->chip.ngpio) 711 return -EINVAL; 712 713 /* Fail if BIOS reserved pin for ACPI use */ 714 if (lp_gpio_acpi_use(lg, hwirq)) { 715 dev_err(lg->dev, "pin %u can't be used as IRQ\n", hwirq); 716 return -EBUSY; 717 } 718 719 raw_spin_lock_irqsave(&lg->lock, flags); 720 value = ioread32(reg); 721 722 /* set both TRIG_SEL and INV bits to 0 for rising edge */ 723 if (type & IRQ_TYPE_EDGE_RISING) 724 value &= ~(TRIG_SEL_BIT | INT_INV_BIT); 725 726 /* TRIG_SEL bit 0, INV bit 1 for falling edge */ 727 if (type & IRQ_TYPE_EDGE_FALLING) 728 value = (value | INT_INV_BIT) & ~TRIG_SEL_BIT; 729 730 /* TRIG_SEL bit 1, INV bit 0 for level low */ 731 if (type & IRQ_TYPE_LEVEL_LOW) 732 value = (value | TRIG_SEL_BIT) & ~INT_INV_BIT; 733 734 /* TRIG_SEL bit 1, INV bit 1 for level high */ 735 if (type & IRQ_TYPE_LEVEL_HIGH) 736 value |= TRIG_SEL_BIT | INT_INV_BIT; 737 738 iowrite32(value, reg); 739 740 if (type & IRQ_TYPE_EDGE_BOTH) 741 irq_set_handler_locked(d, handle_edge_irq); 742 else if (type & IRQ_TYPE_LEVEL_MASK) 743 irq_set_handler_locked(d, handle_level_irq); 744 745 raw_spin_unlock_irqrestore(&lg->lock, flags); 746 747 return 0; 748 } 749 750 static struct irq_chip lp_irqchip = { 751 .name = "LP-GPIO", 752 .irq_ack = lp_irq_ack, 753 .irq_mask = lp_irq_mask, 754 .irq_unmask = lp_irq_unmask, 755 .irq_enable = lp_irq_enable, 756 .irq_disable = lp_irq_disable, 757 .irq_set_type = lp_irq_set_type, 758 .flags = IRQCHIP_SKIP_SET_WAKE, 759 }; 760 761 static int lp_gpio_irq_init_hw(struct gpio_chip *chip) 762 { 763 struct intel_pinctrl *lg = gpiochip_get_data(chip); 764 void __iomem *reg; 765 unsigned int base; 766 767 for (base = 0; base < lg->chip.ngpio; base += 32) { 768 /* disable gpio pin interrupts */ 769 reg = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE); 770 iowrite32(0, reg); 771 /* Clear interrupt status register */ 772 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT); 773 iowrite32(0xffffffff, reg); 774 } 775 776 return 0; 777 } 778 779 static int lp_gpio_add_pin_ranges(struct gpio_chip *chip) 780 { 781 struct intel_pinctrl *lg = gpiochip_get_data(chip); 782 struct device *dev = lg->dev; 783 int ret; 784 785 ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, lg->soc->npins); 786 if (ret) 787 dev_err(dev, "failed to add GPIO pin range\n"); 788 789 return ret; 790 } 791 792 static int lp_gpio_probe(struct platform_device *pdev) 793 { 794 const struct intel_pinctrl_soc_data *soc; 795 struct intel_pinctrl *lg; 796 struct gpio_chip *gc; 797 struct resource *io_rc, *irq_rc; 798 struct device *dev = &pdev->dev; 799 void __iomem *regs; 800 unsigned int i; 801 int ret; 802 803 soc = (const struct intel_pinctrl_soc_data *)device_get_match_data(dev); 804 if (!soc) 805 return -ENODEV; 806 807 lg = devm_kzalloc(dev, sizeof(*lg), GFP_KERNEL); 808 if (!lg) 809 return -ENOMEM; 810 811 lg->dev = dev; 812 lg->soc = soc; 813 814 lg->ncommunities = lg->soc->ncommunities; 815 lg->communities = devm_kcalloc(dev, lg->ncommunities, 816 sizeof(*lg->communities), GFP_KERNEL); 817 if (!lg->communities) 818 return -ENOMEM; 819 820 lg->pctldesc = lptlp_pinctrl_desc; 821 lg->pctldesc.name = dev_name(dev); 822 lg->pctldesc.pins = lg->soc->pins; 823 lg->pctldesc.npins = lg->soc->npins; 824 825 lg->pctldev = devm_pinctrl_register(dev, &lg->pctldesc, lg); 826 if (IS_ERR(lg->pctldev)) { 827 dev_err(dev, "failed to register pinctrl driver\n"); 828 return PTR_ERR(lg->pctldev); 829 } 830 831 platform_set_drvdata(pdev, lg); 832 833 io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0); 834 if (!io_rc) { 835 dev_err(dev, "missing IO resources\n"); 836 return -EINVAL; 837 } 838 839 regs = devm_ioport_map(dev, io_rc->start, resource_size(io_rc)); 840 if (!regs) { 841 dev_err(dev, "failed mapping IO region %pR\n", &io_rc); 842 return -EBUSY; 843 } 844 845 for (i = 0; i < lg->soc->ncommunities; i++) { 846 struct intel_community *comm = &lg->communities[i]; 847 848 *comm = lg->soc->communities[i]; 849 850 comm->regs = regs; 851 comm->pad_regs = regs + 0x100; 852 } 853 854 raw_spin_lock_init(&lg->lock); 855 856 gc = &lg->chip; 857 gc->label = dev_name(dev); 858 gc->owner = THIS_MODULE; 859 gc->request = gpiochip_generic_request; 860 gc->free = gpiochip_generic_free; 861 gc->direction_input = lp_gpio_direction_input; 862 gc->direction_output = lp_gpio_direction_output; 863 gc->get = lp_gpio_get; 864 gc->set = lp_gpio_set; 865 gc->get_direction = lp_gpio_get_direction; 866 gc->base = -1; 867 gc->ngpio = LP_NUM_GPIO; 868 gc->can_sleep = false; 869 gc->add_pin_ranges = lp_gpio_add_pin_ranges; 870 gc->parent = dev; 871 872 /* set up interrupts */ 873 irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 874 if (irq_rc && irq_rc->start) { 875 struct gpio_irq_chip *girq; 876 877 girq = &gc->irq; 878 girq->chip = &lp_irqchip; 879 girq->init_hw = lp_gpio_irq_init_hw; 880 girq->parent_handler = lp_gpio_irq_handler; 881 girq->num_parents = 1; 882 girq->parents = devm_kcalloc(dev, girq->num_parents, 883 sizeof(*girq->parents), 884 GFP_KERNEL); 885 if (!girq->parents) 886 return -ENOMEM; 887 girq->parents[0] = (unsigned int)irq_rc->start; 888 girq->default_type = IRQ_TYPE_NONE; 889 girq->handler = handle_bad_irq; 890 } 891 892 ret = devm_gpiochip_add_data(dev, gc, lg); 893 if (ret) { 894 dev_err(dev, "failed adding lp-gpio chip\n"); 895 return ret; 896 } 897 898 pm_runtime_enable(dev); 899 900 return 0; 901 } 902 903 static int lp_gpio_remove(struct platform_device *pdev) 904 { 905 pm_runtime_disable(&pdev->dev); 906 return 0; 907 } 908 909 static int lp_gpio_runtime_suspend(struct device *dev) 910 { 911 return 0; 912 } 913 914 static int lp_gpio_runtime_resume(struct device *dev) 915 { 916 return 0; 917 } 918 919 static int lp_gpio_resume(struct device *dev) 920 { 921 struct intel_pinctrl *lg = dev_get_drvdata(dev); 922 void __iomem *reg; 923 int i; 924 925 /* on some hardware suspend clears input sensing, re-enable it here */ 926 for (i = 0; i < lg->chip.ngpio; i++) { 927 if (gpiochip_is_requested(&lg->chip, i) != NULL) { 928 reg = lp_gpio_reg(&lg->chip, i, LP_CONFIG2); 929 iowrite32(ioread32(reg) & ~GPINDIS_BIT, reg); 930 } 931 } 932 return 0; 933 } 934 935 static const struct dev_pm_ops lp_gpio_pm_ops = { 936 .runtime_suspend = lp_gpio_runtime_suspend, 937 .runtime_resume = lp_gpio_runtime_resume, 938 .resume = lp_gpio_resume, 939 }; 940 941 static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = { 942 { "INT33C7", (kernel_ulong_t)&lptlp_soc_data }, 943 { "INT3437", (kernel_ulong_t)&lptlp_soc_data }, 944 { } 945 }; 946 MODULE_DEVICE_TABLE(acpi, lynxpoint_gpio_acpi_match); 947 948 static struct platform_driver lp_gpio_driver = { 949 .probe = lp_gpio_probe, 950 .remove = lp_gpio_remove, 951 .driver = { 952 .name = "lp_gpio", 953 .pm = &lp_gpio_pm_ops, 954 .acpi_match_table = ACPI_PTR(lynxpoint_gpio_acpi_match), 955 }, 956 }; 957 958 static int __init lp_gpio_init(void) 959 { 960 return platform_driver_register(&lp_gpio_driver); 961 } 962 963 static void __exit lp_gpio_exit(void) 964 { 965 platform_driver_unregister(&lp_gpio_driver); 966 } 967 968 subsys_initcall(lp_gpio_init); 969 module_exit(lp_gpio_exit); 970 971 MODULE_AUTHOR("Mathias Nyman (Intel)"); 972 MODULE_AUTHOR("Andy Shevchenko (Intel)"); 973 MODULE_DESCRIPTION("Intel Lynxpoint pinctrl driver"); 974 MODULE_LICENSE("GPL v2"); 975 MODULE_ALIAS("platform:lp_gpio"); 976