1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * linux/arch/alpha/kernel/sys_rx164.c 4 * 5 * Copyright (C) 1995 David A Rusling 6 * Copyright (C) 1996 Jay A Estabrook 7 * Copyright (C) 1998, 1999 Richard Henderson 8 * 9 * Code supporting the RX164 (PCA56+POLARIS). 10 */ 11 12 #include <linux/kernel.h> 13 #include <linux/types.h> 14 #include <linux/mm.h> 15 #include <linux/sched.h> 16 #include <linux/pci.h> 17 #include <linux/init.h> 18 #include <linux/bitops.h> 19 20 #include <asm/ptrace.h> 21 #include <asm/dma.h> 22 #include <asm/irq.h> 23 #include <asm/mmu_context.h> 24 #include <asm/io.h> 25 #include <asm/pgtable.h> 26 #include <asm/core_polaris.h> 27 #include <asm/tlbflush.h> 28 29 #include "proto.h" 30 #include "irq_impl.h" 31 #include "pci_impl.h" 32 #include "machvec_impl.h" 33 34 35 /* Note mask bit is true for ENABLED irqs. */ 36 static unsigned long cached_irq_mask; 37 38 static inline void 39 rx164_update_irq_hw(unsigned long mask) 40 { 41 volatile unsigned int *irq_mask; 42 43 irq_mask = (void *)(POLARIS_DENSE_CONFIG_BASE + 0x74); 44 *irq_mask = mask; 45 mb(); 46 *irq_mask; 47 } 48 49 static inline void 50 rx164_enable_irq(struct irq_data *d) 51 { 52 rx164_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16)); 53 } 54 55 static void 56 rx164_disable_irq(struct irq_data *d) 57 { 58 rx164_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16))); 59 } 60 61 static struct irq_chip rx164_irq_type = { 62 .name = "RX164", 63 .irq_unmask = rx164_enable_irq, 64 .irq_mask = rx164_disable_irq, 65 .irq_mask_ack = rx164_disable_irq, 66 }; 67 68 static void 69 rx164_device_interrupt(unsigned long vector) 70 { 71 unsigned long pld; 72 volatile unsigned int *dirr; 73 long i; 74 75 /* Read the interrupt summary register. On Polaris, this is 76 the DIRR register in PCI config space (offset 0x84). */ 77 dirr = (void *)(POLARIS_DENSE_CONFIG_BASE + 0x84); 78 pld = *dirr; 79 80 /* 81 * Now for every possible bit set, work through them and call 82 * the appropriate interrupt handler. 83 */ 84 while (pld) { 85 i = ffz(~pld); 86 pld &= pld - 1; /* clear least bit set */ 87 if (i == 20) { 88 isa_no_iack_sc_device_interrupt(vector); 89 } else { 90 handle_irq(16+i); 91 } 92 } 93 } 94 95 static void __init 96 rx164_init_irq(void) 97 { 98 long i; 99 100 rx164_update_irq_hw(0); 101 for (i = 16; i < 40; ++i) { 102 irq_set_chip_and_handler(i, &rx164_irq_type, handle_level_irq); 103 irq_set_status_flags(i, IRQ_LEVEL); 104 } 105 106 init_i8259a_irqs(); 107 common_init_isa_dma(); 108 109 if (request_irq(16 + 20, no_action, 0, "isa-cascade", NULL)) 110 pr_err("Failed to register isa-cascade interrupt\n"); 111 } 112 113 114 /* 115 * The RX164 changed its interrupt routing between pass1 and pass2... 116 * 117 * PASS1: 118 * 119 * Slot IDSEL INTA INTB INTC INTD 120 * 0 6 5 10 15 20 121 * 1 7 4 9 14 19 122 * 2 5 3 8 13 18 123 * 3 9 2 7 12 17 124 * 4 10 1 6 11 16 125 * 126 * PASS2: 127 * Slot IDSEL INTA INTB INTC INTD 128 * 0 5 1 7 12 17 129 * 1 6 2 8 13 18 130 * 2 8 3 9 14 19 131 * 3 9 4 10 15 20 132 * 4 10 5 11 16 6 133 * 134 */ 135 136 /* 137 * IdSel 138 * 5 32 bit PCI option slot 0 139 * 6 64 bit PCI option slot 1 140 * 7 PCI-ISA bridge 141 * 7 64 bit PCI option slot 2 142 * 9 32 bit PCI option slot 3 143 * 10 PCI-PCI bridge 144 * 145 */ 146 147 static int 148 rx164_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 149 { 150 #if 0 151 static char irq_tab_pass1[6][5] __initdata = { 152 /*INT INTA INTB INTC INTD */ 153 { 16+3, 16+3, 16+8, 16+13, 16+18}, /* IdSel 5, slot 2 */ 154 { 16+5, 16+5, 16+10, 16+15, 16+20}, /* IdSel 6, slot 0 */ 155 { 16+4, 16+4, 16+9, 16+14, 16+19}, /* IdSel 7, slot 1 */ 156 { -1, -1, -1, -1, -1}, /* IdSel 8, PCI/ISA bridge */ 157 { 16+2, 16+2, 16+7, 16+12, 16+17}, /* IdSel 9, slot 3 */ 158 { 16+1, 16+1, 16+6, 16+11, 16+16}, /* IdSel 10, slot 4 */ 159 }; 160 #else 161 static char irq_tab[6][5] = { 162 /*INT INTA INTB INTC INTD */ 163 { 16+0, 16+0, 16+6, 16+11, 16+16}, /* IdSel 5, slot 0 */ 164 { 16+1, 16+1, 16+7, 16+12, 16+17}, /* IdSel 6, slot 1 */ 165 { -1, -1, -1, -1, -1}, /* IdSel 7, PCI/ISA bridge */ 166 { 16+2, 16+2, 16+8, 16+13, 16+18}, /* IdSel 8, slot 2 */ 167 { 16+3, 16+3, 16+9, 16+14, 16+19}, /* IdSel 9, slot 3 */ 168 { 16+4, 16+4, 16+10, 16+15, 16+5}, /* IdSel 10, PCI-PCI */ 169 }; 170 #endif 171 const long min_idsel = 5, max_idsel = 10, irqs_per_slot = 5; 172 173 /* JRP - Need to figure out how to distinguish pass1 from pass2, 174 and use the correct table. */ 175 return COMMON_TABLE_LOOKUP; 176 } 177 178 179 /* 180 * The System Vector 181 */ 182 183 struct alpha_machine_vector rx164_mv __initmv = { 184 .vector_name = "RX164", 185 DO_EV5_MMU, 186 DO_DEFAULT_RTC, 187 DO_POLARIS_IO, 188 .machine_check = polaris_machine_check, 189 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, 190 .min_io_address = DEFAULT_IO_BASE, 191 .min_mem_address = DEFAULT_MEM_BASE, 192 193 .nr_irqs = 40, 194 .device_interrupt = rx164_device_interrupt, 195 196 .init_arch = polaris_init_arch, 197 .init_irq = rx164_init_irq, 198 .init_rtc = common_init_rtc, 199 .init_pci = common_init_pci, 200 .kill_arch = NULL, 201 .pci_map_irq = rx164_map_irq, 202 .pci_swizzle = common_swizzle, 203 }; 204 ALIAS_MV(rx164) 205