1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_GFX_H__ 25 #define __AMDGPU_GFX_H__ 26 27 /* 28 * GFX stuff 29 */ 30 #include "clearstate_defs.h" 31 #include "amdgpu_ring.h" 32 #include "amdgpu_rlc.h" 33 34 /* GFX current status */ 35 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 36 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 37 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 38 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 39 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 40 41 #define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES 42 #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES 43 44 enum gfx_pipe_priority { 45 AMDGPU_GFX_PIPE_PRIO_NORMAL = 1, 46 AMDGPU_GFX_PIPE_PRIO_HIGH, 47 AMDGPU_GFX_PIPE_PRIO_MAX 48 }; 49 50 #define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM 0 51 #define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM 15 52 53 struct amdgpu_mec { 54 struct amdgpu_bo *hpd_eop_obj; 55 u64 hpd_eop_gpu_addr; 56 struct amdgpu_bo *mec_fw_obj; 57 u64 mec_fw_gpu_addr; 58 u32 num_mec; 59 u32 num_pipe_per_mec; 60 u32 num_queue_per_pipe; 61 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1]; 62 63 /* These are the resources for which amdgpu takes ownership */ 64 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 65 }; 66 67 enum amdgpu_unmap_queues_action { 68 PREEMPT_QUEUES = 0, 69 RESET_QUEUES, 70 DISABLE_PROCESS_QUEUES, 71 PREEMPT_QUEUES_NO_UNMAP, 72 }; 73 74 struct kiq_pm4_funcs { 75 /* Support ASIC-specific kiq pm4 packets*/ 76 void (*kiq_set_resources)(struct amdgpu_ring *kiq_ring, 77 uint64_t queue_mask); 78 void (*kiq_map_queues)(struct amdgpu_ring *kiq_ring, 79 struct amdgpu_ring *ring); 80 void (*kiq_unmap_queues)(struct amdgpu_ring *kiq_ring, 81 struct amdgpu_ring *ring, 82 enum amdgpu_unmap_queues_action action, 83 u64 gpu_addr, u64 seq); 84 void (*kiq_query_status)(struct amdgpu_ring *kiq_ring, 85 struct amdgpu_ring *ring, 86 u64 addr, 87 u64 seq); 88 void (*kiq_invalidate_tlbs)(struct amdgpu_ring *kiq_ring, 89 uint16_t pasid, uint32_t flush_type, 90 bool all_hub); 91 /* Packet sizes */ 92 int set_resources_size; 93 int map_queues_size; 94 int unmap_queues_size; 95 int query_status_size; 96 int invalidate_tlbs_size; 97 }; 98 99 struct amdgpu_kiq { 100 u64 eop_gpu_addr; 101 struct amdgpu_bo *eop_obj; 102 spinlock_t ring_lock; 103 struct amdgpu_ring ring; 104 struct amdgpu_irq_src irq; 105 const struct kiq_pm4_funcs *pmf; 106 }; 107 108 /* 109 * GPU scratch registers structures, functions & helpers 110 */ 111 struct amdgpu_scratch { 112 unsigned num_reg; 113 uint32_t reg_base; 114 uint32_t free_mask; 115 }; 116 117 /* 118 * GFX configurations 119 */ 120 #define AMDGPU_GFX_MAX_SE 4 121 #define AMDGPU_GFX_MAX_SH_PER_SE 2 122 123 struct amdgpu_rb_config { 124 uint32_t rb_backend_disable; 125 uint32_t user_rb_backend_disable; 126 uint32_t raster_config; 127 uint32_t raster_config_1; 128 }; 129 130 struct gb_addr_config { 131 uint16_t pipe_interleave_size; 132 uint8_t num_pipes; 133 uint8_t max_compress_frags; 134 uint8_t num_banks; 135 uint8_t num_se; 136 uint8_t num_rb_per_se; 137 }; 138 139 struct amdgpu_gfx_config { 140 unsigned max_shader_engines; 141 unsigned max_tile_pipes; 142 unsigned max_cu_per_sh; 143 unsigned max_sh_per_se; 144 unsigned max_backends_per_se; 145 unsigned max_texture_channel_caches; 146 unsigned max_gprs; 147 unsigned max_gs_threads; 148 unsigned max_hw_contexts; 149 unsigned sc_prim_fifo_size_frontend; 150 unsigned sc_prim_fifo_size_backend; 151 unsigned sc_hiz_tile_fifo_size; 152 unsigned sc_earlyz_tile_fifo_size; 153 154 unsigned num_tile_pipes; 155 unsigned backend_enable_mask; 156 unsigned mem_max_burst_length_bytes; 157 unsigned mem_row_size_in_kb; 158 unsigned shader_engine_tile_size; 159 unsigned num_gpus; 160 unsigned multi_gpu_tile_size; 161 unsigned mc_arb_ramcfg; 162 unsigned num_banks; 163 unsigned num_ranks; 164 unsigned gb_addr_config; 165 unsigned num_rbs; 166 unsigned gs_vgt_table_depth; 167 unsigned gs_prim_buffer_depth; 168 169 uint32_t tile_mode_array[32]; 170 uint32_t macrotile_mode_array[16]; 171 172 struct gb_addr_config gb_addr_config_fields; 173 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE]; 174 175 /* gfx configure feature */ 176 uint32_t double_offchip_lds_buf; 177 /* cached value of DB_DEBUG2 */ 178 uint32_t db_debug2; 179 /* gfx10 specific config */ 180 uint32_t num_sc_per_sh; 181 uint32_t num_packer_per_sc; 182 uint32_t pa_sc_tile_steering_override; 183 uint64_t tcc_disabled_mask; 184 }; 185 186 struct amdgpu_cu_info { 187 uint32_t simd_per_cu; 188 uint32_t max_waves_per_simd; 189 uint32_t wave_front_size; 190 uint32_t max_scratch_slots_per_cu; 191 uint32_t lds_size; 192 193 /* total active CU number */ 194 uint32_t number; 195 uint32_t ao_cu_mask; 196 uint32_t ao_cu_bitmap[4][4]; 197 uint32_t bitmap[4][4]; 198 }; 199 200 struct amdgpu_gfx_funcs { 201 /* get the gpu clock counter */ 202 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 203 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, 204 u32 sh_num, u32 instance); 205 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, 206 uint32_t wave, uint32_t *dst, int *no_fields); 207 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, 208 uint32_t wave, uint32_t thread, uint32_t start, 209 uint32_t size, uint32_t *dst); 210 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, 211 uint32_t wave, uint32_t start, uint32_t size, 212 uint32_t *dst); 213 void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe, 214 u32 queue, u32 vmid); 215 int (*ras_error_inject)(struct amdgpu_device *adev, void *inject_if); 216 int (*query_ras_error_count) (struct amdgpu_device *adev, void *ras_error_status); 217 void (*reset_ras_error_count) (struct amdgpu_device *adev); 218 }; 219 220 struct sq_work { 221 struct work_struct work; 222 unsigned ih_data; 223 }; 224 225 struct amdgpu_pfp { 226 struct amdgpu_bo *pfp_fw_obj; 227 uint64_t pfp_fw_gpu_addr; 228 uint32_t *pfp_fw_ptr; 229 }; 230 231 struct amdgpu_ce { 232 struct amdgpu_bo *ce_fw_obj; 233 uint64_t ce_fw_gpu_addr; 234 uint32_t *ce_fw_ptr; 235 }; 236 237 struct amdgpu_me { 238 struct amdgpu_bo *me_fw_obj; 239 uint64_t me_fw_gpu_addr; 240 uint32_t *me_fw_ptr; 241 uint32_t num_me; 242 uint32_t num_pipe_per_me; 243 uint32_t num_queue_per_pipe; 244 void *mqd_backup[AMDGPU_MAX_GFX_RINGS]; 245 246 /* These are the resources for which amdgpu takes ownership */ 247 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 248 }; 249 250 struct amdgpu_gfx { 251 struct mutex gpu_clock_mutex; 252 struct amdgpu_gfx_config config; 253 struct amdgpu_rlc rlc; 254 struct amdgpu_pfp pfp; 255 struct amdgpu_ce ce; 256 struct amdgpu_me me; 257 struct amdgpu_mec mec; 258 struct amdgpu_kiq kiq; 259 struct amdgpu_scratch scratch; 260 const struct firmware *me_fw; /* ME firmware */ 261 uint32_t me_fw_version; 262 const struct firmware *pfp_fw; /* PFP firmware */ 263 uint32_t pfp_fw_version; 264 const struct firmware *ce_fw; /* CE firmware */ 265 uint32_t ce_fw_version; 266 const struct firmware *rlc_fw; /* RLC firmware */ 267 uint32_t rlc_fw_version; 268 const struct firmware *mec_fw; /* MEC firmware */ 269 uint32_t mec_fw_version; 270 const struct firmware *mec2_fw; /* MEC2 firmware */ 271 uint32_t mec2_fw_version; 272 uint32_t me_feature_version; 273 uint32_t ce_feature_version; 274 uint32_t pfp_feature_version; 275 uint32_t rlc_feature_version; 276 uint32_t rlc_srlc_fw_version; 277 uint32_t rlc_srlc_feature_version; 278 uint32_t rlc_srlg_fw_version; 279 uint32_t rlc_srlg_feature_version; 280 uint32_t rlc_srls_fw_version; 281 uint32_t rlc_srls_feature_version; 282 uint32_t mec_feature_version; 283 uint32_t mec2_feature_version; 284 bool mec_fw_write_wait; 285 bool me_fw_write_wait; 286 bool cp_fw_write_wait; 287 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 288 unsigned num_gfx_rings; 289 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 290 unsigned num_compute_rings; 291 struct amdgpu_irq_src eop_irq; 292 struct amdgpu_irq_src priv_reg_irq; 293 struct amdgpu_irq_src priv_inst_irq; 294 struct amdgpu_irq_src cp_ecc_error_irq; 295 struct amdgpu_irq_src sq_irq; 296 struct sq_work sq_work; 297 298 /* gfx status */ 299 uint32_t gfx_current_status; 300 /* ce ram size*/ 301 unsigned ce_ram_size; 302 struct amdgpu_cu_info cu_info; 303 const struct amdgpu_gfx_funcs *funcs; 304 305 /* reset mask */ 306 uint32_t grbm_soft_reset; 307 uint32_t srbm_soft_reset; 308 309 /* gfx off */ 310 bool gfx_off_state; /* true: enabled, false: disabled */ 311 struct mutex gfx_off_mutex; 312 uint32_t gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */ 313 struct delayed_work gfx_off_delay_work; 314 315 /* pipe reservation */ 316 struct mutex pipe_reserve_mutex; 317 DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 318 319 /*ras */ 320 struct ras_common_if *ras_if; 321 }; 322 323 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) 324 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) 325 #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid)) 326 327 /** 328 * amdgpu_gfx_create_bitmask - create a bitmask 329 * 330 * @bit_width: length of the mask 331 * 332 * create a variable length bit mask. 333 * Returns the bitmask. 334 */ 335 static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width) 336 { 337 return (u32)((1ULL << bit_width) - 1); 338 } 339 340 int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg); 341 void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg); 342 343 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, 344 unsigned max_sh); 345 346 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, 347 struct amdgpu_ring *ring, 348 struct amdgpu_irq_src *irq); 349 350 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring); 351 352 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev); 353 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev, 354 unsigned hpd_size); 355 356 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, 357 unsigned mqd_size); 358 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev); 359 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev); 360 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev); 361 362 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev); 363 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev); 364 365 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec, 366 int pipe, int queue); 367 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit, 368 int *mec, int *pipe, int *queue); 369 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec, 370 int pipe, int queue); 371 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev, 372 int queue); 373 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me, 374 int pipe, int queue); 375 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit, 376 int *me, int *pipe, int *queue); 377 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me, 378 int pipe, int queue); 379 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable); 380 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev); 381 void amdgpu_gfx_ras_fini(struct amdgpu_device *adev); 382 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev, 383 void *err_data, 384 struct amdgpu_iv_entry *entry); 385 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev, 386 struct amdgpu_irq_src *source, 387 struct amdgpu_iv_entry *entry); 388 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg); 389 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v); 390 #endif 391