1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics 2017 5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/delay.h> 10 #include <linux/hwspinlock.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/irq.h> 14 #include <linux/irqchip.h> 15 #include <linux/irqchip/chained_irq.h> 16 #include <linux/irqdomain.h> 17 #include <linux/module.h> 18 #include <linux/of_address.h> 19 #include <linux/of_irq.h> 20 #include <linux/of_platform.h> 21 #include <linux/syscore_ops.h> 22 23 #include <dt-bindings/interrupt-controller/arm-gic.h> 24 25 #define IRQS_PER_BANK 32 26 27 #define HWSPNLCK_TIMEOUT 1000 /* usec */ 28 29 struct stm32_exti_bank { 30 u32 imr_ofst; 31 u32 emr_ofst; 32 u32 rtsr_ofst; 33 u32 ftsr_ofst; 34 u32 swier_ofst; 35 u32 rpr_ofst; 36 u32 fpr_ofst; 37 }; 38 39 #define UNDEF_REG ~0 40 41 struct stm32_desc_irq { 42 u32 exti; 43 u32 irq_parent; 44 struct irq_chip *chip; 45 }; 46 47 struct stm32_exti_drv_data { 48 const struct stm32_exti_bank **exti_banks; 49 const struct stm32_desc_irq *desc_irqs; 50 u32 bank_nr; 51 u32 irq_nr; 52 }; 53 54 struct stm32_exti_chip_data { 55 struct stm32_exti_host_data *host_data; 56 const struct stm32_exti_bank *reg_bank; 57 struct raw_spinlock rlock; 58 u32 wake_active; 59 u32 mask_cache; 60 u32 rtsr_cache; 61 u32 ftsr_cache; 62 }; 63 64 struct stm32_exti_host_data { 65 void __iomem *base; 66 struct stm32_exti_chip_data *chips_data; 67 const struct stm32_exti_drv_data *drv_data; 68 struct hwspinlock *hwlock; 69 }; 70 71 static struct stm32_exti_host_data *stm32_host_data; 72 73 static const struct stm32_exti_bank stm32f4xx_exti_b1 = { 74 .imr_ofst = 0x00, 75 .emr_ofst = 0x04, 76 .rtsr_ofst = 0x08, 77 .ftsr_ofst = 0x0C, 78 .swier_ofst = 0x10, 79 .rpr_ofst = 0x14, 80 .fpr_ofst = UNDEF_REG, 81 }; 82 83 static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = { 84 &stm32f4xx_exti_b1, 85 }; 86 87 static const struct stm32_exti_drv_data stm32f4xx_drv_data = { 88 .exti_banks = stm32f4xx_exti_banks, 89 .bank_nr = ARRAY_SIZE(stm32f4xx_exti_banks), 90 }; 91 92 static const struct stm32_exti_bank stm32h7xx_exti_b1 = { 93 .imr_ofst = 0x80, 94 .emr_ofst = 0x84, 95 .rtsr_ofst = 0x00, 96 .ftsr_ofst = 0x04, 97 .swier_ofst = 0x08, 98 .rpr_ofst = 0x88, 99 .fpr_ofst = UNDEF_REG, 100 }; 101 102 static const struct stm32_exti_bank stm32h7xx_exti_b2 = { 103 .imr_ofst = 0x90, 104 .emr_ofst = 0x94, 105 .rtsr_ofst = 0x20, 106 .ftsr_ofst = 0x24, 107 .swier_ofst = 0x28, 108 .rpr_ofst = 0x98, 109 .fpr_ofst = UNDEF_REG, 110 }; 111 112 static const struct stm32_exti_bank stm32h7xx_exti_b3 = { 113 .imr_ofst = 0xA0, 114 .emr_ofst = 0xA4, 115 .rtsr_ofst = 0x40, 116 .ftsr_ofst = 0x44, 117 .swier_ofst = 0x48, 118 .rpr_ofst = 0xA8, 119 .fpr_ofst = UNDEF_REG, 120 }; 121 122 static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = { 123 &stm32h7xx_exti_b1, 124 &stm32h7xx_exti_b2, 125 &stm32h7xx_exti_b3, 126 }; 127 128 static const struct stm32_exti_drv_data stm32h7xx_drv_data = { 129 .exti_banks = stm32h7xx_exti_banks, 130 .bank_nr = ARRAY_SIZE(stm32h7xx_exti_banks), 131 }; 132 133 static const struct stm32_exti_bank stm32mp1_exti_b1 = { 134 .imr_ofst = 0x80, 135 .emr_ofst = 0x84, 136 .rtsr_ofst = 0x00, 137 .ftsr_ofst = 0x04, 138 .swier_ofst = 0x08, 139 .rpr_ofst = 0x0C, 140 .fpr_ofst = 0x10, 141 }; 142 143 static const struct stm32_exti_bank stm32mp1_exti_b2 = { 144 .imr_ofst = 0x90, 145 .emr_ofst = 0x94, 146 .rtsr_ofst = 0x20, 147 .ftsr_ofst = 0x24, 148 .swier_ofst = 0x28, 149 .rpr_ofst = 0x2C, 150 .fpr_ofst = 0x30, 151 }; 152 153 static const struct stm32_exti_bank stm32mp1_exti_b3 = { 154 .imr_ofst = 0xA0, 155 .emr_ofst = 0xA4, 156 .rtsr_ofst = 0x40, 157 .ftsr_ofst = 0x44, 158 .swier_ofst = 0x48, 159 .rpr_ofst = 0x4C, 160 .fpr_ofst = 0x50, 161 }; 162 163 static const struct stm32_exti_bank *stm32mp1_exti_banks[] = { 164 &stm32mp1_exti_b1, 165 &stm32mp1_exti_b2, 166 &stm32mp1_exti_b3, 167 }; 168 169 static struct irq_chip stm32_exti_h_chip; 170 static struct irq_chip stm32_exti_h_chip_direct; 171 172 static const struct stm32_desc_irq stm32mp1_desc_irq[] = { 173 { .exti = 0, .irq_parent = 6, .chip = &stm32_exti_h_chip }, 174 { .exti = 1, .irq_parent = 7, .chip = &stm32_exti_h_chip }, 175 { .exti = 2, .irq_parent = 8, .chip = &stm32_exti_h_chip }, 176 { .exti = 3, .irq_parent = 9, .chip = &stm32_exti_h_chip }, 177 { .exti = 4, .irq_parent = 10, .chip = &stm32_exti_h_chip }, 178 { .exti = 5, .irq_parent = 23, .chip = &stm32_exti_h_chip }, 179 { .exti = 6, .irq_parent = 64, .chip = &stm32_exti_h_chip }, 180 { .exti = 7, .irq_parent = 65, .chip = &stm32_exti_h_chip }, 181 { .exti = 8, .irq_parent = 66, .chip = &stm32_exti_h_chip }, 182 { .exti = 9, .irq_parent = 67, .chip = &stm32_exti_h_chip }, 183 { .exti = 10, .irq_parent = 40, .chip = &stm32_exti_h_chip }, 184 { .exti = 11, .irq_parent = 42, .chip = &stm32_exti_h_chip }, 185 { .exti = 12, .irq_parent = 76, .chip = &stm32_exti_h_chip }, 186 { .exti = 13, .irq_parent = 77, .chip = &stm32_exti_h_chip }, 187 { .exti = 14, .irq_parent = 121, .chip = &stm32_exti_h_chip }, 188 { .exti = 15, .irq_parent = 127, .chip = &stm32_exti_h_chip }, 189 { .exti = 16, .irq_parent = 1, .chip = &stm32_exti_h_chip }, 190 { .exti = 19, .irq_parent = 3, .chip = &stm32_exti_h_chip_direct }, 191 { .exti = 21, .irq_parent = 31, .chip = &stm32_exti_h_chip_direct }, 192 { .exti = 22, .irq_parent = 33, .chip = &stm32_exti_h_chip_direct }, 193 { .exti = 23, .irq_parent = 72, .chip = &stm32_exti_h_chip_direct }, 194 { .exti = 24, .irq_parent = 95, .chip = &stm32_exti_h_chip_direct }, 195 { .exti = 25, .irq_parent = 107, .chip = &stm32_exti_h_chip_direct }, 196 { .exti = 30, .irq_parent = 52, .chip = &stm32_exti_h_chip_direct }, 197 { .exti = 47, .irq_parent = 93, .chip = &stm32_exti_h_chip_direct }, 198 { .exti = 54, .irq_parent = 135, .chip = &stm32_exti_h_chip_direct }, 199 { .exti = 61, .irq_parent = 100, .chip = &stm32_exti_h_chip_direct }, 200 { .exti = 65, .irq_parent = 144, .chip = &stm32_exti_h_chip }, 201 { .exti = 68, .irq_parent = 143, .chip = &stm32_exti_h_chip }, 202 { .exti = 70, .irq_parent = 62, .chip = &stm32_exti_h_chip_direct }, 203 { .exti = 73, .irq_parent = 129, .chip = &stm32_exti_h_chip }, 204 }; 205 206 static const struct stm32_exti_drv_data stm32mp1_drv_data = { 207 .exti_banks = stm32mp1_exti_banks, 208 .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks), 209 .desc_irqs = stm32mp1_desc_irq, 210 .irq_nr = ARRAY_SIZE(stm32mp1_desc_irq), 211 }; 212 213 static const struct 214 stm32_desc_irq *stm32_exti_get_desc(const struct stm32_exti_drv_data *drv_data, 215 irq_hw_number_t hwirq) 216 { 217 const struct stm32_desc_irq *desc = NULL; 218 int i; 219 220 if (!drv_data->desc_irqs) 221 return NULL; 222 223 for (i = 0; i < drv_data->irq_nr; i++) { 224 desc = &drv_data->desc_irqs[i]; 225 if (desc->exti == hwirq) 226 break; 227 } 228 229 return desc; 230 } 231 232 static unsigned long stm32_exti_pending(struct irq_chip_generic *gc) 233 { 234 struct stm32_exti_chip_data *chip_data = gc->private; 235 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 236 unsigned long pending; 237 238 pending = irq_reg_readl(gc, stm32_bank->rpr_ofst); 239 if (stm32_bank->fpr_ofst != UNDEF_REG) 240 pending |= irq_reg_readl(gc, stm32_bank->fpr_ofst); 241 242 return pending; 243 } 244 245 static void stm32_irq_handler(struct irq_desc *desc) 246 { 247 struct irq_domain *domain = irq_desc_get_handler_data(desc); 248 struct irq_chip *chip = irq_desc_get_chip(desc); 249 unsigned int virq, nbanks = domain->gc->num_chips; 250 struct irq_chip_generic *gc; 251 unsigned long pending; 252 int n, i, irq_base = 0; 253 254 chained_irq_enter(chip, desc); 255 256 for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) { 257 gc = irq_get_domain_generic_chip(domain, irq_base); 258 259 while ((pending = stm32_exti_pending(gc))) { 260 for_each_set_bit(n, &pending, IRQS_PER_BANK) { 261 virq = irq_find_mapping(domain, irq_base + n); 262 generic_handle_irq(virq); 263 } 264 } 265 } 266 267 chained_irq_exit(chip, desc); 268 } 269 270 static int stm32_exti_set_type(struct irq_data *d, 271 unsigned int type, u32 *rtsr, u32 *ftsr) 272 { 273 u32 mask = BIT(d->hwirq % IRQS_PER_BANK); 274 275 switch (type) { 276 case IRQ_TYPE_EDGE_RISING: 277 *rtsr |= mask; 278 *ftsr &= ~mask; 279 break; 280 case IRQ_TYPE_EDGE_FALLING: 281 *rtsr &= ~mask; 282 *ftsr |= mask; 283 break; 284 case IRQ_TYPE_EDGE_BOTH: 285 *rtsr |= mask; 286 *ftsr |= mask; 287 break; 288 default: 289 return -EINVAL; 290 } 291 292 return 0; 293 } 294 295 static int stm32_irq_set_type(struct irq_data *d, unsigned int type) 296 { 297 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 298 struct stm32_exti_chip_data *chip_data = gc->private; 299 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 300 struct hwspinlock *hwlock = chip_data->host_data->hwlock; 301 u32 rtsr, ftsr; 302 int err; 303 304 irq_gc_lock(gc); 305 306 if (hwlock) { 307 err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT); 308 if (err) { 309 pr_err("%s can't get hwspinlock (%d)\n", __func__, err); 310 goto unlock; 311 } 312 } 313 314 rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst); 315 ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst); 316 317 err = stm32_exti_set_type(d, type, &rtsr, &ftsr); 318 if (err) 319 goto unspinlock; 320 321 irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst); 322 irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst); 323 324 unspinlock: 325 if (hwlock) 326 hwspin_unlock_in_atomic(hwlock); 327 unlock: 328 irq_gc_unlock(gc); 329 330 return err; 331 } 332 333 static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data, 334 u32 wake_active) 335 { 336 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 337 void __iomem *base = chip_data->host_data->base; 338 339 /* save rtsr, ftsr registers */ 340 chip_data->rtsr_cache = readl_relaxed(base + stm32_bank->rtsr_ofst); 341 chip_data->ftsr_cache = readl_relaxed(base + stm32_bank->ftsr_ofst); 342 343 writel_relaxed(wake_active, base + stm32_bank->imr_ofst); 344 } 345 346 static void stm32_chip_resume(struct stm32_exti_chip_data *chip_data, 347 u32 mask_cache) 348 { 349 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 350 void __iomem *base = chip_data->host_data->base; 351 352 /* restore rtsr, ftsr, registers */ 353 writel_relaxed(chip_data->rtsr_cache, base + stm32_bank->rtsr_ofst); 354 writel_relaxed(chip_data->ftsr_cache, base + stm32_bank->ftsr_ofst); 355 356 writel_relaxed(mask_cache, base + stm32_bank->imr_ofst); 357 } 358 359 static void stm32_irq_suspend(struct irq_chip_generic *gc) 360 { 361 struct stm32_exti_chip_data *chip_data = gc->private; 362 363 irq_gc_lock(gc); 364 stm32_chip_suspend(chip_data, gc->wake_active); 365 irq_gc_unlock(gc); 366 } 367 368 static void stm32_irq_resume(struct irq_chip_generic *gc) 369 { 370 struct stm32_exti_chip_data *chip_data = gc->private; 371 372 irq_gc_lock(gc); 373 stm32_chip_resume(chip_data, gc->mask_cache); 374 irq_gc_unlock(gc); 375 } 376 377 static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq, 378 unsigned int nr_irqs, void *data) 379 { 380 struct irq_fwspec *fwspec = data; 381 irq_hw_number_t hwirq; 382 383 hwirq = fwspec->param[0]; 384 385 irq_map_generic_chip(d, virq, hwirq); 386 387 return 0; 388 } 389 390 static void stm32_exti_free(struct irq_domain *d, unsigned int virq, 391 unsigned int nr_irqs) 392 { 393 struct irq_data *data = irq_domain_get_irq_data(d, virq); 394 395 irq_domain_reset_irq_data(data); 396 } 397 398 static const struct irq_domain_ops irq_exti_domain_ops = { 399 .map = irq_map_generic_chip, 400 .alloc = stm32_exti_alloc, 401 .free = stm32_exti_free, 402 }; 403 404 static void stm32_irq_ack(struct irq_data *d) 405 { 406 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 407 struct stm32_exti_chip_data *chip_data = gc->private; 408 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 409 410 irq_gc_lock(gc); 411 412 irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst); 413 if (stm32_bank->fpr_ofst != UNDEF_REG) 414 irq_reg_writel(gc, d->mask, stm32_bank->fpr_ofst); 415 416 irq_gc_unlock(gc); 417 } 418 419 static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg) 420 { 421 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 422 void __iomem *base = chip_data->host_data->base; 423 u32 val; 424 425 val = readl_relaxed(base + reg); 426 val |= BIT(d->hwirq % IRQS_PER_BANK); 427 writel_relaxed(val, base + reg); 428 429 return val; 430 } 431 432 static inline u32 stm32_exti_clr_bit(struct irq_data *d, u32 reg) 433 { 434 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 435 void __iomem *base = chip_data->host_data->base; 436 u32 val; 437 438 val = readl_relaxed(base + reg); 439 val &= ~BIT(d->hwirq % IRQS_PER_BANK); 440 writel_relaxed(val, base + reg); 441 442 return val; 443 } 444 445 static void stm32_exti_h_eoi(struct irq_data *d) 446 { 447 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 448 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 449 450 raw_spin_lock(&chip_data->rlock); 451 452 stm32_exti_set_bit(d, stm32_bank->rpr_ofst); 453 if (stm32_bank->fpr_ofst != UNDEF_REG) 454 stm32_exti_set_bit(d, stm32_bank->fpr_ofst); 455 456 raw_spin_unlock(&chip_data->rlock); 457 458 if (d->parent_data->chip) 459 irq_chip_eoi_parent(d); 460 } 461 462 static void stm32_exti_h_mask(struct irq_data *d) 463 { 464 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 465 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 466 467 raw_spin_lock(&chip_data->rlock); 468 chip_data->mask_cache = stm32_exti_clr_bit(d, stm32_bank->imr_ofst); 469 raw_spin_unlock(&chip_data->rlock); 470 471 if (d->parent_data->chip) 472 irq_chip_mask_parent(d); 473 } 474 475 static void stm32_exti_h_unmask(struct irq_data *d) 476 { 477 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 478 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 479 480 raw_spin_lock(&chip_data->rlock); 481 chip_data->mask_cache = stm32_exti_set_bit(d, stm32_bank->imr_ofst); 482 raw_spin_unlock(&chip_data->rlock); 483 484 if (d->parent_data->chip) 485 irq_chip_unmask_parent(d); 486 } 487 488 static int stm32_exti_h_set_type(struct irq_data *d, unsigned int type) 489 { 490 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 491 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 492 struct hwspinlock *hwlock = chip_data->host_data->hwlock; 493 void __iomem *base = chip_data->host_data->base; 494 u32 rtsr, ftsr; 495 int err; 496 497 raw_spin_lock(&chip_data->rlock); 498 499 if (hwlock) { 500 err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT); 501 if (err) { 502 pr_err("%s can't get hwspinlock (%d)\n", __func__, err); 503 goto unlock; 504 } 505 } 506 507 rtsr = readl_relaxed(base + stm32_bank->rtsr_ofst); 508 ftsr = readl_relaxed(base + stm32_bank->ftsr_ofst); 509 510 err = stm32_exti_set_type(d, type, &rtsr, &ftsr); 511 if (err) 512 goto unspinlock; 513 514 writel_relaxed(rtsr, base + stm32_bank->rtsr_ofst); 515 writel_relaxed(ftsr, base + stm32_bank->ftsr_ofst); 516 517 unspinlock: 518 if (hwlock) 519 hwspin_unlock_in_atomic(hwlock); 520 unlock: 521 raw_spin_unlock(&chip_data->rlock); 522 523 return err; 524 } 525 526 static int stm32_exti_h_set_wake(struct irq_data *d, unsigned int on) 527 { 528 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 529 u32 mask = BIT(d->hwirq % IRQS_PER_BANK); 530 531 raw_spin_lock(&chip_data->rlock); 532 533 if (on) 534 chip_data->wake_active |= mask; 535 else 536 chip_data->wake_active &= ~mask; 537 538 raw_spin_unlock(&chip_data->rlock); 539 540 return 0; 541 } 542 543 static int stm32_exti_h_set_affinity(struct irq_data *d, 544 const struct cpumask *dest, bool force) 545 { 546 if (d->parent_data->chip) 547 return irq_chip_set_affinity_parent(d, dest, force); 548 549 return -EINVAL; 550 } 551 552 static int __maybe_unused stm32_exti_h_suspend(void) 553 { 554 struct stm32_exti_chip_data *chip_data; 555 int i; 556 557 for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) { 558 chip_data = &stm32_host_data->chips_data[i]; 559 raw_spin_lock(&chip_data->rlock); 560 stm32_chip_suspend(chip_data, chip_data->wake_active); 561 raw_spin_unlock(&chip_data->rlock); 562 } 563 564 return 0; 565 } 566 567 static void __maybe_unused stm32_exti_h_resume(void) 568 { 569 struct stm32_exti_chip_data *chip_data; 570 int i; 571 572 for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) { 573 chip_data = &stm32_host_data->chips_data[i]; 574 raw_spin_lock(&chip_data->rlock); 575 stm32_chip_resume(chip_data, chip_data->mask_cache); 576 raw_spin_unlock(&chip_data->rlock); 577 } 578 } 579 580 static struct syscore_ops stm32_exti_h_syscore_ops = { 581 #ifdef CONFIG_PM_SLEEP 582 .suspend = stm32_exti_h_suspend, 583 .resume = stm32_exti_h_resume, 584 #endif 585 }; 586 587 static void stm32_exti_h_syscore_init(struct stm32_exti_host_data *host_data) 588 { 589 stm32_host_data = host_data; 590 register_syscore_ops(&stm32_exti_h_syscore_ops); 591 } 592 593 static void stm32_exti_h_syscore_deinit(void) 594 { 595 unregister_syscore_ops(&stm32_exti_h_syscore_ops); 596 } 597 598 static int stm32_exti_h_retrigger(struct irq_data *d) 599 { 600 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 601 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 602 void __iomem *base = chip_data->host_data->base; 603 u32 mask = BIT(d->hwirq % IRQS_PER_BANK); 604 605 writel_relaxed(mask, base + stm32_bank->swier_ofst); 606 607 return 0; 608 } 609 610 static struct irq_chip stm32_exti_h_chip = { 611 .name = "stm32-exti-h", 612 .irq_eoi = stm32_exti_h_eoi, 613 .irq_mask = stm32_exti_h_mask, 614 .irq_unmask = stm32_exti_h_unmask, 615 .irq_retrigger = stm32_exti_h_retrigger, 616 .irq_set_type = stm32_exti_h_set_type, 617 .irq_set_wake = stm32_exti_h_set_wake, 618 .flags = IRQCHIP_MASK_ON_SUSPEND, 619 .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? stm32_exti_h_set_affinity : NULL, 620 }; 621 622 static struct irq_chip stm32_exti_h_chip_direct = { 623 .name = "stm32-exti-h-direct", 624 .irq_eoi = irq_chip_eoi_parent, 625 .irq_ack = irq_chip_ack_parent, 626 .irq_mask = irq_chip_mask_parent, 627 .irq_unmask = irq_chip_unmask_parent, 628 .irq_retrigger = irq_chip_retrigger_hierarchy, 629 .irq_set_type = irq_chip_set_type_parent, 630 .irq_set_wake = stm32_exti_h_set_wake, 631 .flags = IRQCHIP_MASK_ON_SUSPEND, 632 .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? irq_chip_set_affinity_parent : NULL, 633 }; 634 635 static int stm32_exti_h_domain_alloc(struct irq_domain *dm, 636 unsigned int virq, 637 unsigned int nr_irqs, void *data) 638 { 639 struct stm32_exti_host_data *host_data = dm->host_data; 640 struct stm32_exti_chip_data *chip_data; 641 const struct stm32_desc_irq *desc; 642 struct irq_fwspec *fwspec = data; 643 struct irq_fwspec p_fwspec; 644 irq_hw_number_t hwirq; 645 int bank; 646 647 hwirq = fwspec->param[0]; 648 bank = hwirq / IRQS_PER_BANK; 649 chip_data = &host_data->chips_data[bank]; 650 651 652 desc = stm32_exti_get_desc(host_data->drv_data, hwirq); 653 if (!desc) 654 return -EINVAL; 655 656 irq_domain_set_hwirq_and_chip(dm, virq, hwirq, desc->chip, 657 chip_data); 658 if (desc->irq_parent) { 659 p_fwspec.fwnode = dm->parent->fwnode; 660 p_fwspec.param_count = 3; 661 p_fwspec.param[0] = GIC_SPI; 662 p_fwspec.param[1] = desc->irq_parent; 663 p_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH; 664 665 return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec); 666 } 667 668 return 0; 669 } 670 671 static struct 672 stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd, 673 struct device_node *node) 674 { 675 struct stm32_exti_host_data *host_data; 676 677 host_data = kzalloc(sizeof(*host_data), GFP_KERNEL); 678 if (!host_data) 679 return NULL; 680 681 host_data->drv_data = dd; 682 host_data->chips_data = kcalloc(dd->bank_nr, 683 sizeof(struct stm32_exti_chip_data), 684 GFP_KERNEL); 685 if (!host_data->chips_data) 686 goto free_host_data; 687 688 host_data->base = of_iomap(node, 0); 689 if (!host_data->base) { 690 pr_err("%pOF: Unable to map registers\n", node); 691 goto free_chips_data; 692 } 693 694 stm32_host_data = host_data; 695 696 return host_data; 697 698 free_chips_data: 699 kfree(host_data->chips_data); 700 free_host_data: 701 kfree(host_data); 702 703 return NULL; 704 } 705 706 static struct 707 stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data, 708 u32 bank_idx, 709 struct device_node *node) 710 { 711 const struct stm32_exti_bank *stm32_bank; 712 struct stm32_exti_chip_data *chip_data; 713 void __iomem *base = h_data->base; 714 715 stm32_bank = h_data->drv_data->exti_banks[bank_idx]; 716 chip_data = &h_data->chips_data[bank_idx]; 717 chip_data->host_data = h_data; 718 chip_data->reg_bank = stm32_bank; 719 720 raw_spin_lock_init(&chip_data->rlock); 721 722 /* 723 * This IP has no reset, so after hot reboot we should 724 * clear registers to avoid residue 725 */ 726 writel_relaxed(0, base + stm32_bank->imr_ofst); 727 writel_relaxed(0, base + stm32_bank->emr_ofst); 728 729 pr_info("%pOF: bank%d\n", node, bank_idx); 730 731 return chip_data; 732 } 733 734 static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data, 735 struct device_node *node) 736 { 737 struct stm32_exti_host_data *host_data; 738 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 739 int nr_irqs, ret, i; 740 struct irq_chip_generic *gc; 741 struct irq_domain *domain; 742 743 host_data = stm32_exti_host_init(drv_data, node); 744 if (!host_data) 745 return -ENOMEM; 746 747 domain = irq_domain_add_linear(node, drv_data->bank_nr * IRQS_PER_BANK, 748 &irq_exti_domain_ops, NULL); 749 if (!domain) { 750 pr_err("%pOFn: Could not register interrupt domain.\n", 751 node); 752 ret = -ENOMEM; 753 goto out_unmap; 754 } 755 756 ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti", 757 handle_edge_irq, clr, 0, 0); 758 if (ret) { 759 pr_err("%pOF: Could not allocate generic interrupt chip.\n", 760 node); 761 goto out_free_domain; 762 } 763 764 for (i = 0; i < drv_data->bank_nr; i++) { 765 const struct stm32_exti_bank *stm32_bank; 766 struct stm32_exti_chip_data *chip_data; 767 768 stm32_bank = drv_data->exti_banks[i]; 769 chip_data = stm32_exti_chip_init(host_data, i, node); 770 771 gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK); 772 773 gc->reg_base = host_data->base; 774 gc->chip_types->type = IRQ_TYPE_EDGE_BOTH; 775 gc->chip_types->chip.irq_ack = stm32_irq_ack; 776 gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit; 777 gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit; 778 gc->chip_types->chip.irq_set_type = stm32_irq_set_type; 779 gc->chip_types->chip.irq_set_wake = irq_gc_set_wake; 780 gc->suspend = stm32_irq_suspend; 781 gc->resume = stm32_irq_resume; 782 gc->wake_enabled = IRQ_MSK(IRQS_PER_BANK); 783 784 gc->chip_types->regs.mask = stm32_bank->imr_ofst; 785 gc->private = (void *)chip_data; 786 } 787 788 nr_irqs = of_irq_count(node); 789 for (i = 0; i < nr_irqs; i++) { 790 unsigned int irq = irq_of_parse_and_map(node, i); 791 792 irq_set_handler_data(irq, domain); 793 irq_set_chained_handler(irq, stm32_irq_handler); 794 } 795 796 return 0; 797 798 out_free_domain: 799 irq_domain_remove(domain); 800 out_unmap: 801 iounmap(host_data->base); 802 kfree(host_data->chips_data); 803 kfree(host_data); 804 return ret; 805 } 806 807 static const struct irq_domain_ops stm32_exti_h_domain_ops = { 808 .alloc = stm32_exti_h_domain_alloc, 809 .free = irq_domain_free_irqs_common, 810 .xlate = irq_domain_xlate_twocell, 811 }; 812 813 static void stm32_exti_remove_irq(void *data) 814 { 815 struct irq_domain *domain = data; 816 817 irq_domain_remove(domain); 818 } 819 820 static int stm32_exti_remove(struct platform_device *pdev) 821 { 822 stm32_exti_h_syscore_deinit(); 823 return 0; 824 } 825 826 static int stm32_exti_probe(struct platform_device *pdev) 827 { 828 int ret, i; 829 struct device *dev = &pdev->dev; 830 struct device_node *np = dev->of_node; 831 struct irq_domain *parent_domain, *domain; 832 struct stm32_exti_host_data *host_data; 833 const struct stm32_exti_drv_data *drv_data; 834 struct resource *res; 835 836 host_data = devm_kzalloc(dev, sizeof(*host_data), GFP_KERNEL); 837 if (!host_data) 838 return -ENOMEM; 839 840 /* check for optional hwspinlock which may be not available yet */ 841 ret = of_hwspin_lock_get_id(np, 0); 842 if (ret == -EPROBE_DEFER) 843 /* hwspinlock framework not yet ready */ 844 return ret; 845 846 if (ret >= 0) { 847 host_data->hwlock = devm_hwspin_lock_request_specific(dev, ret); 848 if (!host_data->hwlock) { 849 dev_err(dev, "Failed to request hwspinlock\n"); 850 return -EINVAL; 851 } 852 } else if (ret != -ENOENT) { 853 /* note: ENOENT is a valid case (means 'no hwspinlock') */ 854 dev_err(dev, "Failed to get hwspinlock\n"); 855 return ret; 856 } 857 858 /* initialize host_data */ 859 drv_data = of_device_get_match_data(dev); 860 if (!drv_data) { 861 dev_err(dev, "no of match data\n"); 862 return -ENODEV; 863 } 864 host_data->drv_data = drv_data; 865 866 host_data->chips_data = devm_kcalloc(dev, drv_data->bank_nr, 867 sizeof(*host_data->chips_data), 868 GFP_KERNEL); 869 if (!host_data->chips_data) 870 return -ENOMEM; 871 872 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 873 host_data->base = devm_ioremap_resource(dev, res); 874 if (IS_ERR(host_data->base)) { 875 dev_err(dev, "Unable to map registers\n"); 876 return PTR_ERR(host_data->base); 877 } 878 879 for (i = 0; i < drv_data->bank_nr; i++) 880 stm32_exti_chip_init(host_data, i, np); 881 882 parent_domain = irq_find_host(of_irq_find_parent(np)); 883 if (!parent_domain) { 884 dev_err(dev, "GIC interrupt-parent not found\n"); 885 return -EINVAL; 886 } 887 888 domain = irq_domain_add_hierarchy(parent_domain, 0, 889 drv_data->bank_nr * IRQS_PER_BANK, 890 np, &stm32_exti_h_domain_ops, 891 host_data); 892 893 if (!domain) { 894 dev_err(dev, "Could not register exti domain\n"); 895 return -ENOMEM; 896 } 897 898 ret = devm_add_action_or_reset(dev, stm32_exti_remove_irq, domain); 899 if (ret) 900 return ret; 901 902 stm32_exti_h_syscore_init(host_data); 903 904 return 0; 905 } 906 907 /* platform driver only for MP1 */ 908 static const struct of_device_id stm32_exti_ids[] = { 909 { .compatible = "st,stm32mp1-exti", .data = &stm32mp1_drv_data}, 910 {}, 911 }; 912 MODULE_DEVICE_TABLE(of, stm32_exti_ids); 913 914 static struct platform_driver stm32_exti_driver = { 915 .probe = stm32_exti_probe, 916 .remove = stm32_exti_remove, 917 .driver = { 918 .name = "stm32_exti", 919 .of_match_table = stm32_exti_ids, 920 }, 921 }; 922 923 static int __init stm32_exti_arch_init(void) 924 { 925 return platform_driver_register(&stm32_exti_driver); 926 } 927 928 static void __exit stm32_exti_arch_exit(void) 929 { 930 return platform_driver_unregister(&stm32_exti_driver); 931 } 932 933 arch_initcall(stm32_exti_arch_init); 934 module_exit(stm32_exti_arch_exit); 935 936 /* no platform driver for F4 and H7 */ 937 static int __init stm32f4_exti_of_init(struct device_node *np, 938 struct device_node *parent) 939 { 940 return stm32_exti_init(&stm32f4xx_drv_data, np); 941 } 942 943 IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init); 944 945 static int __init stm32h7_exti_of_init(struct device_node *np, 946 struct device_node *parent) 947 { 948 return stm32_exti_init(&stm32h7xx_drv_data, np); 949 } 950 951 IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init); 952