1 /* 2 * SPDX-License-Identifier: MIT 3 * 4 * Copyright © 2014-2018 Intel Corporation 5 */ 6 7 #include "i915_drv.h" 8 #include "intel_context.h" 9 #include "intel_engine_pm.h" 10 #include "intel_gt.h" 11 #include "intel_ring.h" 12 #include "intel_workarounds.h" 13 14 /** 15 * DOC: Hardware workarounds 16 * 17 * This file is intended as a central place to implement most [1]_ of the 18 * required workarounds for hardware to work as originally intended. They fall 19 * in five basic categories depending on how/when they are applied: 20 * 21 * - Workarounds that touch registers that are saved/restored to/from the HW 22 * context image. The list is emitted (via Load Register Immediate commands) 23 * everytime a new context is created. 24 * - GT workarounds. The list of these WAs is applied whenever these registers 25 * revert to default values (on GPU reset, suspend/resume [2]_, etc..). 26 * - Display workarounds. The list is applied during display clock-gating 27 * initialization. 28 * - Workarounds that whitelist a privileged register, so that UMDs can manage 29 * them directly. This is just a special case of a MMMIO workaround (as we 30 * write the list of these to/be-whitelisted registers to some special HW 31 * registers). 32 * - Workaround batchbuffers, that get executed automatically by the hardware 33 * on every HW context restore. 34 * 35 * .. [1] Please notice that there are other WAs that, due to their nature, 36 * cannot be applied from a central place. Those are peppered around the rest 37 * of the code, as needed. 38 * 39 * .. [2] Technically, some registers are powercontext saved & restored, so they 40 * survive a suspend/resume. In practice, writing them again is not too 41 * costly and simplifies things. We can revisit this in the future. 42 * 43 * Layout 44 * ~~~~~~ 45 * 46 * Keep things in this file ordered by WA type, as per the above (context, GT, 47 * display, register whitelist, batchbuffer). Then, inside each type, keep the 48 * following order: 49 * 50 * - Infrastructure functions and macros 51 * - WAs per platform in standard gen/chrono order 52 * - Public functions to init or apply the given workaround type. 53 */ 54 55 static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name) 56 { 57 wal->name = name; 58 wal->engine_name = engine_name; 59 } 60 61 #define WA_LIST_CHUNK (1 << 4) 62 63 static void wa_init_finish(struct i915_wa_list *wal) 64 { 65 /* Trim unused entries. */ 66 if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) { 67 struct i915_wa *list = kmemdup(wal->list, 68 wal->count * sizeof(*list), 69 GFP_KERNEL); 70 71 if (list) { 72 kfree(wal->list); 73 wal->list = list; 74 } 75 } 76 77 if (!wal->count) 78 return; 79 80 DRM_DEBUG_DRIVER("Initialized %u %s workarounds on %s\n", 81 wal->wa_count, wal->name, wal->engine_name); 82 } 83 84 static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) 85 { 86 unsigned int addr = i915_mmio_reg_offset(wa->reg); 87 unsigned int start = 0, end = wal->count; 88 const unsigned int grow = WA_LIST_CHUNK; 89 struct i915_wa *wa_; 90 91 GEM_BUG_ON(!is_power_of_2(grow)); 92 93 if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */ 94 struct i915_wa *list; 95 96 list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa), 97 GFP_KERNEL); 98 if (!list) { 99 DRM_ERROR("No space for workaround init!\n"); 100 return; 101 } 102 103 if (wal->list) 104 memcpy(list, wal->list, sizeof(*wa) * wal->count); 105 106 wal->list = list; 107 } 108 109 while (start < end) { 110 unsigned int mid = start + (end - start) / 2; 111 112 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) { 113 start = mid + 1; 114 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) { 115 end = mid; 116 } else { 117 wa_ = &wal->list[mid]; 118 119 if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) { 120 DRM_ERROR("Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n", 121 i915_mmio_reg_offset(wa_->reg), 122 wa_->clr, wa_->set); 123 124 wa_->set &= ~wa->clr; 125 } 126 127 wal->wa_count++; 128 wa_->set |= wa->set; 129 wa_->clr |= wa->clr; 130 wa_->read |= wa->read; 131 return; 132 } 133 } 134 135 wal->wa_count++; 136 wa_ = &wal->list[wal->count++]; 137 *wa_ = *wa; 138 139 while (wa_-- > wal->list) { 140 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == 141 i915_mmio_reg_offset(wa_[1].reg)); 142 if (i915_mmio_reg_offset(wa_[1].reg) > 143 i915_mmio_reg_offset(wa_[0].reg)) 144 break; 145 146 swap(wa_[1], wa_[0]); 147 } 148 } 149 150 static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, 151 u32 clear, u32 set, u32 read_mask) 152 { 153 struct i915_wa wa = { 154 .reg = reg, 155 .clr = clear, 156 .set = set, 157 .read = read_mask, 158 }; 159 160 _wa_add(wal, &wa); 161 } 162 163 static void 164 wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set) 165 { 166 wa_add(wal, reg, clear, set, clear); 167 } 168 169 static void 170 wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 171 { 172 wa_write_masked_or(wal, reg, ~0, set); 173 } 174 175 static void 176 wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 177 { 178 wa_write_masked_or(wal, reg, set, set); 179 } 180 181 static void 182 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 183 { 184 wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val); 185 } 186 187 static void 188 wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 189 { 190 wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val); 191 } 192 193 #define WA_SET_BIT_MASKED(addr, mask) \ 194 wa_masked_en(wal, (addr), (mask)) 195 196 #define WA_CLR_BIT_MASKED(addr, mask) \ 197 wa_masked_dis(wal, (addr), (mask)) 198 199 #define WA_SET_FIELD_MASKED(addr, mask, value) \ 200 wa_write_masked_or(wal, (addr), 0, _MASKED_FIELD((mask), (value))) 201 202 static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine, 203 struct i915_wa_list *wal) 204 { 205 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); 206 207 /* WaDisableAsyncFlipPerfMode:bdw,chv */ 208 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE); 209 210 /* WaDisablePartialInstShootdown:bdw,chv */ 211 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, 212 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 213 214 /* Use Force Non-Coherent whenever executing a 3D context. This is a 215 * workaround for for a possible hang in the unlikely event a TLB 216 * invalidation occurs during a PSD flush. 217 */ 218 /* WaForceEnableNonCoherent:bdw,chv */ 219 /* WaHdcDisableFetchWhenMasked:bdw,chv */ 220 WA_SET_BIT_MASKED(HDC_CHICKEN0, 221 HDC_DONOT_FETCH_MEM_WHEN_MASKED | 222 HDC_FORCE_NON_COHERENT); 223 224 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: 225 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping 226 * polygons in the same 8x4 pixel/sample area to be processed without 227 * stalling waiting for the earlier ones to write to Hierarchical Z 228 * buffer." 229 * 230 * This optimization is off by default for BDW and CHV; turn it on. 231 */ 232 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); 233 234 /* Wa4x4STCOptimizationDisable:bdw,chv */ 235 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); 236 237 /* 238 * BSpec recommends 8x4 when MSAA is used, 239 * however in practice 16x4 seems fastest. 240 * 241 * Note that PS/WM thread counts depend on the WIZ hashing 242 * disable bit, which we don't touch here, but it's good 243 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 244 */ 245 WA_SET_FIELD_MASKED(GEN7_GT_MODE, 246 GEN6_WIZ_HASHING_MASK, 247 GEN6_WIZ_HASHING_16x4); 248 } 249 250 static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine, 251 struct i915_wa_list *wal) 252 { 253 struct drm_i915_private *i915 = engine->i915; 254 255 gen8_ctx_workarounds_init(engine, wal); 256 257 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ 258 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 259 260 /* WaDisableDopClockGating:bdw 261 * 262 * Also see the related UCGTCL1 write in bdw_init_clock_gating() 263 * to disable EUTC clock gating. 264 */ 265 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, 266 DOP_CLOCK_GATING_DISABLE); 267 268 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, 269 GEN8_SAMPLER_POWER_BYPASS_DIS); 270 271 WA_SET_BIT_MASKED(HDC_CHICKEN0, 272 /* WaForceContextSaveRestoreNonCoherent:bdw */ 273 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 274 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ 275 (IS_BDW_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); 276 } 277 278 static void chv_ctx_workarounds_init(struct intel_engine_cs *engine, 279 struct i915_wa_list *wal) 280 { 281 gen8_ctx_workarounds_init(engine, wal); 282 283 /* WaDisableThreadStallDopClockGating:chv */ 284 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 285 286 /* Improve HiZ throughput on CHV. */ 287 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); 288 } 289 290 static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, 291 struct i915_wa_list *wal) 292 { 293 struct drm_i915_private *i915 = engine->i915; 294 295 if (HAS_LLC(i915)) { 296 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 297 * 298 * Must match Display Engine. See 299 * WaCompressedResourceDisplayNewHashMode. 300 */ 301 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 302 GEN9_PBE_COMPRESSED_HASH_SELECTION); 303 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, 304 GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR); 305 } 306 307 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */ 308 /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */ 309 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, 310 FLOW_CONTROL_ENABLE | 311 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 312 313 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */ 314 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */ 315 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, 316 GEN9_ENABLE_YV12_BUGFIX | 317 GEN9_ENABLE_GPGPU_PREEMPTION); 318 319 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */ 320 /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */ 321 WA_SET_BIT_MASKED(CACHE_MODE_1, 322 GEN8_4x4_STC_OPTIMIZATION_DISABLE | 323 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE); 324 325 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */ 326 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, 327 GEN9_CCS_TLB_PREFETCH_ENABLE); 328 329 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */ 330 WA_SET_BIT_MASKED(HDC_CHICKEN0, 331 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 332 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); 333 334 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are 335 * both tied to WaForceContextSaveRestoreNonCoherent 336 * in some hsds for skl. We keep the tie for all gen9. The 337 * documentation is a bit hazy and so we want to get common behaviour, 338 * even though there is no clear evidence we would need both on kbl/bxt. 339 * This area has been source of system hangs so we play it safe 340 * and mimic the skl regardless of what bspec says. 341 * 342 * Use Force Non-Coherent whenever executing a 3D context. This 343 * is a workaround for a possible hang in the unlikely event 344 * a TLB invalidation occurs during a PSD flush. 345 */ 346 347 /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */ 348 WA_SET_BIT_MASKED(HDC_CHICKEN0, 349 HDC_FORCE_NON_COHERENT); 350 351 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */ 352 if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) 353 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, 354 GEN8_SAMPLER_POWER_BYPASS_DIS); 355 356 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */ 357 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); 358 359 /* 360 * Supporting preemption with fine-granularity requires changes in the 361 * batch buffer programming. Since we can't break old userspace, we 362 * need to set our default preemption level to safe value. Userspace is 363 * still able to use more fine-grained preemption levels, since in 364 * WaEnablePreemptionGranularityControlByUMD we're whitelisting the 365 * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are 366 * not real HW workarounds, but merely a way to start using preemption 367 * while maintaining old contract with userspace. 368 */ 369 370 /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */ 371 WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL); 372 373 /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */ 374 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, 375 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 376 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); 377 378 /* WaClearHIZ_WM_CHICKEN3:bxt,glk */ 379 if (IS_GEN9_LP(i915)) 380 WA_SET_BIT_MASKED(GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ); 381 } 382 383 static void skl_tune_iz_hashing(struct intel_engine_cs *engine, 384 struct i915_wa_list *wal) 385 { 386 struct drm_i915_private *i915 = engine->i915; 387 u8 vals[3] = { 0, 0, 0 }; 388 unsigned int i; 389 390 for (i = 0; i < 3; i++) { 391 u8 ss; 392 393 /* 394 * Only consider slices where one, and only one, subslice has 7 395 * EUs 396 */ 397 if (!is_power_of_2(RUNTIME_INFO(i915)->sseu.subslice_7eu[i])) 398 continue; 399 400 /* 401 * subslice_7eu[i] != 0 (because of the check above) and 402 * ss_max == 4 (maximum number of subslices possible per slice) 403 * 404 * -> 0 <= ss <= 3; 405 */ 406 ss = ffs(RUNTIME_INFO(i915)->sseu.subslice_7eu[i]) - 1; 407 vals[i] = 3 - ss; 408 } 409 410 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) 411 return; 412 413 /* Tune IZ hashing. See intel_device_info_runtime_init() */ 414 WA_SET_FIELD_MASKED(GEN7_GT_MODE, 415 GEN9_IZ_HASHING_MASK(2) | 416 GEN9_IZ_HASHING_MASK(1) | 417 GEN9_IZ_HASHING_MASK(0), 418 GEN9_IZ_HASHING(2, vals[2]) | 419 GEN9_IZ_HASHING(1, vals[1]) | 420 GEN9_IZ_HASHING(0, vals[0])); 421 } 422 423 static void skl_ctx_workarounds_init(struct intel_engine_cs *engine, 424 struct i915_wa_list *wal) 425 { 426 gen9_ctx_workarounds_init(engine, wal); 427 skl_tune_iz_hashing(engine, wal); 428 } 429 430 static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine, 431 struct i915_wa_list *wal) 432 { 433 gen9_ctx_workarounds_init(engine, wal); 434 435 /* WaDisableThreadStallDopClockGating:bxt */ 436 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, 437 STALL_DOP_GATING_DISABLE); 438 439 /* WaToEnableHwFixForPushConstHWBug:bxt */ 440 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 441 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 442 } 443 444 static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine, 445 struct i915_wa_list *wal) 446 { 447 struct drm_i915_private *i915 = engine->i915; 448 449 gen9_ctx_workarounds_init(engine, wal); 450 451 /* WaToEnableHwFixForPushConstHWBug:kbl */ 452 if (IS_KBL_REVID(i915, KBL_REVID_C0, REVID_FOREVER)) 453 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 454 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 455 456 /* WaDisableSbeCacheDispatchPortSharing:kbl */ 457 WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1, 458 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 459 } 460 461 static void glk_ctx_workarounds_init(struct intel_engine_cs *engine, 462 struct i915_wa_list *wal) 463 { 464 gen9_ctx_workarounds_init(engine, wal); 465 466 /* WaToEnableHwFixForPushConstHWBug:glk */ 467 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 468 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 469 } 470 471 static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine, 472 struct i915_wa_list *wal) 473 { 474 gen9_ctx_workarounds_init(engine, wal); 475 476 /* WaToEnableHwFixForPushConstHWBug:cfl */ 477 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 478 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 479 480 /* WaDisableSbeCacheDispatchPortSharing:cfl */ 481 WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1, 482 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 483 } 484 485 static void cnl_ctx_workarounds_init(struct intel_engine_cs *engine, 486 struct i915_wa_list *wal) 487 { 488 /* WaForceContextSaveRestoreNonCoherent:cnl */ 489 WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0, 490 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT); 491 492 /* WaDisableReplayBufferBankArbitrationOptimization:cnl */ 493 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 494 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 495 496 /* WaPushConstantDereferenceHoldDisable:cnl */ 497 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE); 498 499 /* FtrEnableFastAnisoL1BankingFix:cnl */ 500 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX); 501 502 /* WaDisable3DMidCmdPreemption:cnl */ 503 WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL); 504 505 /* WaDisableGPGPUMidCmdPreemption:cnl */ 506 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, 507 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 508 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); 509 510 /* WaDisableEarlyEOT:cnl */ 511 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, DISABLE_EARLY_EOT); 512 } 513 514 static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, 515 struct i915_wa_list *wal) 516 { 517 struct drm_i915_private *i915 = engine->i915; 518 519 /* WaDisableBankHangMode:icl */ 520 wa_write(wal, 521 GEN8_L3CNTLREG, 522 intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) | 523 GEN8_ERRDETBCTRL); 524 525 /* Wa_1604370585:icl (pre-prod) 526 * Formerly known as WaPushConstantDereferenceHoldDisable 527 */ 528 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0)) 529 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, 530 PUSH_CONSTANT_DEREF_DISABLE); 531 532 /* WaForceEnableNonCoherent:icl 533 * This is not the same workaround as in early Gen9 platforms, where 534 * lacking this could cause system hangs, but coherency performance 535 * overhead is high and only a few compute workloads really need it 536 * (the register is whitelisted in hardware now, so UMDs can opt in 537 * for coherency if they have a good reason). 538 */ 539 WA_SET_BIT_MASKED(ICL_HDC_MODE, HDC_FORCE_NON_COHERENT); 540 541 /* Wa_2006611047:icl (pre-prod) 542 * Formerly known as WaDisableImprovedTdlClkGating 543 */ 544 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0)) 545 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, 546 GEN11_TDL_CLOCK_GATING_FIX_DISABLE); 547 548 /* Wa_2006665173:icl (pre-prod) */ 549 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0)) 550 WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, 551 GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC); 552 553 /* WaEnableFloatBlendOptimization:icl */ 554 wa_write_masked_or(wal, 555 GEN10_CACHE_MODE_SS, 556 0, /* write-only, so skip validation */ 557 _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE)); 558 559 /* WaDisableGPGPUMidThreadPreemption:icl */ 560 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, 561 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 562 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 563 564 /* allow headerless messages for preemptible GPGPU context */ 565 WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE, 566 GEN11_SAMPLER_ENABLE_HEADLESS_MSG); 567 568 /* Wa_1604278689:icl,ehl */ 569 wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID); 570 wa_write_masked_or(wal, IVB_FBC_RT_BASE_UPPER, 571 0, /* write-only register; skip validation */ 572 0xFFFFFFFF); 573 574 /* Wa_1406306137:icl,ehl */ 575 wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU); 576 } 577 578 static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, 579 struct i915_wa_list *wal) 580 { 581 /* 582 * Wa_1409142259:tgl 583 * Wa_1409347922:tgl 584 * Wa_1409252684:tgl 585 * Wa_1409217633:tgl 586 * Wa_1409207793:tgl 587 * Wa_1409178076:tgl 588 * Wa_1408979724:tgl 589 */ 590 WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, 591 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); 592 593 /* 594 * Wa_1604555607:gen12 and Wa_1608008084:gen12 595 * FF_MODE2 register will return the wrong value when read. The default 596 * value for this register is zero for all fields and there are no bit 597 * masks. So instead of doing a RMW we should just write the TDS timer 598 * value for Wa_1604555607. 599 */ 600 wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, 601 FF_MODE2_TDS_TIMER_128, 0); 602 603 /* WaDisableGPGPUMidThreadPreemption:tgl */ 604 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, 605 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 606 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 607 } 608 609 static void 610 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, 611 struct i915_wa_list *wal, 612 const char *name) 613 { 614 struct drm_i915_private *i915 = engine->i915; 615 616 if (engine->class != RENDER_CLASS) 617 return; 618 619 wa_init_start(wal, name, engine->name); 620 621 if (IS_GEN(i915, 12)) 622 tgl_ctx_workarounds_init(engine, wal); 623 else if (IS_GEN(i915, 11)) 624 icl_ctx_workarounds_init(engine, wal); 625 else if (IS_CANNONLAKE(i915)) 626 cnl_ctx_workarounds_init(engine, wal); 627 else if (IS_COFFEELAKE(i915)) 628 cfl_ctx_workarounds_init(engine, wal); 629 else if (IS_GEMINILAKE(i915)) 630 glk_ctx_workarounds_init(engine, wal); 631 else if (IS_KABYLAKE(i915)) 632 kbl_ctx_workarounds_init(engine, wal); 633 else if (IS_BROXTON(i915)) 634 bxt_ctx_workarounds_init(engine, wal); 635 else if (IS_SKYLAKE(i915)) 636 skl_ctx_workarounds_init(engine, wal); 637 else if (IS_CHERRYVIEW(i915)) 638 chv_ctx_workarounds_init(engine, wal); 639 else if (IS_BROADWELL(i915)) 640 bdw_ctx_workarounds_init(engine, wal); 641 else if (INTEL_GEN(i915) < 8) 642 return; 643 else 644 MISSING_CASE(INTEL_GEN(i915)); 645 646 wa_init_finish(wal); 647 } 648 649 void intel_engine_init_ctx_wa(struct intel_engine_cs *engine) 650 { 651 __intel_engine_init_ctx_wa(engine, &engine->ctx_wa_list, "context"); 652 } 653 654 int intel_engine_emit_ctx_wa(struct i915_request *rq) 655 { 656 struct i915_wa_list *wal = &rq->engine->ctx_wa_list; 657 struct i915_wa *wa; 658 unsigned int i; 659 u32 *cs; 660 int ret; 661 662 if (wal->count == 0) 663 return 0; 664 665 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 666 if (ret) 667 return ret; 668 669 cs = intel_ring_begin(rq, (wal->count * 2 + 2)); 670 if (IS_ERR(cs)) 671 return PTR_ERR(cs); 672 673 *cs++ = MI_LOAD_REGISTER_IMM(wal->count); 674 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 675 *cs++ = i915_mmio_reg_offset(wa->reg); 676 *cs++ = wa->set; 677 } 678 *cs++ = MI_NOOP; 679 680 intel_ring_advance(rq, cs); 681 682 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 683 if (ret) 684 return ret; 685 686 return 0; 687 } 688 689 static void 690 gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 691 { 692 /* WaDisableKillLogic:bxt,skl,kbl */ 693 if (!IS_COFFEELAKE(i915)) 694 wa_write_or(wal, 695 GAM_ECOCHK, 696 ECOCHK_DIS_TLB); 697 698 if (HAS_LLC(i915)) { 699 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 700 * 701 * Must match Display Engine. See 702 * WaCompressedResourceDisplayNewHashMode. 703 */ 704 wa_write_or(wal, 705 MMCD_MISC_CTRL, 706 MMCD_PCLA | MMCD_HOTSPOT_EN); 707 } 708 709 /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */ 710 wa_write_or(wal, 711 GAM_ECOCHK, 712 BDW_DISABLE_HDC_INVALIDATION); 713 } 714 715 static void 716 skl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 717 { 718 gen9_gt_workarounds_init(i915, wal); 719 720 /* WaDisableGafsUnitClkGating:skl */ 721 wa_write_or(wal, 722 GEN7_UCGCTL4, 723 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 724 725 /* WaInPlaceDecompressionHang:skl */ 726 if (IS_SKL_REVID(i915, SKL_REVID_H0, REVID_FOREVER)) 727 wa_write_or(wal, 728 GEN9_GAMT_ECO_REG_RW_IA, 729 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 730 } 731 732 static void 733 bxt_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 734 { 735 gen9_gt_workarounds_init(i915, wal); 736 737 /* WaInPlaceDecompressionHang:bxt */ 738 wa_write_or(wal, 739 GEN9_GAMT_ECO_REG_RW_IA, 740 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 741 } 742 743 static void 744 kbl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 745 { 746 gen9_gt_workarounds_init(i915, wal); 747 748 /* WaDisableDynamicCreditSharing:kbl */ 749 if (IS_KBL_REVID(i915, 0, KBL_REVID_B0)) 750 wa_write_or(wal, 751 GAMT_CHKN_BIT_REG, 752 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); 753 754 /* WaDisableGafsUnitClkGating:kbl */ 755 wa_write_or(wal, 756 GEN7_UCGCTL4, 757 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 758 759 /* WaInPlaceDecompressionHang:kbl */ 760 wa_write_or(wal, 761 GEN9_GAMT_ECO_REG_RW_IA, 762 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 763 } 764 765 static void 766 glk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 767 { 768 gen9_gt_workarounds_init(i915, wal); 769 } 770 771 static void 772 cfl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 773 { 774 gen9_gt_workarounds_init(i915, wal); 775 776 /* WaDisableGafsUnitClkGating:cfl */ 777 wa_write_or(wal, 778 GEN7_UCGCTL4, 779 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 780 781 /* WaInPlaceDecompressionHang:cfl */ 782 wa_write_or(wal, 783 GEN9_GAMT_ECO_REG_RW_IA, 784 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 785 } 786 787 static void 788 wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) 789 { 790 const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu; 791 unsigned int slice, subslice; 792 u32 l3_en, mcr, mcr_mask; 793 794 GEM_BUG_ON(INTEL_GEN(i915) < 10); 795 796 /* 797 * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl 798 * L3Banks could be fused off in single slice scenario. If that is 799 * the case, we might need to program MCR select to a valid L3Bank 800 * by default, to make sure we correctly read certain registers 801 * later on (in the range 0xB100 - 0xB3FF). 802 * 803 * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl 804 * Before any MMIO read into slice/subslice specific registers, MCR 805 * packet control register needs to be programmed to point to any 806 * enabled s/ss pair. Otherwise, incorrect values will be returned. 807 * This means each subsequent MMIO read will be forwarded to an 808 * specific s/ss combination, but this is OK since these registers 809 * are consistent across s/ss in almost all cases. In the rare 810 * occasions, such as INSTDONE, where this value is dependent 811 * on s/ss combo, the read should be done with read_subslice_reg. 812 * 813 * Since GEN8_MCR_SELECTOR contains dual-purpose bits which select both 814 * to which subslice, or to which L3 bank, the respective mmio reads 815 * will go, we have to find a common index which works for both 816 * accesses. 817 * 818 * Case where we cannot find a common index fortunately should not 819 * happen in production hardware, so we only emit a warning instead of 820 * implementing something more complex that requires checking the range 821 * of every MMIO read. 822 */ 823 824 if (INTEL_GEN(i915) >= 10 && is_power_of_2(sseu->slice_mask)) { 825 u32 l3_fuse = 826 intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3) & 827 GEN10_L3BANK_MASK; 828 829 drm_dbg(&i915->drm, "L3 fuse = %x\n", l3_fuse); 830 l3_en = ~(l3_fuse << GEN10_L3BANK_PAIR_COUNT | l3_fuse); 831 } else { 832 l3_en = ~0; 833 } 834 835 slice = fls(sseu->slice_mask) - 1; 836 subslice = fls(l3_en & intel_sseu_get_subslices(sseu, slice)); 837 if (!subslice) { 838 drm_warn(&i915->drm, 839 "No common index found between subslice mask %x and L3 bank mask %x!\n", 840 intel_sseu_get_subslices(sseu, slice), l3_en); 841 subslice = fls(l3_en); 842 drm_WARN_ON(&i915->drm, !subslice); 843 } 844 subslice--; 845 846 if (INTEL_GEN(i915) >= 11) { 847 mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); 848 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK; 849 } else { 850 mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); 851 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK; 852 } 853 854 drm_dbg(&i915->drm, "MCR slice/subslice = %x\n", mcr); 855 856 wa_write_masked_or(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr); 857 } 858 859 static void 860 cnl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 861 { 862 wa_init_mcr(i915, wal); 863 864 /* WaInPlaceDecompressionHang:cnl */ 865 wa_write_or(wal, 866 GEN9_GAMT_ECO_REG_RW_IA, 867 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 868 } 869 870 static void 871 icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 872 { 873 wa_init_mcr(i915, wal); 874 875 /* WaInPlaceDecompressionHang:icl */ 876 wa_write_or(wal, 877 GEN9_GAMT_ECO_REG_RW_IA, 878 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 879 880 /* WaModifyGamTlbPartitioning:icl */ 881 wa_write_masked_or(wal, 882 GEN11_GACB_PERF_CTRL, 883 GEN11_HASH_CTRL_MASK, 884 GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4); 885 886 /* Wa_1405766107:icl 887 * Formerly known as WaCL2SFHalfMaxAlloc 888 */ 889 wa_write_or(wal, 890 GEN11_LSN_UNSLCVC, 891 GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC | 892 GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC); 893 894 /* Wa_220166154:icl 895 * Formerly known as WaDisCtxReload 896 */ 897 wa_write_or(wal, 898 GEN8_GAMW_ECO_DEV_RW_IA, 899 GAMW_ECO_DEV_CTX_RELOAD_DISABLE); 900 901 /* Wa_1405779004:icl (pre-prod) */ 902 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0)) 903 wa_write_or(wal, 904 SLICE_UNIT_LEVEL_CLKGATE, 905 MSCUNIT_CLKGATE_DIS); 906 907 /* Wa_1406838659:icl (pre-prod) */ 908 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0)) 909 wa_write_or(wal, 910 INF_UNIT_LEVEL_CLKGATE, 911 CGPSF_CLKGATE_DIS); 912 913 /* Wa_1406463099:icl 914 * Formerly known as WaGamTlbPendError 915 */ 916 wa_write_or(wal, 917 GAMT_CHKN_BIT_REG, 918 GAMT_CHKN_DISABLE_L3_COH_PIPE); 919 920 /* Wa_1607087056:icl,ehl,jsl */ 921 if (IS_ICELAKE(i915) || 922 IS_EHL_REVID(i915, EHL_REVID_A0, EHL_REVID_A0)) { 923 wa_write_or(wal, 924 SLICE_UNIT_LEVEL_CLKGATE, 925 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 926 } 927 } 928 929 static void 930 tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 931 { 932 wa_init_mcr(i915, wal); 933 934 /* Wa_1409420604:tgl */ 935 if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) 936 wa_write_or(wal, 937 SUBSLICE_UNIT_LEVEL_CLKGATE2, 938 CPSSUNIT_CLKGATE_DIS); 939 940 /* Wa_1607087056:tgl also know as BUG:1409180338 */ 941 if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) 942 wa_write_or(wal, 943 SLICE_UNIT_LEVEL_CLKGATE, 944 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 945 } 946 947 static void 948 gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) 949 { 950 if (IS_GEN(i915, 12)) 951 tgl_gt_workarounds_init(i915, wal); 952 else if (IS_GEN(i915, 11)) 953 icl_gt_workarounds_init(i915, wal); 954 else if (IS_CANNONLAKE(i915)) 955 cnl_gt_workarounds_init(i915, wal); 956 else if (IS_COFFEELAKE(i915)) 957 cfl_gt_workarounds_init(i915, wal); 958 else if (IS_GEMINILAKE(i915)) 959 glk_gt_workarounds_init(i915, wal); 960 else if (IS_KABYLAKE(i915)) 961 kbl_gt_workarounds_init(i915, wal); 962 else if (IS_BROXTON(i915)) 963 bxt_gt_workarounds_init(i915, wal); 964 else if (IS_SKYLAKE(i915)) 965 skl_gt_workarounds_init(i915, wal); 966 else if (INTEL_GEN(i915) <= 8) 967 return; 968 else 969 MISSING_CASE(INTEL_GEN(i915)); 970 } 971 972 void intel_gt_init_workarounds(struct drm_i915_private *i915) 973 { 974 struct i915_wa_list *wal = &i915->gt_wa_list; 975 976 wa_init_start(wal, "GT", "global"); 977 gt_init_workarounds(i915, wal); 978 wa_init_finish(wal); 979 } 980 981 static enum forcewake_domains 982 wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal) 983 { 984 enum forcewake_domains fw = 0; 985 struct i915_wa *wa; 986 unsigned int i; 987 988 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 989 fw |= intel_uncore_forcewake_for_reg(uncore, 990 wa->reg, 991 FW_REG_READ | 992 FW_REG_WRITE); 993 994 return fw; 995 } 996 997 static bool 998 wa_verify(const struct i915_wa *wa, u32 cur, const char *name, const char *from) 999 { 1000 if ((cur ^ wa->set) & wa->read) { 1001 DRM_ERROR("%s workaround lost on %s! (%x=%x/%x, expected %x)\n", 1002 name, from, i915_mmio_reg_offset(wa->reg), 1003 cur, cur & wa->read, wa->set); 1004 1005 return false; 1006 } 1007 1008 return true; 1009 } 1010 1011 static void 1012 wa_list_apply(struct intel_uncore *uncore, const struct i915_wa_list *wal) 1013 { 1014 enum forcewake_domains fw; 1015 unsigned long flags; 1016 struct i915_wa *wa; 1017 unsigned int i; 1018 1019 if (!wal->count) 1020 return; 1021 1022 fw = wal_get_fw_for_rmw(uncore, wal); 1023 1024 spin_lock_irqsave(&uncore->lock, flags); 1025 intel_uncore_forcewake_get__locked(uncore, fw); 1026 1027 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 1028 if (wa->clr) 1029 intel_uncore_rmw_fw(uncore, wa->reg, wa->clr, wa->set); 1030 else 1031 intel_uncore_write_fw(uncore, wa->reg, wa->set); 1032 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 1033 wa_verify(wa, 1034 intel_uncore_read_fw(uncore, wa->reg), 1035 wal->name, "application"); 1036 } 1037 1038 intel_uncore_forcewake_put__locked(uncore, fw); 1039 spin_unlock_irqrestore(&uncore->lock, flags); 1040 } 1041 1042 void intel_gt_apply_workarounds(struct intel_gt *gt) 1043 { 1044 wa_list_apply(gt->uncore, >->i915->gt_wa_list); 1045 } 1046 1047 static bool wa_list_verify(struct intel_uncore *uncore, 1048 const struct i915_wa_list *wal, 1049 const char *from) 1050 { 1051 struct i915_wa *wa; 1052 unsigned int i; 1053 bool ok = true; 1054 1055 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1056 ok &= wa_verify(wa, 1057 intel_uncore_read(uncore, wa->reg), 1058 wal->name, from); 1059 1060 return ok; 1061 } 1062 1063 bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from) 1064 { 1065 return wa_list_verify(gt->uncore, >->i915->gt_wa_list, from); 1066 } 1067 1068 static inline bool is_nonpriv_flags_valid(u32 flags) 1069 { 1070 /* Check only valid flag bits are set */ 1071 if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID) 1072 return false; 1073 1074 /* NB: Only 3 out of 4 enum values are valid for access field */ 1075 if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) == 1076 RING_FORCE_TO_NONPRIV_ACCESS_INVALID) 1077 return false; 1078 1079 return true; 1080 } 1081 1082 static void 1083 whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags) 1084 { 1085 struct i915_wa wa = { 1086 .reg = reg 1087 }; 1088 1089 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) 1090 return; 1091 1092 if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags))) 1093 return; 1094 1095 wa.reg.reg |= flags; 1096 _wa_add(wal, &wa); 1097 } 1098 1099 static void 1100 whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg) 1101 { 1102 whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); 1103 } 1104 1105 static void gen9_whitelist_build(struct i915_wa_list *w) 1106 { 1107 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */ 1108 whitelist_reg(w, GEN9_CTX_PREEMPT_REG); 1109 1110 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */ 1111 whitelist_reg(w, GEN8_CS_CHICKEN1); 1112 1113 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */ 1114 whitelist_reg(w, GEN8_HDC_CHICKEN1); 1115 1116 /* WaSendPushConstantsFromMMIO:skl,bxt */ 1117 whitelist_reg(w, COMMON_SLICE_CHICKEN2); 1118 } 1119 1120 static void skl_whitelist_build(struct intel_engine_cs *engine) 1121 { 1122 struct i915_wa_list *w = &engine->whitelist; 1123 1124 if (engine->class != RENDER_CLASS) 1125 return; 1126 1127 gen9_whitelist_build(w); 1128 1129 /* WaDisableLSQCROPERFforOCL:skl */ 1130 whitelist_reg(w, GEN8_L3SQCREG4); 1131 } 1132 1133 static void bxt_whitelist_build(struct intel_engine_cs *engine) 1134 { 1135 if (engine->class != RENDER_CLASS) 1136 return; 1137 1138 gen9_whitelist_build(&engine->whitelist); 1139 } 1140 1141 static void kbl_whitelist_build(struct intel_engine_cs *engine) 1142 { 1143 struct i915_wa_list *w = &engine->whitelist; 1144 1145 if (engine->class != RENDER_CLASS) 1146 return; 1147 1148 gen9_whitelist_build(w); 1149 1150 /* WaDisableLSQCROPERFforOCL:kbl */ 1151 whitelist_reg(w, GEN8_L3SQCREG4); 1152 } 1153 1154 static void glk_whitelist_build(struct intel_engine_cs *engine) 1155 { 1156 struct i915_wa_list *w = &engine->whitelist; 1157 1158 if (engine->class != RENDER_CLASS) 1159 return; 1160 1161 gen9_whitelist_build(w); 1162 1163 /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */ 1164 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 1165 } 1166 1167 static void cfl_whitelist_build(struct intel_engine_cs *engine) 1168 { 1169 struct i915_wa_list *w = &engine->whitelist; 1170 1171 if (engine->class != RENDER_CLASS) 1172 return; 1173 1174 gen9_whitelist_build(w); 1175 1176 /* 1177 * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml 1178 * 1179 * This covers 4 register which are next to one another : 1180 * - PS_INVOCATION_COUNT 1181 * - PS_INVOCATION_COUNT_UDW 1182 * - PS_DEPTH_COUNT 1183 * - PS_DEPTH_COUNT_UDW 1184 */ 1185 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1186 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1187 RING_FORCE_TO_NONPRIV_RANGE_4); 1188 } 1189 1190 static void cnl_whitelist_build(struct intel_engine_cs *engine) 1191 { 1192 struct i915_wa_list *w = &engine->whitelist; 1193 1194 if (engine->class != RENDER_CLASS) 1195 return; 1196 1197 /* WaEnablePreemptionGranularityControlByUMD:cnl */ 1198 whitelist_reg(w, GEN8_CS_CHICKEN1); 1199 } 1200 1201 static void icl_whitelist_build(struct intel_engine_cs *engine) 1202 { 1203 struct i915_wa_list *w = &engine->whitelist; 1204 1205 switch (engine->class) { 1206 case RENDER_CLASS: 1207 /* WaAllowUMDToModifyHalfSliceChicken7:icl */ 1208 whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7); 1209 1210 /* WaAllowUMDToModifySamplerMode:icl */ 1211 whitelist_reg(w, GEN10_SAMPLER_MODE); 1212 1213 /* WaEnableStateCacheRedirectToCS:icl */ 1214 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 1215 1216 /* 1217 * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl 1218 * 1219 * This covers 4 register which are next to one another : 1220 * - PS_INVOCATION_COUNT 1221 * - PS_INVOCATION_COUNT_UDW 1222 * - PS_DEPTH_COUNT 1223 * - PS_DEPTH_COUNT_UDW 1224 */ 1225 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1226 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1227 RING_FORCE_TO_NONPRIV_RANGE_4); 1228 break; 1229 1230 case VIDEO_DECODE_CLASS: 1231 /* hucStatusRegOffset */ 1232 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base), 1233 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1234 /* hucUKernelHdrInfoRegOffset */ 1235 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base), 1236 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1237 /* hucStatus2RegOffset */ 1238 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), 1239 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1240 break; 1241 1242 default: 1243 break; 1244 } 1245 } 1246 1247 static void tgl_whitelist_build(struct intel_engine_cs *engine) 1248 { 1249 struct i915_wa_list *w = &engine->whitelist; 1250 1251 switch (engine->class) { 1252 case RENDER_CLASS: 1253 /* 1254 * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl 1255 * Wa_1408556865:tgl 1256 * 1257 * This covers 4 registers which are next to one another : 1258 * - PS_INVOCATION_COUNT 1259 * - PS_INVOCATION_COUNT_UDW 1260 * - PS_DEPTH_COUNT 1261 * - PS_DEPTH_COUNT_UDW 1262 */ 1263 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1264 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1265 RING_FORCE_TO_NONPRIV_RANGE_4); 1266 1267 /* Wa_1808121037:tgl */ 1268 whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); 1269 1270 /* Wa_1806527549:tgl */ 1271 whitelist_reg(w, HIZ_CHICKEN); 1272 break; 1273 default: 1274 break; 1275 } 1276 } 1277 1278 void intel_engine_init_whitelist(struct intel_engine_cs *engine) 1279 { 1280 struct drm_i915_private *i915 = engine->i915; 1281 struct i915_wa_list *w = &engine->whitelist; 1282 1283 wa_init_start(w, "whitelist", engine->name); 1284 1285 if (IS_GEN(i915, 12)) 1286 tgl_whitelist_build(engine); 1287 else if (IS_GEN(i915, 11)) 1288 icl_whitelist_build(engine); 1289 else if (IS_CANNONLAKE(i915)) 1290 cnl_whitelist_build(engine); 1291 else if (IS_COFFEELAKE(i915)) 1292 cfl_whitelist_build(engine); 1293 else if (IS_GEMINILAKE(i915)) 1294 glk_whitelist_build(engine); 1295 else if (IS_KABYLAKE(i915)) 1296 kbl_whitelist_build(engine); 1297 else if (IS_BROXTON(i915)) 1298 bxt_whitelist_build(engine); 1299 else if (IS_SKYLAKE(i915)) 1300 skl_whitelist_build(engine); 1301 else if (INTEL_GEN(i915) <= 8) 1302 return; 1303 else 1304 MISSING_CASE(INTEL_GEN(i915)); 1305 1306 wa_init_finish(w); 1307 } 1308 1309 void intel_engine_apply_whitelist(struct intel_engine_cs *engine) 1310 { 1311 const struct i915_wa_list *wal = &engine->whitelist; 1312 struct intel_uncore *uncore = engine->uncore; 1313 const u32 base = engine->mmio_base; 1314 struct i915_wa *wa; 1315 unsigned int i; 1316 1317 if (!wal->count) 1318 return; 1319 1320 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1321 intel_uncore_write(uncore, 1322 RING_FORCE_TO_NONPRIV(base, i), 1323 i915_mmio_reg_offset(wa->reg)); 1324 1325 /* And clear the rest just in case of garbage */ 1326 for (; i < RING_MAX_NONPRIV_SLOTS; i++) 1327 intel_uncore_write(uncore, 1328 RING_FORCE_TO_NONPRIV(base, i), 1329 i915_mmio_reg_offset(RING_NOPID(base))); 1330 } 1331 1332 static void 1333 rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 1334 { 1335 struct drm_i915_private *i915 = engine->i915; 1336 1337 if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) { 1338 /* 1339 * Wa_1607138336:tgl 1340 * Wa_1607063988:tgl 1341 */ 1342 wa_write_or(wal, 1343 GEN9_CTX_PREEMPT_REG, 1344 GEN12_DISABLE_POSH_BUSY_FF_DOP_CG); 1345 1346 /* 1347 * Wa_1607030317:tgl 1348 * Wa_1607186500:tgl 1349 * Wa_1607297627:tgl there is 3 entries for this WA on BSpec, 2 1350 * of then says it is fixed on B0 the other one says it is 1351 * permanent 1352 */ 1353 wa_masked_en(wal, 1354 GEN6_RC_SLEEP_PSMI_CONTROL, 1355 GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 1356 GEN8_RC_SEMA_IDLE_MSG_DISABLE); 1357 1358 /* 1359 * Wa_1606679103:tgl 1360 * (see also Wa_1606682166:icl) 1361 */ 1362 wa_write_or(wal, 1363 GEN7_SARCHKMD, 1364 GEN7_DISABLE_SAMPLER_PREFETCH); 1365 1366 /* Wa_1407928979:tgl */ 1367 wa_write_or(wal, 1368 GEN7_FF_THREAD_MODE, 1369 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 1370 1371 /* Wa_1408615072:tgl */ 1372 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1373 VSUNIT_CLKGATE_DIS_TGL); 1374 } 1375 1376 if (IS_TIGERLAKE(i915)) { 1377 /* Wa_1606931601:tgl */ 1378 wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ); 1379 1380 /* Wa_1409804808:tgl */ 1381 wa_masked_en(wal, GEN7_ROW_CHICKEN2, 1382 GEN12_PUSH_CONST_DEREF_HOLD_DIS); 1383 1384 /* Wa_1606700617:tgl */ 1385 wa_masked_en(wal, 1386 GEN9_CS_DEBUG_MODE1, 1387 FF_DOP_CLOCK_GATE_DISABLE); 1388 1389 /* 1390 * Wa_1409085225:tgl 1391 * Wa_14010229206:tgl 1392 */ 1393 wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); 1394 } 1395 1396 if (IS_GEN(i915, 11)) { 1397 /* This is not an Wa. Enable for better image quality */ 1398 wa_masked_en(wal, 1399 _3D_CHICKEN3, 1400 _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE); 1401 1402 /* WaPipelineFlushCoherentLines:icl */ 1403 wa_write_or(wal, 1404 GEN8_L3SQCREG4, 1405 GEN8_LQSC_FLUSH_COHERENT_LINES); 1406 1407 /* 1408 * Wa_1405543622:icl 1409 * Formerly known as WaGAPZPriorityScheme 1410 */ 1411 wa_write_or(wal, 1412 GEN8_GARBCNTL, 1413 GEN11_ARBITRATION_PRIO_ORDER_MASK); 1414 1415 /* 1416 * Wa_1604223664:icl 1417 * Formerly known as WaL3BankAddressHashing 1418 */ 1419 wa_write_masked_or(wal, 1420 GEN8_GARBCNTL, 1421 GEN11_HASH_CTRL_EXCL_MASK, 1422 GEN11_HASH_CTRL_EXCL_BIT0); 1423 wa_write_masked_or(wal, 1424 GEN11_GLBLINVL, 1425 GEN11_BANK_HASH_ADDR_EXCL_MASK, 1426 GEN11_BANK_HASH_ADDR_EXCL_BIT0); 1427 1428 /* 1429 * Wa_1405733216:icl 1430 * Formerly known as WaDisableCleanEvicts 1431 */ 1432 wa_write_or(wal, 1433 GEN8_L3SQCREG4, 1434 GEN11_LQSC_CLEAN_EVICT_DISABLE); 1435 1436 /* WaForwardProgressSoftReset:icl */ 1437 wa_write_or(wal, 1438 GEN10_SCRATCH_LNCF2, 1439 PMFLUSHDONE_LNICRSDROP | 1440 PMFLUSH_GAPL3UNBLOCK | 1441 PMFLUSHDONE_LNEBLK); 1442 1443 /* Wa_1406609255:icl (pre-prod) */ 1444 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0)) 1445 wa_write_or(wal, 1446 GEN7_SARCHKMD, 1447 GEN7_DISABLE_DEMAND_PREFETCH); 1448 1449 /* Wa_1606682166:icl */ 1450 wa_write_or(wal, 1451 GEN7_SARCHKMD, 1452 GEN7_DISABLE_SAMPLER_PREFETCH); 1453 1454 /* Wa_1409178092:icl */ 1455 wa_write_masked_or(wal, 1456 GEN11_SCRATCH2, 1457 GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE, 1458 0); 1459 1460 /* WaEnable32PlaneMode:icl */ 1461 wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS, 1462 GEN11_ENABLE_32_PLANE_MODE); 1463 1464 /* 1465 * Wa_1408615072:icl,ehl (vsunit) 1466 * Wa_1407596294:icl,ehl (hsunit) 1467 */ 1468 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1469 VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); 1470 1471 /* Wa_1407352427:icl,ehl */ 1472 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1473 PSDUNIT_CLKGATE_DIS); 1474 1475 /* Wa_1406680159:icl,ehl */ 1476 wa_write_or(wal, 1477 SUBSLICE_UNIT_LEVEL_CLKGATE, 1478 GWUNIT_CLKGATE_DIS); 1479 1480 /* 1481 * Wa_1408767742:icl[a2..forever],ehl[all] 1482 * Wa_1605460711:icl[a0..c0] 1483 */ 1484 wa_write_or(wal, 1485 GEN7_FF_THREAD_MODE, 1486 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 1487 } 1488 1489 if (IS_GEN_RANGE(i915, 9, 12)) { 1490 /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */ 1491 wa_masked_en(wal, 1492 GEN7_FF_SLICE_CS_CHICKEN1, 1493 GEN9_FFSC_PERCTX_PREEMPT_CTRL); 1494 } 1495 1496 if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) { 1497 /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */ 1498 wa_write_or(wal, 1499 GEN8_GARBCNTL, 1500 GEN9_GAPS_TSV_CREDIT_DISABLE); 1501 } 1502 1503 if (IS_BROXTON(i915)) { 1504 /* WaDisablePooledEuLoadBalancingFix:bxt */ 1505 wa_masked_en(wal, 1506 FF_SLICE_CS_CHICKEN2, 1507 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); 1508 } 1509 1510 if (IS_GEN(i915, 9)) { 1511 /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */ 1512 wa_masked_en(wal, 1513 GEN9_CSFE_CHICKEN1_RCS, 1514 GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE); 1515 1516 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */ 1517 wa_write_or(wal, 1518 BDW_SCRATCH1, 1519 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); 1520 1521 /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */ 1522 if (IS_GEN9_LP(i915)) 1523 wa_write_masked_or(wal, 1524 GEN8_L3SQCREG1, 1525 L3_PRIO_CREDITS_MASK, 1526 L3_GENERAL_PRIO_CREDITS(62) | 1527 L3_HIGH_PRIO_CREDITS(2)); 1528 1529 /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */ 1530 wa_write_or(wal, 1531 GEN8_L3SQCREG4, 1532 GEN8_LQSC_FLUSH_COHERENT_LINES); 1533 } 1534 1535 if (IS_GEN(i915, 7)) 1536 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ 1537 wa_masked_en(wal, 1538 GFX_MODE_GEN7, 1539 GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE); 1540 1541 if (IS_GEN_RANGE(i915, 6, 7)) 1542 /* 1543 * We need to disable the AsyncFlip performance optimisations in 1544 * order to use MI_WAIT_FOR_EVENT within the CS. It should 1545 * already be programmed to '1' on all products. 1546 * 1547 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv 1548 */ 1549 wa_masked_en(wal, 1550 MI_MODE, 1551 ASYNC_FLIP_PERF_DISABLE); 1552 1553 if (IS_GEN(i915, 6)) { 1554 /* 1555 * Required for the hardware to program scanline values for 1556 * waiting 1557 * WaEnableFlushTlbInvalidationMode:snb 1558 */ 1559 wa_masked_en(wal, 1560 GFX_MODE, 1561 GFX_TLB_INVALIDATE_EXPLICIT); 1562 1563 /* 1564 * From the Sandybridge PRM, volume 1 part 3, page 24: 1565 * "If this bit is set, STCunit will have LRA as replacement 1566 * policy. [...] This bit must be reset. LRA replacement 1567 * policy is not supported." 1568 */ 1569 wa_masked_dis(wal, 1570 CACHE_MODE_0, 1571 CM0_STC_EVICT_DISABLE_LRA_SNB); 1572 } 1573 1574 if (IS_GEN_RANGE(i915, 4, 6)) 1575 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ 1576 wa_add(wal, MI_MODE, 1577 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), 1578 /* XXX bit doesn't stick on Broadwater */ 1579 IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH); 1580 } 1581 1582 static void 1583 xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 1584 { 1585 struct drm_i915_private *i915 = engine->i915; 1586 1587 /* WaKBLVECSSemaphoreWaitPoll:kbl */ 1588 if (IS_KBL_REVID(i915, KBL_REVID_A0, KBL_REVID_E0)) { 1589 wa_write(wal, 1590 RING_SEMA_WAIT_POLL(engine->mmio_base), 1591 1); 1592 } 1593 } 1594 1595 static void 1596 engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal) 1597 { 1598 if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 4)) 1599 return; 1600 1601 if (engine->class == RENDER_CLASS) 1602 rcs_engine_wa_init(engine, wal); 1603 else 1604 xcs_engine_wa_init(engine, wal); 1605 } 1606 1607 void intel_engine_init_workarounds(struct intel_engine_cs *engine) 1608 { 1609 struct i915_wa_list *wal = &engine->wa_list; 1610 1611 if (INTEL_GEN(engine->i915) < 4) 1612 return; 1613 1614 wa_init_start(wal, "engine", engine->name); 1615 engine_init_workarounds(engine, wal); 1616 wa_init_finish(wal); 1617 } 1618 1619 void intel_engine_apply_workarounds(struct intel_engine_cs *engine) 1620 { 1621 wa_list_apply(engine->uncore, &engine->wa_list); 1622 } 1623 1624 static struct i915_vma * 1625 create_scratch(struct i915_address_space *vm, int count) 1626 { 1627 struct drm_i915_gem_object *obj; 1628 struct i915_vma *vma; 1629 unsigned int size; 1630 int err; 1631 1632 size = round_up(count * sizeof(u32), PAGE_SIZE); 1633 obj = i915_gem_object_create_internal(vm->i915, size); 1634 if (IS_ERR(obj)) 1635 return ERR_CAST(obj); 1636 1637 i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC); 1638 1639 vma = i915_vma_instance(obj, vm, NULL); 1640 if (IS_ERR(vma)) { 1641 err = PTR_ERR(vma); 1642 goto err_obj; 1643 } 1644 1645 err = i915_vma_pin(vma, 0, 0, 1646 i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER); 1647 if (err) 1648 goto err_obj; 1649 1650 return vma; 1651 1652 err_obj: 1653 i915_gem_object_put(obj); 1654 return ERR_PTR(err); 1655 } 1656 1657 static const struct { 1658 u32 start; 1659 u32 end; 1660 } mcr_ranges_gen8[] = { 1661 { .start = 0x5500, .end = 0x55ff }, 1662 { .start = 0x7000, .end = 0x7fff }, 1663 { .start = 0x9400, .end = 0x97ff }, 1664 { .start = 0xb000, .end = 0xb3ff }, 1665 { .start = 0xe000, .end = 0xe7ff }, 1666 {}, 1667 }; 1668 1669 static bool mcr_range(struct drm_i915_private *i915, u32 offset) 1670 { 1671 int i; 1672 1673 if (INTEL_GEN(i915) < 8) 1674 return false; 1675 1676 /* 1677 * Registers in these ranges are affected by the MCR selector 1678 * which only controls CPU initiated MMIO. Routing does not 1679 * work for CS access so we cannot verify them on this path. 1680 */ 1681 for (i = 0; mcr_ranges_gen8[i].start; i++) 1682 if (offset >= mcr_ranges_gen8[i].start && 1683 offset <= mcr_ranges_gen8[i].end) 1684 return true; 1685 1686 return false; 1687 } 1688 1689 static int 1690 wa_list_srm(struct i915_request *rq, 1691 const struct i915_wa_list *wal, 1692 struct i915_vma *vma) 1693 { 1694 struct drm_i915_private *i915 = rq->i915; 1695 unsigned int i, count = 0; 1696 const struct i915_wa *wa; 1697 u32 srm, *cs; 1698 1699 srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; 1700 if (INTEL_GEN(i915) >= 8) 1701 srm++; 1702 1703 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 1704 if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg))) 1705 count++; 1706 } 1707 1708 cs = intel_ring_begin(rq, 4 * count); 1709 if (IS_ERR(cs)) 1710 return PTR_ERR(cs); 1711 1712 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 1713 u32 offset = i915_mmio_reg_offset(wa->reg); 1714 1715 if (mcr_range(i915, offset)) 1716 continue; 1717 1718 *cs++ = srm; 1719 *cs++ = offset; 1720 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i; 1721 *cs++ = 0; 1722 } 1723 intel_ring_advance(rq, cs); 1724 1725 return 0; 1726 } 1727 1728 static int engine_wa_list_verify(struct intel_context *ce, 1729 const struct i915_wa_list * const wal, 1730 const char *from) 1731 { 1732 const struct i915_wa *wa; 1733 struct i915_request *rq; 1734 struct i915_vma *vma; 1735 unsigned int i; 1736 u32 *results; 1737 int err; 1738 1739 if (!wal->count) 1740 return 0; 1741 1742 vma = create_scratch(&ce->engine->gt->ggtt->vm, wal->count); 1743 if (IS_ERR(vma)) 1744 return PTR_ERR(vma); 1745 1746 intel_engine_pm_get(ce->engine); 1747 rq = intel_context_create_request(ce); 1748 intel_engine_pm_put(ce->engine); 1749 if (IS_ERR(rq)) { 1750 err = PTR_ERR(rq); 1751 goto err_vma; 1752 } 1753 1754 i915_vma_lock(vma); 1755 err = i915_request_await_object(rq, vma->obj, true); 1756 if (err == 0) 1757 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); 1758 i915_vma_unlock(vma); 1759 if (err) { 1760 i915_request_add(rq); 1761 goto err_vma; 1762 } 1763 1764 err = wa_list_srm(rq, wal, vma); 1765 if (err) 1766 goto err_vma; 1767 1768 i915_request_get(rq); 1769 i915_request_add(rq); 1770 if (i915_request_wait(rq, 0, HZ / 5) < 0) { 1771 err = -ETIME; 1772 goto err_rq; 1773 } 1774 1775 results = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); 1776 if (IS_ERR(results)) { 1777 err = PTR_ERR(results); 1778 goto err_rq; 1779 } 1780 1781 err = 0; 1782 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 1783 if (mcr_range(rq->i915, i915_mmio_reg_offset(wa->reg))) 1784 continue; 1785 1786 if (!wa_verify(wa, results[i], wal->name, from)) 1787 err = -ENXIO; 1788 } 1789 1790 i915_gem_object_unpin_map(vma->obj); 1791 1792 err_rq: 1793 i915_request_put(rq); 1794 err_vma: 1795 i915_vma_unpin(vma); 1796 i915_vma_put(vma); 1797 return err; 1798 } 1799 1800 int intel_engine_verify_workarounds(struct intel_engine_cs *engine, 1801 const char *from) 1802 { 1803 return engine_wa_list_verify(engine->kernel_context, 1804 &engine->wa_list, 1805 from); 1806 } 1807 1808 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 1809 #include "selftest_workarounds.c" 1810 #endif 1811