1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atombios.h" 30 #include "amdgpu_ih.h" 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_psp.h" 35 #include "amdgpu_smu.h" 36 #include "atom.h" 37 #include "amd_pcie.h" 38 39 #include "gc/gc_10_1_0_offset.h" 40 #include "gc/gc_10_1_0_sh_mask.h" 41 #include "hdp/hdp_5_0_0_offset.h" 42 #include "hdp/hdp_5_0_0_sh_mask.h" 43 #include "smuio/smuio_11_0_0_offset.h" 44 45 #include "soc15.h" 46 #include "soc15_common.h" 47 #include "gmc_v10_0.h" 48 #include "gfxhub_v2_0.h" 49 #include "mmhub_v2_0.h" 50 #include "nbio_v2_3.h" 51 #include "nv.h" 52 #include "navi10_ih.h" 53 #include "gfx_v10_0.h" 54 #include "sdma_v5_0.h" 55 #include "vcn_v2_0.h" 56 #include "jpeg_v2_0.h" 57 #include "dce_virtual.h" 58 #include "mes_v10_1.h" 59 #include "mxgpu_nv.h" 60 61 static const struct amd_ip_funcs nv_common_ip_funcs; 62 63 /* 64 * Indirect registers accessor 65 */ 66 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 67 { 68 unsigned long flags, address, data; 69 u32 r; 70 address = adev->nbio.funcs->get_pcie_index_offset(adev); 71 data = adev->nbio.funcs->get_pcie_data_offset(adev); 72 73 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 74 WREG32(address, reg); 75 (void)RREG32(address); 76 r = RREG32(data); 77 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 78 return r; 79 } 80 81 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 82 { 83 unsigned long flags, address, data; 84 85 address = adev->nbio.funcs->get_pcie_index_offset(adev); 86 data = adev->nbio.funcs->get_pcie_data_offset(adev); 87 88 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 89 WREG32(address, reg); 90 (void)RREG32(address); 91 WREG32(data, v); 92 (void)RREG32(data); 93 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 94 } 95 96 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 97 { 98 unsigned long flags, address, data; 99 u32 r; 100 101 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 102 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 103 104 spin_lock_irqsave(&adev->didt_idx_lock, flags); 105 WREG32(address, (reg)); 106 r = RREG32(data); 107 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 108 return r; 109 } 110 111 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 112 { 113 unsigned long flags, address, data; 114 115 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 116 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 117 118 spin_lock_irqsave(&adev->didt_idx_lock, flags); 119 WREG32(address, (reg)); 120 WREG32(data, (v)); 121 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 122 } 123 124 static u32 nv_get_config_memsize(struct amdgpu_device *adev) 125 { 126 return adev->nbio.funcs->get_memsize(adev); 127 } 128 129 static u32 nv_get_xclk(struct amdgpu_device *adev) 130 { 131 return adev->clock.spll.reference_freq; 132 } 133 134 135 void nv_grbm_select(struct amdgpu_device *adev, 136 u32 me, u32 pipe, u32 queue, u32 vmid) 137 { 138 u32 grbm_gfx_cntl = 0; 139 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 140 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 141 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 142 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 143 144 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); 145 } 146 147 static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 148 { 149 /* todo */ 150 } 151 152 static bool nv_read_disabled_bios(struct amdgpu_device *adev) 153 { 154 /* todo */ 155 return false; 156 } 157 158 static bool nv_read_bios_from_rom(struct amdgpu_device *adev, 159 u8 *bios, u32 length_bytes) 160 { 161 u32 *dw_ptr; 162 u32 i, length_dw; 163 164 if (bios == NULL) 165 return false; 166 if (length_bytes == 0) 167 return false; 168 /* APU vbios image is part of sbios image */ 169 if (adev->flags & AMD_IS_APU) 170 return false; 171 172 dw_ptr = (u32 *)bios; 173 length_dw = ALIGN(length_bytes, 4) / 4; 174 175 /* set rom index to 0 */ 176 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0); 177 /* read out the rom data */ 178 for (i = 0; i < length_dw; i++) 179 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA)); 180 181 return true; 182 } 183 184 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 185 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 186 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 187 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 188 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 189 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 190 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 191 #if 0 /* TODO: will set it when SDMA header is available */ 192 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 193 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 194 #endif 195 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 196 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 197 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 198 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 199 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 200 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 201 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 202 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 203 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 204 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 205 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 206 }; 207 208 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 209 u32 sh_num, u32 reg_offset) 210 { 211 uint32_t val; 212 213 mutex_lock(&adev->grbm_idx_mutex); 214 if (se_num != 0xffffffff || sh_num != 0xffffffff) 215 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 216 217 val = RREG32(reg_offset); 218 219 if (se_num != 0xffffffff || sh_num != 0xffffffff) 220 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 221 mutex_unlock(&adev->grbm_idx_mutex); 222 return val; 223 } 224 225 static uint32_t nv_get_register_value(struct amdgpu_device *adev, 226 bool indexed, u32 se_num, 227 u32 sh_num, u32 reg_offset) 228 { 229 if (indexed) { 230 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 231 } else { 232 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 233 return adev->gfx.config.gb_addr_config; 234 return RREG32(reg_offset); 235 } 236 } 237 238 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 239 u32 sh_num, u32 reg_offset, u32 *value) 240 { 241 uint32_t i; 242 struct soc15_allowed_register_entry *en; 243 244 *value = 0; 245 for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 246 en = &nv_allowed_read_registers[i]; 247 if (reg_offset != 248 (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) 249 continue; 250 251 *value = nv_get_register_value(adev, 252 nv_allowed_read_registers[i].grbm_indexed, 253 se_num, sh_num, reg_offset); 254 return 0; 255 } 256 return -EINVAL; 257 } 258 259 #if 0 260 static void nv_gpu_pci_config_reset(struct amdgpu_device *adev) 261 { 262 u32 i; 263 264 dev_info(adev->dev, "GPU pci config reset\n"); 265 266 /* disable BM */ 267 pci_clear_master(adev->pdev); 268 /* reset */ 269 amdgpu_pci_config_reset(adev); 270 271 udelay(100); 272 273 /* wait for asic to come out of reset */ 274 for (i = 0; i < adev->usec_timeout; i++) { 275 u32 memsize = nbio_v2_3_get_memsize(adev); 276 if (memsize != 0xffffffff) 277 break; 278 udelay(1); 279 } 280 281 } 282 #endif 283 284 static int nv_asic_mode1_reset(struct amdgpu_device *adev) 285 { 286 u32 i; 287 int ret = 0; 288 289 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 290 291 dev_info(adev->dev, "GPU mode1 reset\n"); 292 293 /* disable BM */ 294 pci_clear_master(adev->pdev); 295 296 pci_save_state(adev->pdev); 297 298 ret = psp_gpu_reset(adev); 299 if (ret) 300 dev_err(adev->dev, "GPU mode1 reset failed\n"); 301 302 pci_restore_state(adev->pdev); 303 304 /* wait for asic to come out of reset */ 305 for (i = 0; i < adev->usec_timeout; i++) { 306 u32 memsize = adev->nbio.funcs->get_memsize(adev); 307 308 if (memsize != 0xffffffff) 309 break; 310 udelay(1); 311 } 312 313 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 314 315 return ret; 316 } 317 318 static bool nv_asic_supports_baco(struct amdgpu_device *adev) 319 { 320 struct smu_context *smu = &adev->smu; 321 322 if (smu_baco_is_support(smu)) 323 return true; 324 else 325 return false; 326 } 327 328 static enum amd_reset_method 329 nv_asic_reset_method(struct amdgpu_device *adev) 330 { 331 struct smu_context *smu = &adev->smu; 332 333 if (!amdgpu_sriov_vf(adev) && smu_baco_is_support(smu)) 334 return AMD_RESET_METHOD_BACO; 335 else 336 return AMD_RESET_METHOD_MODE1; 337 } 338 339 static int nv_asic_reset(struct amdgpu_device *adev) 340 { 341 342 /* FIXME: it doesn't work since vega10 */ 343 #if 0 344 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 345 346 nv_gpu_pci_config_reset(adev); 347 348 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 349 #endif 350 int ret = 0; 351 struct smu_context *smu = &adev->smu; 352 353 if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { 354 if (!adev->in_suspend) 355 amdgpu_inc_vram_lost(adev); 356 ret = smu_baco_enter(smu); 357 if (ret) 358 return ret; 359 ret = smu_baco_exit(smu); 360 if (ret) 361 return ret; 362 } else { 363 if (!adev->in_suspend) 364 amdgpu_inc_vram_lost(adev); 365 ret = nv_asic_mode1_reset(adev); 366 } 367 368 return ret; 369 } 370 371 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 372 { 373 /* todo */ 374 return 0; 375 } 376 377 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 378 { 379 /* todo */ 380 return 0; 381 } 382 383 static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 384 { 385 if (pci_is_root_bus(adev->pdev->bus)) 386 return; 387 388 if (amdgpu_pcie_gen2 == 0) 389 return; 390 391 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 392 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 393 return; 394 395 /* todo */ 396 } 397 398 static void nv_program_aspm(struct amdgpu_device *adev) 399 { 400 401 if (amdgpu_aspm == 0) 402 return; 403 404 /* todo */ 405 } 406 407 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 408 bool enable) 409 { 410 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 411 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 412 } 413 414 static const struct amdgpu_ip_block_version nv_common_ip_block = 415 { 416 .type = AMD_IP_BLOCK_TYPE_COMMON, 417 .major = 1, 418 .minor = 0, 419 .rev = 0, 420 .funcs = &nv_common_ip_funcs, 421 }; 422 423 static int nv_reg_base_init(struct amdgpu_device *adev) 424 { 425 int r; 426 427 if (amdgpu_discovery) { 428 r = amdgpu_discovery_reg_base_init(adev); 429 if (r) { 430 DRM_WARN("failed to init reg base from ip discovery table, " 431 "fallback to legacy init method\n"); 432 goto legacy_init; 433 } 434 435 return 0; 436 } 437 438 legacy_init: 439 switch (adev->asic_type) { 440 case CHIP_NAVI10: 441 navi10_reg_base_init(adev); 442 break; 443 case CHIP_NAVI14: 444 navi14_reg_base_init(adev); 445 break; 446 case CHIP_NAVI12: 447 navi12_reg_base_init(adev); 448 break; 449 default: 450 return -EINVAL; 451 } 452 453 return 0; 454 } 455 456 int nv_set_ip_blocks(struct amdgpu_device *adev) 457 { 458 int r; 459 460 /* Set IP register base before any HW register access */ 461 r = nv_reg_base_init(adev); 462 if (r) 463 return r; 464 465 adev->nbio.funcs = &nbio_v2_3_funcs; 466 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 467 468 adev->nbio.funcs->detect_hw_virt(adev); 469 470 if (amdgpu_sriov_vf(adev)) 471 adev->virt.ops = &xgpu_nv_virt_ops; 472 473 switch (adev->asic_type) { 474 case CHIP_NAVI10: 475 case CHIP_NAVI14: 476 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 477 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 478 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 479 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 480 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 481 !amdgpu_sriov_vf(adev)) 482 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 483 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 484 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 485 #if defined(CONFIG_DRM_AMD_DC) 486 else if (amdgpu_device_has_dc_support(adev)) 487 amdgpu_device_ip_block_add(adev, &dm_ip_block); 488 #endif 489 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 490 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 491 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 492 !amdgpu_sriov_vf(adev)) 493 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 494 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 495 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 496 if (adev->enable_mes) 497 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 498 break; 499 case CHIP_NAVI12: 500 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 501 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 502 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 503 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 504 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 505 !amdgpu_sriov_vf(adev)) 506 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 507 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 508 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 509 #if defined(CONFIG_DRM_AMD_DC) 510 else if (amdgpu_device_has_dc_support(adev)) 511 amdgpu_device_ip_block_add(adev, &dm_ip_block); 512 #endif 513 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 514 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 515 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 516 !amdgpu_sriov_vf(adev)) 517 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 518 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 519 if (!amdgpu_sriov_vf(adev)) 520 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 521 break; 522 default: 523 return -EINVAL; 524 } 525 526 return 0; 527 } 528 529 static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 530 { 531 return adev->nbio.funcs->get_rev_id(adev); 532 } 533 534 static void nv_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 535 { 536 adev->nbio.funcs->hdp_flush(adev, ring); 537 } 538 539 static void nv_invalidate_hdp(struct amdgpu_device *adev, 540 struct amdgpu_ring *ring) 541 { 542 if (!ring || !ring->funcs->emit_wreg) { 543 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1); 544 } else { 545 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 546 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); 547 } 548 } 549 550 static bool nv_need_full_reset(struct amdgpu_device *adev) 551 { 552 return true; 553 } 554 555 static void nv_get_pcie_usage(struct amdgpu_device *adev, 556 uint64_t *count0, 557 uint64_t *count1) 558 { 559 /*TODO*/ 560 } 561 562 static bool nv_need_reset_on_init(struct amdgpu_device *adev) 563 { 564 #if 0 565 u32 sol_reg; 566 567 if (adev->flags & AMD_IS_APU) 568 return false; 569 570 /* Check sOS sign of life register to confirm sys driver and sOS 571 * are already been loaded. 572 */ 573 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 574 if (sol_reg) 575 return true; 576 #endif 577 /* TODO: re-enable it when mode1 reset is functional */ 578 return false; 579 } 580 581 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 582 { 583 584 /* TODO 585 * dummy implement for pcie_replay_count sysfs interface 586 * */ 587 588 return 0; 589 } 590 591 static void nv_init_doorbell_index(struct amdgpu_device *adev) 592 { 593 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 594 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 595 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 596 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 597 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 598 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 599 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 600 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 601 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 602 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 603 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 604 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 605 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 606 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 607 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 608 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 609 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 610 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 611 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 612 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 613 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 614 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 615 616 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 617 adev->doorbell_index.sdma_doorbell_range = 20; 618 } 619 620 static const struct amdgpu_asic_funcs nv_asic_funcs = 621 { 622 .read_disabled_bios = &nv_read_disabled_bios, 623 .read_bios_from_rom = &nv_read_bios_from_rom, 624 .read_register = &nv_read_register, 625 .reset = &nv_asic_reset, 626 .reset_method = &nv_asic_reset_method, 627 .set_vga_state = &nv_vga_set_state, 628 .get_xclk = &nv_get_xclk, 629 .set_uvd_clocks = &nv_set_uvd_clocks, 630 .set_vce_clocks = &nv_set_vce_clocks, 631 .get_config_memsize = &nv_get_config_memsize, 632 .flush_hdp = &nv_flush_hdp, 633 .invalidate_hdp = &nv_invalidate_hdp, 634 .init_doorbell_index = &nv_init_doorbell_index, 635 .need_full_reset = &nv_need_full_reset, 636 .get_pcie_usage = &nv_get_pcie_usage, 637 .need_reset_on_init = &nv_need_reset_on_init, 638 .get_pcie_replay_count = &nv_get_pcie_replay_count, 639 .supports_baco = &nv_asic_supports_baco, 640 }; 641 642 static int nv_common_early_init(void *handle) 643 { 644 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 645 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 646 647 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 648 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 649 adev->smc_rreg = NULL; 650 adev->smc_wreg = NULL; 651 adev->pcie_rreg = &nv_pcie_rreg; 652 adev->pcie_wreg = &nv_pcie_wreg; 653 654 /* TODO: will add them during VCN v2 implementation */ 655 adev->uvd_ctx_rreg = NULL; 656 adev->uvd_ctx_wreg = NULL; 657 658 adev->didt_rreg = &nv_didt_rreg; 659 adev->didt_wreg = &nv_didt_wreg; 660 661 adev->asic_funcs = &nv_asic_funcs; 662 663 adev->rev_id = nv_get_rev_id(adev); 664 adev->external_rev_id = 0xff; 665 switch (adev->asic_type) { 666 case CHIP_NAVI10: 667 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 668 AMD_CG_SUPPORT_GFX_CGCG | 669 AMD_CG_SUPPORT_IH_CG | 670 AMD_CG_SUPPORT_HDP_MGCG | 671 AMD_CG_SUPPORT_HDP_LS | 672 AMD_CG_SUPPORT_SDMA_MGCG | 673 AMD_CG_SUPPORT_SDMA_LS | 674 AMD_CG_SUPPORT_MC_MGCG | 675 AMD_CG_SUPPORT_MC_LS | 676 AMD_CG_SUPPORT_ATHUB_MGCG | 677 AMD_CG_SUPPORT_ATHUB_LS | 678 AMD_CG_SUPPORT_VCN_MGCG | 679 AMD_CG_SUPPORT_JPEG_MGCG | 680 AMD_CG_SUPPORT_BIF_MGCG | 681 AMD_CG_SUPPORT_BIF_LS; 682 adev->pg_flags = AMD_PG_SUPPORT_VCN | 683 AMD_PG_SUPPORT_VCN_DPG | 684 AMD_PG_SUPPORT_JPEG | 685 AMD_PG_SUPPORT_ATHUB; 686 adev->external_rev_id = adev->rev_id + 0x1; 687 break; 688 case CHIP_NAVI14: 689 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 690 AMD_CG_SUPPORT_GFX_CGCG | 691 AMD_CG_SUPPORT_IH_CG | 692 AMD_CG_SUPPORT_HDP_MGCG | 693 AMD_CG_SUPPORT_HDP_LS | 694 AMD_CG_SUPPORT_SDMA_MGCG | 695 AMD_CG_SUPPORT_SDMA_LS | 696 AMD_CG_SUPPORT_MC_MGCG | 697 AMD_CG_SUPPORT_MC_LS | 698 AMD_CG_SUPPORT_ATHUB_MGCG | 699 AMD_CG_SUPPORT_ATHUB_LS | 700 AMD_CG_SUPPORT_VCN_MGCG | 701 AMD_CG_SUPPORT_JPEG_MGCG | 702 AMD_CG_SUPPORT_BIF_MGCG | 703 AMD_CG_SUPPORT_BIF_LS; 704 adev->pg_flags = AMD_PG_SUPPORT_VCN | 705 AMD_PG_SUPPORT_JPEG | 706 AMD_PG_SUPPORT_VCN_DPG; 707 adev->external_rev_id = adev->rev_id + 20; 708 break; 709 case CHIP_NAVI12: 710 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 711 AMD_CG_SUPPORT_GFX_MGLS | 712 AMD_CG_SUPPORT_GFX_CGCG | 713 AMD_CG_SUPPORT_GFX_CP_LS | 714 AMD_CG_SUPPORT_GFX_RLC_LS | 715 AMD_CG_SUPPORT_IH_CG | 716 AMD_CG_SUPPORT_HDP_MGCG | 717 AMD_CG_SUPPORT_HDP_LS | 718 AMD_CG_SUPPORT_SDMA_MGCG | 719 AMD_CG_SUPPORT_SDMA_LS | 720 AMD_CG_SUPPORT_MC_MGCG | 721 AMD_CG_SUPPORT_MC_LS | 722 AMD_CG_SUPPORT_ATHUB_MGCG | 723 AMD_CG_SUPPORT_ATHUB_LS | 724 AMD_CG_SUPPORT_VCN_MGCG | 725 AMD_CG_SUPPORT_JPEG_MGCG; 726 adev->pg_flags = AMD_PG_SUPPORT_VCN | 727 AMD_PG_SUPPORT_VCN_DPG | 728 AMD_PG_SUPPORT_JPEG | 729 AMD_PG_SUPPORT_ATHUB; 730 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 731 * as a consequence, the rev_id and external_rev_id are wrong. 732 * workaround it by hardcoding rev_id to 0 (default value). 733 */ 734 if (amdgpu_sriov_vf(adev)) 735 adev->rev_id = 0; 736 adev->external_rev_id = adev->rev_id + 0xa; 737 break; 738 default: 739 /* FIXME: not supported yet */ 740 return -EINVAL; 741 } 742 743 if (amdgpu_sriov_vf(adev)) { 744 amdgpu_virt_init_setting(adev); 745 xgpu_nv_mailbox_set_irq_funcs(adev); 746 } 747 748 return 0; 749 } 750 751 static int nv_common_late_init(void *handle) 752 { 753 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 754 755 if (amdgpu_sriov_vf(adev)) 756 xgpu_nv_mailbox_get_irq(adev); 757 758 return 0; 759 } 760 761 static int nv_common_sw_init(void *handle) 762 { 763 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 764 765 if (amdgpu_sriov_vf(adev)) 766 xgpu_nv_mailbox_add_irq_id(adev); 767 768 return 0; 769 } 770 771 static int nv_common_sw_fini(void *handle) 772 { 773 return 0; 774 } 775 776 static int nv_common_hw_init(void *handle) 777 { 778 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 779 780 /* enable pcie gen2/3 link */ 781 nv_pcie_gen3_enable(adev); 782 /* enable aspm */ 783 nv_program_aspm(adev); 784 /* setup nbio registers */ 785 adev->nbio.funcs->init_registers(adev); 786 /* remap HDP registers to a hole in mmio space, 787 * for the purpose of expose those registers 788 * to process space 789 */ 790 if (adev->nbio.funcs->remap_hdp_registers) 791 adev->nbio.funcs->remap_hdp_registers(adev); 792 /* enable the doorbell aperture */ 793 nv_enable_doorbell_aperture(adev, true); 794 795 return 0; 796 } 797 798 static int nv_common_hw_fini(void *handle) 799 { 800 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 801 802 /* disable the doorbell aperture */ 803 nv_enable_doorbell_aperture(adev, false); 804 805 return 0; 806 } 807 808 static int nv_common_suspend(void *handle) 809 { 810 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 811 812 return nv_common_hw_fini(adev); 813 } 814 815 static int nv_common_resume(void *handle) 816 { 817 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 818 819 return nv_common_hw_init(adev); 820 } 821 822 static bool nv_common_is_idle(void *handle) 823 { 824 return true; 825 } 826 827 static int nv_common_wait_for_idle(void *handle) 828 { 829 return 0; 830 } 831 832 static int nv_common_soft_reset(void *handle) 833 { 834 return 0; 835 } 836 837 static void nv_update_hdp_mem_power_gating(struct amdgpu_device *adev, 838 bool enable) 839 { 840 uint32_t hdp_clk_cntl, hdp_clk_cntl1; 841 uint32_t hdp_mem_pwr_cntl; 842 843 if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | 844 AMD_CG_SUPPORT_HDP_DS | 845 AMD_CG_SUPPORT_HDP_SD))) 846 return; 847 848 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 849 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 850 851 /* Before doing clock/power mode switch, 852 * forced on IPH & RC clock */ 853 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 854 IPH_MEM_CLK_SOFT_OVERRIDE, 1); 855 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 856 RC_MEM_CLK_SOFT_OVERRIDE, 1); 857 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 858 859 /* HDP 5.0 doesn't support dynamic power mode switch, 860 * disable clock and power gating before any changing */ 861 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 862 IPH_MEM_POWER_CTRL_EN, 0); 863 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 864 IPH_MEM_POWER_LS_EN, 0); 865 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 866 IPH_MEM_POWER_DS_EN, 0); 867 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 868 IPH_MEM_POWER_SD_EN, 0); 869 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 870 RC_MEM_POWER_CTRL_EN, 0); 871 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 872 RC_MEM_POWER_LS_EN, 0); 873 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 874 RC_MEM_POWER_DS_EN, 0); 875 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 876 RC_MEM_POWER_SD_EN, 0); 877 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 878 879 /* only one clock gating mode (LS/DS/SD) can be enabled */ 880 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { 881 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 882 HDP_MEM_POWER_CTRL, 883 IPH_MEM_POWER_LS_EN, enable); 884 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 885 HDP_MEM_POWER_CTRL, 886 RC_MEM_POWER_LS_EN, enable); 887 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) { 888 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 889 HDP_MEM_POWER_CTRL, 890 IPH_MEM_POWER_DS_EN, enable); 891 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 892 HDP_MEM_POWER_CTRL, 893 RC_MEM_POWER_DS_EN, enable); 894 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) { 895 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 896 HDP_MEM_POWER_CTRL, 897 IPH_MEM_POWER_SD_EN, enable); 898 /* RC should not use shut down mode, fallback to ds */ 899 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 900 HDP_MEM_POWER_CTRL, 901 RC_MEM_POWER_DS_EN, enable); 902 } 903 904 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 905 906 /* restore IPH & RC clock override after clock/power mode changing */ 907 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl1); 908 } 909 910 static void nv_update_hdp_clock_gating(struct amdgpu_device *adev, 911 bool enable) 912 { 913 uint32_t hdp_clk_cntl; 914 915 if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 916 return; 917 918 hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 919 920 if (enable) { 921 hdp_clk_cntl &= 922 ~(uint32_t) 923 (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 924 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 925 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 926 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 927 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 928 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK); 929 } else { 930 hdp_clk_cntl |= HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 931 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 932 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 933 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 934 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 935 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK; 936 } 937 938 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 939 } 940 941 static int nv_common_set_clockgating_state(void *handle, 942 enum amd_clockgating_state state) 943 { 944 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 945 946 if (amdgpu_sriov_vf(adev)) 947 return 0; 948 949 switch (adev->asic_type) { 950 case CHIP_NAVI10: 951 case CHIP_NAVI14: 952 case CHIP_NAVI12: 953 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 954 state == AMD_CG_STATE_GATE); 955 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 956 state == AMD_CG_STATE_GATE); 957 nv_update_hdp_mem_power_gating(adev, 958 state == AMD_CG_STATE_GATE); 959 nv_update_hdp_clock_gating(adev, 960 state == AMD_CG_STATE_GATE); 961 break; 962 default: 963 break; 964 } 965 return 0; 966 } 967 968 static int nv_common_set_powergating_state(void *handle, 969 enum amd_powergating_state state) 970 { 971 /* TODO */ 972 return 0; 973 } 974 975 static void nv_common_get_clockgating_state(void *handle, u32 *flags) 976 { 977 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 978 uint32_t tmp; 979 980 if (amdgpu_sriov_vf(adev)) 981 *flags = 0; 982 983 adev->nbio.funcs->get_clockgating_state(adev, flags); 984 985 /* AMD_CG_SUPPORT_HDP_MGCG */ 986 tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 987 if (!(tmp & (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 988 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 989 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 990 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 991 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 992 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK))) 993 *flags |= AMD_CG_SUPPORT_HDP_MGCG; 994 995 /* AMD_CG_SUPPORT_HDP_LS/DS/SD */ 996 tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 997 if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK) 998 *flags |= AMD_CG_SUPPORT_HDP_LS; 999 else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK) 1000 *flags |= AMD_CG_SUPPORT_HDP_DS; 1001 else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK) 1002 *flags |= AMD_CG_SUPPORT_HDP_SD; 1003 1004 return; 1005 } 1006 1007 static const struct amd_ip_funcs nv_common_ip_funcs = { 1008 .name = "nv_common", 1009 .early_init = nv_common_early_init, 1010 .late_init = nv_common_late_init, 1011 .sw_init = nv_common_sw_init, 1012 .sw_fini = nv_common_sw_fini, 1013 .hw_init = nv_common_hw_init, 1014 .hw_fini = nv_common_hw_fini, 1015 .suspend = nv_common_suspend, 1016 .resume = nv_common_resume, 1017 .is_idle = nv_common_is_idle, 1018 .wait_for_idle = nv_common_wait_for_idle, 1019 .soft_reset = nv_common_soft_reset, 1020 .set_clockgating_state = nv_common_set_clockgating_state, 1021 .set_powergating_state = nv_common_set_powergating_state, 1022 .get_clockgating_state = nv_common_get_clockgating_state, 1023 }; 1024