1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/pm_runtime.h> 8 #include <linux/soc/mediatek/mtk-cmdq.h> 9 #include <linux/soc/mediatek/mtk-mmsys.h> 10 11 #include <asm/barrier.h> 12 #include <soc/mediatek/smi.h> 13 14 #include <drm/drm_atomic_helper.h> 15 #include <drm/drm_plane_helper.h> 16 #include <drm/drm_probe_helper.h> 17 #include <drm/drm_vblank.h> 18 19 #include "mtk_drm_drv.h" 20 #include "mtk_drm_crtc.h" 21 #include "mtk_drm_ddp.h" 22 #include "mtk_drm_ddp_comp.h" 23 #include "mtk_drm_gem.h" 24 #include "mtk_drm_plane.h" 25 26 /** 27 * struct mtk_drm_crtc - MediaTek specific crtc structure. 28 * @base: crtc object. 29 * @enabled: records whether crtc_enable succeeded 30 * @planes: array of 4 drm_plane structures, one for each overlay plane 31 * @pending_planes: whether any plane has pending changes to be applied 32 * @mmsys_dev: pointer to the mmsys device for configuration registers 33 * @mutex: handle to one of the ten disp_mutex streams 34 * @ddp_comp_nr: number of components in ddp_comp 35 * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc 36 */ 37 struct mtk_drm_crtc { 38 struct drm_crtc base; 39 bool enabled; 40 41 bool pending_needs_vblank; 42 struct drm_pending_vblank_event *event; 43 44 struct drm_plane *planes; 45 unsigned int layer_nr; 46 bool pending_planes; 47 bool pending_async_planes; 48 49 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 50 struct cmdq_client *cmdq_client; 51 u32 cmdq_event; 52 #endif 53 54 struct device *mmsys_dev; 55 struct mtk_disp_mutex *mutex; 56 unsigned int ddp_comp_nr; 57 struct mtk_ddp_comp **ddp_comp; 58 59 /* lock for display hardware access */ 60 struct mutex hw_lock; 61 }; 62 63 struct mtk_crtc_state { 64 struct drm_crtc_state base; 65 66 bool pending_config; 67 unsigned int pending_width; 68 unsigned int pending_height; 69 unsigned int pending_vrefresh; 70 }; 71 72 static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c) 73 { 74 return container_of(c, struct mtk_drm_crtc, base); 75 } 76 77 static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s) 78 { 79 return container_of(s, struct mtk_crtc_state, base); 80 } 81 82 static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 83 { 84 struct drm_crtc *crtc = &mtk_crtc->base; 85 unsigned long flags; 86 87 spin_lock_irqsave(&crtc->dev->event_lock, flags); 88 drm_crtc_send_vblank_event(crtc, mtk_crtc->event); 89 drm_crtc_vblank_put(crtc); 90 mtk_crtc->event = NULL; 91 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 92 } 93 94 static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 95 { 96 drm_crtc_handle_vblank(&mtk_crtc->base); 97 if (mtk_crtc->pending_needs_vblank) { 98 mtk_drm_crtc_finish_page_flip(mtk_crtc); 99 mtk_crtc->pending_needs_vblank = false; 100 } 101 } 102 103 static void mtk_drm_crtc_destroy(struct drm_crtc *crtc) 104 { 105 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 106 107 mtk_disp_mutex_put(mtk_crtc->mutex); 108 109 drm_crtc_cleanup(crtc); 110 } 111 112 static void mtk_drm_crtc_reset(struct drm_crtc *crtc) 113 { 114 struct mtk_crtc_state *state; 115 116 if (crtc->state) { 117 __drm_atomic_helper_crtc_destroy_state(crtc->state); 118 119 state = to_mtk_crtc_state(crtc->state); 120 memset(state, 0, sizeof(*state)); 121 } else { 122 state = kzalloc(sizeof(*state), GFP_KERNEL); 123 if (!state) 124 return; 125 crtc->state = &state->base; 126 } 127 128 state->base.crtc = crtc; 129 } 130 131 static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc) 132 { 133 struct mtk_crtc_state *state; 134 135 state = kzalloc(sizeof(*state), GFP_KERNEL); 136 if (!state) 137 return NULL; 138 139 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 140 141 WARN_ON(state->base.crtc != crtc); 142 state->base.crtc = crtc; 143 144 return &state->base; 145 } 146 147 static void mtk_drm_crtc_destroy_state(struct drm_crtc *crtc, 148 struct drm_crtc_state *state) 149 { 150 __drm_atomic_helper_crtc_destroy_state(state); 151 kfree(to_mtk_crtc_state(state)); 152 } 153 154 static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc, 155 const struct drm_display_mode *mode, 156 struct drm_display_mode *adjusted_mode) 157 { 158 /* Nothing to do here, but this callback is mandatory. */ 159 return true; 160 } 161 162 static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) 163 { 164 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state); 165 166 state->pending_width = crtc->mode.hdisplay; 167 state->pending_height = crtc->mode.vdisplay; 168 state->pending_vrefresh = crtc->mode.vrefresh; 169 wmb(); /* Make sure the above parameters are set before update */ 170 state->pending_config = true; 171 } 172 173 static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc) 174 { 175 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 176 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 177 178 mtk_ddp_comp_enable_vblank(comp, &mtk_crtc->base); 179 180 return 0; 181 } 182 183 static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc) 184 { 185 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 186 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 187 188 mtk_ddp_comp_disable_vblank(comp); 189 } 190 191 static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc) 192 { 193 int ret; 194 int i; 195 196 DRM_DEBUG_DRIVER("%s\n", __func__); 197 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 198 ret = clk_prepare_enable(mtk_crtc->ddp_comp[i]->clk); 199 if (ret) { 200 DRM_ERROR("Failed to enable clock %d: %d\n", i, ret); 201 goto err; 202 } 203 } 204 205 return 0; 206 err: 207 while (--i >= 0) 208 clk_disable_unprepare(mtk_crtc->ddp_comp[i]->clk); 209 return ret; 210 } 211 212 static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc) 213 { 214 int i; 215 216 DRM_DEBUG_DRIVER("%s\n", __func__); 217 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 218 clk_disable_unprepare(mtk_crtc->ddp_comp[i]->clk); 219 } 220 221 static 222 struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc, 223 struct drm_plane *plane, 224 unsigned int *local_layer) 225 { 226 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 227 struct mtk_ddp_comp *comp; 228 int i, count = 0; 229 unsigned int local_index = plane - mtk_crtc->planes; 230 231 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 232 comp = mtk_crtc->ddp_comp[i]; 233 if (local_index < (count + mtk_ddp_comp_layer_nr(comp))) { 234 *local_layer = local_index - count; 235 return comp; 236 } 237 count += mtk_ddp_comp_layer_nr(comp); 238 } 239 240 WARN(1, "Failed to find component for plane %d\n", plane->index); 241 return NULL; 242 } 243 244 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 245 static void ddp_cmdq_cb(struct cmdq_cb_data data) 246 { 247 cmdq_pkt_destroy(data.data); 248 } 249 #endif 250 251 static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) 252 { 253 struct drm_crtc *crtc = &mtk_crtc->base; 254 struct drm_connector *connector; 255 struct drm_encoder *encoder; 256 struct drm_connector_list_iter conn_iter; 257 unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC; 258 int ret; 259 int i; 260 261 DRM_DEBUG_DRIVER("%s\n", __func__); 262 if (WARN_ON(!crtc->state)) 263 return -EINVAL; 264 265 width = crtc->state->adjusted_mode.hdisplay; 266 height = crtc->state->adjusted_mode.vdisplay; 267 vrefresh = crtc->state->adjusted_mode.vrefresh; 268 269 drm_for_each_encoder(encoder, crtc->dev) { 270 if (encoder->crtc != crtc) 271 continue; 272 273 drm_connector_list_iter_begin(crtc->dev, &conn_iter); 274 drm_for_each_connector_iter(connector, &conn_iter) { 275 if (connector->encoder != encoder) 276 continue; 277 if (connector->display_info.bpc != 0 && 278 bpc > connector->display_info.bpc) 279 bpc = connector->display_info.bpc; 280 } 281 drm_connector_list_iter_end(&conn_iter); 282 } 283 284 ret = pm_runtime_get_sync(crtc->dev->dev); 285 if (ret < 0) { 286 DRM_ERROR("Failed to enable power domain: %d\n", ret); 287 return ret; 288 } 289 290 ret = mtk_disp_mutex_prepare(mtk_crtc->mutex); 291 if (ret < 0) { 292 DRM_ERROR("Failed to enable mutex clock: %d\n", ret); 293 goto err_pm_runtime_put; 294 } 295 296 ret = mtk_crtc_ddp_clk_enable(mtk_crtc); 297 if (ret < 0) { 298 DRM_ERROR("Failed to enable component clocks: %d\n", ret); 299 goto err_mutex_unprepare; 300 } 301 302 DRM_DEBUG_DRIVER("mediatek_ddp_ddp_path_setup\n"); 303 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 304 mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev, 305 mtk_crtc->ddp_comp[i]->id, 306 mtk_crtc->ddp_comp[i + 1]->id); 307 mtk_disp_mutex_add_comp(mtk_crtc->mutex, 308 mtk_crtc->ddp_comp[i]->id); 309 } 310 mtk_disp_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 311 mtk_disp_mutex_enable(mtk_crtc->mutex); 312 313 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 314 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i]; 315 316 if (i == 1) 317 mtk_ddp_comp_bgclr_in_on(comp); 318 319 mtk_ddp_comp_config(comp, width, height, vrefresh, bpc, NULL); 320 mtk_ddp_comp_start(comp); 321 } 322 323 /* Initially configure all planes */ 324 for (i = 0; i < mtk_crtc->layer_nr; i++) { 325 struct drm_plane *plane = &mtk_crtc->planes[i]; 326 struct mtk_plane_state *plane_state; 327 struct mtk_ddp_comp *comp; 328 unsigned int local_layer; 329 330 plane_state = to_mtk_plane_state(plane->state); 331 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer); 332 if (comp) 333 mtk_ddp_comp_layer_config(comp, local_layer, 334 plane_state, NULL); 335 } 336 337 return 0; 338 339 err_mutex_unprepare: 340 mtk_disp_mutex_unprepare(mtk_crtc->mutex); 341 err_pm_runtime_put: 342 pm_runtime_put(crtc->dev->dev); 343 return ret; 344 } 345 346 static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) 347 { 348 struct drm_device *drm = mtk_crtc->base.dev; 349 struct drm_crtc *crtc = &mtk_crtc->base; 350 int i; 351 352 DRM_DEBUG_DRIVER("%s\n", __func__); 353 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 354 mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]); 355 if (i == 1) 356 mtk_ddp_comp_bgclr_in_off(mtk_crtc->ddp_comp[i]); 357 } 358 359 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 360 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, 361 mtk_crtc->ddp_comp[i]->id); 362 mtk_disp_mutex_disable(mtk_crtc->mutex); 363 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 364 mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev, 365 mtk_crtc->ddp_comp[i]->id, 366 mtk_crtc->ddp_comp[i + 1]->id); 367 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, 368 mtk_crtc->ddp_comp[i]->id); 369 } 370 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 371 mtk_crtc_ddp_clk_disable(mtk_crtc); 372 mtk_disp_mutex_unprepare(mtk_crtc->mutex); 373 374 pm_runtime_put(drm->dev); 375 376 if (crtc->state->event && !crtc->state->active) { 377 spin_lock_irq(&crtc->dev->event_lock); 378 drm_crtc_send_vblank_event(crtc, crtc->state->event); 379 crtc->state->event = NULL; 380 spin_unlock_irq(&crtc->dev->event_lock); 381 } 382 } 383 384 static void mtk_crtc_ddp_config(struct drm_crtc *crtc, 385 struct cmdq_pkt *cmdq_handle) 386 { 387 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 388 struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state); 389 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 390 unsigned int i; 391 unsigned int local_layer; 392 393 /* 394 * TODO: instead of updating the registers here, we should prepare 395 * working registers in atomic_commit and let the hardware command 396 * queue update module registers on vblank. 397 */ 398 if (state->pending_config) { 399 mtk_ddp_comp_config(comp, state->pending_width, 400 state->pending_height, 401 state->pending_vrefresh, 0, 402 cmdq_handle); 403 404 state->pending_config = false; 405 } 406 407 if (mtk_crtc->pending_planes) { 408 for (i = 0; i < mtk_crtc->layer_nr; i++) { 409 struct drm_plane *plane = &mtk_crtc->planes[i]; 410 struct mtk_plane_state *plane_state; 411 412 plane_state = to_mtk_plane_state(plane->state); 413 414 if (!plane_state->pending.config) 415 continue; 416 417 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, 418 &local_layer); 419 420 if (comp) 421 mtk_ddp_comp_layer_config(comp, local_layer, 422 plane_state, 423 cmdq_handle); 424 plane_state->pending.config = false; 425 } 426 mtk_crtc->pending_planes = false; 427 } 428 429 if (mtk_crtc->pending_async_planes) { 430 for (i = 0; i < mtk_crtc->layer_nr; i++) { 431 struct drm_plane *plane = &mtk_crtc->planes[i]; 432 struct mtk_plane_state *plane_state; 433 434 plane_state = to_mtk_plane_state(plane->state); 435 436 if (!plane_state->pending.async_config) 437 continue; 438 439 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, 440 &local_layer); 441 442 if (comp) 443 mtk_ddp_comp_layer_config(comp, local_layer, 444 plane_state, 445 cmdq_handle); 446 plane_state->pending.async_config = false; 447 } 448 mtk_crtc->pending_async_planes = false; 449 } 450 } 451 452 static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc) 453 { 454 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 455 struct cmdq_pkt *cmdq_handle; 456 #endif 457 struct drm_crtc *crtc = &mtk_crtc->base; 458 struct mtk_drm_private *priv = crtc->dev->dev_private; 459 unsigned int pending_planes = 0, pending_async_planes = 0; 460 int i; 461 462 mutex_lock(&mtk_crtc->hw_lock); 463 for (i = 0; i < mtk_crtc->layer_nr; i++) { 464 struct drm_plane *plane = &mtk_crtc->planes[i]; 465 struct mtk_plane_state *plane_state; 466 467 plane_state = to_mtk_plane_state(plane->state); 468 if (plane_state->pending.dirty) { 469 plane_state->pending.config = true; 470 plane_state->pending.dirty = false; 471 pending_planes |= BIT(i); 472 } else if (plane_state->pending.async_dirty) { 473 plane_state->pending.async_config = true; 474 plane_state->pending.async_dirty = false; 475 pending_async_planes |= BIT(i); 476 } 477 } 478 if (pending_planes) 479 mtk_crtc->pending_planes = true; 480 if (pending_async_planes) 481 mtk_crtc->pending_async_planes = true; 482 483 if (priv->data->shadow_register) { 484 mtk_disp_mutex_acquire(mtk_crtc->mutex); 485 mtk_crtc_ddp_config(crtc, NULL); 486 mtk_disp_mutex_release(mtk_crtc->mutex); 487 } 488 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 489 if (mtk_crtc->cmdq_client) { 490 mbox_flush(mtk_crtc->cmdq_client->chan, 2000); 491 cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE); 492 cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event); 493 cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event); 494 mtk_crtc_ddp_config(crtc, cmdq_handle); 495 cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cmdq_handle); 496 } 497 #endif 498 mutex_unlock(&mtk_crtc->hw_lock); 499 } 500 501 int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane, 502 struct mtk_plane_state *state) 503 { 504 unsigned int local_layer; 505 struct mtk_ddp_comp *comp; 506 507 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer); 508 if (comp) 509 return mtk_ddp_comp_layer_check(comp, local_layer, state); 510 return 0; 511 } 512 513 void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane, 514 struct drm_plane_state *new_state) 515 { 516 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 517 const struct drm_plane_helper_funcs *plane_helper_funcs = 518 plane->helper_private; 519 520 if (!mtk_crtc->enabled) 521 return; 522 523 plane_helper_funcs->atomic_update(plane, new_state); 524 mtk_drm_crtc_hw_config(mtk_crtc); 525 } 526 527 static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc, 528 struct drm_crtc_state *old_state) 529 { 530 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 531 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 532 int ret; 533 534 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 535 536 ret = mtk_smi_larb_get(comp->larb_dev); 537 if (ret) { 538 DRM_ERROR("Failed to get larb: %d\n", ret); 539 return; 540 } 541 542 ret = mtk_crtc_ddp_hw_init(mtk_crtc); 543 if (ret) { 544 mtk_smi_larb_put(comp->larb_dev); 545 return; 546 } 547 548 drm_crtc_vblank_on(crtc); 549 mtk_crtc->enabled = true; 550 } 551 552 static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc, 553 struct drm_crtc_state *old_state) 554 { 555 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 556 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 557 int i; 558 559 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 560 if (!mtk_crtc->enabled) 561 return; 562 563 /* Set all pending plane state to disabled */ 564 for (i = 0; i < mtk_crtc->layer_nr; i++) { 565 struct drm_plane *plane = &mtk_crtc->planes[i]; 566 struct mtk_plane_state *plane_state; 567 568 plane_state = to_mtk_plane_state(plane->state); 569 plane_state->pending.enable = false; 570 plane_state->pending.config = true; 571 } 572 mtk_crtc->pending_planes = true; 573 574 mtk_drm_crtc_hw_config(mtk_crtc); 575 /* Wait for planes to be disabled */ 576 drm_crtc_wait_one_vblank(crtc); 577 578 drm_crtc_vblank_off(crtc); 579 mtk_crtc_ddp_hw_fini(mtk_crtc); 580 mtk_smi_larb_put(comp->larb_dev); 581 582 mtk_crtc->enabled = false; 583 } 584 585 static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc, 586 struct drm_crtc_state *old_crtc_state) 587 { 588 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state); 589 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 590 591 if (mtk_crtc->event && state->base.event) 592 DRM_ERROR("new event while there is still a pending event\n"); 593 594 if (state->base.event) { 595 state->base.event->pipe = drm_crtc_index(crtc); 596 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 597 mtk_crtc->event = state->base.event; 598 state->base.event = NULL; 599 } 600 } 601 602 static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc, 603 struct drm_crtc_state *old_crtc_state) 604 { 605 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 606 int i; 607 608 if (mtk_crtc->event) 609 mtk_crtc->pending_needs_vblank = true; 610 if (crtc->state->color_mgmt_changed) 611 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 612 mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state); 613 mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state); 614 } 615 mtk_drm_crtc_hw_config(mtk_crtc); 616 } 617 618 static const struct drm_crtc_funcs mtk_crtc_funcs = { 619 .set_config = drm_atomic_helper_set_config, 620 .page_flip = drm_atomic_helper_page_flip, 621 .destroy = mtk_drm_crtc_destroy, 622 .reset = mtk_drm_crtc_reset, 623 .atomic_duplicate_state = mtk_drm_crtc_duplicate_state, 624 .atomic_destroy_state = mtk_drm_crtc_destroy_state, 625 .gamma_set = drm_atomic_helper_legacy_gamma_set, 626 .enable_vblank = mtk_drm_crtc_enable_vblank, 627 .disable_vblank = mtk_drm_crtc_disable_vblank, 628 }; 629 630 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = { 631 .mode_fixup = mtk_drm_crtc_mode_fixup, 632 .mode_set_nofb = mtk_drm_crtc_mode_set_nofb, 633 .atomic_begin = mtk_drm_crtc_atomic_begin, 634 .atomic_flush = mtk_drm_crtc_atomic_flush, 635 .atomic_enable = mtk_drm_crtc_atomic_enable, 636 .atomic_disable = mtk_drm_crtc_atomic_disable, 637 }; 638 639 static int mtk_drm_crtc_init(struct drm_device *drm, 640 struct mtk_drm_crtc *mtk_crtc, 641 unsigned int pipe) 642 { 643 struct drm_plane *primary = NULL; 644 struct drm_plane *cursor = NULL; 645 int i, ret; 646 647 for (i = 0; i < mtk_crtc->layer_nr; i++) { 648 if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_PRIMARY) 649 primary = &mtk_crtc->planes[i]; 650 else if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_CURSOR) 651 cursor = &mtk_crtc->planes[i]; 652 } 653 654 ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor, 655 &mtk_crtc_funcs, NULL); 656 if (ret) 657 goto err_cleanup_crtc; 658 659 drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs); 660 661 return 0; 662 663 err_cleanup_crtc: 664 drm_crtc_cleanup(&mtk_crtc->base); 665 return ret; 666 } 667 668 void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp) 669 { 670 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 671 struct mtk_drm_private *priv = crtc->dev->dev_private; 672 673 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 674 if (!priv->data->shadow_register && !mtk_crtc->cmdq_client) 675 #else 676 if (!priv->data->shadow_register) 677 #endif 678 mtk_crtc_ddp_config(crtc, NULL); 679 680 mtk_drm_finish_page_flip(mtk_crtc); 681 } 682 683 static int mtk_drm_crtc_num_comp_planes(struct mtk_drm_crtc *mtk_crtc, 684 int comp_idx) 685 { 686 struct mtk_ddp_comp *comp; 687 688 if (comp_idx > 1) 689 return 0; 690 691 comp = mtk_crtc->ddp_comp[comp_idx]; 692 if (!comp->funcs) 693 return 0; 694 695 if (comp_idx == 1 && !comp->funcs->bgclr_in_on) 696 return 0; 697 698 return mtk_ddp_comp_layer_nr(comp); 699 } 700 701 static inline 702 enum drm_plane_type mtk_drm_crtc_plane_type(unsigned int plane_idx, 703 unsigned int num_planes) 704 { 705 if (plane_idx == 0) 706 return DRM_PLANE_TYPE_PRIMARY; 707 else if (plane_idx == (num_planes - 1)) 708 return DRM_PLANE_TYPE_CURSOR; 709 else 710 return DRM_PLANE_TYPE_OVERLAY; 711 712 } 713 714 static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev, 715 struct mtk_drm_crtc *mtk_crtc, 716 int comp_idx, int pipe) 717 { 718 int num_planes = mtk_drm_crtc_num_comp_planes(mtk_crtc, comp_idx); 719 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[comp_idx]; 720 int i, ret; 721 722 for (i = 0; i < num_planes; i++) { 723 ret = mtk_plane_init(drm_dev, 724 &mtk_crtc->planes[mtk_crtc->layer_nr], 725 BIT(pipe), 726 mtk_drm_crtc_plane_type(mtk_crtc->layer_nr, 727 num_planes), 728 mtk_ddp_comp_supported_rotations(comp)); 729 if (ret) 730 return ret; 731 732 mtk_crtc->layer_nr++; 733 } 734 return 0; 735 } 736 737 int mtk_drm_crtc_create(struct drm_device *drm_dev, 738 const enum mtk_ddp_comp_id *path, unsigned int path_len) 739 { 740 struct mtk_drm_private *priv = drm_dev->dev_private; 741 struct device *dev = drm_dev->dev; 742 struct mtk_drm_crtc *mtk_crtc; 743 unsigned int num_comp_planes = 0; 744 int pipe = priv->num_pipes; 745 int ret; 746 int i; 747 bool has_ctm = false; 748 uint gamma_lut_size = 0; 749 750 if (!path) 751 return 0; 752 753 for (i = 0; i < path_len; i++) { 754 enum mtk_ddp_comp_id comp_id = path[i]; 755 struct device_node *node; 756 757 node = priv->comp_node[comp_id]; 758 if (!node) { 759 dev_info(dev, 760 "Not creating crtc %d because component %d is disabled or missing\n", 761 pipe, comp_id); 762 return 0; 763 } 764 } 765 766 mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL); 767 if (!mtk_crtc) 768 return -ENOMEM; 769 770 mtk_crtc->mmsys_dev = priv->mmsys_dev; 771 mtk_crtc->ddp_comp_nr = path_len; 772 mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr, 773 sizeof(*mtk_crtc->ddp_comp), 774 GFP_KERNEL); 775 if (!mtk_crtc->ddp_comp) 776 return -ENOMEM; 777 778 mtk_crtc->mutex = mtk_disp_mutex_get(priv->mutex_dev, pipe); 779 if (IS_ERR(mtk_crtc->mutex)) { 780 ret = PTR_ERR(mtk_crtc->mutex); 781 dev_err(dev, "Failed to get mutex: %d\n", ret); 782 return ret; 783 } 784 785 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 786 enum mtk_ddp_comp_id comp_id = path[i]; 787 struct mtk_ddp_comp *comp; 788 struct device_node *node; 789 790 node = priv->comp_node[comp_id]; 791 comp = priv->ddp_comp[comp_id]; 792 if (!comp) { 793 dev_err(dev, "Component %pOF not initialized\n", node); 794 ret = -ENODEV; 795 return ret; 796 } 797 798 mtk_crtc->ddp_comp[i] = comp; 799 800 if (comp->funcs) { 801 if (comp->funcs->gamma_set) 802 gamma_lut_size = MTK_LUT_SIZE; 803 804 if (comp->funcs->ctm_set) 805 has_ctm = true; 806 } 807 } 808 809 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 810 num_comp_planes += mtk_drm_crtc_num_comp_planes(mtk_crtc, i); 811 812 mtk_crtc->planes = devm_kcalloc(dev, num_comp_planes, 813 sizeof(struct drm_plane), GFP_KERNEL); 814 815 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 816 ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i, 817 pipe); 818 if (ret) 819 return ret; 820 } 821 822 ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe); 823 if (ret < 0) 824 return ret; 825 826 if (gamma_lut_size) 827 drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size); 828 drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size); 829 priv->num_pipes++; 830 mutex_init(&mtk_crtc->hw_lock); 831 832 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 833 mtk_crtc->cmdq_client = 834 cmdq_mbox_create(dev, drm_crtc_index(&mtk_crtc->base), 835 2000); 836 if (IS_ERR(mtk_crtc->cmdq_client)) { 837 dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n", 838 drm_crtc_index(&mtk_crtc->base)); 839 mtk_crtc->cmdq_client = NULL; 840 } 841 ret = of_property_read_u32_index(priv->mutex_node, 842 "mediatek,gce-events", 843 drm_crtc_index(&mtk_crtc->base), 844 &mtk_crtc->cmdq_event); 845 if (ret) 846 dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n", 847 drm_crtc_index(&mtk_crtc->base)); 848 #endif 849 return 0; 850 } 851