1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <drm/drm_atomic_helper.h> 25 26 #include "display/intel_dp.h" 27 28 #include "i915_drv.h" 29 #include "intel_atomic.h" 30 #include "intel_display_types.h" 31 #include "intel_psr.h" 32 #include "intel_sprite.h" 33 #include "intel_hdmi.h" 34 35 /** 36 * DOC: Panel Self Refresh (PSR/SRD) 37 * 38 * Since Haswell Display controller supports Panel Self-Refresh on display 39 * panels witch have a remote frame buffer (RFB) implemented according to PSR 40 * spec in eDP1.3. PSR feature allows the display to go to lower standby states 41 * when system is idle but display is on as it eliminates display refresh 42 * request to DDR memory completely as long as the frame buffer for that 43 * display is unchanged. 44 * 45 * Panel Self Refresh must be supported by both Hardware (source) and 46 * Panel (sink). 47 * 48 * PSR saves power by caching the framebuffer in the panel RFB, which allows us 49 * to power down the link and memory controller. For DSI panels the same idea 50 * is called "manual mode". 51 * 52 * The implementation uses the hardware-based PSR support which automatically 53 * enters/exits self-refresh mode. The hardware takes care of sending the 54 * required DP aux message and could even retrain the link (that part isn't 55 * enabled yet though). The hardware also keeps track of any frontbuffer 56 * changes to know when to exit self-refresh mode again. Unfortunately that 57 * part doesn't work too well, hence why the i915 PSR support uses the 58 * software frontbuffer tracking to make sure it doesn't miss a screen 59 * update. For this integration intel_psr_invalidate() and intel_psr_flush() 60 * get called by the frontbuffer tracking code. Note that because of locking 61 * issues the self-refresh re-enable code is done from a work queue, which 62 * must be correctly synchronized/cancelled when shutting down the pipe." 63 * 64 * DC3CO (DC3 clock off) 65 * 66 * On top of PSR2, GEN12 adds a intermediate power savings state that turns 67 * clock off automatically during PSR2 idle state. 68 * The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep 69 * entry/exit allows the HW to enter a low-power state even when page flipping 70 * periodically (for instance a 30fps video playback scenario). 71 * 72 * Every time a flips occurs PSR2 will get out of deep sleep state(if it was), 73 * so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6 74 * frames, if no other flip occurs and the function above is executed, DC3CO is 75 * disabled and PSR2 is configured to enter deep sleep, resetting again in case 76 * of another flip. 77 * Front buffer modifications do not trigger DC3CO activation on purpose as it 78 * would bring a lot of complexity and most of the moderns systems will only 79 * use page flips. 80 */ 81 82 static bool psr_global_enabled(struct drm_i915_private *i915) 83 { 84 switch (i915->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 85 case I915_PSR_DEBUG_DEFAULT: 86 return i915_modparams.enable_psr; 87 case I915_PSR_DEBUG_DISABLE: 88 return false; 89 default: 90 return true; 91 } 92 } 93 94 static bool intel_psr2_enabled(struct drm_i915_private *dev_priv, 95 const struct intel_crtc_state *crtc_state) 96 { 97 /* Cannot enable DSC and PSR2 simultaneously */ 98 drm_WARN_ON(&dev_priv->drm, crtc_state->dsc.compression_enable && 99 crtc_state->has_psr2); 100 101 switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 102 case I915_PSR_DEBUG_DISABLE: 103 case I915_PSR_DEBUG_FORCE_PSR1: 104 return false; 105 default: 106 return crtc_state->has_psr2; 107 } 108 } 109 110 static void psr_irq_control(struct drm_i915_private *dev_priv) 111 { 112 enum transcoder trans_shift; 113 u32 mask, val; 114 i915_reg_t imr_reg; 115 116 /* 117 * gen12+ has registers relative to transcoder and one per transcoder 118 * using the same bit definition: handle it as TRANSCODER_EDP to force 119 * 0 shift in bit definition 120 */ 121 if (INTEL_GEN(dev_priv) >= 12) { 122 trans_shift = 0; 123 imr_reg = TRANS_PSR_IMR(dev_priv->psr.transcoder); 124 } else { 125 trans_shift = dev_priv->psr.transcoder; 126 imr_reg = EDP_PSR_IMR; 127 } 128 129 mask = EDP_PSR_ERROR(trans_shift); 130 if (dev_priv->psr.debug & I915_PSR_DEBUG_IRQ) 131 mask |= EDP_PSR_POST_EXIT(trans_shift) | 132 EDP_PSR_PRE_ENTRY(trans_shift); 133 134 /* Warning: it is masking/setting reserved bits too */ 135 val = intel_de_read(dev_priv, imr_reg); 136 val &= ~EDP_PSR_TRANS_MASK(trans_shift); 137 val |= ~mask; 138 intel_de_write(dev_priv, imr_reg, val); 139 } 140 141 static void psr_event_print(struct drm_i915_private *i915, 142 u32 val, bool psr2_enabled) 143 { 144 drm_dbg_kms(&i915->drm, "PSR exit events: 0x%x\n", val); 145 if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE) 146 drm_dbg_kms(&i915->drm, "\tPSR2 watchdog timer expired\n"); 147 if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled) 148 drm_dbg_kms(&i915->drm, "\tPSR2 disabled\n"); 149 if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN) 150 drm_dbg_kms(&i915->drm, "\tSU dirty FIFO underrun\n"); 151 if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN) 152 drm_dbg_kms(&i915->drm, "\tSU CRC FIFO underrun\n"); 153 if (val & PSR_EVENT_GRAPHICS_RESET) 154 drm_dbg_kms(&i915->drm, "\tGraphics reset\n"); 155 if (val & PSR_EVENT_PCH_INTERRUPT) 156 drm_dbg_kms(&i915->drm, "\tPCH interrupt\n"); 157 if (val & PSR_EVENT_MEMORY_UP) 158 drm_dbg_kms(&i915->drm, "\tMemory up\n"); 159 if (val & PSR_EVENT_FRONT_BUFFER_MODIFY) 160 drm_dbg_kms(&i915->drm, "\tFront buffer modification\n"); 161 if (val & PSR_EVENT_WD_TIMER_EXPIRE) 162 drm_dbg_kms(&i915->drm, "\tPSR watchdog timer expired\n"); 163 if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE) 164 drm_dbg_kms(&i915->drm, "\tPIPE registers updated\n"); 165 if (val & PSR_EVENT_REGISTER_UPDATE) 166 drm_dbg_kms(&i915->drm, "\tRegister updated\n"); 167 if (val & PSR_EVENT_HDCP_ENABLE) 168 drm_dbg_kms(&i915->drm, "\tHDCP enabled\n"); 169 if (val & PSR_EVENT_KVMR_SESSION_ENABLE) 170 drm_dbg_kms(&i915->drm, "\tKVMR session enabled\n"); 171 if (val & PSR_EVENT_VBI_ENABLE) 172 drm_dbg_kms(&i915->drm, "\tVBI enabled\n"); 173 if (val & PSR_EVENT_LPSP_MODE_EXIT) 174 drm_dbg_kms(&i915->drm, "\tLPSP mode exited\n"); 175 if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled) 176 drm_dbg_kms(&i915->drm, "\tPSR disabled\n"); 177 } 178 179 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir) 180 { 181 enum transcoder cpu_transcoder = dev_priv->psr.transcoder; 182 enum transcoder trans_shift; 183 i915_reg_t imr_reg; 184 ktime_t time_ns = ktime_get(); 185 186 if (INTEL_GEN(dev_priv) >= 12) { 187 trans_shift = 0; 188 imr_reg = TRANS_PSR_IMR(dev_priv->psr.transcoder); 189 } else { 190 trans_shift = dev_priv->psr.transcoder; 191 imr_reg = EDP_PSR_IMR; 192 } 193 194 if (psr_iir & EDP_PSR_PRE_ENTRY(trans_shift)) { 195 dev_priv->psr.last_entry_attempt = time_ns; 196 drm_dbg_kms(&dev_priv->drm, 197 "[transcoder %s] PSR entry attempt in 2 vblanks\n", 198 transcoder_name(cpu_transcoder)); 199 } 200 201 if (psr_iir & EDP_PSR_POST_EXIT(trans_shift)) { 202 dev_priv->psr.last_exit = time_ns; 203 drm_dbg_kms(&dev_priv->drm, 204 "[transcoder %s] PSR exit completed\n", 205 transcoder_name(cpu_transcoder)); 206 207 if (INTEL_GEN(dev_priv) >= 9) { 208 u32 val = intel_de_read(dev_priv, 209 PSR_EVENT(cpu_transcoder)); 210 bool psr2_enabled = dev_priv->psr.psr2_enabled; 211 212 intel_de_write(dev_priv, PSR_EVENT(cpu_transcoder), 213 val); 214 psr_event_print(dev_priv, val, psr2_enabled); 215 } 216 } 217 218 if (psr_iir & EDP_PSR_ERROR(trans_shift)) { 219 u32 val; 220 221 drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n", 222 transcoder_name(cpu_transcoder)); 223 224 dev_priv->psr.irq_aux_error = true; 225 226 /* 227 * If this interruption is not masked it will keep 228 * interrupting so fast that it prevents the scheduled 229 * work to run. 230 * Also after a PSR error, we don't want to arm PSR 231 * again so we don't care about unmask the interruption 232 * or unset irq_aux_error. 233 */ 234 val = intel_de_read(dev_priv, imr_reg); 235 val |= EDP_PSR_ERROR(trans_shift); 236 intel_de_write(dev_priv, imr_reg, val); 237 238 schedule_work(&dev_priv->psr.work); 239 } 240 } 241 242 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp) 243 { 244 u8 alpm_caps = 0; 245 246 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, 247 &alpm_caps) != 1) 248 return false; 249 return alpm_caps & DP_ALPM_CAP; 250 } 251 252 static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp) 253 { 254 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 255 u8 val = 8; /* assume the worst if we can't read the value */ 256 257 if (drm_dp_dpcd_readb(&intel_dp->aux, 258 DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1) 259 val &= DP_MAX_RESYNC_FRAME_COUNT_MASK; 260 else 261 drm_dbg_kms(&i915->drm, 262 "Unable to get sink synchronization latency, assuming 8 frames\n"); 263 return val; 264 } 265 266 static u16 intel_dp_get_su_x_granulartiy(struct intel_dp *intel_dp) 267 { 268 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 269 u16 val; 270 ssize_t r; 271 272 /* 273 * Returning the default X granularity if granularity not required or 274 * if DPCD read fails 275 */ 276 if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) 277 return 4; 278 279 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &val, 2); 280 if (r != 2) 281 drm_dbg_kms(&i915->drm, 282 "Unable to read DP_PSR2_SU_X_GRANULARITY\n"); 283 284 /* 285 * Spec says that if the value read is 0 the default granularity should 286 * be used instead. 287 */ 288 if (r != 2 || val == 0) 289 val = 4; 290 291 return val; 292 } 293 294 void intel_psr_init_dpcd(struct intel_dp *intel_dp) 295 { 296 struct drm_i915_private *dev_priv = 297 to_i915(dp_to_dig_port(intel_dp)->base.base.dev); 298 299 if (dev_priv->psr.dp) { 300 drm_warn(&dev_priv->drm, 301 "More than one eDP panel found, PSR support should be extended\n"); 302 return; 303 } 304 305 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, 306 sizeof(intel_dp->psr_dpcd)); 307 308 if (!intel_dp->psr_dpcd[0]) 309 return; 310 drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version %x\n", 311 intel_dp->psr_dpcd[0]); 312 313 if (drm_dp_has_quirk(&intel_dp->desc, 0, DP_DPCD_QUIRK_NO_PSR)) { 314 drm_dbg_kms(&dev_priv->drm, 315 "PSR support not currently available for this panel\n"); 316 return; 317 } 318 319 if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { 320 drm_dbg_kms(&dev_priv->drm, 321 "Panel lacks power state control, PSR cannot be enabled\n"); 322 return; 323 } 324 325 dev_priv->psr.sink_support = true; 326 dev_priv->psr.sink_sync_latency = 327 intel_dp_get_sink_sync_latency(intel_dp); 328 329 dev_priv->psr.dp = intel_dp; 330 331 if (INTEL_GEN(dev_priv) >= 9 && 332 (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) { 333 bool y_req = intel_dp->psr_dpcd[1] & 334 DP_PSR2_SU_Y_COORDINATE_REQUIRED; 335 bool alpm = intel_dp_get_alpm_status(intel_dp); 336 337 /* 338 * All panels that supports PSR version 03h (PSR2 + 339 * Y-coordinate) can handle Y-coordinates in VSC but we are 340 * only sure that it is going to be used when required by the 341 * panel. This way panel is capable to do selective update 342 * without a aux frame sync. 343 * 344 * To support PSR version 02h and PSR version 03h without 345 * Y-coordinate requirement panels we would need to enable 346 * GTC first. 347 */ 348 dev_priv->psr.sink_psr2_support = y_req && alpm; 349 drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n", 350 dev_priv->psr.sink_psr2_support ? "" : "not "); 351 352 if (dev_priv->psr.sink_psr2_support) { 353 dev_priv->psr.colorimetry_support = 354 intel_dp_get_colorimetry_status(intel_dp); 355 dev_priv->psr.su_x_granularity = 356 intel_dp_get_su_x_granulartiy(intel_dp); 357 } 358 } 359 } 360 361 static void hsw_psr_setup_aux(struct intel_dp *intel_dp) 362 { 363 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 364 u32 aux_clock_divider, aux_ctl; 365 int i; 366 static const u8 aux_msg[] = { 367 [0] = DP_AUX_NATIVE_WRITE << 4, 368 [1] = DP_SET_POWER >> 8, 369 [2] = DP_SET_POWER & 0xff, 370 [3] = 1 - 1, 371 [4] = DP_SET_POWER_D0, 372 }; 373 u32 psr_aux_mask = EDP_PSR_AUX_CTL_TIME_OUT_MASK | 374 EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK | 375 EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK | 376 EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK; 377 378 BUILD_BUG_ON(sizeof(aux_msg) > 20); 379 for (i = 0; i < sizeof(aux_msg); i += 4) 380 intel_de_write(dev_priv, 381 EDP_PSR_AUX_DATA(dev_priv->psr.transcoder, i >> 2), 382 intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i)); 383 384 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); 385 386 /* Start with bits set for DDI_AUX_CTL register */ 387 aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg), 388 aux_clock_divider); 389 390 /* Select only valid bits for SRD_AUX_CTL */ 391 aux_ctl &= psr_aux_mask; 392 intel_de_write(dev_priv, EDP_PSR_AUX_CTL(dev_priv->psr.transcoder), 393 aux_ctl); 394 } 395 396 static void intel_psr_enable_sink(struct intel_dp *intel_dp) 397 { 398 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 399 u8 dpcd_val = DP_PSR_ENABLE; 400 401 /* Enable ALPM at sink for psr2 */ 402 if (dev_priv->psr.psr2_enabled) { 403 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 404 DP_ALPM_ENABLE | 405 DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE); 406 407 dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS; 408 } else { 409 if (dev_priv->psr.link_standby) 410 dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE; 411 412 if (INTEL_GEN(dev_priv) >= 8) 413 dpcd_val |= DP_PSR_CRC_VERIFICATION; 414 } 415 416 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); 417 418 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 419 } 420 421 static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp) 422 { 423 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 424 u32 val = 0; 425 426 if (INTEL_GEN(dev_priv) >= 11) 427 val |= EDP_PSR_TP4_TIME_0US; 428 429 if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0) 430 val |= EDP_PSR_TP1_TIME_0us; 431 else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100) 432 val |= EDP_PSR_TP1_TIME_100us; 433 else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500) 434 val |= EDP_PSR_TP1_TIME_500us; 435 else 436 val |= EDP_PSR_TP1_TIME_2500us; 437 438 if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0) 439 val |= EDP_PSR_TP2_TP3_TIME_0us; 440 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100) 441 val |= EDP_PSR_TP2_TP3_TIME_100us; 442 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500) 443 val |= EDP_PSR_TP2_TP3_TIME_500us; 444 else 445 val |= EDP_PSR_TP2_TP3_TIME_2500us; 446 447 if (intel_dp_source_supports_hbr2(intel_dp) && 448 drm_dp_tps3_supported(intel_dp->dpcd)) 449 val |= EDP_PSR_TP1_TP3_SEL; 450 else 451 val |= EDP_PSR_TP1_TP2_SEL; 452 453 return val; 454 } 455 456 static u8 psr_compute_idle_frames(struct intel_dp *intel_dp) 457 { 458 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 459 int idle_frames; 460 461 /* Let's use 6 as the minimum to cover all known cases including the 462 * off-by-one issue that HW has in some cases. 463 */ 464 idle_frames = max(6, dev_priv->vbt.psr.idle_frames); 465 idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1); 466 467 if (drm_WARN_ON(&dev_priv->drm, idle_frames > 0xf)) 468 idle_frames = 0xf; 469 470 return idle_frames; 471 } 472 473 static void hsw_activate_psr1(struct intel_dp *intel_dp) 474 { 475 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 476 u32 max_sleep_time = 0x1f; 477 u32 val = EDP_PSR_ENABLE; 478 479 val |= psr_compute_idle_frames(intel_dp) << EDP_PSR_IDLE_FRAME_SHIFT; 480 481 val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT; 482 if (IS_HASWELL(dev_priv)) 483 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; 484 485 if (dev_priv->psr.link_standby) 486 val |= EDP_PSR_LINK_STANDBY; 487 488 val |= intel_psr1_get_tp_time(intel_dp); 489 490 if (INTEL_GEN(dev_priv) >= 8) 491 val |= EDP_PSR_CRC_ENABLE; 492 493 val |= (intel_de_read(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder)) & 494 EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK); 495 intel_de_write(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder), val); 496 } 497 498 static void hsw_activate_psr2(struct intel_dp *intel_dp) 499 { 500 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 501 u32 val; 502 503 val = psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT; 504 505 val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE; 506 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 507 val |= EDP_Y_COORDINATE_ENABLE; 508 509 val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1); 510 511 if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 && 512 dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50) 513 val |= EDP_PSR2_TP2_TIME_50us; 514 else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100) 515 val |= EDP_PSR2_TP2_TIME_100us; 516 else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500) 517 val |= EDP_PSR2_TP2_TIME_500us; 518 else 519 val |= EDP_PSR2_TP2_TIME_2500us; 520 521 /* 522 * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is 523 * recommending keep this bit unset while PSR2 is enabled. 524 */ 525 intel_de_write(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder), 0); 526 527 intel_de_write(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder), val); 528 } 529 530 static bool 531 transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans) 532 { 533 if (INTEL_GEN(dev_priv) < 9) 534 return false; 535 else if (INTEL_GEN(dev_priv) >= 12) 536 return trans == TRANSCODER_A; 537 else 538 return trans == TRANSCODER_EDP; 539 } 540 541 static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate) 542 { 543 if (!cstate || !cstate->hw.active) 544 return 0; 545 546 return DIV_ROUND_UP(1000 * 1000, 547 drm_mode_vrefresh(&cstate->hw.adjusted_mode)); 548 } 549 550 static void psr2_program_idle_frames(struct drm_i915_private *dev_priv, 551 u32 idle_frames) 552 { 553 u32 val; 554 555 idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT; 556 val = intel_de_read(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder)); 557 val &= ~EDP_PSR2_IDLE_FRAME_MASK; 558 val |= idle_frames; 559 intel_de_write(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder), val); 560 } 561 562 static void tgl_psr2_enable_dc3co(struct drm_i915_private *dev_priv) 563 { 564 psr2_program_idle_frames(dev_priv, 0); 565 intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO); 566 } 567 568 static void tgl_psr2_disable_dc3co(struct drm_i915_private *dev_priv) 569 { 570 struct intel_dp *intel_dp = dev_priv->psr.dp; 571 572 intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); 573 psr2_program_idle_frames(dev_priv, psr_compute_idle_frames(intel_dp)); 574 } 575 576 static void tgl_dc3co_disable_work(struct work_struct *work) 577 { 578 struct drm_i915_private *dev_priv = 579 container_of(work, typeof(*dev_priv), psr.dc3co_work.work); 580 581 mutex_lock(&dev_priv->psr.lock); 582 /* If delayed work is pending, it is not idle */ 583 if (delayed_work_pending(&dev_priv->psr.dc3co_work)) 584 goto unlock; 585 586 tgl_psr2_disable_dc3co(dev_priv); 587 unlock: 588 mutex_unlock(&dev_priv->psr.lock); 589 } 590 591 static void tgl_disallow_dc3co_on_psr2_exit(struct drm_i915_private *dev_priv) 592 { 593 if (!dev_priv->psr.dc3co_enabled) 594 return; 595 596 cancel_delayed_work(&dev_priv->psr.dc3co_work); 597 /* Before PSR2 exit disallow dc3co*/ 598 tgl_psr2_disable_dc3co(dev_priv); 599 } 600 601 static void 602 tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, 603 struct intel_crtc_state *crtc_state) 604 { 605 const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay; 606 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 607 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 608 u32 exit_scanlines; 609 610 if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)) 611 return; 612 613 /* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/ 614 if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A || 615 dig_port->base.port != PORT_A) 616 return; 617 618 /* 619 * DC3CO Exit time 200us B.Spec 49196 620 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1 621 */ 622 exit_scanlines = 623 intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1; 624 625 if (drm_WARN_ON(&dev_priv->drm, exit_scanlines > crtc_vdisplay)) 626 return; 627 628 crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines; 629 } 630 631 static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 632 struct intel_crtc_state *crtc_state) 633 { 634 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 635 int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 636 int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 637 int psr_max_h = 0, psr_max_v = 0, max_bpp = 0; 638 639 if (!dev_priv->psr.sink_psr2_support) 640 return false; 641 642 if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) { 643 drm_dbg_kms(&dev_priv->drm, 644 "PSR2 not supported in transcoder %s\n", 645 transcoder_name(crtc_state->cpu_transcoder)); 646 return false; 647 } 648 649 /* 650 * DSC and PSR2 cannot be enabled simultaneously. If a requested 651 * resolution requires DSC to be enabled, priority is given to DSC 652 * over PSR2. 653 */ 654 if (crtc_state->dsc.compression_enable) { 655 drm_dbg_kms(&dev_priv->drm, 656 "PSR2 cannot be enabled since DSC is enabled\n"); 657 return false; 658 } 659 660 if (INTEL_GEN(dev_priv) >= 12) { 661 psr_max_h = 5120; 662 psr_max_v = 3200; 663 max_bpp = 30; 664 } else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { 665 psr_max_h = 4096; 666 psr_max_v = 2304; 667 max_bpp = 24; 668 } else if (IS_GEN(dev_priv, 9)) { 669 psr_max_h = 3640; 670 psr_max_v = 2304; 671 max_bpp = 24; 672 } 673 674 if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) { 675 drm_dbg_kms(&dev_priv->drm, 676 "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", 677 crtc_hdisplay, crtc_vdisplay, 678 psr_max_h, psr_max_v); 679 return false; 680 } 681 682 if (crtc_state->pipe_bpp > max_bpp) { 683 drm_dbg_kms(&dev_priv->drm, 684 "PSR2 not enabled, pipe bpp %d > max supported %d\n", 685 crtc_state->pipe_bpp, max_bpp); 686 return false; 687 } 688 689 /* 690 * HW sends SU blocks of size four scan lines, which means the starting 691 * X coordinate and Y granularity requirements will always be met. We 692 * only need to validate the SU block width is a multiple of 693 * x granularity. 694 */ 695 if (crtc_hdisplay % dev_priv->psr.su_x_granularity) { 696 drm_dbg_kms(&dev_priv->drm, 697 "PSR2 not enabled, hdisplay(%d) not multiple of %d\n", 698 crtc_hdisplay, dev_priv->psr.su_x_granularity); 699 return false; 700 } 701 702 if (crtc_state->crc_enabled) { 703 drm_dbg_kms(&dev_priv->drm, 704 "PSR2 not enabled because it would inhibit pipe CRC calculation\n"); 705 return false; 706 } 707 708 tgl_dc3co_exitline_compute_config(intel_dp, crtc_state); 709 return true; 710 } 711 712 void intel_psr_compute_config(struct intel_dp *intel_dp, 713 struct intel_crtc_state *crtc_state) 714 { 715 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 716 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 717 const struct drm_display_mode *adjusted_mode = 718 &crtc_state->hw.adjusted_mode; 719 int psr_setup_time; 720 721 if (!CAN_PSR(dev_priv)) 722 return; 723 724 if (intel_dp != dev_priv->psr.dp) 725 return; 726 727 if (!psr_global_enabled(dev_priv)) 728 return; 729 /* 730 * HSW spec explicitly says PSR is tied to port A. 731 * BDW+ platforms have a instance of PSR registers per transcoder but 732 * for now it only supports one instance of PSR, so lets keep it 733 * hardcoded to PORT_A 734 */ 735 if (dig_port->base.port != PORT_A) { 736 drm_dbg_kms(&dev_priv->drm, 737 "PSR condition failed: Port not supported\n"); 738 return; 739 } 740 741 if (dev_priv->psr.sink_not_reliable) { 742 drm_dbg_kms(&dev_priv->drm, 743 "PSR sink implementation is not reliable\n"); 744 return; 745 } 746 747 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 748 drm_dbg_kms(&dev_priv->drm, 749 "PSR condition failed: Interlaced mode enabled\n"); 750 return; 751 } 752 753 psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); 754 if (psr_setup_time < 0) { 755 drm_dbg_kms(&dev_priv->drm, 756 "PSR condition failed: Invalid PSR setup time (0x%02x)\n", 757 intel_dp->psr_dpcd[1]); 758 return; 759 } 760 761 if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > 762 adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { 763 drm_dbg_kms(&dev_priv->drm, 764 "PSR condition failed: PSR setup time (%d us) too long\n", 765 psr_setup_time); 766 return; 767 } 768 769 crtc_state->has_psr = true; 770 crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); 771 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 772 } 773 774 static void intel_psr_activate(struct intel_dp *intel_dp) 775 { 776 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 777 778 if (transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder)) 779 drm_WARN_ON(&dev_priv->drm, 780 intel_de_read(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder)) & EDP_PSR2_ENABLE); 781 782 drm_WARN_ON(&dev_priv->drm, 783 intel_de_read(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder)) & EDP_PSR_ENABLE); 784 drm_WARN_ON(&dev_priv->drm, dev_priv->psr.active); 785 lockdep_assert_held(&dev_priv->psr.lock); 786 787 /* psr1 and psr2 are mutually exclusive.*/ 788 if (dev_priv->psr.psr2_enabled) 789 hsw_activate_psr2(intel_dp); 790 else 791 hsw_activate_psr1(intel_dp); 792 793 dev_priv->psr.active = true; 794 } 795 796 static void intel_psr_enable_source(struct intel_dp *intel_dp, 797 const struct intel_crtc_state *crtc_state) 798 { 799 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 800 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 801 u32 mask; 802 803 /* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+ 804 * use hardcoded values PSR AUX transactions 805 */ 806 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 807 hsw_psr_setup_aux(intel_dp); 808 809 if (dev_priv->psr.psr2_enabled && (IS_GEN(dev_priv, 9) && 810 !IS_GEMINILAKE(dev_priv))) { 811 i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder); 812 u32 chicken = intel_de_read(dev_priv, reg); 813 814 chicken |= PSR2_VSC_ENABLE_PROG_HEADER | 815 PSR2_ADD_VERTICAL_LINE_COUNT; 816 intel_de_write(dev_priv, reg, chicken); 817 } 818 819 /* 820 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also 821 * mask LPSP to avoid dependency on other drivers that might block 822 * runtime_pm besides preventing other hw tracking issues now we 823 * can rely on frontbuffer tracking. 824 */ 825 mask = EDP_PSR_DEBUG_MASK_MEMUP | 826 EDP_PSR_DEBUG_MASK_HPD | 827 EDP_PSR_DEBUG_MASK_LPSP | 828 EDP_PSR_DEBUG_MASK_MAX_SLEEP; 829 830 if (INTEL_GEN(dev_priv) < 11) 831 mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE; 832 833 intel_de_write(dev_priv, EDP_PSR_DEBUG(dev_priv->psr.transcoder), 834 mask); 835 836 psr_irq_control(dev_priv); 837 838 if (crtc_state->dc3co_exitline) { 839 u32 val; 840 841 /* 842 * TODO: if future platforms supports DC3CO in more than one 843 * transcoder, EXITLINE will need to be unset when disabling PSR 844 */ 845 val = intel_de_read(dev_priv, EXITLINE(cpu_transcoder)); 846 val &= ~EXITLINE_MASK; 847 val |= crtc_state->dc3co_exitline << EXITLINE_SHIFT; 848 val |= EXITLINE_ENABLE; 849 intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val); 850 } 851 } 852 853 static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, 854 const struct intel_crtc_state *crtc_state, 855 const struct drm_connector_state *conn_state) 856 { 857 struct intel_dp *intel_dp = dev_priv->psr.dp; 858 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 859 struct intel_encoder *encoder = &intel_dig_port->base; 860 u32 val; 861 862 drm_WARN_ON(&dev_priv->drm, dev_priv->psr.enabled); 863 864 dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state); 865 dev_priv->psr.busy_frontbuffer_bits = 0; 866 dev_priv->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 867 dev_priv->psr.dc3co_enabled = !!crtc_state->dc3co_exitline; 868 dev_priv->psr.transcoder = crtc_state->cpu_transcoder; 869 /* DC5/DC6 requires at least 6 idle frames */ 870 val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); 871 dev_priv->psr.dc3co_exit_delay = val; 872 873 /* 874 * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR 875 * will still keep the error set even after the reset done in the 876 * irq_preinstall and irq_uninstall hooks. 877 * And enabling in this situation cause the screen to freeze in the 878 * first time that PSR HW tries to activate so lets keep PSR disabled 879 * to avoid any rendering problems. 880 */ 881 if (INTEL_GEN(dev_priv) >= 12) { 882 val = intel_de_read(dev_priv, 883 TRANS_PSR_IIR(dev_priv->psr.transcoder)); 884 val &= EDP_PSR_ERROR(0); 885 } else { 886 val = intel_de_read(dev_priv, EDP_PSR_IIR); 887 val &= EDP_PSR_ERROR(dev_priv->psr.transcoder); 888 } 889 if (val) { 890 dev_priv->psr.sink_not_reliable = true; 891 drm_dbg_kms(&dev_priv->drm, 892 "PSR interruption error set, not enabling PSR\n"); 893 return; 894 } 895 896 drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n", 897 dev_priv->psr.psr2_enabled ? "2" : "1"); 898 intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state, 899 &dev_priv->psr.vsc); 900 intel_write_dp_vsc_sdp(encoder, crtc_state, &dev_priv->psr.vsc); 901 intel_psr_enable_sink(intel_dp); 902 intel_psr_enable_source(intel_dp, crtc_state); 903 dev_priv->psr.enabled = true; 904 905 intel_psr_activate(intel_dp); 906 } 907 908 /** 909 * intel_psr_enable - Enable PSR 910 * @intel_dp: Intel DP 911 * @crtc_state: new CRTC state 912 * @conn_state: new CONNECTOR state 913 * 914 * This function can only be called after the pipe is fully trained and enabled. 915 */ 916 void intel_psr_enable(struct intel_dp *intel_dp, 917 const struct intel_crtc_state *crtc_state, 918 const struct drm_connector_state *conn_state) 919 { 920 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 921 922 if (!CAN_PSR(dev_priv) || dev_priv->psr.dp != intel_dp) 923 return; 924 925 dev_priv->psr.force_mode_changed = false; 926 927 if (!crtc_state->has_psr) 928 return; 929 930 drm_WARN_ON(&dev_priv->drm, dev_priv->drrs.dp); 931 932 mutex_lock(&dev_priv->psr.lock); 933 934 if (!psr_global_enabled(dev_priv)) { 935 drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n"); 936 goto unlock; 937 } 938 939 intel_psr_enable_locked(dev_priv, crtc_state, conn_state); 940 941 unlock: 942 mutex_unlock(&dev_priv->psr.lock); 943 } 944 945 static void intel_psr_exit(struct drm_i915_private *dev_priv) 946 { 947 u32 val; 948 949 if (!dev_priv->psr.active) { 950 if (transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder)) { 951 val = intel_de_read(dev_priv, 952 EDP_PSR2_CTL(dev_priv->psr.transcoder)); 953 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR2_ENABLE); 954 } 955 956 val = intel_de_read(dev_priv, 957 EDP_PSR_CTL(dev_priv->psr.transcoder)); 958 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR_ENABLE); 959 960 return; 961 } 962 963 if (dev_priv->psr.psr2_enabled) { 964 tgl_disallow_dc3co_on_psr2_exit(dev_priv); 965 val = intel_de_read(dev_priv, 966 EDP_PSR2_CTL(dev_priv->psr.transcoder)); 967 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE)); 968 val &= ~EDP_PSR2_ENABLE; 969 intel_de_write(dev_priv, 970 EDP_PSR2_CTL(dev_priv->psr.transcoder), val); 971 } else { 972 val = intel_de_read(dev_priv, 973 EDP_PSR_CTL(dev_priv->psr.transcoder)); 974 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR_ENABLE)); 975 val &= ~EDP_PSR_ENABLE; 976 intel_de_write(dev_priv, 977 EDP_PSR_CTL(dev_priv->psr.transcoder), val); 978 } 979 dev_priv->psr.active = false; 980 } 981 982 static void intel_psr_disable_locked(struct intel_dp *intel_dp) 983 { 984 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 985 i915_reg_t psr_status; 986 u32 psr_status_mask; 987 988 lockdep_assert_held(&dev_priv->psr.lock); 989 990 if (!dev_priv->psr.enabled) 991 return; 992 993 drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n", 994 dev_priv->psr.psr2_enabled ? "2" : "1"); 995 996 intel_psr_exit(dev_priv); 997 998 if (dev_priv->psr.psr2_enabled) { 999 psr_status = EDP_PSR2_STATUS(dev_priv->psr.transcoder); 1000 psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; 1001 } else { 1002 psr_status = EDP_PSR_STATUS(dev_priv->psr.transcoder); 1003 psr_status_mask = EDP_PSR_STATUS_STATE_MASK; 1004 } 1005 1006 /* Wait till PSR is idle */ 1007 if (intel_de_wait_for_clear(dev_priv, psr_status, 1008 psr_status_mask, 2000)) 1009 drm_err(&dev_priv->drm, "Timed out waiting PSR idle state\n"); 1010 1011 /* Disable PSR on Sink */ 1012 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); 1013 1014 if (dev_priv->psr.psr2_enabled) 1015 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0); 1016 1017 dev_priv->psr.enabled = false; 1018 } 1019 1020 /** 1021 * intel_psr_disable - Disable PSR 1022 * @intel_dp: Intel DP 1023 * @old_crtc_state: old CRTC state 1024 * 1025 * This function needs to be called before disabling pipe. 1026 */ 1027 void intel_psr_disable(struct intel_dp *intel_dp, 1028 const struct intel_crtc_state *old_crtc_state) 1029 { 1030 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1031 1032 if (!old_crtc_state->has_psr) 1033 return; 1034 1035 if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(dev_priv))) 1036 return; 1037 1038 mutex_lock(&dev_priv->psr.lock); 1039 1040 intel_psr_disable_locked(intel_dp); 1041 1042 mutex_unlock(&dev_priv->psr.lock); 1043 cancel_work_sync(&dev_priv->psr.work); 1044 cancel_delayed_work_sync(&dev_priv->psr.dc3co_work); 1045 } 1046 1047 static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv) 1048 { 1049 if (INTEL_GEN(dev_priv) >= 9) 1050 /* 1051 * Display WA #0884: skl+ 1052 * This documented WA for bxt can be safely applied 1053 * broadly so we can force HW tracking to exit PSR 1054 * instead of disabling and re-enabling. 1055 * Workaround tells us to write 0 to CUR_SURFLIVE_A, 1056 * but it makes more sense write to the current active 1057 * pipe. 1058 */ 1059 intel_de_write(dev_priv, CURSURFLIVE(dev_priv->psr.pipe), 0); 1060 else 1061 /* 1062 * A write to CURSURFLIVE do not cause HW tracking to exit PSR 1063 * on older gens so doing the manual exit instead. 1064 */ 1065 intel_psr_exit(dev_priv); 1066 } 1067 1068 /** 1069 * intel_psr_update - Update PSR state 1070 * @intel_dp: Intel DP 1071 * @crtc_state: new CRTC state 1072 * @conn_state: new CONNECTOR state 1073 * 1074 * This functions will update PSR states, disabling, enabling or switching PSR 1075 * version when executing fastsets. For full modeset, intel_psr_disable() and 1076 * intel_psr_enable() should be called instead. 1077 */ 1078 void intel_psr_update(struct intel_dp *intel_dp, 1079 const struct intel_crtc_state *crtc_state, 1080 const struct drm_connector_state *conn_state) 1081 { 1082 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1083 struct i915_psr *psr = &dev_priv->psr; 1084 bool enable, psr2_enable; 1085 1086 if (!CAN_PSR(dev_priv) || READ_ONCE(psr->dp) != intel_dp) 1087 return; 1088 1089 dev_priv->psr.force_mode_changed = false; 1090 1091 mutex_lock(&dev_priv->psr.lock); 1092 1093 enable = crtc_state->has_psr && psr_global_enabled(dev_priv); 1094 psr2_enable = intel_psr2_enabled(dev_priv, crtc_state); 1095 1096 if (enable == psr->enabled && psr2_enable == psr->psr2_enabled) { 1097 /* Force a PSR exit when enabling CRC to avoid CRC timeouts */ 1098 if (crtc_state->crc_enabled && psr->enabled) 1099 psr_force_hw_tracking_exit(dev_priv); 1100 else if (INTEL_GEN(dev_priv) < 9 && psr->enabled) { 1101 /* 1102 * Activate PSR again after a force exit when enabling 1103 * CRC in older gens 1104 */ 1105 if (!dev_priv->psr.active && 1106 !dev_priv->psr.busy_frontbuffer_bits) 1107 schedule_work(&dev_priv->psr.work); 1108 } 1109 1110 goto unlock; 1111 } 1112 1113 if (psr->enabled) 1114 intel_psr_disable_locked(intel_dp); 1115 1116 if (enable) 1117 intel_psr_enable_locked(dev_priv, crtc_state, conn_state); 1118 1119 unlock: 1120 mutex_unlock(&dev_priv->psr.lock); 1121 } 1122 1123 /** 1124 * intel_psr_wait_for_idle - wait for PSR1 to idle 1125 * @new_crtc_state: new CRTC state 1126 * @out_value: PSR status in case of failure 1127 * 1128 * This function is expected to be called from pipe_update_start() where it is 1129 * not expected to race with PSR enable or disable. 1130 * 1131 * Returns: 0 on success or -ETIMEOUT if PSR status does not idle. 1132 */ 1133 int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state, 1134 u32 *out_value) 1135 { 1136 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 1137 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1138 1139 if (!dev_priv->psr.enabled || !new_crtc_state->has_psr) 1140 return 0; 1141 1142 /* FIXME: Update this for PSR2 if we need to wait for idle */ 1143 if (READ_ONCE(dev_priv->psr.psr2_enabled)) 1144 return 0; 1145 1146 /* 1147 * From bspec: Panel Self Refresh (BDW+) 1148 * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of 1149 * exit training time + 1.5 ms of aux channel handshake. 50 ms is 1150 * defensive enough to cover everything. 1151 */ 1152 1153 return __intel_wait_for_register(&dev_priv->uncore, 1154 EDP_PSR_STATUS(dev_priv->psr.transcoder), 1155 EDP_PSR_STATUS_STATE_MASK, 1156 EDP_PSR_STATUS_STATE_IDLE, 2, 50, 1157 out_value); 1158 } 1159 1160 static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv) 1161 { 1162 i915_reg_t reg; 1163 u32 mask; 1164 int err; 1165 1166 if (!dev_priv->psr.enabled) 1167 return false; 1168 1169 if (dev_priv->psr.psr2_enabled) { 1170 reg = EDP_PSR2_STATUS(dev_priv->psr.transcoder); 1171 mask = EDP_PSR2_STATUS_STATE_MASK; 1172 } else { 1173 reg = EDP_PSR_STATUS(dev_priv->psr.transcoder); 1174 mask = EDP_PSR_STATUS_STATE_MASK; 1175 } 1176 1177 mutex_unlock(&dev_priv->psr.lock); 1178 1179 err = intel_de_wait_for_clear(dev_priv, reg, mask, 50); 1180 if (err) 1181 drm_err(&dev_priv->drm, 1182 "Timed out waiting for PSR Idle for re-enable\n"); 1183 1184 /* After the unlocked wait, verify that PSR is still wanted! */ 1185 mutex_lock(&dev_priv->psr.lock); 1186 return err == 0 && dev_priv->psr.enabled; 1187 } 1188 1189 static int intel_psr_fastset_force(struct drm_i915_private *dev_priv) 1190 { 1191 struct drm_device *dev = &dev_priv->drm; 1192 struct drm_modeset_acquire_ctx ctx; 1193 struct drm_atomic_state *state; 1194 struct intel_crtc *crtc; 1195 int err; 1196 1197 state = drm_atomic_state_alloc(dev); 1198 if (!state) 1199 return -ENOMEM; 1200 1201 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 1202 state->acquire_ctx = &ctx; 1203 1204 retry: 1205 for_each_intel_crtc(dev, crtc) { 1206 struct intel_crtc_state *crtc_state = 1207 intel_atomic_get_crtc_state(state, crtc); 1208 1209 if (IS_ERR(crtc_state)) { 1210 err = PTR_ERR(crtc_state); 1211 goto error; 1212 } 1213 1214 if (crtc_state->hw.active && crtc_state->has_psr) { 1215 /* Mark mode as changed to trigger a pipe->update() */ 1216 crtc_state->uapi.mode_changed = true; 1217 break; 1218 } 1219 } 1220 1221 err = drm_atomic_commit(state); 1222 1223 error: 1224 if (err == -EDEADLK) { 1225 drm_atomic_state_clear(state); 1226 err = drm_modeset_backoff(&ctx); 1227 if (!err) 1228 goto retry; 1229 } 1230 1231 drm_modeset_drop_locks(&ctx); 1232 drm_modeset_acquire_fini(&ctx); 1233 drm_atomic_state_put(state); 1234 1235 return err; 1236 } 1237 1238 int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 val) 1239 { 1240 const u32 mode = val & I915_PSR_DEBUG_MODE_MASK; 1241 u32 old_mode; 1242 int ret; 1243 1244 if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) || 1245 mode > I915_PSR_DEBUG_FORCE_PSR1) { 1246 drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n", val); 1247 return -EINVAL; 1248 } 1249 1250 ret = mutex_lock_interruptible(&dev_priv->psr.lock); 1251 if (ret) 1252 return ret; 1253 1254 old_mode = dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK; 1255 dev_priv->psr.debug = val; 1256 1257 /* 1258 * Do it right away if it's already enabled, otherwise it will be done 1259 * when enabling the source. 1260 */ 1261 if (dev_priv->psr.enabled) 1262 psr_irq_control(dev_priv); 1263 1264 mutex_unlock(&dev_priv->psr.lock); 1265 1266 if (old_mode != mode) 1267 ret = intel_psr_fastset_force(dev_priv); 1268 1269 return ret; 1270 } 1271 1272 static void intel_psr_handle_irq(struct drm_i915_private *dev_priv) 1273 { 1274 struct i915_psr *psr = &dev_priv->psr; 1275 1276 intel_psr_disable_locked(psr->dp); 1277 psr->sink_not_reliable = true; 1278 /* let's make sure that sink is awaken */ 1279 drm_dp_dpcd_writeb(&psr->dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 1280 } 1281 1282 static void intel_psr_work(struct work_struct *work) 1283 { 1284 struct drm_i915_private *dev_priv = 1285 container_of(work, typeof(*dev_priv), psr.work); 1286 1287 mutex_lock(&dev_priv->psr.lock); 1288 1289 if (!dev_priv->psr.enabled) 1290 goto unlock; 1291 1292 if (READ_ONCE(dev_priv->psr.irq_aux_error)) 1293 intel_psr_handle_irq(dev_priv); 1294 1295 /* 1296 * We have to make sure PSR is ready for re-enable 1297 * otherwise it keeps disabled until next full enable/disable cycle. 1298 * PSR might take some time to get fully disabled 1299 * and be ready for re-enable. 1300 */ 1301 if (!__psr_wait_for_idle_locked(dev_priv)) 1302 goto unlock; 1303 1304 /* 1305 * The delayed work can race with an invalidate hence we need to 1306 * recheck. Since psr_flush first clears this and then reschedules we 1307 * won't ever miss a flush when bailing out here. 1308 */ 1309 if (dev_priv->psr.busy_frontbuffer_bits || dev_priv->psr.active) 1310 goto unlock; 1311 1312 intel_psr_activate(dev_priv->psr.dp); 1313 unlock: 1314 mutex_unlock(&dev_priv->psr.lock); 1315 } 1316 1317 /** 1318 * intel_psr_invalidate - Invalidade PSR 1319 * @dev_priv: i915 device 1320 * @frontbuffer_bits: frontbuffer plane tracking bits 1321 * @origin: which operation caused the invalidate 1322 * 1323 * Since the hardware frontbuffer tracking has gaps we need to integrate 1324 * with the software frontbuffer tracking. This function gets called every 1325 * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be 1326 * disabled if the frontbuffer mask contains a buffer relevant to PSR. 1327 * 1328 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." 1329 */ 1330 void intel_psr_invalidate(struct drm_i915_private *dev_priv, 1331 unsigned frontbuffer_bits, enum fb_op_origin origin) 1332 { 1333 if (!CAN_PSR(dev_priv)) 1334 return; 1335 1336 if (origin == ORIGIN_FLIP) 1337 return; 1338 1339 mutex_lock(&dev_priv->psr.lock); 1340 if (!dev_priv->psr.enabled) { 1341 mutex_unlock(&dev_priv->psr.lock); 1342 return; 1343 } 1344 1345 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe); 1346 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits; 1347 1348 if (frontbuffer_bits) 1349 intel_psr_exit(dev_priv); 1350 1351 mutex_unlock(&dev_priv->psr.lock); 1352 } 1353 1354 /* 1355 * When we will be completely rely on PSR2 S/W tracking in future, 1356 * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP 1357 * event also therefore tgl_dc3co_flush() require to be changed 1358 * accordingly in future. 1359 */ 1360 static void 1361 tgl_dc3co_flush(struct drm_i915_private *dev_priv, 1362 unsigned int frontbuffer_bits, enum fb_op_origin origin) 1363 { 1364 mutex_lock(&dev_priv->psr.lock); 1365 1366 if (!dev_priv->psr.dc3co_enabled) 1367 goto unlock; 1368 1369 if (!dev_priv->psr.psr2_enabled || !dev_priv->psr.active) 1370 goto unlock; 1371 1372 /* 1373 * At every frontbuffer flush flip event modified delay of delayed work, 1374 * when delayed work schedules that means display has been idle. 1375 */ 1376 if (!(frontbuffer_bits & 1377 INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe))) 1378 goto unlock; 1379 1380 tgl_psr2_enable_dc3co(dev_priv); 1381 mod_delayed_work(system_wq, &dev_priv->psr.dc3co_work, 1382 dev_priv->psr.dc3co_exit_delay); 1383 1384 unlock: 1385 mutex_unlock(&dev_priv->psr.lock); 1386 } 1387 1388 /** 1389 * intel_psr_flush - Flush PSR 1390 * @dev_priv: i915 device 1391 * @frontbuffer_bits: frontbuffer plane tracking bits 1392 * @origin: which operation caused the flush 1393 * 1394 * Since the hardware frontbuffer tracking has gaps we need to integrate 1395 * with the software frontbuffer tracking. This function gets called every 1396 * time frontbuffer rendering has completed and flushed out to memory. PSR 1397 * can be enabled again if no other frontbuffer relevant to PSR is dirty. 1398 * 1399 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. 1400 */ 1401 void intel_psr_flush(struct drm_i915_private *dev_priv, 1402 unsigned frontbuffer_bits, enum fb_op_origin origin) 1403 { 1404 if (!CAN_PSR(dev_priv)) 1405 return; 1406 1407 if (origin == ORIGIN_FLIP) { 1408 tgl_dc3co_flush(dev_priv, frontbuffer_bits, origin); 1409 return; 1410 } 1411 1412 mutex_lock(&dev_priv->psr.lock); 1413 if (!dev_priv->psr.enabled) { 1414 mutex_unlock(&dev_priv->psr.lock); 1415 return; 1416 } 1417 1418 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe); 1419 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits; 1420 1421 /* By definition flush = invalidate + flush */ 1422 if (frontbuffer_bits) 1423 psr_force_hw_tracking_exit(dev_priv); 1424 1425 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits) 1426 schedule_work(&dev_priv->psr.work); 1427 mutex_unlock(&dev_priv->psr.lock); 1428 } 1429 1430 /** 1431 * intel_psr_init - Init basic PSR work and mutex. 1432 * @dev_priv: i915 device private 1433 * 1434 * This function is called only once at driver load to initialize basic 1435 * PSR stuff. 1436 */ 1437 void intel_psr_init(struct drm_i915_private *dev_priv) 1438 { 1439 if (!HAS_PSR(dev_priv)) 1440 return; 1441 1442 if (!dev_priv->psr.sink_support) 1443 return; 1444 1445 if (IS_HASWELL(dev_priv)) 1446 /* 1447 * HSW don't have PSR registers on the same space as transcoder 1448 * so set this to a value that when subtract to the register 1449 * in transcoder space results in the right offset for HSW 1450 */ 1451 dev_priv->hsw_psr_mmio_adjust = _SRD_CTL_EDP - _HSW_EDP_PSR_BASE; 1452 1453 if (i915_modparams.enable_psr == -1) 1454 if (INTEL_GEN(dev_priv) < 9 || !dev_priv->vbt.psr.enable) 1455 i915_modparams.enable_psr = 0; 1456 1457 /* Set link_standby x link_off defaults */ 1458 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 1459 /* HSW and BDW require workarounds that we don't implement. */ 1460 dev_priv->psr.link_standby = false; 1461 else if (INTEL_GEN(dev_priv) < 12) 1462 /* For new platforms up to TGL let's respect VBT back again */ 1463 dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link; 1464 1465 INIT_WORK(&dev_priv->psr.work, intel_psr_work); 1466 INIT_DELAYED_WORK(&dev_priv->psr.dc3co_work, tgl_dc3co_disable_work); 1467 mutex_init(&dev_priv->psr.lock); 1468 } 1469 1470 static int psr_get_status_and_error_status(struct intel_dp *intel_dp, 1471 u8 *status, u8 *error_status) 1472 { 1473 struct drm_dp_aux *aux = &intel_dp->aux; 1474 int ret; 1475 1476 ret = drm_dp_dpcd_readb(aux, DP_PSR_STATUS, status); 1477 if (ret != 1) 1478 return ret; 1479 1480 ret = drm_dp_dpcd_readb(aux, DP_PSR_ERROR_STATUS, error_status); 1481 if (ret != 1) 1482 return ret; 1483 1484 *status = *status & DP_PSR_SINK_STATE_MASK; 1485 1486 return 0; 1487 } 1488 1489 static void psr_alpm_check(struct intel_dp *intel_dp) 1490 { 1491 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1492 struct drm_dp_aux *aux = &intel_dp->aux; 1493 struct i915_psr *psr = &dev_priv->psr; 1494 u8 val; 1495 int r; 1496 1497 if (!psr->psr2_enabled) 1498 return; 1499 1500 r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val); 1501 if (r != 1) { 1502 drm_err(&dev_priv->drm, "Error reading ALPM status\n"); 1503 return; 1504 } 1505 1506 if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) { 1507 intel_psr_disable_locked(intel_dp); 1508 psr->sink_not_reliable = true; 1509 drm_dbg_kms(&dev_priv->drm, 1510 "ALPM lock timeout error, disabling PSR\n"); 1511 1512 /* Clearing error */ 1513 drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, val); 1514 } 1515 } 1516 1517 static void psr_capability_changed_check(struct intel_dp *intel_dp) 1518 { 1519 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1520 struct i915_psr *psr = &dev_priv->psr; 1521 u8 val; 1522 int r; 1523 1524 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val); 1525 if (r != 1) { 1526 drm_err(&dev_priv->drm, "Error reading DP_PSR_ESI\n"); 1527 return; 1528 } 1529 1530 if (val & DP_PSR_CAPS_CHANGE) { 1531 intel_psr_disable_locked(intel_dp); 1532 psr->sink_not_reliable = true; 1533 drm_dbg_kms(&dev_priv->drm, 1534 "Sink PSR capability changed, disabling PSR\n"); 1535 1536 /* Clearing it */ 1537 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val); 1538 } 1539 } 1540 1541 void intel_psr_short_pulse(struct intel_dp *intel_dp) 1542 { 1543 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1544 struct i915_psr *psr = &dev_priv->psr; 1545 u8 status, error_status; 1546 const u8 errors = DP_PSR_RFB_STORAGE_ERROR | 1547 DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | 1548 DP_PSR_LINK_CRC_ERROR; 1549 1550 if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp)) 1551 return; 1552 1553 mutex_lock(&psr->lock); 1554 1555 if (!psr->enabled || psr->dp != intel_dp) 1556 goto exit; 1557 1558 if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) { 1559 drm_err(&dev_priv->drm, 1560 "Error reading PSR status or error status\n"); 1561 goto exit; 1562 } 1563 1564 if (status == DP_PSR_SINK_INTERNAL_ERROR || (error_status & errors)) { 1565 intel_psr_disable_locked(intel_dp); 1566 psr->sink_not_reliable = true; 1567 } 1568 1569 if (status == DP_PSR_SINK_INTERNAL_ERROR && !error_status) 1570 drm_dbg_kms(&dev_priv->drm, 1571 "PSR sink internal error, disabling PSR\n"); 1572 if (error_status & DP_PSR_RFB_STORAGE_ERROR) 1573 drm_dbg_kms(&dev_priv->drm, 1574 "PSR RFB storage error, disabling PSR\n"); 1575 if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR) 1576 drm_dbg_kms(&dev_priv->drm, 1577 "PSR VSC SDP uncorrectable error, disabling PSR\n"); 1578 if (error_status & DP_PSR_LINK_CRC_ERROR) 1579 drm_dbg_kms(&dev_priv->drm, 1580 "PSR Link CRC error, disabling PSR\n"); 1581 1582 if (error_status & ~errors) 1583 drm_err(&dev_priv->drm, 1584 "PSR_ERROR_STATUS unhandled errors %x\n", 1585 error_status & ~errors); 1586 /* clear status register */ 1587 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status); 1588 1589 psr_alpm_check(intel_dp); 1590 psr_capability_changed_check(intel_dp); 1591 1592 exit: 1593 mutex_unlock(&psr->lock); 1594 } 1595 1596 bool intel_psr_enabled(struct intel_dp *intel_dp) 1597 { 1598 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1599 bool ret; 1600 1601 if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp)) 1602 return false; 1603 1604 mutex_lock(&dev_priv->psr.lock); 1605 ret = (dev_priv->psr.dp == intel_dp && dev_priv->psr.enabled); 1606 mutex_unlock(&dev_priv->psr.lock); 1607 1608 return ret; 1609 } 1610 1611 void intel_psr_atomic_check(struct drm_connector *connector, 1612 struct drm_connector_state *old_state, 1613 struct drm_connector_state *new_state) 1614 { 1615 struct drm_i915_private *dev_priv = to_i915(connector->dev); 1616 struct intel_connector *intel_connector; 1617 struct intel_digital_port *dig_port; 1618 struct drm_crtc_state *crtc_state; 1619 1620 if (!CAN_PSR(dev_priv) || !new_state->crtc || 1621 !dev_priv->psr.force_mode_changed) 1622 return; 1623 1624 intel_connector = to_intel_connector(connector); 1625 dig_port = enc_to_dig_port(intel_attached_encoder(intel_connector)); 1626 if (dev_priv->psr.dp != &dig_port->dp) 1627 return; 1628 1629 crtc_state = drm_atomic_get_new_crtc_state(new_state->state, 1630 new_state->crtc); 1631 crtc_state->mode_changed = true; 1632 } 1633 1634 void intel_psr_set_force_mode_changed(struct intel_dp *intel_dp) 1635 { 1636 struct drm_i915_private *dev_priv; 1637 1638 if (!intel_dp) 1639 return; 1640 1641 dev_priv = dp_to_i915(intel_dp); 1642 if (!CAN_PSR(dev_priv) || intel_dp != dev_priv->psr.dp) 1643 return; 1644 1645 dev_priv->psr.force_mode_changed = true; 1646 } 1647