1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #include <linux/sort.h> 9 10 #include <drm/drm_mode.h> 11 #include <drm/drm_crtc.h> 12 #include <drm/drm_flip_work.h> 13 #include <drm/drm_fourcc.h> 14 #include <drm/drm_probe_helper.h> 15 #include <drm/drm_vblank.h> 16 17 #include "mdp5_kms.h" 18 19 #define CURSOR_WIDTH 64 20 #define CURSOR_HEIGHT 64 21 22 struct mdp5_crtc { 23 struct drm_crtc base; 24 int id; 25 bool enabled; 26 27 spinlock_t lm_lock; /* protect REG_MDP5_LM_* registers */ 28 29 /* if there is a pending flip, these will be non-null: */ 30 struct drm_pending_vblank_event *event; 31 32 /* Bits have been flushed at the last commit, 33 * used to decide if a vsync has happened since last commit. 34 */ 35 u32 flushed_mask; 36 37 #define PENDING_CURSOR 0x1 38 #define PENDING_FLIP 0x2 39 atomic_t pending; 40 41 /* for unref'ing cursor bo's after scanout completes: */ 42 struct drm_flip_work unref_cursor_work; 43 44 struct mdp_irq vblank; 45 struct mdp_irq err; 46 struct mdp_irq pp_done; 47 48 struct completion pp_completion; 49 50 bool lm_cursor_enabled; 51 52 struct { 53 /* protect REG_MDP5_LM_CURSOR* registers and cursor scanout_bo*/ 54 spinlock_t lock; 55 56 /* current cursor being scanned out: */ 57 struct drm_gem_object *scanout_bo; 58 uint64_t iova; 59 uint32_t width, height; 60 int x, y; 61 } cursor; 62 }; 63 #define to_mdp5_crtc(x) container_of(x, struct mdp5_crtc, base) 64 65 static void mdp5_crtc_restore_cursor(struct drm_crtc *crtc); 66 67 static struct mdp5_kms *get_kms(struct drm_crtc *crtc) 68 { 69 struct msm_drm_private *priv = crtc->dev->dev_private; 70 return to_mdp5_kms(to_mdp_kms(priv->kms)); 71 } 72 73 static void request_pending(struct drm_crtc *crtc, uint32_t pending) 74 { 75 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); 76 77 atomic_or(pending, &mdp5_crtc->pending); 78 mdp_irq_register(&get_kms(crtc)->base, &mdp5_crtc->vblank); 79 } 80 81 static void request_pp_done_pending(struct drm_crtc *crtc) 82 { 83 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); 84 reinit_completion(&mdp5_crtc->pp_completion); 85 } 86 87 static u32 crtc_flush(struct drm_crtc *crtc, u32 flush_mask) 88 { 89 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); 90 struct mdp5_ctl *ctl = mdp5_cstate->ctl; 91 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; 92 bool start = !mdp5_cstate->defer_start; 93 94 mdp5_cstate->defer_start = false; 95 96 DBG("%s: flush=%08x", crtc->name, flush_mask); 97 98 return mdp5_ctl_commit(ctl, pipeline, flush_mask, start); 99 } 100 101 /* 102 * flush updates, to make sure hw is updated to new scanout fb, 103 * so that we can safely queue unref to current fb (ie. next 104 * vblank we know hw is done w/ previous scanout_fb). 105 */ 106 static u32 crtc_flush_all(struct drm_crtc *crtc) 107 { 108 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); 109 struct mdp5_hw_mixer *mixer, *r_mixer; 110 struct drm_plane *plane; 111 uint32_t flush_mask = 0; 112 113 /* this should not happen: */ 114 if (WARN_ON(!mdp5_cstate->ctl)) 115 return 0; 116 117 drm_atomic_crtc_for_each_plane(plane, crtc) { 118 if (!plane->state->visible) 119 continue; 120 flush_mask |= mdp5_plane_get_flush(plane); 121 } 122 123 mixer = mdp5_cstate->pipeline.mixer; 124 flush_mask |= mdp_ctl_flush_mask_lm(mixer->lm); 125 126 r_mixer = mdp5_cstate->pipeline.r_mixer; 127 if (r_mixer) 128 flush_mask |= mdp_ctl_flush_mask_lm(r_mixer->lm); 129 130 return crtc_flush(crtc, flush_mask); 131 } 132 133 /* if file!=NULL, this is preclose potential cancel-flip path */ 134 static void complete_flip(struct drm_crtc *crtc, struct drm_file *file) 135 { 136 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); 137 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; 138 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); 139 struct mdp5_ctl *ctl = mdp5_cstate->ctl; 140 struct drm_device *dev = crtc->dev; 141 struct drm_pending_vblank_event *event; 142 unsigned long flags; 143 144 spin_lock_irqsave(&dev->event_lock, flags); 145 event = mdp5_crtc->event; 146 if (event) { 147 mdp5_crtc->event = NULL; 148 DBG("%s: send event: %p", crtc->name, event); 149 drm_crtc_send_vblank_event(crtc, event); 150 } 151 spin_unlock_irqrestore(&dev->event_lock, flags); 152 153 if (ctl && !crtc->state->enable) { 154 /* set STAGE_UNUSED for all layers */ 155 mdp5_ctl_blend(ctl, pipeline, NULL, NULL, 0, 0); 156 /* XXX: What to do here? */ 157 /* mdp5_crtc->ctl = NULL; */ 158 } 159 } 160 161 static void unref_cursor_worker(struct drm_flip_work *work, void *val) 162 { 163 struct mdp5_crtc *mdp5_crtc = 164 container_of(work, struct mdp5_crtc, unref_cursor_work); 165 struct mdp5_kms *mdp5_kms = get_kms(&mdp5_crtc->base); 166 struct msm_kms *kms = &mdp5_kms->base.base; 167 168 msm_gem_unpin_iova(val, kms->aspace); 169 drm_gem_object_put_unlocked(val); 170 } 171 172 static void mdp5_crtc_destroy(struct drm_crtc *crtc) 173 { 174 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); 175 176 drm_crtc_cleanup(crtc); 177 drm_flip_work_cleanup(&mdp5_crtc->unref_cursor_work); 178 179 kfree(mdp5_crtc); 180 } 181 182 static inline u32 mdp5_lm_use_fg_alpha_mask(enum mdp_mixer_stage_id stage) 183 { 184 switch (stage) { 185 case STAGE0: return MDP5_LM_BLEND_COLOR_OUT_STAGE0_FG_ALPHA; 186 case STAGE1: return MDP5_LM_BLEND_COLOR_OUT_STAGE1_FG_ALPHA; 187 case STAGE2: return MDP5_LM_BLEND_COLOR_OUT_STAGE2_FG_ALPHA; 188 case STAGE3: return MDP5_LM_BLEND_COLOR_OUT_STAGE3_FG_ALPHA; 189 case STAGE4: return MDP5_LM_BLEND_COLOR_OUT_STAGE4_FG_ALPHA; 190 case STAGE5: return MDP5_LM_BLEND_COLOR_OUT_STAGE5_FG_ALPHA; 191 case STAGE6: return MDP5_LM_BLEND_COLOR_OUT_STAGE6_FG_ALPHA; 192 default: 193 return 0; 194 } 195 } 196 197 /* 198 * left/right pipe offsets for the stage array used in blend_setup() 199 */ 200 #define PIPE_LEFT 0 201 #define PIPE_RIGHT 1 202 203 /* 204 * blend_setup() - blend all the planes of a CRTC 205 * 206 * If no base layer is available, border will be enabled as the base layer. 207 * Otherwise all layers will be blended based on their stage calculated 208 * in mdp5_crtc_atomic_check. 209 */ 210 static void blend_setup(struct drm_crtc *crtc) 211 { 212 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); 213 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); 214 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; 215 struct mdp5_kms *mdp5_kms = get_kms(crtc); 216 struct drm_plane *plane; 217 struct mdp5_plane_state *pstate, *pstates[STAGE_MAX + 1] = {NULL}; 218 const struct mdp_format *format; 219 struct mdp5_hw_mixer *mixer = pipeline->mixer; 220 uint32_t lm = mixer->lm; 221 struct mdp5_hw_mixer *r_mixer = pipeline->r_mixer; 222 uint32_t r_lm = r_mixer ? r_mixer->lm : 0; 223 struct mdp5_ctl *ctl = mdp5_cstate->ctl; 224 uint32_t blend_op, fg_alpha, bg_alpha, ctl_blend_flags = 0; 225 unsigned long flags; 226 enum mdp5_pipe stage[STAGE_MAX + 1][MAX_PIPE_STAGE] = { { SSPP_NONE } }; 227 enum mdp5_pipe r_stage[STAGE_MAX + 1][MAX_PIPE_STAGE] = { { SSPP_NONE } }; 228 int i, plane_cnt = 0; 229 bool bg_alpha_enabled = false; 230 u32 mixer_op_mode = 0; 231 u32 val; 232 #define blender(stage) ((stage) - STAGE0) 233 234 spin_lock_irqsave(&mdp5_crtc->lm_lock, flags); 235 236 /* ctl could be released already when we are shutting down: */ 237 /* XXX: Can this happen now? */ 238 if (!ctl) 239 goto out; 240 241 /* Collect all plane information */ 242 drm_atomic_crtc_for_each_plane(plane, crtc) { 243 enum mdp5_pipe right_pipe; 244 245 if (!plane->state->visible) 246 continue; 247 248 pstate = to_mdp5_plane_state(plane->state); 249 pstates[pstate->stage] = pstate; 250 stage[pstate->stage][PIPE_LEFT] = mdp5_plane_pipe(plane); 251 /* 252 * if we have a right mixer, stage the same pipe as we 253 * have on the left mixer 254 */ 255 if (r_mixer) 256 r_stage[pstate->stage][PIPE_LEFT] = 257 mdp5_plane_pipe(plane); 258 /* 259 * if we have a right pipe (i.e, the plane comprises of 2 260 * hwpipes, then stage the right pipe on the right side of both 261 * the layer mixers 262 */ 263 right_pipe = mdp5_plane_right_pipe(plane); 264 if (right_pipe) { 265 stage[pstate->stage][PIPE_RIGHT] = right_pipe; 266 r_stage[pstate->stage][PIPE_RIGHT] = right_pipe; 267 } 268 269 plane_cnt++; 270 } 271 272 if (!pstates[STAGE_BASE]) { 273 ctl_blend_flags |= MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT; 274 DBG("Border Color is enabled"); 275 } else if (plane_cnt) { 276 format = to_mdp_format(msm_framebuffer_format(pstates[STAGE_BASE]->base.fb)); 277 278 if (format->alpha_enable) 279 bg_alpha_enabled = true; 280 } 281 282 /* The reset for blending */ 283 for (i = STAGE0; i <= STAGE_MAX; i++) { 284 if (!pstates[i]) 285 continue; 286 287 format = to_mdp_format( 288 msm_framebuffer_format(pstates[i]->base.fb)); 289 plane = pstates[i]->base.plane; 290 blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) | 291 MDP5_LM_BLEND_OP_MODE_BG_ALPHA(BG_CONST); 292 fg_alpha = pstates[i]->alpha; 293 bg_alpha = 0xFF - pstates[i]->alpha; 294 295 if (!format->alpha_enable && bg_alpha_enabled) 296 mixer_op_mode = 0; 297 else 298 mixer_op_mode |= mdp5_lm_use_fg_alpha_mask(i); 299 300 DBG("Stage %d fg_alpha %x bg_alpha %x", i, fg_alpha, bg_alpha); 301 302 if (format->alpha_enable && pstates[i]->premultiplied) { 303 blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) | 304 MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL); 305 if (fg_alpha != 0xff) { 306 bg_alpha = fg_alpha; 307 blend_op |= 308 MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA | 309 MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA; 310 } else { 311 blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA; 312 } 313 } else if (format->alpha_enable) { 314 blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_PIXEL) | 315 MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL); 316 if (fg_alpha != 0xff) { 317 bg_alpha = fg_alpha; 318 blend_op |= 319 MDP5_LM_BLEND_OP_MODE_FG_MOD_ALPHA | 320 MDP5_LM_BLEND_OP_MODE_FG_INV_MOD_ALPHA | 321 MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA | 322 MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA; 323 } else { 324 blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA; 325 } 326 } 327 328 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(lm, 329 blender(i)), blend_op); 330 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(lm, 331 blender(i)), fg_alpha); 332 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(lm, 333 blender(i)), bg_alpha); 334 if (r_mixer) { 335 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(r_lm, 336 blender(i)), blend_op); 337 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(r_lm, 338 blender(i)), fg_alpha); 339 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(r_lm, 340 blender(i)), bg_alpha); 341 } 342 } 343 344 val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm)); 345 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm), 346 val | mixer_op_mode); 347 if (r_mixer) { 348 val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm)); 349 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm), 350 val | mixer_op_mode); 351 } 352 353 mdp5_ctl_blend(ctl, pipeline, stage, r_stage, plane_cnt, 354 ctl_blend_flags); 355 out: 356 spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags); 357 } 358 359 static void mdp5_crtc_mode_set_nofb(struct drm_crtc *crtc) 360 { 361 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); 362 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); 363 struct mdp5_kms *mdp5_kms = get_kms(crtc); 364 struct mdp5_hw_mixer *mixer = mdp5_cstate->pipeline.mixer; 365 struct mdp5_hw_mixer *r_mixer = mdp5_cstate->pipeline.r_mixer; 366 uint32_t lm = mixer->lm; 367 u32 mixer_width, val; 368 unsigned long flags; 369 struct drm_display_mode *mode; 370 371 if (WARN_ON(!crtc->state)) 372 return; 373 374 mode = &crtc->state->adjusted_mode; 375 376 DBG("%s: set mode: " DRM_MODE_FMT, crtc->name, DRM_MODE_ARG(mode)); 377 378 mixer_width = mode->hdisplay; 379 if (r_mixer) 380 mixer_width /= 2; 381 382 spin_lock_irqsave(&mdp5_crtc->lm_lock, flags); 383 mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(lm), 384 MDP5_LM_OUT_SIZE_WIDTH(mixer_width) | 385 MDP5_LM_OUT_SIZE_HEIGHT(mode->vdisplay)); 386 387 /* Assign mixer to LEFT side in source split mode */ 388 val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm)); 389 val &= ~MDP5_LM_BLEND_COLOR_OUT_SPLIT_LEFT_RIGHT; 390 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm), val); 391 392 if (r_mixer) { 393 u32 r_lm = r_mixer->lm; 394 395 mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(r_lm), 396 MDP5_LM_OUT_SIZE_WIDTH(mixer_width) | 397 MDP5_LM_OUT_SIZE_HEIGHT(mode->vdisplay)); 398 399 /* Assign mixer to RIGHT side in source split mode */ 400 val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm)); 401 val |= MDP5_LM_BLEND_COLOR_OUT_SPLIT_LEFT_RIGHT; 402 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm), val); 403 } 404 405 spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags); 406 } 407 408 static struct drm_encoder *get_encoder_from_crtc(struct drm_crtc *crtc) 409 { 410 struct drm_device *dev = crtc->dev; 411 struct drm_encoder *encoder; 412 413 drm_for_each_encoder(encoder, dev) 414 if (encoder->crtc == crtc) 415 return encoder; 416 417 return NULL; 418 } 419 420 static bool mdp5_crtc_get_scanout_position(struct drm_crtc *crtc, 421 bool in_vblank_irq, 422 int *vpos, int *hpos, 423 ktime_t *stime, ktime_t *etime, 424 const struct drm_display_mode *mode) 425 { 426 unsigned int pipe = crtc->index; 427 struct drm_encoder *encoder; 428 int line, vsw, vbp, vactive_start, vactive_end, vfp_end; 429 430 431 encoder = get_encoder_from_crtc(crtc); 432 if (!encoder) { 433 DRM_ERROR("no encoder found for crtc %d\n", pipe); 434 return false; 435 } 436 437 vsw = mode->crtc_vsync_end - mode->crtc_vsync_start; 438 vbp = mode->crtc_vtotal - mode->crtc_vsync_end; 439 440 /* 441 * the line counter is 1 at the start of the VSYNC pulse and VTOTAL at 442 * the end of VFP. Translate the porch values relative to the line 443 * counter positions. 444 */ 445 446 vactive_start = vsw + vbp + 1; 447 448 vactive_end = vactive_start + mode->crtc_vdisplay; 449 450 /* last scan line before VSYNC */ 451 vfp_end = mode->crtc_vtotal; 452 453 if (stime) 454 *stime = ktime_get(); 455 456 line = mdp5_encoder_get_linecount(encoder); 457 458 if (line < vactive_start) 459 line -= vactive_start; 460 else if (line > vactive_end) 461 line = line - vfp_end - vactive_start; 462 else 463 line -= vactive_start; 464 465 *vpos = line; 466 *hpos = 0; 467 468 if (etime) 469 *etime = ktime_get(); 470 471 return true; 472 } 473 474 static u32 mdp5_crtc_get_vblank_counter(struct drm_crtc *crtc) 475 { 476 struct drm_encoder *encoder; 477 478 encoder = get_encoder_from_crtc(crtc); 479 if (!encoder) 480 return 0; 481 482 return mdp5_encoder_get_framecount(encoder); 483 } 484 485 static void mdp5_crtc_atomic_disable(struct drm_crtc *crtc, 486 struct drm_crtc_state *old_state) 487 { 488 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); 489 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); 490 struct mdp5_kms *mdp5_kms = get_kms(crtc); 491 struct device *dev = &mdp5_kms->pdev->dev; 492 unsigned long flags; 493 494 DBG("%s", crtc->name); 495 496 if (WARN_ON(!mdp5_crtc->enabled)) 497 return; 498 499 /* Disable/save vblank irq handling before power is disabled */ 500 drm_crtc_vblank_off(crtc); 501 502 if (mdp5_cstate->cmd_mode) 503 mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->pp_done); 504 505 mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->err); 506 pm_runtime_put_sync(dev); 507 508 if (crtc->state->event && !crtc->state->active) { 509 WARN_ON(mdp5_crtc->event); 510 spin_lock_irqsave(&mdp5_kms->dev->event_lock, flags); 511 drm_crtc_send_vblank_event(crtc, crtc->state->event); 512 crtc->state->event = NULL; 513 spin_unlock_irqrestore(&mdp5_kms->dev->event_lock, flags); 514 } 515 516 mdp5_crtc->enabled = false; 517 } 518 519 static void mdp5_crtc_vblank_on(struct drm_crtc *crtc) 520 { 521 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); 522 struct mdp5_interface *intf = mdp5_cstate->pipeline.intf; 523 u32 count; 524 525 count = intf->mode == MDP5_INTF_DSI_MODE_COMMAND ? 0 : 0xffffffff; 526 drm_crtc_set_max_vblank_count(crtc, count); 527 528 drm_crtc_vblank_on(crtc); 529 } 530 531 static void mdp5_crtc_atomic_enable(struct drm_crtc *crtc, 532 struct drm_crtc_state *old_state) 533 { 534 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); 535 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); 536 struct mdp5_kms *mdp5_kms = get_kms(crtc); 537 struct device *dev = &mdp5_kms->pdev->dev; 538 539 DBG("%s", crtc->name); 540 541 if (WARN_ON(mdp5_crtc->enabled)) 542 return; 543 544 pm_runtime_get_sync(dev); 545 546 if (mdp5_crtc->lm_cursor_enabled) { 547 /* 548 * Restore LM cursor state, as it might have been lost 549 * with suspend: 550 */ 551 if (mdp5_crtc->cursor.iova) { 552 unsigned long flags; 553 554 spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags); 555 mdp5_crtc_restore_cursor(crtc); 556 spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags); 557 558 mdp5_ctl_set_cursor(mdp5_cstate->ctl, 559 &mdp5_cstate->pipeline, 0, true); 560 } else { 561 mdp5_ctl_set_cursor(mdp5_cstate->ctl, 562 &mdp5_cstate->pipeline, 0, false); 563 } 564 } 565 566 /* Restore vblank irq handling after power is enabled */ 567 mdp5_crtc_vblank_on(crtc); 568 569 mdp5_crtc_mode_set_nofb(crtc); 570 571 mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->err); 572 573 if (mdp5_cstate->cmd_mode) 574 mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->pp_done); 575 576 mdp5_crtc->enabled = true; 577 } 578 579 int mdp5_crtc_setup_pipeline(struct drm_crtc *crtc, 580 struct drm_crtc_state *new_crtc_state, 581 bool need_right_mixer) 582 { 583 struct mdp5_crtc_state *mdp5_cstate = 584 to_mdp5_crtc_state(new_crtc_state); 585 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; 586 struct mdp5_interface *intf; 587 bool new_mixer = false; 588 589 new_mixer = !pipeline->mixer; 590 591 if ((need_right_mixer && !pipeline->r_mixer) || 592 (!need_right_mixer && pipeline->r_mixer)) 593 new_mixer = true; 594 595 if (new_mixer) { 596 struct mdp5_hw_mixer *old_mixer = pipeline->mixer; 597 struct mdp5_hw_mixer *old_r_mixer = pipeline->r_mixer; 598 u32 caps; 599 int ret; 600 601 caps = MDP_LM_CAP_DISPLAY; 602 if (need_right_mixer) 603 caps |= MDP_LM_CAP_PAIR; 604 605 ret = mdp5_mixer_assign(new_crtc_state->state, crtc, caps, 606 &pipeline->mixer, need_right_mixer ? 607 &pipeline->r_mixer : NULL); 608 if (ret) 609 return ret; 610 611 mdp5_mixer_release(new_crtc_state->state, old_mixer); 612 if (old_r_mixer) { 613 mdp5_mixer_release(new_crtc_state->state, old_r_mixer); 614 if (!need_right_mixer) 615 pipeline->r_mixer = NULL; 616 } 617 } 618 619 /* 620 * these should have been already set up in the encoder's atomic 621 * check (called by drm_atomic_helper_check_modeset) 622 */ 623 intf = pipeline->intf; 624 625 mdp5_cstate->err_irqmask = intf2err(intf->num); 626 mdp5_cstate->vblank_irqmask = intf2vblank(pipeline->mixer, intf); 627 628 if ((intf->type == INTF_DSI) && 629 (intf->mode == MDP5_INTF_DSI_MODE_COMMAND)) { 630 mdp5_cstate->pp_done_irqmask = lm2ppdone(pipeline->mixer); 631 mdp5_cstate->cmd_mode = true; 632 } else { 633 mdp5_cstate->pp_done_irqmask = 0; 634 mdp5_cstate->cmd_mode = false; 635 } 636 637 return 0; 638 } 639 640 struct plane_state { 641 struct drm_plane *plane; 642 struct mdp5_plane_state *state; 643 }; 644 645 static int pstate_cmp(const void *a, const void *b) 646 { 647 struct plane_state *pa = (struct plane_state *)a; 648 struct plane_state *pb = (struct plane_state *)b; 649 return pa->state->zpos - pb->state->zpos; 650 } 651 652 /* is there a helper for this? */ 653 static bool is_fullscreen(struct drm_crtc_state *cstate, 654 struct drm_plane_state *pstate) 655 { 656 return (pstate->crtc_x <= 0) && (pstate->crtc_y <= 0) && 657 ((pstate->crtc_x + pstate->crtc_w) >= cstate->mode.hdisplay) && 658 ((pstate->crtc_y + pstate->crtc_h) >= cstate->mode.vdisplay); 659 } 660 661 static enum mdp_mixer_stage_id get_start_stage(struct drm_crtc *crtc, 662 struct drm_crtc_state *new_crtc_state, 663 struct drm_plane_state *bpstate) 664 { 665 struct mdp5_crtc_state *mdp5_cstate = 666 to_mdp5_crtc_state(new_crtc_state); 667 668 /* 669 * if we're in source split mode, it's mandatory to have 670 * border out on the base stage 671 */ 672 if (mdp5_cstate->pipeline.r_mixer) 673 return STAGE0; 674 675 /* if the bottom-most layer is not fullscreen, we need to use 676 * it for solid-color: 677 */ 678 if (!is_fullscreen(new_crtc_state, bpstate)) 679 return STAGE0; 680 681 return STAGE_BASE; 682 } 683 684 static int mdp5_crtc_atomic_check(struct drm_crtc *crtc, 685 struct drm_crtc_state *state) 686 { 687 struct mdp5_kms *mdp5_kms = get_kms(crtc); 688 struct drm_plane *plane; 689 struct drm_device *dev = crtc->dev; 690 struct plane_state pstates[STAGE_MAX + 1]; 691 const struct mdp5_cfg_hw *hw_cfg; 692 const struct drm_plane_state *pstate; 693 const struct drm_display_mode *mode = &state->adjusted_mode; 694 bool cursor_plane = false; 695 bool need_right_mixer = false; 696 int cnt = 0, i; 697 int ret; 698 enum mdp_mixer_stage_id start; 699 700 DBG("%s: check", crtc->name); 701 702 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) { 703 if (!pstate->visible) 704 continue; 705 706 pstates[cnt].plane = plane; 707 pstates[cnt].state = to_mdp5_plane_state(pstate); 708 709 /* 710 * if any plane on this crtc uses 2 hwpipes, then we need 711 * the crtc to have a right hwmixer. 712 */ 713 if (pstates[cnt].state->r_hwpipe) 714 need_right_mixer = true; 715 cnt++; 716 717 if (plane->type == DRM_PLANE_TYPE_CURSOR) 718 cursor_plane = true; 719 } 720 721 /* bail out early if there aren't any planes */ 722 if (!cnt) 723 return 0; 724 725 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); 726 727 /* 728 * we need a right hwmixer if the mode's width is greater than a single 729 * LM's max width 730 */ 731 if (mode->hdisplay > hw_cfg->lm.max_width) 732 need_right_mixer = true; 733 734 ret = mdp5_crtc_setup_pipeline(crtc, state, need_right_mixer); 735 if (ret) { 736 DRM_DEV_ERROR(dev->dev, "couldn't assign mixers %d\n", ret); 737 return ret; 738 } 739 740 /* assign a stage based on sorted zpos property */ 741 sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL); 742 743 /* trigger a warning if cursor isn't the highest zorder */ 744 WARN_ON(cursor_plane && 745 (pstates[cnt - 1].plane->type != DRM_PLANE_TYPE_CURSOR)); 746 747 start = get_start_stage(crtc, state, &pstates[0].state->base); 748 749 /* verify that there are not too many planes attached to crtc 750 * and that we don't have conflicting mixer stages: 751 */ 752 if ((cnt + start - 1) >= hw_cfg->lm.nb_stages) { 753 DRM_DEV_ERROR(dev->dev, "too many planes! cnt=%d, start stage=%d\n", 754 cnt, start); 755 return -EINVAL; 756 } 757 758 for (i = 0; i < cnt; i++) { 759 if (cursor_plane && (i == (cnt - 1))) 760 pstates[i].state->stage = hw_cfg->lm.nb_stages; 761 else 762 pstates[i].state->stage = start + i; 763 DBG("%s: assign pipe %s on stage=%d", crtc->name, 764 pstates[i].plane->name, 765 pstates[i].state->stage); 766 } 767 768 return 0; 769 } 770 771 static void mdp5_crtc_atomic_begin(struct drm_crtc *crtc, 772 struct drm_crtc_state *old_crtc_state) 773 { 774 DBG("%s: begin", crtc->name); 775 } 776 777 static void mdp5_crtc_atomic_flush(struct drm_crtc *crtc, 778 struct drm_crtc_state *old_crtc_state) 779 { 780 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); 781 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); 782 struct drm_device *dev = crtc->dev; 783 unsigned long flags; 784 785 DBG("%s: event: %p", crtc->name, crtc->state->event); 786 787 WARN_ON(mdp5_crtc->event); 788 789 spin_lock_irqsave(&dev->event_lock, flags); 790 mdp5_crtc->event = crtc->state->event; 791 crtc->state->event = NULL; 792 spin_unlock_irqrestore(&dev->event_lock, flags); 793 794 /* 795 * If no CTL has been allocated in mdp5_crtc_atomic_check(), 796 * it means we are trying to flush a CRTC whose state is disabled: 797 * nothing else needs to be done. 798 */ 799 /* XXX: Can this happen now ? */ 800 if (unlikely(!mdp5_cstate->ctl)) 801 return; 802 803 blend_setup(crtc); 804 805 /* PP_DONE irq is only used by command mode for now. 806 * It is better to request pending before FLUSH and START trigger 807 * to make sure no pp_done irq missed. 808 * This is safe because no pp_done will happen before SW trigger 809 * in command mode. 810 */ 811 if (mdp5_cstate->cmd_mode) 812 request_pp_done_pending(crtc); 813 814 mdp5_crtc->flushed_mask = crtc_flush_all(crtc); 815 816 /* XXX are we leaking out state here? */ 817 mdp5_crtc->vblank.irqmask = mdp5_cstate->vblank_irqmask; 818 mdp5_crtc->err.irqmask = mdp5_cstate->err_irqmask; 819 mdp5_crtc->pp_done.irqmask = mdp5_cstate->pp_done_irqmask; 820 821 request_pending(crtc, PENDING_FLIP); 822 } 823 824 static void get_roi(struct drm_crtc *crtc, uint32_t *roi_w, uint32_t *roi_h) 825 { 826 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); 827 uint32_t xres = crtc->mode.hdisplay; 828 uint32_t yres = crtc->mode.vdisplay; 829 830 /* 831 * Cursor Region Of Interest (ROI) is a plane read from cursor 832 * buffer to render. The ROI region is determined by the visibility of 833 * the cursor point. In the default Cursor image the cursor point will 834 * be at the top left of the cursor image. 835 * 836 * Without rotation: 837 * If the cursor point reaches the right (xres - x < cursor.width) or 838 * bottom (yres - y < cursor.height) boundary of the screen, then ROI 839 * width and ROI height need to be evaluated to crop the cursor image 840 * accordingly. 841 * (xres-x) will be new cursor width when x > (xres - cursor.width) 842 * (yres-y) will be new cursor height when y > (yres - cursor.height) 843 * 844 * With rotation: 845 * We get negative x and/or y coordinates. 846 * (cursor.width - abs(x)) will be new cursor width when x < 0 847 * (cursor.height - abs(y)) will be new cursor width when y < 0 848 */ 849 if (mdp5_crtc->cursor.x >= 0) 850 *roi_w = min(mdp5_crtc->cursor.width, xres - 851 mdp5_crtc->cursor.x); 852 else 853 *roi_w = mdp5_crtc->cursor.width - abs(mdp5_crtc->cursor.x); 854 if (mdp5_crtc->cursor.y >= 0) 855 *roi_h = min(mdp5_crtc->cursor.height, yres - 856 mdp5_crtc->cursor.y); 857 else 858 *roi_h = mdp5_crtc->cursor.height - abs(mdp5_crtc->cursor.y); 859 } 860 861 static void mdp5_crtc_restore_cursor(struct drm_crtc *crtc) 862 { 863 const struct drm_format_info *info = drm_format_info(DRM_FORMAT_ARGB8888); 864 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); 865 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); 866 struct mdp5_kms *mdp5_kms = get_kms(crtc); 867 const enum mdp5_cursor_alpha cur_alpha = CURSOR_ALPHA_PER_PIXEL; 868 uint32_t blendcfg, stride; 869 uint32_t x, y, src_x, src_y, width, height; 870 uint32_t roi_w, roi_h; 871 int lm; 872 873 assert_spin_locked(&mdp5_crtc->cursor.lock); 874 875 lm = mdp5_cstate->pipeline.mixer->lm; 876 877 x = mdp5_crtc->cursor.x; 878 y = mdp5_crtc->cursor.y; 879 width = mdp5_crtc->cursor.width; 880 height = mdp5_crtc->cursor.height; 881 882 stride = width * info->cpp[0]; 883 884 get_roi(crtc, &roi_w, &roi_h); 885 886 /* If cusror buffer overlaps due to rotation on the 887 * upper or left screen border the pixel offset inside 888 * the cursor buffer of the ROI is the positive overlap 889 * distance. 890 */ 891 if (mdp5_crtc->cursor.x < 0) { 892 src_x = abs(mdp5_crtc->cursor.x); 893 x = 0; 894 } else { 895 src_x = 0; 896 } 897 if (mdp5_crtc->cursor.y < 0) { 898 src_y = abs(mdp5_crtc->cursor.y); 899 y = 0; 900 } else { 901 src_y = 0; 902 } 903 DBG("%s: x=%d, y=%d roi_w=%d roi_h=%d src_x=%d src_y=%d", 904 crtc->name, x, y, roi_w, roi_h, src_x, src_y); 905 906 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_STRIDE(lm), stride); 907 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_FORMAT(lm), 908 MDP5_LM_CURSOR_FORMAT_FORMAT(CURSOR_FMT_ARGB8888)); 909 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_IMG_SIZE(lm), 910 MDP5_LM_CURSOR_IMG_SIZE_SRC_H(height) | 911 MDP5_LM_CURSOR_IMG_SIZE_SRC_W(width)); 912 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(lm), 913 MDP5_LM_CURSOR_SIZE_ROI_H(roi_h) | 914 MDP5_LM_CURSOR_SIZE_ROI_W(roi_w)); 915 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_START_XY(lm), 916 MDP5_LM_CURSOR_START_XY_Y_START(y) | 917 MDP5_LM_CURSOR_START_XY_X_START(x)); 918 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_XY(lm), 919 MDP5_LM_CURSOR_XY_SRC_Y(src_y) | 920 MDP5_LM_CURSOR_XY_SRC_X(src_x)); 921 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BASE_ADDR(lm), 922 mdp5_crtc->cursor.iova); 923 924 blendcfg = MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN; 925 blendcfg |= MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(cur_alpha); 926 mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BLEND_CONFIG(lm), blendcfg); 927 } 928 929 static int mdp5_crtc_cursor_set(struct drm_crtc *crtc, 930 struct drm_file *file, uint32_t handle, 931 uint32_t width, uint32_t height) 932 { 933 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); 934 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); 935 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; 936 struct drm_device *dev = crtc->dev; 937 struct mdp5_kms *mdp5_kms = get_kms(crtc); 938 struct platform_device *pdev = mdp5_kms->pdev; 939 struct msm_kms *kms = &mdp5_kms->base.base; 940 struct drm_gem_object *cursor_bo, *old_bo = NULL; 941 struct mdp5_ctl *ctl; 942 int ret; 943 uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0); 944 bool cursor_enable = true; 945 unsigned long flags; 946 947 if (!mdp5_crtc->lm_cursor_enabled) { 948 dev_warn(dev->dev, 949 "cursor_set is deprecated with cursor planes\n"); 950 return -EINVAL; 951 } 952 953 if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) { 954 DRM_DEV_ERROR(dev->dev, "bad cursor size: %dx%d\n", width, height); 955 return -EINVAL; 956 } 957 958 ctl = mdp5_cstate->ctl; 959 if (!ctl) 960 return -EINVAL; 961 962 /* don't support LM cursors when we have source split enabled */ 963 if (mdp5_cstate->pipeline.r_mixer) 964 return -EINVAL; 965 966 if (!handle) { 967 DBG("Cursor off"); 968 cursor_enable = false; 969 mdp5_crtc->cursor.iova = 0; 970 pm_runtime_get_sync(&pdev->dev); 971 goto set_cursor; 972 } 973 974 cursor_bo = drm_gem_object_lookup(file, handle); 975 if (!cursor_bo) 976 return -ENOENT; 977 978 ret = msm_gem_get_and_pin_iova(cursor_bo, kms->aspace, 979 &mdp5_crtc->cursor.iova); 980 if (ret) 981 return -EINVAL; 982 983 pm_runtime_get_sync(&pdev->dev); 984 985 spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags); 986 old_bo = mdp5_crtc->cursor.scanout_bo; 987 988 mdp5_crtc->cursor.scanout_bo = cursor_bo; 989 mdp5_crtc->cursor.width = width; 990 mdp5_crtc->cursor.height = height; 991 992 mdp5_crtc_restore_cursor(crtc); 993 994 spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags); 995 996 set_cursor: 997 ret = mdp5_ctl_set_cursor(ctl, pipeline, 0, cursor_enable); 998 if (ret) { 999 DRM_DEV_ERROR(dev->dev, "failed to %sable cursor: %d\n", 1000 cursor_enable ? "en" : "dis", ret); 1001 goto end; 1002 } 1003 1004 crtc_flush(crtc, flush_mask); 1005 1006 end: 1007 pm_runtime_put_sync(&pdev->dev); 1008 if (old_bo) { 1009 drm_flip_work_queue(&mdp5_crtc->unref_cursor_work, old_bo); 1010 /* enable vblank to complete cursor work: */ 1011 request_pending(crtc, PENDING_CURSOR); 1012 } 1013 return ret; 1014 } 1015 1016 static int mdp5_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) 1017 { 1018 struct mdp5_kms *mdp5_kms = get_kms(crtc); 1019 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); 1020 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); 1021 uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0); 1022 struct drm_device *dev = crtc->dev; 1023 uint32_t roi_w; 1024 uint32_t roi_h; 1025 unsigned long flags; 1026 1027 if (!mdp5_crtc->lm_cursor_enabled) { 1028 dev_warn(dev->dev, 1029 "cursor_move is deprecated with cursor planes\n"); 1030 return -EINVAL; 1031 } 1032 1033 /* don't support LM cursors when we have source split enabled */ 1034 if (mdp5_cstate->pipeline.r_mixer) 1035 return -EINVAL; 1036 1037 /* In case the CRTC is disabled, just drop the cursor update */ 1038 if (unlikely(!crtc->state->enable)) 1039 return 0; 1040 1041 /* accept negative x/y coordinates up to maximum cursor overlap */ 1042 mdp5_crtc->cursor.x = x = max(x, -(int)mdp5_crtc->cursor.width); 1043 mdp5_crtc->cursor.y = y = max(y, -(int)mdp5_crtc->cursor.height); 1044 1045 get_roi(crtc, &roi_w, &roi_h); 1046 1047 pm_runtime_get_sync(&mdp5_kms->pdev->dev); 1048 1049 spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags); 1050 mdp5_crtc_restore_cursor(crtc); 1051 spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags); 1052 1053 crtc_flush(crtc, flush_mask); 1054 1055 pm_runtime_put_sync(&mdp5_kms->pdev->dev); 1056 1057 return 0; 1058 } 1059 1060 static void 1061 mdp5_crtc_atomic_print_state(struct drm_printer *p, 1062 const struct drm_crtc_state *state) 1063 { 1064 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(state); 1065 struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; 1066 struct mdp5_kms *mdp5_kms = get_kms(state->crtc); 1067 1068 if (WARN_ON(!pipeline)) 1069 return; 1070 1071 if (mdp5_cstate->ctl) 1072 drm_printf(p, "\tctl=%d\n", mdp5_ctl_get_ctl_id(mdp5_cstate->ctl)); 1073 1074 drm_printf(p, "\thwmixer=%s\n", pipeline->mixer ? 1075 pipeline->mixer->name : "(null)"); 1076 1077 if (mdp5_kms->caps & MDP_CAP_SRC_SPLIT) 1078 drm_printf(p, "\tright hwmixer=%s\n", pipeline->r_mixer ? 1079 pipeline->r_mixer->name : "(null)"); 1080 1081 drm_printf(p, "\tcmd_mode=%d\n", mdp5_cstate->cmd_mode); 1082 } 1083 1084 static struct drm_crtc_state * 1085 mdp5_crtc_duplicate_state(struct drm_crtc *crtc) 1086 { 1087 struct mdp5_crtc_state *mdp5_cstate; 1088 1089 if (WARN_ON(!crtc->state)) 1090 return NULL; 1091 1092 mdp5_cstate = kmemdup(to_mdp5_crtc_state(crtc->state), 1093 sizeof(*mdp5_cstate), GFP_KERNEL); 1094 if (!mdp5_cstate) 1095 return NULL; 1096 1097 __drm_atomic_helper_crtc_duplicate_state(crtc, &mdp5_cstate->base); 1098 1099 return &mdp5_cstate->base; 1100 } 1101 1102 static void mdp5_crtc_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *state) 1103 { 1104 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(state); 1105 1106 __drm_atomic_helper_crtc_destroy_state(state); 1107 1108 kfree(mdp5_cstate); 1109 } 1110 1111 static void mdp5_crtc_reset(struct drm_crtc *crtc) 1112 { 1113 struct mdp5_crtc_state *mdp5_cstate = 1114 kzalloc(sizeof(*mdp5_cstate), GFP_KERNEL); 1115 1116 if (crtc->state) 1117 mdp5_crtc_destroy_state(crtc, crtc->state); 1118 1119 __drm_atomic_helper_crtc_reset(crtc, &mdp5_cstate->base); 1120 1121 drm_crtc_vblank_reset(crtc); 1122 } 1123 1124 static const struct drm_crtc_funcs mdp5_crtc_funcs = { 1125 .set_config = drm_atomic_helper_set_config, 1126 .destroy = mdp5_crtc_destroy, 1127 .page_flip = drm_atomic_helper_page_flip, 1128 .reset = mdp5_crtc_reset, 1129 .atomic_duplicate_state = mdp5_crtc_duplicate_state, 1130 .atomic_destroy_state = mdp5_crtc_destroy_state, 1131 .cursor_set = mdp5_crtc_cursor_set, 1132 .cursor_move = mdp5_crtc_cursor_move, 1133 .atomic_print_state = mdp5_crtc_atomic_print_state, 1134 .get_vblank_counter = mdp5_crtc_get_vblank_counter, 1135 .enable_vblank = msm_crtc_enable_vblank, 1136 .disable_vblank = msm_crtc_disable_vblank, 1137 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 1138 }; 1139 1140 static const struct drm_crtc_helper_funcs mdp5_crtc_helper_funcs = { 1141 .mode_set_nofb = mdp5_crtc_mode_set_nofb, 1142 .atomic_check = mdp5_crtc_atomic_check, 1143 .atomic_begin = mdp5_crtc_atomic_begin, 1144 .atomic_flush = mdp5_crtc_atomic_flush, 1145 .atomic_enable = mdp5_crtc_atomic_enable, 1146 .atomic_disable = mdp5_crtc_atomic_disable, 1147 .get_scanout_position = mdp5_crtc_get_scanout_position, 1148 }; 1149 1150 static void mdp5_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus) 1151 { 1152 struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, vblank); 1153 struct drm_crtc *crtc = &mdp5_crtc->base; 1154 struct msm_drm_private *priv = crtc->dev->dev_private; 1155 unsigned pending; 1156 1157 mdp_irq_unregister(&get_kms(crtc)->base, &mdp5_crtc->vblank); 1158 1159 pending = atomic_xchg(&mdp5_crtc->pending, 0); 1160 1161 if (pending & PENDING_FLIP) { 1162 complete_flip(crtc, NULL); 1163 } 1164 1165 if (pending & PENDING_CURSOR) 1166 drm_flip_work_commit(&mdp5_crtc->unref_cursor_work, priv->wq); 1167 } 1168 1169 static void mdp5_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus) 1170 { 1171 struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, err); 1172 1173 DBG("%s: error: %08x", mdp5_crtc->base.name, irqstatus); 1174 } 1175 1176 static void mdp5_crtc_pp_done_irq(struct mdp_irq *irq, uint32_t irqstatus) 1177 { 1178 struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, 1179 pp_done); 1180 1181 complete(&mdp5_crtc->pp_completion); 1182 } 1183 1184 static void mdp5_crtc_wait_for_pp_done(struct drm_crtc *crtc) 1185 { 1186 struct drm_device *dev = crtc->dev; 1187 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); 1188 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); 1189 int ret; 1190 1191 ret = wait_for_completion_timeout(&mdp5_crtc->pp_completion, 1192 msecs_to_jiffies(50)); 1193 if (ret == 0) 1194 dev_warn_ratelimited(dev->dev, "pp done time out, lm=%d\n", 1195 mdp5_cstate->pipeline.mixer->lm); 1196 } 1197 1198 static void mdp5_crtc_wait_for_flush_done(struct drm_crtc *crtc) 1199 { 1200 struct drm_device *dev = crtc->dev; 1201 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); 1202 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); 1203 struct mdp5_ctl *ctl = mdp5_cstate->ctl; 1204 int ret; 1205 1206 /* Should not call this function if crtc is disabled. */ 1207 if (!ctl) 1208 return; 1209 1210 ret = drm_crtc_vblank_get(crtc); 1211 if (ret) 1212 return; 1213 1214 ret = wait_event_timeout(dev->vblank[drm_crtc_index(crtc)].queue, 1215 ((mdp5_ctl_get_commit_status(ctl) & 1216 mdp5_crtc->flushed_mask) == 0), 1217 msecs_to_jiffies(50)); 1218 if (ret <= 0) 1219 dev_warn(dev->dev, "vblank time out, crtc=%d\n", mdp5_crtc->id); 1220 1221 mdp5_crtc->flushed_mask = 0; 1222 1223 drm_crtc_vblank_put(crtc); 1224 } 1225 1226 uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc) 1227 { 1228 struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); 1229 return mdp5_crtc->vblank.irqmask; 1230 } 1231 1232 void mdp5_crtc_set_pipeline(struct drm_crtc *crtc) 1233 { 1234 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); 1235 struct mdp5_kms *mdp5_kms = get_kms(crtc); 1236 1237 /* should this be done elsewhere ? */ 1238 mdp_irq_update(&mdp5_kms->base); 1239 1240 mdp5_ctl_set_pipeline(mdp5_cstate->ctl, &mdp5_cstate->pipeline); 1241 } 1242 1243 struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc) 1244 { 1245 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); 1246 1247 return mdp5_cstate->ctl; 1248 } 1249 1250 struct mdp5_hw_mixer *mdp5_crtc_get_mixer(struct drm_crtc *crtc) 1251 { 1252 struct mdp5_crtc_state *mdp5_cstate; 1253 1254 if (WARN_ON(!crtc)) 1255 return ERR_PTR(-EINVAL); 1256 1257 mdp5_cstate = to_mdp5_crtc_state(crtc->state); 1258 1259 return WARN_ON(!mdp5_cstate->pipeline.mixer) ? 1260 ERR_PTR(-EINVAL) : mdp5_cstate->pipeline.mixer; 1261 } 1262 1263 struct mdp5_pipeline *mdp5_crtc_get_pipeline(struct drm_crtc *crtc) 1264 { 1265 struct mdp5_crtc_state *mdp5_cstate; 1266 1267 if (WARN_ON(!crtc)) 1268 return ERR_PTR(-EINVAL); 1269 1270 mdp5_cstate = to_mdp5_crtc_state(crtc->state); 1271 1272 return &mdp5_cstate->pipeline; 1273 } 1274 1275 void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc) 1276 { 1277 struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); 1278 1279 if (mdp5_cstate->cmd_mode) 1280 mdp5_crtc_wait_for_pp_done(crtc); 1281 else 1282 mdp5_crtc_wait_for_flush_done(crtc); 1283 } 1284 1285 /* initialize crtc */ 1286 struct drm_crtc *mdp5_crtc_init(struct drm_device *dev, 1287 struct drm_plane *plane, 1288 struct drm_plane *cursor_plane, int id) 1289 { 1290 struct drm_crtc *crtc = NULL; 1291 struct mdp5_crtc *mdp5_crtc; 1292 1293 mdp5_crtc = kzalloc(sizeof(*mdp5_crtc), GFP_KERNEL); 1294 if (!mdp5_crtc) 1295 return ERR_PTR(-ENOMEM); 1296 1297 crtc = &mdp5_crtc->base; 1298 1299 mdp5_crtc->id = id; 1300 1301 spin_lock_init(&mdp5_crtc->lm_lock); 1302 spin_lock_init(&mdp5_crtc->cursor.lock); 1303 init_completion(&mdp5_crtc->pp_completion); 1304 1305 mdp5_crtc->vblank.irq = mdp5_crtc_vblank_irq; 1306 mdp5_crtc->err.irq = mdp5_crtc_err_irq; 1307 mdp5_crtc->pp_done.irq = mdp5_crtc_pp_done_irq; 1308 1309 mdp5_crtc->lm_cursor_enabled = cursor_plane ? false : true; 1310 1311 drm_crtc_init_with_planes(dev, crtc, plane, cursor_plane, 1312 &mdp5_crtc_funcs, NULL); 1313 1314 drm_flip_work_init(&mdp5_crtc->unref_cursor_work, 1315 "unref cursor", unref_cursor_worker); 1316 1317 drm_crtc_helper_add(crtc, &mdp5_crtc_helper_funcs); 1318 1319 return crtc; 1320 } 1321