1// SPDX-License-Identifier: GPL-2.0 2// Copyright (c) 2018, Linaro Limited 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/qcom,gcc-qcs404.h> 6#include <dt-bindings/clock/qcom,turingcc-qcs404.h> 7#include <dt-bindings/clock/qcom,rpmcc.h> 8#include <dt-bindings/power/qcom-rpmpd.h> 9#include <dt-bindings/thermal/thermal.h> 10 11/ { 12 interrupt-parent = <&intc>; 13 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 chosen { }; 18 19 clocks { 20 xo_board: xo-board { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <19200000>; 24 }; 25 26 sleep_clk: sleep-clk { 27 compatible = "fixed-clock"; 28 #clock-cells = <0>; 29 clock-frequency = <32768>; 30 }; 31 }; 32 33 cpus { 34 #address-cells = <1>; 35 #size-cells = <0>; 36 37 CPU0: cpu@100 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a53"; 40 reg = <0x100>; 41 enable-method = "psci"; 42 cpu-idle-states = <&CPU_SLEEP_0>; 43 next-level-cache = <&L2_0>; 44 #cooling-cells = <2>; 45 clocks = <&apcs_glb>; 46 operating-points-v2 = <&cpu_opp_table>; 47 power-domains = <&cpr>; 48 power-domain-names = "cpr"; 49 }; 50 51 CPU1: cpu@101 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53"; 54 reg = <0x101>; 55 enable-method = "psci"; 56 cpu-idle-states = <&CPU_SLEEP_0>; 57 next-level-cache = <&L2_0>; 58 #cooling-cells = <2>; 59 clocks = <&apcs_glb>; 60 operating-points-v2 = <&cpu_opp_table>; 61 power-domains = <&cpr>; 62 power-domain-names = "cpr"; 63 }; 64 65 CPU2: cpu@102 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a53"; 68 reg = <0x102>; 69 enable-method = "psci"; 70 cpu-idle-states = <&CPU_SLEEP_0>; 71 next-level-cache = <&L2_0>; 72 #cooling-cells = <2>; 73 clocks = <&apcs_glb>; 74 operating-points-v2 = <&cpu_opp_table>; 75 power-domains = <&cpr>; 76 power-domain-names = "cpr"; 77 }; 78 79 CPU3: cpu@103 { 80 device_type = "cpu"; 81 compatible = "arm,cortex-a53"; 82 reg = <0x103>; 83 enable-method = "psci"; 84 cpu-idle-states = <&CPU_SLEEP_0>; 85 next-level-cache = <&L2_0>; 86 #cooling-cells = <2>; 87 clocks = <&apcs_glb>; 88 operating-points-v2 = <&cpu_opp_table>; 89 power-domains = <&cpr>; 90 power-domain-names = "cpr"; 91 }; 92 93 L2_0: l2-cache { 94 compatible = "cache"; 95 cache-level = <2>; 96 }; 97 98 idle-states { 99 entry-method = "psci"; 100 101 CPU_SLEEP_0: cpu-sleep-0 { 102 compatible = "arm,idle-state"; 103 idle-state-name = "standalone-power-collapse"; 104 arm,psci-suspend-param = <0x40000003>; 105 entry-latency-us = <125>; 106 exit-latency-us = <180>; 107 min-residency-us = <595>; 108 local-timer-stop; 109 }; 110 }; 111 }; 112 113 cpu_opp_table: cpu-opp-table { 114 compatible = "operating-points-v2-kryo-cpu"; 115 opp-shared; 116 117 opp-1094400000 { 118 opp-hz = /bits/ 64 <1094400000>; 119 required-opps = <&cpr_opp1>; 120 }; 121 opp-1248000000 { 122 opp-hz = /bits/ 64 <1248000000>; 123 required-opps = <&cpr_opp2>; 124 }; 125 opp-1401600000 { 126 opp-hz = /bits/ 64 <1401600000>; 127 required-opps = <&cpr_opp3>; 128 }; 129 }; 130 131 cpr_opp_table: cpr-opp-table { 132 compatible = "operating-points-v2-qcom-level"; 133 134 cpr_opp1: opp1 { 135 opp-level = <1>; 136 qcom,opp-fuse-level = <1>; 137 }; 138 cpr_opp2: opp2 { 139 opp-level = <2>; 140 qcom,opp-fuse-level = <2>; 141 }; 142 cpr_opp3: opp3 { 143 opp-level = <3>; 144 qcom,opp-fuse-level = <3>; 145 }; 146 }; 147 148 firmware { 149 scm: scm { 150 compatible = "qcom,scm-qcs404", "qcom,scm"; 151 #reset-cells = <1>; 152 }; 153 }; 154 155 memory@80000000 { 156 device_type = "memory"; 157 /* We expect the bootloader to fill in the size */ 158 reg = <0 0x80000000 0 0>; 159 }; 160 161 psci { 162 compatible = "arm,psci-1.0"; 163 method = "smc"; 164 }; 165 166 reserved-memory { 167 #address-cells = <2>; 168 #size-cells = <2>; 169 ranges; 170 171 tz_apps_mem: memory@85900000 { 172 reg = <0 0x85900000 0 0x500000>; 173 no-map; 174 }; 175 176 xbl_mem: memory@85e00000 { 177 reg = <0 0x85e00000 0 0x100000>; 178 no-map; 179 }; 180 181 smem_region: memory@85f00000 { 182 reg = <0 0x85f00000 0 0x200000>; 183 no-map; 184 }; 185 186 tz_mem: memory@86100000 { 187 reg = <0 0x86100000 0 0x300000>; 188 no-map; 189 }; 190 191 wlan_fw_mem: memory@86400000 { 192 reg = <0 0x86400000 0 0x1100000>; 193 no-map; 194 }; 195 196 adsp_fw_mem: memory@87500000 { 197 reg = <0 0x87500000 0 0x1a00000>; 198 no-map; 199 }; 200 201 cdsp_fw_mem: memory@88f00000 { 202 reg = <0 0x88f00000 0 0x600000>; 203 no-map; 204 }; 205 206 wlan_msa_mem: memory@89500000 { 207 reg = <0 0x89500000 0 0x100000>; 208 no-map; 209 }; 210 211 uefi_mem: memory@9f800000 { 212 reg = <0 0x9f800000 0 0x800000>; 213 no-map; 214 }; 215 }; 216 217 rpm-glink { 218 compatible = "qcom,glink-rpm"; 219 220 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 221 qcom,rpm-msg-ram = <&rpm_msg_ram>; 222 mboxes = <&apcs_glb 0>; 223 224 rpm_requests: glink-channel { 225 compatible = "qcom,rpm-qcs404"; 226 qcom,glink-channels = "rpm_requests"; 227 228 rpmcc: clock-controller { 229 compatible = "qcom,rpmcc-qcs404"; 230 #clock-cells = <1>; 231 }; 232 233 rpmpd: power-controller { 234 compatible = "qcom,qcs404-rpmpd"; 235 #power-domain-cells = <1>; 236 operating-points-v2 = <&rpmpd_opp_table>; 237 238 rpmpd_opp_table: opp-table { 239 compatible = "operating-points-v2"; 240 241 rpmpd_opp_ret: opp1 { 242 opp-level = <16>; 243 }; 244 245 rpmpd_opp_ret_plus: opp2 { 246 opp-level = <32>; 247 }; 248 249 rpmpd_opp_min_svs: opp3 { 250 opp-level = <48>; 251 }; 252 253 rpmpd_opp_low_svs: opp4 { 254 opp-level = <64>; 255 }; 256 257 rpmpd_opp_svs: opp5 { 258 opp-level = <128>; 259 }; 260 261 rpmpd_opp_svs_plus: opp6 { 262 opp-level = <192>; 263 }; 264 265 rpmpd_opp_nom: opp7 { 266 opp-level = <256>; 267 }; 268 269 rpmpd_opp_nom_plus: opp8 { 270 opp-level = <320>; 271 }; 272 273 rpmpd_opp_turbo: opp9 { 274 opp-level = <384>; 275 }; 276 277 rpmpd_opp_turbo_no_cpr: opp10 { 278 opp-level = <416>; 279 }; 280 281 rpmpd_opp_turbo_plus: opp11 { 282 opp-level = <512>; 283 }; 284 }; 285 }; 286 }; 287 }; 288 289 smem { 290 compatible = "qcom,smem"; 291 292 memory-region = <&smem_region>; 293 qcom,rpm-msg-ram = <&rpm_msg_ram>; 294 295 hwlocks = <&tcsr_mutex 3>; 296 }; 297 298 tcsr_mutex: hwlock { 299 compatible = "qcom,tcsr-mutex"; 300 syscon = <&tcsr_mutex_regs 0 0x1000>; 301 #hwlock-cells = <1>; 302 }; 303 304 soc: soc@0 { 305 #address-cells = <1>; 306 #size-cells = <1>; 307 ranges = <0 0 0 0xffffffff>; 308 compatible = "simple-bus"; 309 310 turingcc: clock-controller@800000 { 311 compatible = "qcom,qcs404-turingcc"; 312 reg = <0x00800000 0x30000>; 313 clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>; 314 315 #clock-cells = <1>; 316 #reset-cells = <1>; 317 318 status = "disabled"; 319 }; 320 321 rpm_msg_ram: memory@60000 { 322 compatible = "qcom,rpm-msg-ram"; 323 reg = <0x00060000 0x6000>; 324 }; 325 326 qfprom: qfprom@a4000 { 327 compatible = "qcom,qfprom"; 328 reg = <0x000a4000 0x1000>; 329 #address-cells = <1>; 330 #size-cells = <1>; 331 tsens_caldata: caldata@d0 { 332 reg = <0x1f8 0x14>; 333 }; 334 cpr_efuse_speedbin: speedbin@13c { 335 reg = <0x13c 0x4>; 336 bits = <2 3>; 337 }; 338 cpr_efuse_quot_offset1: qoffset1@231 { 339 reg = <0x231 0x4>; 340 bits = <4 7>; 341 }; 342 cpr_efuse_quot_offset2: qoffset2@232 { 343 reg = <0x232 0x4>; 344 bits = <3 7>; 345 }; 346 cpr_efuse_quot_offset3: qoffset3@233 { 347 reg = <0x233 0x4>; 348 bits = <2 7>; 349 }; 350 cpr_efuse_init_voltage1: ivoltage1@229 { 351 reg = <0x229 0x4>; 352 bits = <4 6>; 353 }; 354 cpr_efuse_init_voltage2: ivoltage2@22a { 355 reg = <0x22a 0x4>; 356 bits = <2 6>; 357 }; 358 cpr_efuse_init_voltage3: ivoltage3@22b { 359 reg = <0x22b 0x4>; 360 bits = <0 6>; 361 }; 362 cpr_efuse_quot1: quot1@22b { 363 reg = <0x22b 0x4>; 364 bits = <6 12>; 365 }; 366 cpr_efuse_quot2: quot2@22d { 367 reg = <0x22d 0x4>; 368 bits = <2 12>; 369 }; 370 cpr_efuse_quot3: quot3@230 { 371 reg = <0x230 0x4>; 372 bits = <0 12>; 373 }; 374 cpr_efuse_ring1: ring1@228 { 375 reg = <0x228 0x4>; 376 bits = <0 3>; 377 }; 378 cpr_efuse_ring2: ring2@228 { 379 reg = <0x228 0x4>; 380 bits = <4 3>; 381 }; 382 cpr_efuse_ring3: ring3@229 { 383 reg = <0x229 0x4>; 384 bits = <0 3>; 385 }; 386 cpr_efuse_revision: revision@218 { 387 reg = <0x218 0x4>; 388 bits = <3 3>; 389 }; 390 }; 391 392 rng: rng@e3000 { 393 compatible = "qcom,prng-ee"; 394 reg = <0x000e3000 0x1000>; 395 clocks = <&gcc GCC_PRNG_AHB_CLK>; 396 clock-names = "core"; 397 }; 398 399 bimc: interconnect@400000 { 400 reg = <0x00400000 0x80000>; 401 compatible = "qcom,qcs404-bimc"; 402 #interconnect-cells = <1>; 403 clock-names = "bus", "bus_a"; 404 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 405 <&rpmcc RPM_SMD_BIMC_A_CLK>; 406 }; 407 408 tsens: thermal-sensor@4a9000 { 409 compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; 410 reg = <0x004a9000 0x1000>, /* TM */ 411 <0x004a8000 0x1000>; /* SROT */ 412 nvmem-cells = <&tsens_caldata>; 413 nvmem-cell-names = "calib"; 414 #qcom,sensors = <10>; 415 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 416 interrupt-names = "uplow"; 417 #thermal-sensor-cells = <1>; 418 }; 419 420 pcnoc: interconnect@500000 { 421 reg = <0x00500000 0x15080>; 422 compatible = "qcom,qcs404-pcnoc"; 423 #interconnect-cells = <1>; 424 clock-names = "bus", "bus_a"; 425 clocks = <&rpmcc RPM_SMD_PNOC_CLK>, 426 <&rpmcc RPM_SMD_PNOC_A_CLK>; 427 }; 428 429 snoc: interconnect@580000 { 430 reg = <0x00580000 0x23080>; 431 compatible = "qcom,qcs404-snoc"; 432 #interconnect-cells = <1>; 433 clock-names = "bus", "bus_a"; 434 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 435 <&rpmcc RPM_SMD_SNOC_A_CLK>; 436 }; 437 438 remoteproc_cdsp: remoteproc@b00000 { 439 compatible = "qcom,qcs404-cdsp-pas"; 440 reg = <0x00b00000 0x4040>; 441 442 interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, 443 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 444 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 445 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 446 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 447 interrupt-names = "wdog", "fatal", "ready", 448 "handover", "stop-ack"; 449 450 clocks = <&xo_board>, 451 <&gcc GCC_CDSP_CFG_AHB_CLK>, 452 <&gcc GCC_CDSP_TBU_CLK>, 453 <&gcc GCC_BIMC_CDSP_CLK>, 454 <&turingcc TURING_WRAPPER_AON_CLK>, 455 <&turingcc TURING_Q6SS_AHBS_AON_CLK>, 456 <&turingcc TURING_Q6SS_AHBM_AON_CLK>, 457 <&turingcc TURING_Q6SS_Q6_AXIM_CLK>; 458 clock-names = "xo", 459 "sway", 460 "tbu", 461 "bimc", 462 "ahb_aon", 463 "q6ss_slave", 464 "q6ss_master", 465 "q6_axim"; 466 467 resets = <&gcc GCC_CDSP_RESTART>; 468 reset-names = "restart"; 469 470 qcom,halt-regs = <&tcsr 0x19004>; 471 472 memory-region = <&cdsp_fw_mem>; 473 474 qcom,smem-states = <&cdsp_smp2p_out 0>; 475 qcom,smem-state-names = "stop"; 476 477 status = "disabled"; 478 479 glink-edge { 480 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>; 481 482 qcom,remote-pid = <5>; 483 mboxes = <&apcs_glb 12>; 484 485 label = "cdsp"; 486 }; 487 }; 488 489 tlmm: pinctrl@1000000 { 490 compatible = "qcom,qcs404-pinctrl"; 491 reg = <0x01000000 0x200000>, 492 <0x01300000 0x200000>, 493 <0x07b00000 0x200000>; 494 reg-names = "south", "north", "east"; 495 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 496 gpio-ranges = <&tlmm 0 0 120>; 497 gpio-controller; 498 #gpio-cells = <2>; 499 interrupt-controller; 500 #interrupt-cells = <2>; 501 502 blsp1_i2c0_default: blsp1-i2c0-default { 503 pins = "gpio32", "gpio33"; 504 function = "blsp_i2c0"; 505 }; 506 507 blsp1_i2c1_default: blsp1-i2c1-default { 508 pins = "gpio24", "gpio25"; 509 function = "blsp_i2c1"; 510 }; 511 512 blsp1_i2c2_default: blsp1-i2c2-default { 513 sda { 514 pins = "gpio19"; 515 function = "blsp_i2c_sda_a2"; 516 }; 517 518 scl { 519 pins = "gpio20"; 520 function = "blsp_i2c_scl_a2"; 521 }; 522 }; 523 524 blsp1_i2c3_default: blsp1-i2c3-default { 525 pins = "gpio84", "gpio85"; 526 function = "blsp_i2c3"; 527 }; 528 529 blsp1_i2c4_default: blsp1-i2c4-default { 530 pins = "gpio117", "gpio118"; 531 function = "blsp_i2c4"; 532 }; 533 534 blsp1_uart0_default: blsp1-uart0-default { 535 pins = "gpio30", "gpio31", "gpio32", "gpio33"; 536 function = "blsp_uart0"; 537 }; 538 539 blsp1_uart1_default: blsp1-uart1-default { 540 pins = "gpio22", "gpio23"; 541 function = "blsp_uart1"; 542 }; 543 544 blsp1_uart2_default: blsp1-uart2-default { 545 rx { 546 pins = "gpio18"; 547 function = "blsp_uart_rx_a2"; 548 }; 549 550 tx { 551 pins = "gpio17"; 552 function = "blsp_uart_tx_a2"; 553 }; 554 }; 555 556 blsp1_uart3_default: blsp1-uart3-default { 557 pins = "gpio82", "gpio83", "gpio84", "gpio85"; 558 function = "blsp_uart3"; 559 }; 560 561 blsp2_i2c0_default: blsp2-i2c0-default { 562 pins = "gpio28", "gpio29"; 563 function = "blsp_i2c5"; 564 }; 565 566 blsp1_spi0_default: blsp1-spi0-default { 567 pins = "gpio30", "gpio31", "gpio32", "gpio33"; 568 function = "blsp_spi0"; 569 }; 570 571 blsp1_spi1_default: blsp1-spi1-default { 572 pins = "gpio22", "gpio23", "gpio24", "gpio25"; 573 function = "blsp_spi1"; 574 }; 575 576 blsp1_spi2_default: blsp1-spi2-default { 577 pins = "gpio17", "gpio18", "gpio19", "gpio20"; 578 function = "blsp_spi2"; 579 }; 580 581 blsp1_spi3_default: blsp1-spi3-default { 582 pins = "gpio82", "gpio83", "gpio84", "gpio85"; 583 function = "blsp_spi3"; 584 }; 585 586 blsp1_spi4_default: blsp1-spi4-default { 587 pins = "gpio37", "gpio38", "gpio117", "gpio118"; 588 function = "blsp_spi4"; 589 }; 590 591 blsp2_spi0_default: blsp2-spi0-default { 592 pins = "gpio26", "gpio27", "gpio28", "gpio29"; 593 function = "blsp_spi5"; 594 }; 595 596 blsp2_uart0_default: blsp2-uart0-default { 597 pins = "gpio26", "gpio27", "gpio28", "gpio29"; 598 function = "blsp_uart5"; 599 }; 600 }; 601 602 gcc: clock-controller@1800000 { 603 compatible = "qcom,gcc-qcs404"; 604 reg = <0x01800000 0x80000>; 605 #clock-cells = <1>; 606 #reset-cells = <1>; 607 608 assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; 609 assigned-clock-rates = <19200000>; 610 }; 611 612 tcsr_mutex_regs: syscon@1905000 { 613 compatible = "syscon"; 614 reg = <0x01905000 0x20000>; 615 }; 616 617 tcsr: syscon@1937000 { 618 compatible = "syscon"; 619 reg = <0x01937000 0x25000>; 620 }; 621 622 spmi_bus: spmi@200f000 { 623 compatible = "qcom,spmi-pmic-arb"; 624 reg = <0x0200f000 0x001000>, 625 <0x02400000 0x800000>, 626 <0x02c00000 0x800000>, 627 <0x03800000 0x200000>, 628 <0x0200a000 0x002100>; 629 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 630 interrupt-names = "periph_irq"; 631 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 632 qcom,ee = <0>; 633 qcom,channel = <0>; 634 #address-cells = <2>; 635 #size-cells = <0>; 636 interrupt-controller; 637 #interrupt-cells = <4>; 638 }; 639 640 remoteproc_wcss: remoteproc@7400000 { 641 compatible = "qcom,qcs404-wcss-pas"; 642 reg = <0x07400000 0x4040>; 643 644 interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>, 645 <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 646 <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 647 <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 648 <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 649 interrupt-names = "wdog", "fatal", "ready", 650 "handover", "stop-ack"; 651 652 clocks = <&xo_board>; 653 clock-names = "xo"; 654 655 memory-region = <&wlan_fw_mem>; 656 657 qcom,smem-states = <&wcss_smp2p_out 0>; 658 qcom,smem-state-names = "stop"; 659 660 status = "disabled"; 661 662 glink-edge { 663 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 664 665 qcom,remote-pid = <1>; 666 mboxes = <&apcs_glb 16>; 667 668 label = "wcss"; 669 }; 670 }; 671 672 pcie_phy: phy@7786000 { 673 compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; 674 reg = <0x07786000 0xb8>; 675 676 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 677 resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, 678 <&gcc 21>; 679 reset-names = "phy", "pipe"; 680 681 clock-output-names = "pcie_0_pipe_clk"; 682 #phy-cells = <0>; 683 684 status = "disabled"; 685 }; 686 687 sdcc1: sdcc@7804000 { 688 compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5"; 689 reg = <0x07804000 0x1000>, <0x7805000 0x1000>; 690 reg-names = "hc", "cqhci"; 691 692 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 693 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 694 interrupt-names = "hc_irq", "pwr_irq"; 695 696 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 697 <&gcc GCC_SDCC1_AHB_CLK>, 698 <&xo_board>; 699 clock-names = "core", "iface", "xo"; 700 701 status = "disabled"; 702 }; 703 704 blsp1_dma: dma@7884000 { 705 compatible = "qcom,bam-v1.7.0"; 706 reg = <0x07884000 0x25000>; 707 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 708 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 709 clock-names = "bam_clk"; 710 #dma-cells = <1>; 711 qcom,ee = <0>; 712 status = "okay"; 713 }; 714 715 blsp1_uart0: serial@78af000 { 716 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 717 reg = <0x078af000 0x200>; 718 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 719 clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 720 clock-names = "core", "iface"; 721 dmas = <&blsp1_dma 1>, <&blsp1_dma 0>; 722 dma-names = "rx", "tx"; 723 pinctrl-names = "default"; 724 pinctrl-0 = <&blsp1_uart0_default>; 725 status = "disabled"; 726 }; 727 728 blsp1_uart1: serial@78b0000 { 729 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 730 reg = <0x078b0000 0x200>; 731 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 732 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 733 clock-names = "core", "iface"; 734 dmas = <&blsp1_dma 3>, <&blsp1_dma 2>; 735 dma-names = "rx", "tx"; 736 pinctrl-names = "default"; 737 pinctrl-0 = <&blsp1_uart1_default>; 738 status = "disabled"; 739 }; 740 741 blsp1_uart2: serial@78b1000 { 742 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 743 reg = <0x078b1000 0x200>; 744 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 745 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 746 clock-names = "core", "iface"; 747 dmas = <&blsp1_dma 5>, <&blsp1_dma 4>; 748 dma-names = "rx", "tx"; 749 pinctrl-names = "default"; 750 pinctrl-0 = <&blsp1_uart2_default>; 751 status = "okay"; 752 }; 753 754 ethernet: ethernet@7a80000 { 755 compatible = "qcom,qcs404-ethqos"; 756 reg = <0x07a80000 0x10000>, 757 <0x07a96000 0x100>; 758 reg-names = "stmmaceth", "rgmii"; 759 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; 760 clocks = <&gcc GCC_ETH_AXI_CLK>, 761 <&gcc GCC_ETH_SLAVE_AHB_CLK>, 762 <&gcc GCC_ETH_PTP_CLK>, 763 <&gcc GCC_ETH_RGMII_CLK>; 764 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 766 interrupt-names = "macirq", "eth_lpi"; 767 768 snps,tso; 769 rx-fifo-depth = <4096>; 770 tx-fifo-depth = <4096>; 771 772 status = "disabled"; 773 }; 774 775 wifi: wifi@a000000 { 776 compatible = "qcom,wcn3990-wifi"; 777 reg = <0xa000000 0x800000>; 778 reg-names = "membase"; 779 memory-region = <&wlan_msa_mem>; 780 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 791 <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 792 status = "disabled"; 793 }; 794 795 blsp1_uart3: serial@78b2000 { 796 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 797 reg = <0x078b2000 0x200>; 798 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 799 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 800 clock-names = "core", "iface"; 801 dmas = <&blsp1_dma 7>, <&blsp1_dma 6>; 802 dma-names = "rx", "tx"; 803 pinctrl-names = "default"; 804 pinctrl-0 = <&blsp1_uart3_default>; 805 status = "disabled"; 806 }; 807 808 blsp1_i2c0: i2c@78b5000 { 809 compatible = "qcom,i2c-qup-v2.2.1"; 810 reg = <0x078b5000 0x600>; 811 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 812 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 813 <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>; 814 clock-names = "iface", "core"; 815 pinctrl-names = "default"; 816 pinctrl-0 = <&blsp1_i2c0_default>; 817 #address-cells = <1>; 818 #size-cells = <0>; 819 status = "disabled"; 820 }; 821 822 blsp1_spi0: spi@78b5000 { 823 compatible = "qcom,spi-qup-v2.2.1"; 824 reg = <0x078b5000 0x600>; 825 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 826 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 827 <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>; 828 clock-names = "iface", "core"; 829 pinctrl-names = "default"; 830 pinctrl-0 = <&blsp1_spi0_default>; 831 #address-cells = <1>; 832 #size-cells = <0>; 833 status = "disabled"; 834 }; 835 836 blsp1_i2c1: i2c@78b6000 { 837 compatible = "qcom,i2c-qup-v2.2.1"; 838 reg = <0x078b6000 0x600>; 839 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 840 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 841 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; 842 clock-names = "iface", "core"; 843 pinctrl-names = "default"; 844 pinctrl-0 = <&blsp1_i2c1_default>; 845 #address-cells = <1>; 846 #size-cells = <0>; 847 status = "disabled"; 848 }; 849 850 blsp1_spi1: spi@78b6000 { 851 compatible = "qcom,spi-qup-v2.2.1"; 852 reg = <0x078b6000 0x600>; 853 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 854 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 855 <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>; 856 clock-names = "iface", "core"; 857 pinctrl-names = "default"; 858 pinctrl-0 = <&blsp1_spi1_default>; 859 #address-cells = <1>; 860 #size-cells = <0>; 861 status = "disabled"; 862 }; 863 864 blsp1_i2c2: i2c@78b7000 { 865 compatible = "qcom,i2c-qup-v2.2.1"; 866 reg = <0x078b7000 0x600>; 867 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 868 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 869 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 870 clock-names = "iface", "core"; 871 pinctrl-names = "default"; 872 pinctrl-0 = <&blsp1_i2c2_default>; 873 #address-cells = <1>; 874 #size-cells = <0>; 875 status = "disabled"; 876 }; 877 878 blsp1_spi2: spi@78b7000 { 879 compatible = "qcom,spi-qup-v2.2.1"; 880 reg = <0x078b7000 0x600>; 881 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 882 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 883 <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>; 884 clock-names = "iface", "core"; 885 pinctrl-names = "default"; 886 pinctrl-0 = <&blsp1_spi2_default>; 887 #address-cells = <1>; 888 #size-cells = <0>; 889 status = "disabled"; 890 }; 891 892 blsp1_i2c3: i2c@78b8000 { 893 compatible = "qcom,i2c-qup-v2.2.1"; 894 reg = <0x078b8000 0x600>; 895 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 896 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 897 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 898 clock-names = "iface", "core"; 899 pinctrl-names = "default"; 900 pinctrl-0 = <&blsp1_i2c3_default>; 901 #address-cells = <1>; 902 #size-cells = <0>; 903 status = "disabled"; 904 }; 905 906 blsp1_spi3: spi@78b8000 { 907 compatible = "qcom,spi-qup-v2.2.1"; 908 reg = <0x078b8000 0x600>; 909 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 910 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 911 <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>; 912 clock-names = "iface", "core"; 913 pinctrl-names = "default"; 914 pinctrl-0 = <&blsp1_spi3_default>; 915 #address-cells = <1>; 916 #size-cells = <0>; 917 status = "disabled"; 918 }; 919 920 blsp1_i2c4: i2c@78b9000 { 921 compatible = "qcom,i2c-qup-v2.2.1"; 922 reg = <0x078b9000 0x600>; 923 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 924 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 925 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; 926 clock-names = "iface", "core"; 927 pinctrl-names = "default"; 928 pinctrl-0 = <&blsp1_i2c4_default>; 929 #address-cells = <1>; 930 #size-cells = <0>; 931 status = "disabled"; 932 }; 933 934 blsp1_spi4: spi@78b9000 { 935 compatible = "qcom,spi-qup-v2.2.1"; 936 reg = <0x078b9000 0x600>; 937 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 938 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 939 <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>; 940 clock-names = "iface", "core"; 941 pinctrl-names = "default"; 942 pinctrl-0 = <&blsp1_spi4_default>; 943 #address-cells = <1>; 944 #size-cells = <0>; 945 status = "disabled"; 946 }; 947 948 blsp2_dma: dma@7ac4000 { 949 compatible = "qcom,bam-v1.7.0"; 950 reg = <0x07ac4000 0x17000>; 951 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 952 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 953 clock-names = "bam_clk"; 954 #dma-cells = <1>; 955 qcom,ee = <0>; 956 status = "disabled"; 957 }; 958 959 blsp2_uart0: serial@7aef000 { 960 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 961 reg = <0x07aef000 0x200>; 962 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 963 clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 964 clock-names = "core", "iface"; 965 dmas = <&blsp2_dma 1>, <&blsp2_dma 0>; 966 dma-names = "rx", "tx"; 967 pinctrl-names = "default"; 968 pinctrl-0 = <&blsp2_uart0_default>; 969 status = "disabled"; 970 }; 971 972 blsp2_i2c0: i2c@7af5000 { 973 compatible = "qcom,i2c-qup-v2.2.1"; 974 reg = <0x07af5000 0x600>; 975 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 976 clocks = <&gcc GCC_BLSP2_AHB_CLK>, 977 <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>; 978 clock-names = "iface", "core"; 979 pinctrl-names = "default"; 980 pinctrl-0 = <&blsp2_i2c0_default>; 981 #address-cells = <1>; 982 #size-cells = <0>; 983 status = "disabled"; 984 }; 985 986 blsp2_spi0: spi@7af5000 { 987 compatible = "qcom,spi-qup-v2.2.1"; 988 reg = <0x07af5000 0x600>; 989 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 990 clocks = <&gcc GCC_BLSP2_AHB_CLK>, 991 <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>; 992 clock-names = "iface", "core"; 993 pinctrl-names = "default"; 994 pinctrl-0 = <&blsp2_spi0_default>; 995 #address-cells = <1>; 996 #size-cells = <0>; 997 status = "disabled"; 998 }; 999 1000 intc: interrupt-controller@b000000 { 1001 compatible = "qcom,msm-qgic2"; 1002 interrupt-controller; 1003 #interrupt-cells = <3>; 1004 reg = <0x0b000000 0x1000>, 1005 <0x0b002000 0x1000>; 1006 }; 1007 1008 apcs_glb: mailbox@b011000 { 1009 compatible = "qcom,qcs404-apcs-apps-global", "syscon"; 1010 reg = <0x0b011000 0x1000>; 1011 #mbox-cells = <1>; 1012 clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>; 1013 clock-names = "pll", "aux"; 1014 #clock-cells = <0>; 1015 }; 1016 1017 apcs_hfpll: clock-controller@b016000 { 1018 compatible = "qcom,hfpll"; 1019 reg = <0x0b016000 0x30>; 1020 #clock-cells = <0>; 1021 clock-output-names = "apcs_hfpll"; 1022 clocks = <&xo_board>; 1023 clock-names = "xo"; 1024 }; 1025 1026 watchdog@b017000 { 1027 compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt"; 1028 reg = <0x0b017000 0x1000>; 1029 clocks = <&sleep_clk>; 1030 }; 1031 1032 cpr: power-controller@b018000 { 1033 compatible = "qcom,qcs404-cpr", "qcom,cpr"; 1034 reg = <0x0b018000 0x1000>; 1035 interrupts = <0 15 IRQ_TYPE_EDGE_RISING>; 1036 clocks = <&xo_board>; 1037 clock-names = "ref"; 1038 vdd-apc-supply = <&pms405_s3>; 1039 #power-domain-cells = <0>; 1040 operating-points-v2 = <&cpr_opp_table>; 1041 acc-syscon = <&tcsr>; 1042 1043 nvmem-cells = <&cpr_efuse_quot_offset1>, 1044 <&cpr_efuse_quot_offset2>, 1045 <&cpr_efuse_quot_offset3>, 1046 <&cpr_efuse_init_voltage1>, 1047 <&cpr_efuse_init_voltage2>, 1048 <&cpr_efuse_init_voltage3>, 1049 <&cpr_efuse_quot1>, 1050 <&cpr_efuse_quot2>, 1051 <&cpr_efuse_quot3>, 1052 <&cpr_efuse_ring1>, 1053 <&cpr_efuse_ring2>, 1054 <&cpr_efuse_ring3>, 1055 <&cpr_efuse_revision>; 1056 nvmem-cell-names = "cpr_quotient_offset1", 1057 "cpr_quotient_offset2", 1058 "cpr_quotient_offset3", 1059 "cpr_init_voltage1", 1060 "cpr_init_voltage2", 1061 "cpr_init_voltage3", 1062 "cpr_quotient1", 1063 "cpr_quotient2", 1064 "cpr_quotient3", 1065 "cpr_ring_osc1", 1066 "cpr_ring_osc2", 1067 "cpr_ring_osc3", 1068 "cpr_fuse_revision"; 1069 }; 1070 1071 timer@b120000 { 1072 #address-cells = <1>; 1073 #size-cells = <1>; 1074 ranges; 1075 compatible = "arm,armv7-timer-mem"; 1076 reg = <0x0b120000 0x1000>; 1077 clock-frequency = <19200000>; 1078 1079 frame@b121000 { 1080 frame-number = <0>; 1081 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1082 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1083 reg = <0x0b121000 0x1000>, 1084 <0x0b122000 0x1000>; 1085 }; 1086 1087 frame@b123000 { 1088 frame-number = <1>; 1089 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1090 reg = <0x0b123000 0x1000>; 1091 status = "disabled"; 1092 }; 1093 1094 frame@b124000 { 1095 frame-number = <2>; 1096 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1097 reg = <0x0b124000 0x1000>; 1098 status = "disabled"; 1099 }; 1100 1101 frame@b125000 { 1102 frame-number = <3>; 1103 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1104 reg = <0x0b125000 0x1000>; 1105 status = "disabled"; 1106 }; 1107 1108 frame@b126000 { 1109 frame-number = <4>; 1110 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1111 reg = <0x0b126000 0x1000>; 1112 status = "disabled"; 1113 }; 1114 1115 frame@b127000 { 1116 frame-number = <5>; 1117 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1118 reg = <0xb127000 0x1000>; 1119 status = "disabled"; 1120 }; 1121 1122 frame@b128000 { 1123 frame-number = <6>; 1124 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1125 reg = <0x0b128000 0x1000>; 1126 status = "disabled"; 1127 }; 1128 }; 1129 1130 remoteproc_adsp: remoteproc@c700000 { 1131 compatible = "qcom,qcs404-adsp-pas"; 1132 reg = <0x0c700000 0x4040>; 1133 1134 interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>, 1135 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1136 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1137 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1138 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1139 interrupt-names = "wdog", "fatal", "ready", 1140 "handover", "stop-ack"; 1141 1142 clocks = <&xo_board>; 1143 clock-names = "xo"; 1144 1145 memory-region = <&adsp_fw_mem>; 1146 1147 qcom,smem-states = <&adsp_smp2p_out 0>; 1148 qcom,smem-state-names = "stop"; 1149 1150 status = "disabled"; 1151 1152 glink-edge { 1153 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; 1154 1155 qcom,remote-pid = <2>; 1156 mboxes = <&apcs_glb 8>; 1157 1158 label = "adsp"; 1159 }; 1160 }; 1161 1162 pcie: pci@10000000 { 1163 compatible = "qcom,pcie-qcs404", "snps,dw-pcie"; 1164 reg = <0x10000000 0xf1d>, 1165 <0x10000f20 0xa8>, 1166 <0x07780000 0x2000>, 1167 <0x10001000 0x2000>; 1168 reg-names = "dbi", "elbi", "parf", "config"; 1169 device_type = "pci"; 1170 linux,pci-domain = <0>; 1171 bus-range = <0x00 0xff>; 1172 num-lanes = <1>; 1173 #address-cells = <3>; 1174 #size-cells = <2>; 1175 1176 ranges = <0x81000000 0 0 0x10003000 0 0x00010000>, /* I/O */ 1177 <0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */ 1178 1179 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1180 interrupt-names = "msi"; 1181 #interrupt-cells = <1>; 1182 interrupt-map-mask = <0 0 0 0x7>; 1183 interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1184 <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1185 <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1186 <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1187 clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1188 <&gcc GCC_PCIE_0_AUX_CLK>, 1189 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1190 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 1191 clock-names = "iface", "aux", "master_bus", "slave_bus"; 1192 1193 resets = <&gcc 18>, 1194 <&gcc 17>, 1195 <&gcc 15>, 1196 <&gcc 19>, 1197 <&gcc GCC_PCIE_0_BCR>, 1198 <&gcc 16>; 1199 reset-names = "axi_m", 1200 "axi_s", 1201 "axi_m_sticky", 1202 "pipe_sticky", 1203 "pwr", 1204 "ahb"; 1205 1206 phys = <&pcie_phy>; 1207 phy-names = "pciephy"; 1208 1209 status = "disabled"; 1210 }; 1211 }; 1212 1213 timer { 1214 compatible = "arm,armv8-timer"; 1215 interrupts = <GIC_PPI 2 0xff08>, 1216 <GIC_PPI 3 0xff08>, 1217 <GIC_PPI 4 0xff08>, 1218 <GIC_PPI 1 0xff08>; 1219 }; 1220 1221 smp2p-adsp { 1222 compatible = "qcom,smp2p"; 1223 qcom,smem = <443>, <429>; 1224 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>; 1225 mboxes = <&apcs_glb 10>; 1226 qcom,local-pid = <0>; 1227 qcom,remote-pid = <2>; 1228 1229 adsp_smp2p_out: master-kernel { 1230 qcom,entry-name = "master-kernel"; 1231 #qcom,smem-state-cells = <1>; 1232 }; 1233 1234 adsp_smp2p_in: slave-kernel { 1235 qcom,entry-name = "slave-kernel"; 1236 interrupt-controller; 1237 #interrupt-cells = <2>; 1238 }; 1239 }; 1240 1241 smp2p-cdsp { 1242 compatible = "qcom,smp2p"; 1243 qcom,smem = <94>, <432>; 1244 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 1245 mboxes = <&apcs_glb 14>; 1246 qcom,local-pid = <0>; 1247 qcom,remote-pid = <5>; 1248 1249 cdsp_smp2p_out: master-kernel { 1250 qcom,entry-name = "master-kernel"; 1251 #qcom,smem-state-cells = <1>; 1252 }; 1253 1254 cdsp_smp2p_in: slave-kernel { 1255 qcom,entry-name = "slave-kernel"; 1256 interrupt-controller; 1257 #interrupt-cells = <2>; 1258 }; 1259 }; 1260 1261 smp2p-wcss { 1262 compatible = "qcom,smp2p"; 1263 qcom,smem = <435>, <428>; 1264 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 1265 mboxes = <&apcs_glb 18>; 1266 qcom,local-pid = <0>; 1267 qcom,remote-pid = <1>; 1268 1269 wcss_smp2p_out: master-kernel { 1270 qcom,entry-name = "master-kernel"; 1271 #qcom,smem-state-cells = <1>; 1272 }; 1273 1274 wcss_smp2p_in: slave-kernel { 1275 qcom,entry-name = "slave-kernel"; 1276 interrupt-controller; 1277 #interrupt-cells = <2>; 1278 }; 1279 }; 1280 1281 thermal-zones { 1282 aoss-thermal { 1283 polling-delay-passive = <250>; 1284 polling-delay = <1000>; 1285 1286 thermal-sensors = <&tsens 0>; 1287 1288 trips { 1289 aoss_alert0: trip-point0 { 1290 temperature = <105000>; 1291 hysteresis = <2000>; 1292 type = "hot"; 1293 }; 1294 }; 1295 }; 1296 1297 q6-hvx-thermal { 1298 polling-delay-passive = <250>; 1299 polling-delay = <1000>; 1300 1301 thermal-sensors = <&tsens 1>; 1302 1303 trips { 1304 q6_hvx_alert0: trip-point0 { 1305 temperature = <105000>; 1306 hysteresis = <2000>; 1307 type = "hot"; 1308 }; 1309 }; 1310 }; 1311 1312 lpass-thermal { 1313 polling-delay-passive = <250>; 1314 polling-delay = <1000>; 1315 1316 thermal-sensors = <&tsens 2>; 1317 1318 trips { 1319 lpass_alert0: trip-point0 { 1320 temperature = <105000>; 1321 hysteresis = <2000>; 1322 type = "hot"; 1323 }; 1324 }; 1325 }; 1326 1327 wlan-thermal { 1328 polling-delay-passive = <250>; 1329 polling-delay = <1000>; 1330 1331 thermal-sensors = <&tsens 3>; 1332 1333 trips { 1334 wlan_alert0: trip-point0 { 1335 temperature = <105000>; 1336 hysteresis = <2000>; 1337 type = "hot"; 1338 }; 1339 }; 1340 }; 1341 1342 cluster-thermal { 1343 polling-delay-passive = <250>; 1344 polling-delay = <1000>; 1345 1346 thermal-sensors = <&tsens 4>; 1347 1348 trips { 1349 cluster_alert0: trip-point0 { 1350 temperature = <95000>; 1351 hysteresis = <2000>; 1352 type = "hot"; 1353 }; 1354 cluster_alert1: trip-point1 { 1355 temperature = <105000>; 1356 hysteresis = <2000>; 1357 type = "passive"; 1358 }; 1359 cluster_crit: cluster_crit { 1360 temperature = <120000>; 1361 hysteresis = <2000>; 1362 type = "critical"; 1363 }; 1364 }; 1365 cooling-maps { 1366 map0 { 1367 trip = <&cluster_alert1>; 1368 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1369 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1370 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1371 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1372 }; 1373 }; 1374 }; 1375 1376 cpu0-thermal { 1377 polling-delay-passive = <250>; 1378 polling-delay = <1000>; 1379 1380 thermal-sensors = <&tsens 5>; 1381 1382 trips { 1383 cpu0_alert0: trip-point0 { 1384 temperature = <95000>; 1385 hysteresis = <2000>; 1386 type = "hot"; 1387 }; 1388 cpu0_alert1: trip-point1 { 1389 temperature = <105000>; 1390 hysteresis = <2000>; 1391 type = "passive"; 1392 }; 1393 cpu0_crit: cpu_crit { 1394 temperature = <120000>; 1395 hysteresis = <2000>; 1396 type = "critical"; 1397 }; 1398 }; 1399 cooling-maps { 1400 map0 { 1401 trip = <&cpu0_alert1>; 1402 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1403 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1404 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1405 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1406 }; 1407 }; 1408 }; 1409 1410 cpu1-thermal { 1411 polling-delay-passive = <250>; 1412 polling-delay = <1000>; 1413 1414 thermal-sensors = <&tsens 6>; 1415 1416 trips { 1417 cpu1_alert0: trip-point0 { 1418 temperature = <95000>; 1419 hysteresis = <2000>; 1420 type = "hot"; 1421 }; 1422 cpu1_alert1: trip-point1 { 1423 temperature = <105000>; 1424 hysteresis = <2000>; 1425 type = "passive"; 1426 }; 1427 cpu1_crit: cpu_crit { 1428 temperature = <120000>; 1429 hysteresis = <2000>; 1430 type = "critical"; 1431 }; 1432 }; 1433 cooling-maps { 1434 map0 { 1435 trip = <&cpu1_alert1>; 1436 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1437 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1438 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1439 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1440 }; 1441 }; 1442 }; 1443 1444 cpu2-thermal { 1445 polling-delay-passive = <250>; 1446 polling-delay = <1000>; 1447 1448 thermal-sensors = <&tsens 7>; 1449 1450 trips { 1451 cpu2_alert0: trip-point0 { 1452 temperature = <95000>; 1453 hysteresis = <2000>; 1454 type = "hot"; 1455 }; 1456 cpu2_alert1: trip-point1 { 1457 temperature = <105000>; 1458 hysteresis = <2000>; 1459 type = "passive"; 1460 }; 1461 cpu2_crit: cpu_crit { 1462 temperature = <120000>; 1463 hysteresis = <2000>; 1464 type = "critical"; 1465 }; 1466 }; 1467 cooling-maps { 1468 map0 { 1469 trip = <&cpu2_alert1>; 1470 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1471 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1472 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1473 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1474 }; 1475 }; 1476 }; 1477 1478 cpu3-thermal { 1479 polling-delay-passive = <250>; 1480 polling-delay = <1000>; 1481 1482 thermal-sensors = <&tsens 8>; 1483 1484 trips { 1485 cpu3_alert0: trip-point0 { 1486 temperature = <95000>; 1487 hysteresis = <2000>; 1488 type = "hot"; 1489 }; 1490 cpu3_alert1: trip-point1 { 1491 temperature = <105000>; 1492 hysteresis = <2000>; 1493 type = "passive"; 1494 }; 1495 cpu3_crit: cpu_crit { 1496 temperature = <120000>; 1497 hysteresis = <2000>; 1498 type = "critical"; 1499 }; 1500 }; 1501 cooling-maps { 1502 map0 { 1503 trip = <&cpu3_alert1>; 1504 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1505 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1506 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1507 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1508 }; 1509 }; 1510 }; 1511 1512 gpu-thermal { 1513 polling-delay-passive = <250>; 1514 polling-delay = <1000>; 1515 1516 thermal-sensors = <&tsens 9>; 1517 1518 trips { 1519 gpu_alert0: trip-point0 { 1520 temperature = <95000>; 1521 hysteresis = <2000>; 1522 type = "hot"; 1523 }; 1524 }; 1525 }; 1526 }; 1527}; 1528