1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <drm/drm_print.h> 26 #include <drm/i915_pciids.h> 27 28 #include "display/intel_cdclk.h" 29 #include "intel_device_info.h" 30 #include "i915_drv.h" 31 32 #define PLATFORM_NAME(x) [INTEL_##x] = #x 33 static const char * const platform_names[] = { 34 PLATFORM_NAME(I830), 35 PLATFORM_NAME(I845G), 36 PLATFORM_NAME(I85X), 37 PLATFORM_NAME(I865G), 38 PLATFORM_NAME(I915G), 39 PLATFORM_NAME(I915GM), 40 PLATFORM_NAME(I945G), 41 PLATFORM_NAME(I945GM), 42 PLATFORM_NAME(G33), 43 PLATFORM_NAME(PINEVIEW), 44 PLATFORM_NAME(I965G), 45 PLATFORM_NAME(I965GM), 46 PLATFORM_NAME(G45), 47 PLATFORM_NAME(GM45), 48 PLATFORM_NAME(IRONLAKE), 49 PLATFORM_NAME(SANDYBRIDGE), 50 PLATFORM_NAME(IVYBRIDGE), 51 PLATFORM_NAME(VALLEYVIEW), 52 PLATFORM_NAME(HASWELL), 53 PLATFORM_NAME(BROADWELL), 54 PLATFORM_NAME(CHERRYVIEW), 55 PLATFORM_NAME(SKYLAKE), 56 PLATFORM_NAME(BROXTON), 57 PLATFORM_NAME(KABYLAKE), 58 PLATFORM_NAME(GEMINILAKE), 59 PLATFORM_NAME(COFFEELAKE), 60 PLATFORM_NAME(CANNONLAKE), 61 PLATFORM_NAME(ICELAKE), 62 PLATFORM_NAME(ELKHARTLAKE), 63 PLATFORM_NAME(TIGERLAKE), 64 }; 65 #undef PLATFORM_NAME 66 67 const char *intel_platform_name(enum intel_platform platform) 68 { 69 BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS); 70 71 if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) || 72 platform_names[platform] == NULL)) 73 return "<unknown>"; 74 75 return platform_names[platform]; 76 } 77 78 static const char *iommu_name(void) 79 { 80 const char *msg = "n/a"; 81 82 #ifdef CONFIG_INTEL_IOMMU 83 msg = enableddisabled(intel_iommu_gfx_mapped); 84 #endif 85 86 return msg; 87 } 88 89 void intel_device_info_print_static(const struct intel_device_info *info, 90 struct drm_printer *p) 91 { 92 drm_printf(p, "engines: %x\n", info->engine_mask); 93 drm_printf(p, "gen: %d\n", info->gen); 94 drm_printf(p, "gt: %d\n", info->gt); 95 drm_printf(p, "iommu: %s\n", iommu_name()); 96 drm_printf(p, "memory-regions: %x\n", info->memory_regions); 97 drm_printf(p, "page-sizes: %x\n", info->page_sizes); 98 drm_printf(p, "platform: %s\n", intel_platform_name(info->platform)); 99 drm_printf(p, "ppgtt-size: %d\n", info->ppgtt_size); 100 drm_printf(p, "ppgtt-type: %d\n", info->ppgtt_type); 101 drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size); 102 103 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name)); 104 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); 105 #undef PRINT_FLAG 106 107 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->display.name)); 108 DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG); 109 #undef PRINT_FLAG 110 } 111 112 static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p) 113 { 114 int s; 115 116 drm_printf(p, "slice total: %u, mask=%04x\n", 117 hweight8(sseu->slice_mask), sseu->slice_mask); 118 drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu)); 119 for (s = 0; s < sseu->max_slices; s++) { 120 drm_printf(p, "slice%d: %u subslices, mask=%08x\n", 121 s, intel_sseu_subslices_per_slice(sseu, s), 122 intel_sseu_get_subslices(sseu, s)); 123 } 124 drm_printf(p, "EU total: %u\n", sseu->eu_total); 125 drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice); 126 drm_printf(p, "has slice power gating: %s\n", 127 yesno(sseu->has_slice_pg)); 128 drm_printf(p, "has subslice power gating: %s\n", 129 yesno(sseu->has_subslice_pg)); 130 drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg)); 131 } 132 133 void intel_device_info_print_runtime(const struct intel_runtime_info *info, 134 struct drm_printer *p) 135 { 136 sseu_dump(&info->sseu, p); 137 138 drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq); 139 drm_printf(p, "CS timestamp frequency: %u Hz\n", 140 info->cs_timestamp_frequency_hz); 141 } 142 143 static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice, 144 int subslice) 145 { 146 int slice_stride = sseu->max_subslices * sseu->eu_stride; 147 148 return slice * slice_stride + subslice * sseu->eu_stride; 149 } 150 151 static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice, 152 int subslice) 153 { 154 int i, offset = sseu_eu_idx(sseu, slice, subslice); 155 u16 eu_mask = 0; 156 157 for (i = 0; i < sseu->eu_stride; i++) { 158 eu_mask |= ((u16)sseu->eu_mask[offset + i]) << 159 (i * BITS_PER_BYTE); 160 } 161 162 return eu_mask; 163 } 164 165 static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice, 166 u16 eu_mask) 167 { 168 int i, offset = sseu_eu_idx(sseu, slice, subslice); 169 170 for (i = 0; i < sseu->eu_stride; i++) { 171 sseu->eu_mask[offset + i] = 172 (eu_mask >> (BITS_PER_BYTE * i)) & 0xff; 173 } 174 } 175 176 void intel_device_info_print_topology(const struct sseu_dev_info *sseu, 177 struct drm_printer *p) 178 { 179 int s, ss; 180 181 if (sseu->max_slices == 0) { 182 drm_printf(p, "Unavailable\n"); 183 return; 184 } 185 186 for (s = 0; s < sseu->max_slices; s++) { 187 drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n", 188 s, intel_sseu_subslices_per_slice(sseu, s), 189 intel_sseu_get_subslices(sseu, s)); 190 191 for (ss = 0; ss < sseu->max_subslices; ss++) { 192 u16 enabled_eus = sseu_get_eus(sseu, s, ss); 193 194 drm_printf(p, "\tsubslice%d: %u EUs (0x%hx)\n", 195 ss, hweight16(enabled_eus), enabled_eus); 196 } 197 } 198 } 199 200 static u16 compute_eu_total(const struct sseu_dev_info *sseu) 201 { 202 u16 i, total = 0; 203 204 for (i = 0; i < ARRAY_SIZE(sseu->eu_mask); i++) 205 total += hweight8(sseu->eu_mask[i]); 206 207 return total; 208 } 209 210 static void gen11_compute_sseu_info(struct sseu_dev_info *sseu, 211 u8 s_en, u32 ss_en, u16 eu_en) 212 { 213 int s, ss; 214 215 /* ss_en represents entire subslice mask across all slices */ 216 GEM_BUG_ON(sseu->max_slices * sseu->max_subslices > 217 sizeof(ss_en) * BITS_PER_BYTE); 218 219 for (s = 0; s < sseu->max_slices; s++) { 220 if ((s_en & BIT(s)) == 0) 221 continue; 222 223 sseu->slice_mask |= BIT(s); 224 225 intel_sseu_set_subslices(sseu, s, ss_en); 226 227 for (ss = 0; ss < sseu->max_subslices; ss++) 228 if (intel_sseu_has_subslice(sseu, s, ss)) 229 sseu_set_eus(sseu, s, ss, eu_en); 230 } 231 sseu->eu_per_subslice = hweight16(eu_en); 232 sseu->eu_total = compute_eu_total(sseu); 233 } 234 235 static void gen12_sseu_info_init(struct drm_i915_private *dev_priv) 236 { 237 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; 238 u8 s_en; 239 u32 dss_en; 240 u16 eu_en = 0; 241 u8 eu_en_fuse; 242 int eu; 243 244 /* 245 * Gen12 has Dual-Subslices, which behave similarly to 2 gen11 SS. 246 * Instead of splitting these, provide userspace with an array 247 * of DSS to more closely represent the hardware resource. 248 */ 249 intel_sseu_set_info(sseu, 1, 6, 16); 250 251 s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK; 252 253 dss_en = I915_READ(GEN12_GT_DSS_ENABLE); 254 255 /* one bit per pair of EUs */ 256 eu_en_fuse = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK); 257 for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++) 258 if (eu_en_fuse & BIT(eu)) 259 eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1); 260 261 gen11_compute_sseu_info(sseu, s_en, dss_en, eu_en); 262 263 /* TGL only supports slice-level power gating */ 264 sseu->has_slice_pg = 1; 265 } 266 267 static void gen11_sseu_info_init(struct drm_i915_private *dev_priv) 268 { 269 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; 270 u8 s_en; 271 u32 ss_en; 272 u8 eu_en; 273 274 if (IS_ELKHARTLAKE(dev_priv)) 275 intel_sseu_set_info(sseu, 1, 4, 8); 276 else 277 intel_sseu_set_info(sseu, 1, 8, 8); 278 279 s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK; 280 ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE); 281 eu_en = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK); 282 283 gen11_compute_sseu_info(sseu, s_en, ss_en, eu_en); 284 285 /* ICL has no power gating restrictions. */ 286 sseu->has_slice_pg = 1; 287 sseu->has_subslice_pg = 1; 288 sseu->has_eu_pg = 1; 289 } 290 291 static void gen10_sseu_info_init(struct drm_i915_private *dev_priv) 292 { 293 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; 294 const u32 fuse2 = I915_READ(GEN8_FUSE2); 295 int s, ss; 296 const int eu_mask = 0xff; 297 u32 subslice_mask, eu_en; 298 299 intel_sseu_set_info(sseu, 6, 4, 8); 300 301 sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >> 302 GEN10_F2_S_ENA_SHIFT; 303 304 /* Slice0 */ 305 eu_en = ~I915_READ(GEN8_EU_DISABLE0); 306 for (ss = 0; ss < sseu->max_subslices; ss++) 307 sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask); 308 /* Slice1 */ 309 sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask); 310 eu_en = ~I915_READ(GEN8_EU_DISABLE1); 311 sseu_set_eus(sseu, 1, 1, eu_en & eu_mask); 312 /* Slice2 */ 313 sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask); 314 sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask); 315 /* Slice3 */ 316 sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask); 317 eu_en = ~I915_READ(GEN8_EU_DISABLE2); 318 sseu_set_eus(sseu, 3, 1, eu_en & eu_mask); 319 /* Slice4 */ 320 sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask); 321 sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask); 322 /* Slice5 */ 323 sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask); 324 eu_en = ~I915_READ(GEN10_EU_DISABLE3); 325 sseu_set_eus(sseu, 5, 1, eu_en & eu_mask); 326 327 subslice_mask = (1 << 4) - 1; 328 subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >> 329 GEN10_F2_SS_DIS_SHIFT); 330 331 for (s = 0; s < sseu->max_slices; s++) { 332 u32 subslice_mask_with_eus = subslice_mask; 333 334 for (ss = 0; ss < sseu->max_subslices; ss++) { 335 if (sseu_get_eus(sseu, s, ss) == 0) 336 subslice_mask_with_eus &= ~BIT(ss); 337 } 338 339 /* 340 * Slice0 can have up to 3 subslices, but there are only 2 in 341 * slice1/2. 342 */ 343 intel_sseu_set_subslices(sseu, s, s == 0 ? 344 subslice_mask_with_eus : 345 subslice_mask_with_eus & 0x3); 346 } 347 348 sseu->eu_total = compute_eu_total(sseu); 349 350 /* 351 * CNL is expected to always have a uniform distribution 352 * of EU across subslices with the exception that any one 353 * EU in any one subslice may be fused off for die 354 * recovery. 355 */ 356 sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? 357 DIV_ROUND_UP(sseu->eu_total, 358 intel_sseu_subslice_total(sseu)) : 359 0; 360 361 /* No restrictions on Power Gating */ 362 sseu->has_slice_pg = 1; 363 sseu->has_subslice_pg = 1; 364 sseu->has_eu_pg = 1; 365 } 366 367 static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv) 368 { 369 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; 370 u32 fuse; 371 u8 subslice_mask = 0; 372 373 fuse = I915_READ(CHV_FUSE_GT); 374 375 sseu->slice_mask = BIT(0); 376 intel_sseu_set_info(sseu, 1, 2, 8); 377 378 if (!(fuse & CHV_FGT_DISABLE_SS0)) { 379 u8 disabled_mask = 380 ((fuse & CHV_FGT_EU_DIS_SS0_R0_MASK) >> 381 CHV_FGT_EU_DIS_SS0_R0_SHIFT) | 382 (((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >> 383 CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4); 384 385 subslice_mask |= BIT(0); 386 sseu_set_eus(sseu, 0, 0, ~disabled_mask); 387 } 388 389 if (!(fuse & CHV_FGT_DISABLE_SS1)) { 390 u8 disabled_mask = 391 ((fuse & CHV_FGT_EU_DIS_SS1_R0_MASK) >> 392 CHV_FGT_EU_DIS_SS1_R0_SHIFT) | 393 (((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >> 394 CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4); 395 396 subslice_mask |= BIT(1); 397 sseu_set_eus(sseu, 0, 1, ~disabled_mask); 398 } 399 400 intel_sseu_set_subslices(sseu, 0, subslice_mask); 401 402 sseu->eu_total = compute_eu_total(sseu); 403 404 /* 405 * CHV expected to always have a uniform distribution of EU 406 * across subslices. 407 */ 408 sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? 409 sseu->eu_total / 410 intel_sseu_subslice_total(sseu) : 411 0; 412 /* 413 * CHV supports subslice power gating on devices with more than 414 * one subslice, and supports EU power gating on devices with 415 * more than one EU pair per subslice. 416 */ 417 sseu->has_slice_pg = 0; 418 sseu->has_subslice_pg = intel_sseu_subslice_total(sseu) > 1; 419 sseu->has_eu_pg = (sseu->eu_per_subslice > 2); 420 } 421 422 static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) 423 { 424 struct intel_device_info *info = mkwrite_device_info(dev_priv); 425 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; 426 int s, ss; 427 u32 fuse2, eu_disable, subslice_mask; 428 const u8 eu_mask = 0xff; 429 430 fuse2 = I915_READ(GEN8_FUSE2); 431 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; 432 433 /* BXT has a single slice and at most 3 subslices. */ 434 intel_sseu_set_info(sseu, IS_GEN9_LP(dev_priv) ? 1 : 3, 435 IS_GEN9_LP(dev_priv) ? 3 : 4, 8); 436 437 /* 438 * The subslice disable field is global, i.e. it applies 439 * to each of the enabled slices. 440 */ 441 subslice_mask = (1 << sseu->max_subslices) - 1; 442 subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >> 443 GEN9_F2_SS_DIS_SHIFT); 444 445 /* 446 * Iterate through enabled slices and subslices to 447 * count the total enabled EU. 448 */ 449 for (s = 0; s < sseu->max_slices; s++) { 450 if (!(sseu->slice_mask & BIT(s))) 451 /* skip disabled slice */ 452 continue; 453 454 intel_sseu_set_subslices(sseu, s, subslice_mask); 455 456 eu_disable = I915_READ(GEN9_EU_DISABLE(s)); 457 for (ss = 0; ss < sseu->max_subslices; ss++) { 458 int eu_per_ss; 459 u8 eu_disabled_mask; 460 461 if (!intel_sseu_has_subslice(sseu, s, ss)) 462 /* skip disabled subslice */ 463 continue; 464 465 eu_disabled_mask = (eu_disable >> (ss * 8)) & eu_mask; 466 467 sseu_set_eus(sseu, s, ss, ~eu_disabled_mask); 468 469 eu_per_ss = sseu->max_eus_per_subslice - 470 hweight8(eu_disabled_mask); 471 472 /* 473 * Record which subslice(s) has(have) 7 EUs. we 474 * can tune the hash used to spread work among 475 * subslices if they are unbalanced. 476 */ 477 if (eu_per_ss == 7) 478 sseu->subslice_7eu[s] |= BIT(ss); 479 } 480 } 481 482 sseu->eu_total = compute_eu_total(sseu); 483 484 /* 485 * SKL is expected to always have a uniform distribution 486 * of EU across subslices with the exception that any one 487 * EU in any one subslice may be fused off for die 488 * recovery. BXT is expected to be perfectly uniform in EU 489 * distribution. 490 */ 491 sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? 492 DIV_ROUND_UP(sseu->eu_total, 493 intel_sseu_subslice_total(sseu)) : 494 0; 495 /* 496 * SKL+ supports slice power gating on devices with more than 497 * one slice, and supports EU power gating on devices with 498 * more than one EU pair per subslice. BXT+ supports subslice 499 * power gating on devices with more than one subslice, and 500 * supports EU power gating on devices with more than one EU 501 * pair per subslice. 502 */ 503 sseu->has_slice_pg = 504 !IS_GEN9_LP(dev_priv) && hweight8(sseu->slice_mask) > 1; 505 sseu->has_subslice_pg = 506 IS_GEN9_LP(dev_priv) && intel_sseu_subslice_total(sseu) > 1; 507 sseu->has_eu_pg = sseu->eu_per_subslice > 2; 508 509 if (IS_GEN9_LP(dev_priv)) { 510 #define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss))) 511 info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3; 512 513 sseu->min_eu_in_pool = 0; 514 if (info->has_pooled_eu) { 515 if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0)) 516 sseu->min_eu_in_pool = 3; 517 else if (IS_SS_DISABLED(1)) 518 sseu->min_eu_in_pool = 6; 519 else 520 sseu->min_eu_in_pool = 9; 521 } 522 #undef IS_SS_DISABLED 523 } 524 } 525 526 static void bdw_sseu_info_init(struct drm_i915_private *dev_priv) 527 { 528 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; 529 int s, ss; 530 u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */ 531 532 fuse2 = I915_READ(GEN8_FUSE2); 533 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; 534 intel_sseu_set_info(sseu, 3, 3, 8); 535 536 /* 537 * The subslice disable field is global, i.e. it applies 538 * to each of the enabled slices. 539 */ 540 subslice_mask = GENMASK(sseu->max_subslices - 1, 0); 541 subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >> 542 GEN8_F2_SS_DIS_SHIFT); 543 544 eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK; 545 eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) | 546 ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) << 547 (32 - GEN8_EU_DIS0_S1_SHIFT)); 548 eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) | 549 ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) << 550 (32 - GEN8_EU_DIS1_S2_SHIFT)); 551 552 /* 553 * Iterate through enabled slices and subslices to 554 * count the total enabled EU. 555 */ 556 for (s = 0; s < sseu->max_slices; s++) { 557 if (!(sseu->slice_mask & BIT(s))) 558 /* skip disabled slice */ 559 continue; 560 561 intel_sseu_set_subslices(sseu, s, subslice_mask); 562 563 for (ss = 0; ss < sseu->max_subslices; ss++) { 564 u8 eu_disabled_mask; 565 u32 n_disabled; 566 567 if (!intel_sseu_has_subslice(sseu, s, ss)) 568 /* skip disabled subslice */ 569 continue; 570 571 eu_disabled_mask = 572 eu_disable[s] >> (ss * sseu->max_eus_per_subslice); 573 574 sseu_set_eus(sseu, s, ss, ~eu_disabled_mask); 575 576 n_disabled = hweight8(eu_disabled_mask); 577 578 /* 579 * Record which subslices have 7 EUs. 580 */ 581 if (sseu->max_eus_per_subslice - n_disabled == 7) 582 sseu->subslice_7eu[s] |= 1 << ss; 583 } 584 } 585 586 sseu->eu_total = compute_eu_total(sseu); 587 588 /* 589 * BDW is expected to always have a uniform distribution of EU across 590 * subslices with the exception that any one EU in any one subslice may 591 * be fused off for die recovery. 592 */ 593 sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? 594 DIV_ROUND_UP(sseu->eu_total, 595 intel_sseu_subslice_total(sseu)) : 596 0; 597 598 /* 599 * BDW supports slice power gating on devices with more than 600 * one slice. 601 */ 602 sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1; 603 sseu->has_subslice_pg = 0; 604 sseu->has_eu_pg = 0; 605 } 606 607 static void hsw_sseu_info_init(struct drm_i915_private *dev_priv) 608 { 609 struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; 610 u32 fuse1; 611 u8 subslice_mask = 0; 612 int s, ss; 613 614 /* 615 * There isn't a register to tell us how many slices/subslices. We 616 * work off the PCI-ids here. 617 */ 618 switch (INTEL_INFO(dev_priv)->gt) { 619 default: 620 MISSING_CASE(INTEL_INFO(dev_priv)->gt); 621 /* fall through */ 622 case 1: 623 sseu->slice_mask = BIT(0); 624 subslice_mask = BIT(0); 625 break; 626 case 2: 627 sseu->slice_mask = BIT(0); 628 subslice_mask = BIT(0) | BIT(1); 629 break; 630 case 3: 631 sseu->slice_mask = BIT(0) | BIT(1); 632 subslice_mask = BIT(0) | BIT(1); 633 break; 634 } 635 636 fuse1 = I915_READ(HSW_PAVP_FUSE1); 637 switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) { 638 default: 639 MISSING_CASE((fuse1 & HSW_F1_EU_DIS_MASK) >> 640 HSW_F1_EU_DIS_SHIFT); 641 /* fall through */ 642 case HSW_F1_EU_DIS_10EUS: 643 sseu->eu_per_subslice = 10; 644 break; 645 case HSW_F1_EU_DIS_8EUS: 646 sseu->eu_per_subslice = 8; 647 break; 648 case HSW_F1_EU_DIS_6EUS: 649 sseu->eu_per_subslice = 6; 650 break; 651 } 652 653 intel_sseu_set_info(sseu, hweight8(sseu->slice_mask), 654 hweight8(subslice_mask), 655 sseu->eu_per_subslice); 656 657 for (s = 0; s < sseu->max_slices; s++) { 658 intel_sseu_set_subslices(sseu, s, subslice_mask); 659 660 for (ss = 0; ss < sseu->max_subslices; ss++) { 661 sseu_set_eus(sseu, s, ss, 662 (1UL << sseu->eu_per_subslice) - 1); 663 } 664 } 665 666 sseu->eu_total = compute_eu_total(sseu); 667 668 /* No powergating for you. */ 669 sseu->has_slice_pg = 0; 670 sseu->has_subslice_pg = 0; 671 sseu->has_eu_pg = 0; 672 } 673 674 static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv) 675 { 676 u32 ts_override = I915_READ(GEN9_TIMESTAMP_OVERRIDE); 677 u32 base_freq, frac_freq; 678 679 base_freq = ((ts_override & GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >> 680 GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1; 681 base_freq *= 1000000; 682 683 frac_freq = ((ts_override & 684 GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >> 685 GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT); 686 frac_freq = 1000000 / (frac_freq + 1); 687 688 return base_freq + frac_freq; 689 } 690 691 static u32 gen10_get_crystal_clock_freq(struct drm_i915_private *dev_priv, 692 u32 rpm_config_reg) 693 { 694 u32 f19_2_mhz = 19200000; 695 u32 f24_mhz = 24000000; 696 u32 crystal_clock = (rpm_config_reg & 697 GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >> 698 GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT; 699 700 switch (crystal_clock) { 701 case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ: 702 return f19_2_mhz; 703 case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ: 704 return f24_mhz; 705 default: 706 MISSING_CASE(crystal_clock); 707 return 0; 708 } 709 } 710 711 static u32 gen11_get_crystal_clock_freq(struct drm_i915_private *dev_priv, 712 u32 rpm_config_reg) 713 { 714 u32 f19_2_mhz = 19200000; 715 u32 f24_mhz = 24000000; 716 u32 f25_mhz = 25000000; 717 u32 f38_4_mhz = 38400000; 718 u32 crystal_clock = (rpm_config_reg & 719 GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >> 720 GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT; 721 722 switch (crystal_clock) { 723 case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ: 724 return f24_mhz; 725 case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ: 726 return f19_2_mhz; 727 case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ: 728 return f38_4_mhz; 729 case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ: 730 return f25_mhz; 731 default: 732 MISSING_CASE(crystal_clock); 733 return 0; 734 } 735 } 736 737 static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv) 738 { 739 u32 f12_5_mhz = 12500000; 740 u32 f19_2_mhz = 19200000; 741 u32 f24_mhz = 24000000; 742 743 if (INTEL_GEN(dev_priv) <= 4) { 744 /* PRMs say: 745 * 746 * "The value in this register increments once every 16 747 * hclks." (through the “Clocking Configuration” 748 * (“CLKCFG”) MCHBAR register) 749 */ 750 return RUNTIME_INFO(dev_priv)->rawclk_freq * 1000 / 16; 751 } else if (INTEL_GEN(dev_priv) <= 8) { 752 /* PRMs say: 753 * 754 * "The PCU TSC counts 10ns increments; this timestamp 755 * reflects bits 38:3 of the TSC (i.e. 80ns granularity, 756 * rolling over every 1.5 hours). 757 */ 758 return f12_5_mhz; 759 } else if (INTEL_GEN(dev_priv) <= 9) { 760 u32 ctc_reg = I915_READ(CTC_MODE); 761 u32 freq = 0; 762 763 if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) { 764 freq = read_reference_ts_freq(dev_priv); 765 } else { 766 freq = IS_GEN9_LP(dev_priv) ? f19_2_mhz : f24_mhz; 767 768 /* Now figure out how the command stream's timestamp 769 * register increments from this frequency (it might 770 * increment only every few clock cycle). 771 */ 772 freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >> 773 CTC_SHIFT_PARAMETER_SHIFT); 774 } 775 776 return freq; 777 } else if (INTEL_GEN(dev_priv) <= 12) { 778 u32 ctc_reg = I915_READ(CTC_MODE); 779 u32 freq = 0; 780 781 /* First figure out the reference frequency. There are 2 ways 782 * we can compute the frequency, either through the 783 * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE 784 * tells us which one we should use. 785 */ 786 if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) { 787 freq = read_reference_ts_freq(dev_priv); 788 } else { 789 u32 rpm_config_reg = I915_READ(RPM_CONFIG0); 790 791 if (INTEL_GEN(dev_priv) <= 10) 792 freq = gen10_get_crystal_clock_freq(dev_priv, 793 rpm_config_reg); 794 else 795 freq = gen11_get_crystal_clock_freq(dev_priv, 796 rpm_config_reg); 797 798 /* Now figure out how the command stream's timestamp 799 * register increments from this frequency (it might 800 * increment only every few clock cycle). 801 */ 802 freq >>= 3 - ((rpm_config_reg & 803 GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >> 804 GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT); 805 } 806 807 return freq; 808 } 809 810 MISSING_CASE("Unknown gen, unable to read command streamer timestamp frequency\n"); 811 return 0; 812 } 813 814 #undef INTEL_VGA_DEVICE 815 #define INTEL_VGA_DEVICE(id, info) (id) 816 817 static const u16 subplatform_ult_ids[] = { 818 INTEL_HSW_ULT_GT1_IDS(0), 819 INTEL_HSW_ULT_GT2_IDS(0), 820 INTEL_HSW_ULT_GT3_IDS(0), 821 INTEL_BDW_ULT_GT1_IDS(0), 822 INTEL_BDW_ULT_GT2_IDS(0), 823 INTEL_BDW_ULT_GT3_IDS(0), 824 INTEL_BDW_ULT_RSVD_IDS(0), 825 INTEL_SKL_ULT_GT1_IDS(0), 826 INTEL_SKL_ULT_GT2_IDS(0), 827 INTEL_SKL_ULT_GT3_IDS(0), 828 INTEL_KBL_ULT_GT1_IDS(0), 829 INTEL_KBL_ULT_GT2_IDS(0), 830 INTEL_KBL_ULT_GT3_IDS(0), 831 INTEL_CFL_U_GT2_IDS(0), 832 INTEL_CFL_U_GT3_IDS(0), 833 INTEL_WHL_U_GT1_IDS(0), 834 INTEL_WHL_U_GT2_IDS(0), 835 INTEL_WHL_U_GT3_IDS(0), 836 INTEL_CML_U_GT1_IDS(0), 837 INTEL_CML_U_GT2_IDS(0), 838 }; 839 840 static const u16 subplatform_ulx_ids[] = { 841 INTEL_HSW_ULX_GT1_IDS(0), 842 INTEL_HSW_ULX_GT2_IDS(0), 843 INTEL_BDW_ULX_GT1_IDS(0), 844 INTEL_BDW_ULX_GT2_IDS(0), 845 INTEL_BDW_ULX_GT3_IDS(0), 846 INTEL_BDW_ULX_RSVD_IDS(0), 847 INTEL_SKL_ULX_GT1_IDS(0), 848 INTEL_SKL_ULX_GT2_IDS(0), 849 INTEL_KBL_ULX_GT1_IDS(0), 850 INTEL_KBL_ULX_GT2_IDS(0), 851 INTEL_AML_KBL_GT2_IDS(0), 852 INTEL_AML_CFL_GT2_IDS(0), 853 }; 854 855 static const u16 subplatform_portf_ids[] = { 856 INTEL_CNL_PORT_F_IDS(0), 857 INTEL_ICL_PORT_F_IDS(0), 858 }; 859 860 static bool find_devid(u16 id, const u16 *p, unsigned int num) 861 { 862 for (; num; num--, p++) { 863 if (*p == id) 864 return true; 865 } 866 867 return false; 868 } 869 870 void intel_device_info_subplatform_init(struct drm_i915_private *i915) 871 { 872 const struct intel_device_info *info = INTEL_INFO(i915); 873 const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915); 874 const unsigned int pi = __platform_mask_index(rinfo, info->platform); 875 const unsigned int pb = __platform_mask_bit(rinfo, info->platform); 876 u16 devid = INTEL_DEVID(i915); 877 u32 mask = 0; 878 879 /* Make sure IS_<platform> checks are working. */ 880 RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb); 881 882 /* Find and mark subplatform bits based on the PCI device id. */ 883 if (find_devid(devid, subplatform_ult_ids, 884 ARRAY_SIZE(subplatform_ult_ids))) { 885 mask = BIT(INTEL_SUBPLATFORM_ULT); 886 } else if (find_devid(devid, subplatform_ulx_ids, 887 ARRAY_SIZE(subplatform_ulx_ids))) { 888 mask = BIT(INTEL_SUBPLATFORM_ULX); 889 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 890 /* ULX machines are also considered ULT. */ 891 mask |= BIT(INTEL_SUBPLATFORM_ULT); 892 } 893 } else if (find_devid(devid, subplatform_portf_ids, 894 ARRAY_SIZE(subplatform_portf_ids))) { 895 mask = BIT(INTEL_SUBPLATFORM_PORTF); 896 } 897 898 GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_BITS); 899 900 RUNTIME_INFO(i915)->platform_mask[pi] |= mask; 901 } 902 903 /** 904 * intel_device_info_runtime_init - initialize runtime info 905 * @dev_priv: the i915 device 906 * 907 * Determine various intel_device_info fields at runtime. 908 * 909 * Use it when either: 910 * - it's judged too laborious to fill n static structures with the limit 911 * when a simple if statement does the job, 912 * - run-time checks (eg read fuse/strap registers) are needed. 913 * 914 * This function needs to be called: 915 * - after the MMIO has been setup as we are reading registers, 916 * - after the PCH has been detected, 917 * - before the first usage of the fields it can tweak. 918 */ 919 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) 920 { 921 struct intel_device_info *info = mkwrite_device_info(dev_priv); 922 struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv); 923 enum pipe pipe; 924 925 if (INTEL_GEN(dev_priv) >= 10) { 926 for_each_pipe(dev_priv, pipe) 927 runtime->num_scalers[pipe] = 2; 928 } else if (IS_GEN(dev_priv, 9)) { 929 runtime->num_scalers[PIPE_A] = 2; 930 runtime->num_scalers[PIPE_B] = 2; 931 runtime->num_scalers[PIPE_C] = 1; 932 } 933 934 BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES); 935 936 if (INTEL_GEN(dev_priv) >= 11) 937 for_each_pipe(dev_priv, pipe) 938 runtime->num_sprites[pipe] = 6; 939 else if (IS_GEN(dev_priv, 10) || IS_GEMINILAKE(dev_priv)) 940 for_each_pipe(dev_priv, pipe) 941 runtime->num_sprites[pipe] = 3; 942 else if (IS_BROXTON(dev_priv)) { 943 /* 944 * Skylake and Broxton currently don't expose the topmost plane as its 945 * use is exclusive with the legacy cursor and we only want to expose 946 * one of those, not both. Until we can safely expose the topmost plane 947 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported, 948 * we don't expose the topmost plane at all to prevent ABI breakage 949 * down the line. 950 */ 951 952 runtime->num_sprites[PIPE_A] = 2; 953 runtime->num_sprites[PIPE_B] = 2; 954 runtime->num_sprites[PIPE_C] = 1; 955 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 956 for_each_pipe(dev_priv, pipe) 957 runtime->num_sprites[pipe] = 2; 958 } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) { 959 for_each_pipe(dev_priv, pipe) 960 runtime->num_sprites[pipe] = 1; 961 } 962 963 if (HAS_DISPLAY(dev_priv) && IS_GEN_RANGE(dev_priv, 7, 8) && 964 HAS_PCH_SPLIT(dev_priv)) { 965 u32 fuse_strap = I915_READ(FUSE_STRAP); 966 u32 sfuse_strap = I915_READ(SFUSE_STRAP); 967 968 /* 969 * SFUSE_STRAP is supposed to have a bit signalling the display 970 * is fused off. Unfortunately it seems that, at least in 971 * certain cases, fused off display means that PCH display 972 * reads don't land anywhere. In that case, we read 0s. 973 * 974 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK 975 * should be set when taking over after the firmware. 976 */ 977 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || 978 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || 979 (HAS_PCH_CPT(dev_priv) && 980 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { 981 drm_info(&dev_priv->drm, 982 "Display fused off, disabling\n"); 983 info->pipe_mask = 0; 984 info->cpu_transcoder_mask = 0; 985 } else if (fuse_strap & IVB_PIPE_C_DISABLE) { 986 drm_info(&dev_priv->drm, "PipeC fused off\n"); 987 info->pipe_mask &= ~BIT(PIPE_C); 988 info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); 989 } 990 } else if (HAS_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 9) { 991 u32 dfsm = I915_READ(SKL_DFSM); 992 993 if (dfsm & SKL_DFSM_PIPE_A_DISABLE) { 994 info->pipe_mask &= ~BIT(PIPE_A); 995 info->cpu_transcoder_mask &= ~BIT(TRANSCODER_A); 996 } 997 if (dfsm & SKL_DFSM_PIPE_B_DISABLE) { 998 info->pipe_mask &= ~BIT(PIPE_B); 999 info->cpu_transcoder_mask &= ~BIT(TRANSCODER_B); 1000 } 1001 if (dfsm & SKL_DFSM_PIPE_C_DISABLE) { 1002 info->pipe_mask &= ~BIT(PIPE_C); 1003 info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); 1004 } 1005 if (INTEL_GEN(dev_priv) >= 12 && 1006 (dfsm & TGL_DFSM_PIPE_D_DISABLE)) { 1007 info->pipe_mask &= ~BIT(PIPE_D); 1008 info->cpu_transcoder_mask &= ~BIT(TRANSCODER_D); 1009 } 1010 1011 if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE) 1012 info->display.has_hdcp = 0; 1013 1014 if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE) 1015 info->display.has_fbc = 0; 1016 1017 if (INTEL_GEN(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) 1018 info->display.has_csr = 0; 1019 1020 if (INTEL_GEN(dev_priv) >= 10 && 1021 (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE)) 1022 info->display.has_dsc = 0; 1023 } 1024 1025 /* Initialize slice/subslice/EU info */ 1026 if (IS_HASWELL(dev_priv)) 1027 hsw_sseu_info_init(dev_priv); 1028 else if (IS_CHERRYVIEW(dev_priv)) 1029 cherryview_sseu_info_init(dev_priv); 1030 else if (IS_BROADWELL(dev_priv)) 1031 bdw_sseu_info_init(dev_priv); 1032 else if (IS_GEN(dev_priv, 9)) 1033 gen9_sseu_info_init(dev_priv); 1034 else if (IS_GEN(dev_priv, 10)) 1035 gen10_sseu_info_init(dev_priv); 1036 else if (IS_GEN(dev_priv, 11)) 1037 gen11_sseu_info_init(dev_priv); 1038 else if (INTEL_GEN(dev_priv) >= 12) 1039 gen12_sseu_info_init(dev_priv); 1040 1041 if (IS_GEN(dev_priv, 6) && intel_vtd_active()) { 1042 drm_info(&dev_priv->drm, 1043 "Disabling ppGTT for VT-d support\n"); 1044 info->ppgtt_type = INTEL_PPGTT_NONE; 1045 } 1046 1047 runtime->rawclk_freq = intel_read_rawclk(dev_priv); 1048 drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq); 1049 1050 /* Initialize command stream timestamp frequency */ 1051 runtime->cs_timestamp_frequency_hz = 1052 read_timestamp_frequency(dev_priv); 1053 if (runtime->cs_timestamp_frequency_hz) { 1054 runtime->cs_timestamp_period_ns = 1055 i915_cs_timestamp_ticks_to_ns(dev_priv, 1); 1056 drm_dbg(&dev_priv->drm, 1057 "CS timestamp wraparound in %lldms\n", 1058 div_u64(mul_u32_u32(runtime->cs_timestamp_period_ns, 1059 S32_MAX), 1060 USEC_PER_SEC)); 1061 } 1062 } 1063 1064 void intel_driver_caps_print(const struct intel_driver_caps *caps, 1065 struct drm_printer *p) 1066 { 1067 drm_printf(p, "Has logical contexts? %s\n", 1068 yesno(caps->has_logical_contexts)); 1069 drm_printf(p, "scheduler: %x\n", caps->scheduler); 1070 } 1071 1072 /* 1073 * Determine which engines are fused off in our particular hardware. Since the 1074 * fuse register is in the blitter powerwell, we need forcewake to be ready at 1075 * this point (but later we need to prune the forcewake domains for engines that 1076 * are indeed fused off). 1077 */ 1078 void intel_device_info_init_mmio(struct drm_i915_private *dev_priv) 1079 { 1080 struct intel_device_info *info = mkwrite_device_info(dev_priv); 1081 unsigned int logical_vdbox = 0; 1082 unsigned int i; 1083 u32 media_fuse; 1084 u16 vdbox_mask; 1085 u16 vebox_mask; 1086 1087 if (INTEL_GEN(dev_priv) < 11) 1088 return; 1089 1090 media_fuse = ~I915_READ(GEN11_GT_VEBOX_VDBOX_DISABLE); 1091 1092 vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK; 1093 vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >> 1094 GEN11_GT_VEBOX_DISABLE_SHIFT; 1095 1096 for (i = 0; i < I915_MAX_VCS; i++) { 1097 if (!HAS_ENGINE(dev_priv, _VCS(i))) { 1098 vdbox_mask &= ~BIT(i); 1099 continue; 1100 } 1101 1102 if (!(BIT(i) & vdbox_mask)) { 1103 info->engine_mask &= ~BIT(_VCS(i)); 1104 drm_dbg(&dev_priv->drm, "vcs%u fused off\n", i); 1105 continue; 1106 } 1107 1108 /* 1109 * In Gen11, only even numbered logical VDBOXes are 1110 * hooked up to an SFC (Scaler & Format Converter) unit. 1111 * In TGL each VDBOX has access to an SFC. 1112 */ 1113 if (INTEL_GEN(dev_priv) >= 12 || logical_vdbox++ % 2 == 0) 1114 RUNTIME_INFO(dev_priv)->vdbox_sfc_access |= BIT(i); 1115 } 1116 drm_dbg(&dev_priv->drm, "vdbox enable: %04x, instances: %04lx\n", 1117 vdbox_mask, VDBOX_MASK(dev_priv)); 1118 GEM_BUG_ON(vdbox_mask != VDBOX_MASK(dev_priv)); 1119 1120 for (i = 0; i < I915_MAX_VECS; i++) { 1121 if (!HAS_ENGINE(dev_priv, _VECS(i))) { 1122 vebox_mask &= ~BIT(i); 1123 continue; 1124 } 1125 1126 if (!(BIT(i) & vebox_mask)) { 1127 info->engine_mask &= ~BIT(_VECS(i)); 1128 drm_dbg(&dev_priv->drm, "vecs%u fused off\n", i); 1129 } 1130 } 1131 drm_dbg(&dev_priv->drm, "vebox enable: %04x, instances: %04lx\n", 1132 vebox_mask, VEBOX_MASK(dev_priv)); 1133 GEM_BUG_ON(vebox_mask != VEBOX_MASK(dev_priv)); 1134 } 1135