1 /*
2  * Copyright 2015 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 /* The caprices of the preprocessor require that this be declared right here */
27 #define CREATE_TRACE_POINTS
28 
29 #include "dm_services_types.h"
30 #include "dc.h"
31 #include "dc/inc/core_types.h"
32 #include "dal_asic_id.h"
33 #include "dmub/inc/dmub_srv.h"
34 #include "dc/inc/hw/dmcu.h"
35 #include "dc/inc/hw/abm.h"
36 #include "dc/dc_dmub_srv.h"
37 
38 #include "vid.h"
39 #include "amdgpu.h"
40 #include "amdgpu_display.h"
41 #include "amdgpu_ucode.h"
42 #include "atom.h"
43 #include "amdgpu_dm.h"
44 #ifdef CONFIG_DRM_AMD_DC_HDCP
45 #include "amdgpu_dm_hdcp.h"
46 #include <drm/drm_hdcp.h>
47 #endif
48 #include "amdgpu_pm.h"
49 
50 #include "amd_shared.h"
51 #include "amdgpu_dm_irq.h"
52 #include "dm_helpers.h"
53 #include "amdgpu_dm_mst_types.h"
54 #if defined(CONFIG_DEBUG_FS)
55 #include "amdgpu_dm_debugfs.h"
56 #endif
57 
58 #include "ivsrcid/ivsrcid_vislands30.h"
59 
60 #include <linux/module.h>
61 #include <linux/moduleparam.h>
62 #include <linux/version.h>
63 #include <linux/types.h>
64 #include <linux/pm_runtime.h>
65 #include <linux/pci.h>
66 #include <linux/firmware.h>
67 #include <linux/component.h>
68 
69 #include <drm/drm_atomic.h>
70 #include <drm/drm_atomic_uapi.h>
71 #include <drm/drm_atomic_helper.h>
72 #include <drm/drm_dp_mst_helper.h>
73 #include <drm/drm_fb_helper.h>
74 #include <drm/drm_fourcc.h>
75 #include <drm/drm_edid.h>
76 #include <drm/drm_vblank.h>
77 #include <drm/drm_audio_component.h>
78 #include <drm/drm_hdcp.h>
79 
80 #if defined(CONFIG_DRM_AMD_DC_DCN)
81 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
82 
83 #include "dcn/dcn_1_0_offset.h"
84 #include "dcn/dcn_1_0_sh_mask.h"
85 #include "soc15_hw_ip.h"
86 #include "vega10_ip_offset.h"
87 
88 #include "soc15_common.h"
89 #endif
90 
91 #include "modules/inc/mod_freesync.h"
92 #include "modules/power/power_helpers.h"
93 #include "modules/inc/mod_info_packet.h"
94 
95 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
96 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
97 
98 #define FIRMWARE_RAVEN_DMCU		"amdgpu/raven_dmcu.bin"
99 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
100 
101 /* Number of bytes in PSP header for firmware. */
102 #define PSP_HEADER_BYTES 0x100
103 
104 /* Number of bytes in PSP footer for firmware. */
105 #define PSP_FOOTER_BYTES 0x100
106 
107 /**
108  * DOC: overview
109  *
110  * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
111  * **dm**) sits between DRM and DC. It acts as a liason, converting DRM
112  * requests into DC requests, and DC responses into DRM responses.
113  *
114  * The root control structure is &struct amdgpu_display_manager.
115  */
116 
117 /* basic init/fini API */
118 static int amdgpu_dm_init(struct amdgpu_device *adev);
119 static void amdgpu_dm_fini(struct amdgpu_device *adev);
120 
121 /*
122  * initializes drm_device display related structures, based on the information
123  * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
124  * drm_encoder, drm_mode_config
125  *
126  * Returns 0 on success
127  */
128 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
129 /* removes and deallocates the drm structures, created by the above function */
130 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
131 
132 static void
133 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
134 
135 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
136 				struct drm_plane *plane,
137 				unsigned long possible_crtcs,
138 				const struct dc_plane_cap *plane_cap);
139 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
140 			       struct drm_plane *plane,
141 			       uint32_t link_index);
142 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
143 				    struct amdgpu_dm_connector *amdgpu_dm_connector,
144 				    uint32_t link_index,
145 				    struct amdgpu_encoder *amdgpu_encoder);
146 static int amdgpu_dm_encoder_init(struct drm_device *dev,
147 				  struct amdgpu_encoder *aencoder,
148 				  uint32_t link_index);
149 
150 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
151 
152 static int amdgpu_dm_atomic_commit(struct drm_device *dev,
153 				   struct drm_atomic_state *state,
154 				   bool nonblock);
155 
156 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
157 
158 static int amdgpu_dm_atomic_check(struct drm_device *dev,
159 				  struct drm_atomic_state *state);
160 
161 static void handle_cursor_update(struct drm_plane *plane,
162 				 struct drm_plane_state *old_plane_state);
163 
164 static void amdgpu_dm_set_psr_caps(struct dc_link *link);
165 static bool amdgpu_dm_psr_enable(struct dc_stream_state *stream);
166 static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream);
167 static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream);
168 
169 
170 /*
171  * dm_vblank_get_counter
172  *
173  * @brief
174  * Get counter for number of vertical blanks
175  *
176  * @param
177  * struct amdgpu_device *adev - [in] desired amdgpu device
178  * int disp_idx - [in] which CRTC to get the counter from
179  *
180  * @return
181  * Counter for vertical blanks
182  */
183 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
184 {
185 	if (crtc >= adev->mode_info.num_crtc)
186 		return 0;
187 	else {
188 		struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
189 		struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
190 				acrtc->base.state);
191 
192 
193 		if (acrtc_state->stream == NULL) {
194 			DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
195 				  crtc);
196 			return 0;
197 		}
198 
199 		return dc_stream_get_vblank_counter(acrtc_state->stream);
200 	}
201 }
202 
203 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
204 				  u32 *vbl, u32 *position)
205 {
206 	uint32_t v_blank_start, v_blank_end, h_position, v_position;
207 
208 	if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
209 		return -EINVAL;
210 	else {
211 		struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
212 		struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
213 						acrtc->base.state);
214 
215 		if (acrtc_state->stream ==  NULL) {
216 			DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
217 				  crtc);
218 			return 0;
219 		}
220 
221 		/*
222 		 * TODO rework base driver to use values directly.
223 		 * for now parse it back into reg-format
224 		 */
225 		dc_stream_get_scanoutpos(acrtc_state->stream,
226 					 &v_blank_start,
227 					 &v_blank_end,
228 					 &h_position,
229 					 &v_position);
230 
231 		*position = v_position | (h_position << 16);
232 		*vbl = v_blank_start | (v_blank_end << 16);
233 	}
234 
235 	return 0;
236 }
237 
238 static bool dm_is_idle(void *handle)
239 {
240 	/* XXX todo */
241 	return true;
242 }
243 
244 static int dm_wait_for_idle(void *handle)
245 {
246 	/* XXX todo */
247 	return 0;
248 }
249 
250 static bool dm_check_soft_reset(void *handle)
251 {
252 	return false;
253 }
254 
255 static int dm_soft_reset(void *handle)
256 {
257 	/* XXX todo */
258 	return 0;
259 }
260 
261 static struct amdgpu_crtc *
262 get_crtc_by_otg_inst(struct amdgpu_device *adev,
263 		     int otg_inst)
264 {
265 	struct drm_device *dev = adev->ddev;
266 	struct drm_crtc *crtc;
267 	struct amdgpu_crtc *amdgpu_crtc;
268 
269 	if (otg_inst == -1) {
270 		WARN_ON(1);
271 		return adev->mode_info.crtcs[0];
272 	}
273 
274 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
275 		amdgpu_crtc = to_amdgpu_crtc(crtc);
276 
277 		if (amdgpu_crtc->otg_inst == otg_inst)
278 			return amdgpu_crtc;
279 	}
280 
281 	return NULL;
282 }
283 
284 static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state)
285 {
286 	return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||
287 	       dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
288 }
289 
290 /**
291  * dm_pflip_high_irq() - Handle pageflip interrupt
292  * @interrupt_params: ignored
293  *
294  * Handles the pageflip interrupt by notifying all interested parties
295  * that the pageflip has been completed.
296  */
297 static void dm_pflip_high_irq(void *interrupt_params)
298 {
299 	struct amdgpu_crtc *amdgpu_crtc;
300 	struct common_irq_params *irq_params = interrupt_params;
301 	struct amdgpu_device *adev = irq_params->adev;
302 	unsigned long flags;
303 	struct drm_pending_vblank_event *e;
304 	struct dm_crtc_state *acrtc_state;
305 	uint32_t vpos, hpos, v_blank_start, v_blank_end;
306 	bool vrr_active;
307 
308 	amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
309 
310 	/* IRQ could occur when in initial stage */
311 	/* TODO work and BO cleanup */
312 	if (amdgpu_crtc == NULL) {
313 		DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
314 		return;
315 	}
316 
317 	spin_lock_irqsave(&adev->ddev->event_lock, flags);
318 
319 	if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
320 		DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
321 						 amdgpu_crtc->pflip_status,
322 						 AMDGPU_FLIP_SUBMITTED,
323 						 amdgpu_crtc->crtc_id,
324 						 amdgpu_crtc);
325 		spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
326 		return;
327 	}
328 
329 	/* page flip completed. */
330 	e = amdgpu_crtc->event;
331 	amdgpu_crtc->event = NULL;
332 
333 	if (!e)
334 		WARN_ON(1);
335 
336 	acrtc_state = to_dm_crtc_state(amdgpu_crtc->base.state);
337 	vrr_active = amdgpu_dm_vrr_active(acrtc_state);
338 
339 	/* Fixed refresh rate, or VRR scanout position outside front-porch? */
340 	if (!vrr_active ||
341 	    !dc_stream_get_scanoutpos(acrtc_state->stream, &v_blank_start,
342 				      &v_blank_end, &hpos, &vpos) ||
343 	    (vpos < v_blank_start)) {
344 		/* Update to correct count and vblank timestamp if racing with
345 		 * vblank irq. This also updates to the correct vblank timestamp
346 		 * even in VRR mode, as scanout is past the front-porch atm.
347 		 */
348 		drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
349 
350 		/* Wake up userspace by sending the pageflip event with proper
351 		 * count and timestamp of vblank of flip completion.
352 		 */
353 		if (e) {
354 			drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
355 
356 			/* Event sent, so done with vblank for this flip */
357 			drm_crtc_vblank_put(&amdgpu_crtc->base);
358 		}
359 	} else if (e) {
360 		/* VRR active and inside front-porch: vblank count and
361 		 * timestamp for pageflip event will only be up to date after
362 		 * drm_crtc_handle_vblank() has been executed from late vblank
363 		 * irq handler after start of back-porch (vline 0). We queue the
364 		 * pageflip event for send-out by drm_crtc_handle_vblank() with
365 		 * updated timestamp and count, once it runs after us.
366 		 *
367 		 * We need to open-code this instead of using the helper
368 		 * drm_crtc_arm_vblank_event(), as that helper would
369 		 * call drm_crtc_accurate_vblank_count(), which we must
370 		 * not call in VRR mode while we are in front-porch!
371 		 */
372 
373 		/* sequence will be replaced by real count during send-out. */
374 		e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
375 		e->pipe = amdgpu_crtc->crtc_id;
376 
377 		list_add_tail(&e->base.link, &adev->ddev->vblank_event_list);
378 		e = NULL;
379 	}
380 
381 	/* Keep track of vblank of this flip for flip throttling. We use the
382 	 * cooked hw counter, as that one incremented at start of this vblank
383 	 * of pageflip completion, so last_flip_vblank is the forbidden count
384 	 * for queueing new pageflips if vsync + VRR is enabled.
385 	 */
386 	amdgpu_crtc->last_flip_vblank = amdgpu_get_vblank_counter_kms(adev->ddev,
387 							amdgpu_crtc->crtc_id);
388 
389 	amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
390 	spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
391 
392 	DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
393 			 amdgpu_crtc->crtc_id, amdgpu_crtc,
394 			 vrr_active, (int) !e);
395 }
396 
397 static void dm_vupdate_high_irq(void *interrupt_params)
398 {
399 	struct common_irq_params *irq_params = interrupt_params;
400 	struct amdgpu_device *adev = irq_params->adev;
401 	struct amdgpu_crtc *acrtc;
402 	struct dm_crtc_state *acrtc_state;
403 	unsigned long flags;
404 
405 	acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
406 
407 	if (acrtc) {
408 		acrtc_state = to_dm_crtc_state(acrtc->base.state);
409 
410 		DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
411 				 amdgpu_dm_vrr_active(acrtc_state));
412 
413 		/* Core vblank handling is done here after end of front-porch in
414 		 * vrr mode, as vblank timestamping will give valid results
415 		 * while now done after front-porch. This will also deliver
416 		 * page-flip completion events that have been queued to us
417 		 * if a pageflip happened inside front-porch.
418 		 */
419 		if (amdgpu_dm_vrr_active(acrtc_state)) {
420 			drm_crtc_handle_vblank(&acrtc->base);
421 
422 			/* BTR processing for pre-DCE12 ASICs */
423 			if (acrtc_state->stream &&
424 			    adev->family < AMDGPU_FAMILY_AI) {
425 				spin_lock_irqsave(&adev->ddev->event_lock, flags);
426 				mod_freesync_handle_v_update(
427 				    adev->dm.freesync_module,
428 				    acrtc_state->stream,
429 				    &acrtc_state->vrr_params);
430 
431 				dc_stream_adjust_vmin_vmax(
432 				    adev->dm.dc,
433 				    acrtc_state->stream,
434 				    &acrtc_state->vrr_params.adjust);
435 				spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
436 			}
437 		}
438 	}
439 }
440 
441 /**
442  * dm_crtc_high_irq() - Handles CRTC interrupt
443  * @interrupt_params: ignored
444  *
445  * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
446  * event handler.
447  */
448 static void dm_crtc_high_irq(void *interrupt_params)
449 {
450 	struct common_irq_params *irq_params = interrupt_params;
451 	struct amdgpu_device *adev = irq_params->adev;
452 	struct amdgpu_crtc *acrtc;
453 	struct dm_crtc_state *acrtc_state;
454 	unsigned long flags;
455 
456 	acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
457 
458 	if (acrtc) {
459 		acrtc_state = to_dm_crtc_state(acrtc->base.state);
460 
461 		DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
462 				 amdgpu_dm_vrr_active(acrtc_state));
463 
464 		/* Core vblank handling at start of front-porch is only possible
465 		 * in non-vrr mode, as only there vblank timestamping will give
466 		 * valid results while done in front-porch. Otherwise defer it
467 		 * to dm_vupdate_high_irq after end of front-porch.
468 		 */
469 		if (!amdgpu_dm_vrr_active(acrtc_state))
470 			drm_crtc_handle_vblank(&acrtc->base);
471 
472 		/* Following stuff must happen at start of vblank, for crc
473 		 * computation and below-the-range btr support in vrr mode.
474 		 */
475 		amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
476 
477 		if (acrtc_state->stream && adev->family >= AMDGPU_FAMILY_AI &&
478 		    acrtc_state->vrr_params.supported &&
479 		    acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) {
480 			spin_lock_irqsave(&adev->ddev->event_lock, flags);
481 			mod_freesync_handle_v_update(
482 				adev->dm.freesync_module,
483 				acrtc_state->stream,
484 				&acrtc_state->vrr_params);
485 
486 			dc_stream_adjust_vmin_vmax(
487 				adev->dm.dc,
488 				acrtc_state->stream,
489 				&acrtc_state->vrr_params.adjust);
490 			spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
491 		}
492 	}
493 }
494 
495 #if defined(CONFIG_DRM_AMD_DC_DCN)
496 /**
497  * dm_dcn_crtc_high_irq() - Handles VStartup interrupt for DCN generation ASICs
498  * @interrupt params - interrupt parameters
499  *
500  * Notify DRM's vblank event handler at VSTARTUP
501  *
502  * Unlike DCE hardware, we trigger the handler at VSTARTUP. at which:
503  * * We are close enough to VUPDATE - the point of no return for hw
504  * * We are in the fixed portion of variable front porch when vrr is enabled
505  * * We are before VUPDATE, where double-buffered vrr registers are swapped
506  *
507  * It is therefore the correct place to signal vblank, send user flip events,
508  * and update VRR.
509  */
510 static void dm_dcn_crtc_high_irq(void *interrupt_params)
511 {
512 	struct common_irq_params *irq_params = interrupt_params;
513 	struct amdgpu_device *adev = irq_params->adev;
514 	struct amdgpu_crtc *acrtc;
515 	struct dm_crtc_state *acrtc_state;
516 	unsigned long flags;
517 
518 	acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
519 
520 	if (!acrtc)
521 		return;
522 
523 	acrtc_state = to_dm_crtc_state(acrtc->base.state);
524 
525 	DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
526 				amdgpu_dm_vrr_active(acrtc_state));
527 
528 	amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
529 	drm_crtc_handle_vblank(&acrtc->base);
530 
531 	spin_lock_irqsave(&adev->ddev->event_lock, flags);
532 
533 	if (acrtc_state->vrr_params.supported &&
534 	    acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) {
535 		mod_freesync_handle_v_update(
536 		adev->dm.freesync_module,
537 		acrtc_state->stream,
538 		&acrtc_state->vrr_params);
539 
540 		dc_stream_adjust_vmin_vmax(
541 			adev->dm.dc,
542 			acrtc_state->stream,
543 			&acrtc_state->vrr_params.adjust);
544 	}
545 
546 	if (acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED) {
547 		if (acrtc->event) {
548 			drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
549 			acrtc->event = NULL;
550 			drm_crtc_vblank_put(&acrtc->base);
551 		}
552 		acrtc->pflip_status = AMDGPU_FLIP_NONE;
553 	}
554 
555 	spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
556 }
557 #endif
558 
559 static int dm_set_clockgating_state(void *handle,
560 		  enum amd_clockgating_state state)
561 {
562 	return 0;
563 }
564 
565 static int dm_set_powergating_state(void *handle,
566 		  enum amd_powergating_state state)
567 {
568 	return 0;
569 }
570 
571 /* Prototypes of private functions */
572 static int dm_early_init(void* handle);
573 
574 /* Allocate memory for FBC compressed data  */
575 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
576 {
577 	struct drm_device *dev = connector->dev;
578 	struct amdgpu_device *adev = dev->dev_private;
579 	struct dm_comressor_info *compressor = &adev->dm.compressor;
580 	struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
581 	struct drm_display_mode *mode;
582 	unsigned long max_size = 0;
583 
584 	if (adev->dm.dc->fbc_compressor == NULL)
585 		return;
586 
587 	if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
588 		return;
589 
590 	if (compressor->bo_ptr)
591 		return;
592 
593 
594 	list_for_each_entry(mode, &connector->modes, head) {
595 		if (max_size < mode->htotal * mode->vtotal)
596 			max_size = mode->htotal * mode->vtotal;
597 	}
598 
599 	if (max_size) {
600 		int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
601 			    AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
602 			    &compressor->gpu_addr, &compressor->cpu_addr);
603 
604 		if (r)
605 			DRM_ERROR("DM: Failed to initialize FBC\n");
606 		else {
607 			adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
608 			DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
609 		}
610 
611 	}
612 
613 }
614 
615 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
616 					  int pipe, bool *enabled,
617 					  unsigned char *buf, int max_bytes)
618 {
619 	struct drm_device *dev = dev_get_drvdata(kdev);
620 	struct amdgpu_device *adev = dev->dev_private;
621 	struct drm_connector *connector;
622 	struct drm_connector_list_iter conn_iter;
623 	struct amdgpu_dm_connector *aconnector;
624 	int ret = 0;
625 
626 	*enabled = false;
627 
628 	mutex_lock(&adev->dm.audio_lock);
629 
630 	drm_connector_list_iter_begin(dev, &conn_iter);
631 	drm_for_each_connector_iter(connector, &conn_iter) {
632 		aconnector = to_amdgpu_dm_connector(connector);
633 		if (aconnector->audio_inst != port)
634 			continue;
635 
636 		*enabled = true;
637 		ret = drm_eld_size(connector->eld);
638 		memcpy(buf, connector->eld, min(max_bytes, ret));
639 
640 		break;
641 	}
642 	drm_connector_list_iter_end(&conn_iter);
643 
644 	mutex_unlock(&adev->dm.audio_lock);
645 
646 	DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
647 
648 	return ret;
649 }
650 
651 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
652 	.get_eld = amdgpu_dm_audio_component_get_eld,
653 };
654 
655 static int amdgpu_dm_audio_component_bind(struct device *kdev,
656 				       struct device *hda_kdev, void *data)
657 {
658 	struct drm_device *dev = dev_get_drvdata(kdev);
659 	struct amdgpu_device *adev = dev->dev_private;
660 	struct drm_audio_component *acomp = data;
661 
662 	acomp->ops = &amdgpu_dm_audio_component_ops;
663 	acomp->dev = kdev;
664 	adev->dm.audio_component = acomp;
665 
666 	return 0;
667 }
668 
669 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
670 					  struct device *hda_kdev, void *data)
671 {
672 	struct drm_device *dev = dev_get_drvdata(kdev);
673 	struct amdgpu_device *adev = dev->dev_private;
674 	struct drm_audio_component *acomp = data;
675 
676 	acomp->ops = NULL;
677 	acomp->dev = NULL;
678 	adev->dm.audio_component = NULL;
679 }
680 
681 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
682 	.bind	= amdgpu_dm_audio_component_bind,
683 	.unbind	= amdgpu_dm_audio_component_unbind,
684 };
685 
686 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
687 {
688 	int i, ret;
689 
690 	if (!amdgpu_audio)
691 		return 0;
692 
693 	adev->mode_info.audio.enabled = true;
694 
695 	adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
696 
697 	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
698 		adev->mode_info.audio.pin[i].channels = -1;
699 		adev->mode_info.audio.pin[i].rate = -1;
700 		adev->mode_info.audio.pin[i].bits_per_sample = -1;
701 		adev->mode_info.audio.pin[i].status_bits = 0;
702 		adev->mode_info.audio.pin[i].category_code = 0;
703 		adev->mode_info.audio.pin[i].connected = false;
704 		adev->mode_info.audio.pin[i].id =
705 			adev->dm.dc->res_pool->audios[i]->inst;
706 		adev->mode_info.audio.pin[i].offset = 0;
707 	}
708 
709 	ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
710 	if (ret < 0)
711 		return ret;
712 
713 	adev->dm.audio_registered = true;
714 
715 	return 0;
716 }
717 
718 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
719 {
720 	if (!amdgpu_audio)
721 		return;
722 
723 	if (!adev->mode_info.audio.enabled)
724 		return;
725 
726 	if (adev->dm.audio_registered) {
727 		component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
728 		adev->dm.audio_registered = false;
729 	}
730 
731 	/* TODO: Disable audio? */
732 
733 	adev->mode_info.audio.enabled = false;
734 }
735 
736 void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
737 {
738 	struct drm_audio_component *acomp = adev->dm.audio_component;
739 
740 	if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
741 		DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
742 
743 		acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
744 						 pin, -1);
745 	}
746 }
747 
748 static int dm_dmub_hw_init(struct amdgpu_device *adev)
749 {
750 	const struct dmcub_firmware_header_v1_0 *hdr;
751 	struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
752 	struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
753 	const struct firmware *dmub_fw = adev->dm.dmub_fw;
754 	struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
755 	struct abm *abm = adev->dm.dc->res_pool->abm;
756 	struct dmub_srv_hw_params hw_params;
757 	enum dmub_status status;
758 	const unsigned char *fw_inst_const, *fw_bss_data;
759 	uint32_t i, fw_inst_const_size, fw_bss_data_size;
760 	bool has_hw_support;
761 
762 	if (!dmub_srv)
763 		/* DMUB isn't supported on the ASIC. */
764 		return 0;
765 
766 	if (!fb_info) {
767 		DRM_ERROR("No framebuffer info for DMUB service.\n");
768 		return -EINVAL;
769 	}
770 
771 	if (!dmub_fw) {
772 		/* Firmware required for DMUB support. */
773 		DRM_ERROR("No firmware provided for DMUB.\n");
774 		return -EINVAL;
775 	}
776 
777 	status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
778 	if (status != DMUB_STATUS_OK) {
779 		DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
780 		return -EINVAL;
781 	}
782 
783 	if (!has_hw_support) {
784 		DRM_INFO("DMUB unsupported on ASIC\n");
785 		return 0;
786 	}
787 
788 	hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
789 
790 	fw_inst_const = dmub_fw->data +
791 			le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
792 			PSP_HEADER_BYTES;
793 
794 	fw_bss_data = dmub_fw->data +
795 		      le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
796 		      le32_to_cpu(hdr->inst_const_bytes);
797 
798 	/* Copy firmware and bios info into FB memory. */
799 	fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
800 			     PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
801 
802 	fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
803 
804 	memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
805 	       fw_inst_const_size);
806 	memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr, fw_bss_data,
807 	       fw_bss_data_size);
808 	memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
809 	       adev->bios_size);
810 
811 	/* Reset regions that need to be reset. */
812 	memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
813 	fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
814 
815 	memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
816 	       fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
817 
818 	memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
819 	       fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
820 
821 	/* Initialize hardware. */
822 	memset(&hw_params, 0, sizeof(hw_params));
823 	hw_params.fb_base = adev->gmc.fb_start;
824 	hw_params.fb_offset = adev->gmc.aper_base;
825 
826 	if (dmcu)
827 		hw_params.psp_version = dmcu->psp_version;
828 
829 	for (i = 0; i < fb_info->num_fb; ++i)
830 		hw_params.fb[i] = &fb_info->fb[i];
831 
832 	status = dmub_srv_hw_init(dmub_srv, &hw_params);
833 	if (status != DMUB_STATUS_OK) {
834 		DRM_ERROR("Error initializing DMUB HW: %d\n", status);
835 		return -EINVAL;
836 	}
837 
838 	/* Wait for firmware load to finish. */
839 	status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
840 	if (status != DMUB_STATUS_OK)
841 		DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
842 
843 	/* Init DMCU and ABM if available. */
844 	if (dmcu && abm) {
845 		dmcu->funcs->dmcu_init(dmcu);
846 		abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
847 	}
848 
849 	adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
850 	if (!adev->dm.dc->ctx->dmub_srv) {
851 		DRM_ERROR("Couldn't allocate DC DMUB server!\n");
852 		return -ENOMEM;
853 	}
854 
855 	DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
856 		 adev->dm.dmcub_fw_version);
857 
858 	return 0;
859 }
860 
861 static int amdgpu_dm_init(struct amdgpu_device *adev)
862 {
863 	struct dc_init_data init_data;
864 #ifdef CONFIG_DRM_AMD_DC_HDCP
865 	struct dc_callback_init init_params;
866 #endif
867 	int r;
868 
869 	adev->dm.ddev = adev->ddev;
870 	adev->dm.adev = adev;
871 
872 	/* Zero all the fields */
873 	memset(&init_data, 0, sizeof(init_data));
874 #ifdef CONFIG_DRM_AMD_DC_HDCP
875 	memset(&init_params, 0, sizeof(init_params));
876 #endif
877 
878 	mutex_init(&adev->dm.dc_lock);
879 	mutex_init(&adev->dm.audio_lock);
880 
881 	if(amdgpu_dm_irq_init(adev)) {
882 		DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
883 		goto error;
884 	}
885 
886 	init_data.asic_id.chip_family = adev->family;
887 
888 	init_data.asic_id.pci_revision_id = adev->rev_id;
889 	init_data.asic_id.hw_internal_rev = adev->external_rev_id;
890 
891 	init_data.asic_id.vram_width = adev->gmc.vram_width;
892 	/* TODO: initialize init_data.asic_id.vram_type here!!!! */
893 	init_data.asic_id.atombios_base_address =
894 		adev->mode_info.atom_context->bios;
895 
896 	init_data.driver = adev;
897 
898 	adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
899 
900 	if (!adev->dm.cgs_device) {
901 		DRM_ERROR("amdgpu: failed to create cgs device.\n");
902 		goto error;
903 	}
904 
905 	init_data.cgs_device = adev->dm.cgs_device;
906 
907 	init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
908 
909 	switch (adev->asic_type) {
910 	case CHIP_CARRIZO:
911 	case CHIP_STONEY:
912 	case CHIP_RAVEN:
913 	case CHIP_RENOIR:
914 		init_data.flags.gpu_vm_support = true;
915 		break;
916 	default:
917 		break;
918 	}
919 
920 	if (amdgpu_dc_feature_mask & DC_FBC_MASK)
921 		init_data.flags.fbc_support = true;
922 
923 	if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
924 		init_data.flags.multi_mon_pp_mclk_switch = true;
925 
926 	if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
927 		init_data.flags.disable_fractional_pwm = true;
928 
929 	init_data.flags.power_down_display_on_boot = true;
930 
931 	init_data.soc_bounding_box = adev->dm.soc_bounding_box;
932 
933 	/* Display Core create. */
934 	adev->dm.dc = dc_create(&init_data);
935 
936 	if (adev->dm.dc) {
937 		DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
938 	} else {
939 		DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
940 		goto error;
941 	}
942 
943 	r = dm_dmub_hw_init(adev);
944 	if (r) {
945 		DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
946 		goto error;
947 	}
948 
949 	dc_hardware_init(adev->dm.dc);
950 
951 	adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
952 	if (!adev->dm.freesync_module) {
953 		DRM_ERROR(
954 		"amdgpu: failed to initialize freesync_module.\n");
955 	} else
956 		DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
957 				adev->dm.freesync_module);
958 
959 	amdgpu_dm_init_color_mod();
960 
961 #ifdef CONFIG_DRM_AMD_DC_HDCP
962 	if (adev->asic_type >= CHIP_RAVEN) {
963 		adev->dm.hdcp_workqueue = hdcp_create_workqueue(&adev->psp, &init_params.cp_psp, adev->dm.dc);
964 
965 		if (!adev->dm.hdcp_workqueue)
966 			DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
967 		else
968 			DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
969 
970 		dc_init_callbacks(adev->dm.dc, &init_params);
971 	}
972 #endif
973 	if (amdgpu_dm_initialize_drm_device(adev)) {
974 		DRM_ERROR(
975 		"amdgpu: failed to initialize sw for display support.\n");
976 		goto error;
977 	}
978 
979 	/* Update the actual used number of crtc */
980 	adev->mode_info.num_crtc = adev->dm.display_indexes_num;
981 
982 	/* TODO: Add_display_info? */
983 
984 	/* TODO use dynamic cursor width */
985 	adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
986 	adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
987 
988 	if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
989 		DRM_ERROR(
990 		"amdgpu: failed to initialize sw for display support.\n");
991 		goto error;
992 	}
993 
994 #if defined(CONFIG_DEBUG_FS)
995 	if (dtn_debugfs_init(adev))
996 		DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n");
997 #endif
998 
999 	DRM_DEBUG_DRIVER("KMS initialized.\n");
1000 
1001 	return 0;
1002 error:
1003 	amdgpu_dm_fini(adev);
1004 
1005 	return -EINVAL;
1006 }
1007 
1008 static void amdgpu_dm_fini(struct amdgpu_device *adev)
1009 {
1010 	amdgpu_dm_audio_fini(adev);
1011 
1012 	amdgpu_dm_destroy_drm_device(&adev->dm);
1013 
1014 #ifdef CONFIG_DRM_AMD_DC_HDCP
1015 	if (adev->dm.hdcp_workqueue) {
1016 		hdcp_destroy(adev->dm.hdcp_workqueue);
1017 		adev->dm.hdcp_workqueue = NULL;
1018 	}
1019 
1020 	if (adev->dm.dc)
1021 		dc_deinit_callbacks(adev->dm.dc);
1022 #endif
1023 	if (adev->dm.dc->ctx->dmub_srv) {
1024 		dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1025 		adev->dm.dc->ctx->dmub_srv = NULL;
1026 	}
1027 
1028 	if (adev->dm.dmub_bo)
1029 		amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1030 				      &adev->dm.dmub_bo_gpu_addr,
1031 				      &adev->dm.dmub_bo_cpu_addr);
1032 
1033 	/* DC Destroy TODO: Replace destroy DAL */
1034 	if (adev->dm.dc)
1035 		dc_destroy(&adev->dm.dc);
1036 	/*
1037 	 * TODO: pageflip, vlank interrupt
1038 	 *
1039 	 * amdgpu_dm_irq_fini(adev);
1040 	 */
1041 
1042 	if (adev->dm.cgs_device) {
1043 		amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1044 		adev->dm.cgs_device = NULL;
1045 	}
1046 	if (adev->dm.freesync_module) {
1047 		mod_freesync_destroy(adev->dm.freesync_module);
1048 		adev->dm.freesync_module = NULL;
1049 	}
1050 
1051 	mutex_destroy(&adev->dm.audio_lock);
1052 	mutex_destroy(&adev->dm.dc_lock);
1053 
1054 	return;
1055 }
1056 
1057 static int load_dmcu_fw(struct amdgpu_device *adev)
1058 {
1059 	const char *fw_name_dmcu = NULL;
1060 	int r;
1061 	const struct dmcu_firmware_header_v1_0 *hdr;
1062 
1063 	switch(adev->asic_type) {
1064 	case CHIP_BONAIRE:
1065 	case CHIP_HAWAII:
1066 	case CHIP_KAVERI:
1067 	case CHIP_KABINI:
1068 	case CHIP_MULLINS:
1069 	case CHIP_TONGA:
1070 	case CHIP_FIJI:
1071 	case CHIP_CARRIZO:
1072 	case CHIP_STONEY:
1073 	case CHIP_POLARIS11:
1074 	case CHIP_POLARIS10:
1075 	case CHIP_POLARIS12:
1076 	case CHIP_VEGAM:
1077 	case CHIP_VEGA10:
1078 	case CHIP_VEGA12:
1079 	case CHIP_VEGA20:
1080 	case CHIP_NAVI10:
1081 	case CHIP_NAVI14:
1082 	case CHIP_NAVI12:
1083 	case CHIP_RENOIR:
1084 		return 0;
1085 	case CHIP_RAVEN:
1086 		if (ASICREV_IS_PICASSO(adev->external_rev_id))
1087 			fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1088 		else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
1089 			fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1090 		else
1091 			return 0;
1092 		break;
1093 	default:
1094 		DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
1095 		return -EINVAL;
1096 	}
1097 
1098 	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1099 		DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
1100 		return 0;
1101 	}
1102 
1103 	r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev);
1104 	if (r == -ENOENT) {
1105 		/* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
1106 		DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
1107 		adev->dm.fw_dmcu = NULL;
1108 		return 0;
1109 	}
1110 	if (r) {
1111 		dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",
1112 			fw_name_dmcu);
1113 		return r;
1114 	}
1115 
1116 	r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
1117 	if (r) {
1118 		dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
1119 			fw_name_dmcu);
1120 		release_firmware(adev->dm.fw_dmcu);
1121 		adev->dm.fw_dmcu = NULL;
1122 		return r;
1123 	}
1124 
1125 	hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
1126 	adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
1127 	adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
1128 	adev->firmware.fw_size +=
1129 		ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
1130 
1131 	adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
1132 	adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
1133 	adev->firmware.fw_size +=
1134 		ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
1135 
1136 	adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
1137 
1138 	DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
1139 
1140 	return 0;
1141 }
1142 
1143 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
1144 {
1145 	struct amdgpu_device *adev = ctx;
1146 
1147 	return dm_read_reg(adev->dm.dc->ctx, address);
1148 }
1149 
1150 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
1151 				     uint32_t value)
1152 {
1153 	struct amdgpu_device *adev = ctx;
1154 
1155 	return dm_write_reg(adev->dm.dc->ctx, address, value);
1156 }
1157 
1158 static int dm_dmub_sw_init(struct amdgpu_device *adev)
1159 {
1160 	struct dmub_srv_create_params create_params;
1161 	struct dmub_srv_region_params region_params;
1162 	struct dmub_srv_region_info region_info;
1163 	struct dmub_srv_fb_params fb_params;
1164 	struct dmub_srv_fb_info *fb_info;
1165 	struct dmub_srv *dmub_srv;
1166 	const struct dmcub_firmware_header_v1_0 *hdr;
1167 	const char *fw_name_dmub;
1168 	enum dmub_asic dmub_asic;
1169 	enum dmub_status status;
1170 	int r;
1171 
1172 	switch (adev->asic_type) {
1173 	case CHIP_RENOIR:
1174 		dmub_asic = DMUB_ASIC_DCN21;
1175 		fw_name_dmub = FIRMWARE_RENOIR_DMUB;
1176 		break;
1177 
1178 	default:
1179 		/* ASIC doesn't support DMUB. */
1180 		return 0;
1181 	}
1182 
1183 	r = request_firmware_direct(&adev->dm.dmub_fw, fw_name_dmub, adev->dev);
1184 	if (r) {
1185 		DRM_ERROR("DMUB firmware loading failed: %d\n", r);
1186 		return 0;
1187 	}
1188 
1189 	r = amdgpu_ucode_validate(adev->dm.dmub_fw);
1190 	if (r) {
1191 		DRM_ERROR("Couldn't validate DMUB firmware: %d\n", r);
1192 		return 0;
1193 	}
1194 
1195 	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1196 		DRM_WARN("Only PSP firmware loading is supported for DMUB\n");
1197 		return 0;
1198 	}
1199 
1200 	hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
1201 	adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
1202 		AMDGPU_UCODE_ID_DMCUB;
1203 	adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw = adev->dm.dmub_fw;
1204 	adev->firmware.fw_size +=
1205 		ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
1206 
1207 	adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
1208 
1209 	DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
1210 		 adev->dm.dmcub_fw_version);
1211 
1212 	adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
1213 	dmub_srv = adev->dm.dmub_srv;
1214 
1215 	if (!dmub_srv) {
1216 		DRM_ERROR("Failed to allocate DMUB service!\n");
1217 		return -ENOMEM;
1218 	}
1219 
1220 	memset(&create_params, 0, sizeof(create_params));
1221 	create_params.user_ctx = adev;
1222 	create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
1223 	create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
1224 	create_params.asic = dmub_asic;
1225 
1226 	/* Create the DMUB service. */
1227 	status = dmub_srv_create(dmub_srv, &create_params);
1228 	if (status != DMUB_STATUS_OK) {
1229 		DRM_ERROR("Error creating DMUB service: %d\n", status);
1230 		return -EINVAL;
1231 	}
1232 
1233 	/* Calculate the size of all the regions for the DMUB service. */
1234 	memset(&region_params, 0, sizeof(region_params));
1235 
1236 	region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1237 					PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1238 	region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1239 	region_params.vbios_size = adev->bios_size;
1240 	region_params.fw_bss_data =
1241 		adev->dm.dmub_fw->data +
1242 		le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1243 		le32_to_cpu(hdr->inst_const_bytes);
1244 
1245 	status = dmub_srv_calc_region_info(dmub_srv, &region_params,
1246 					   &region_info);
1247 
1248 	if (status != DMUB_STATUS_OK) {
1249 		DRM_ERROR("Error calculating DMUB region info: %d\n", status);
1250 		return -EINVAL;
1251 	}
1252 
1253 	/*
1254 	 * Allocate a framebuffer based on the total size of all the regions.
1255 	 * TODO: Move this into GART.
1256 	 */
1257 	r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
1258 				    AMDGPU_GEM_DOMAIN_VRAM, &adev->dm.dmub_bo,
1259 				    &adev->dm.dmub_bo_gpu_addr,
1260 				    &adev->dm.dmub_bo_cpu_addr);
1261 	if (r)
1262 		return r;
1263 
1264 	/* Rebase the regions on the framebuffer address. */
1265 	memset(&fb_params, 0, sizeof(fb_params));
1266 	fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
1267 	fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
1268 	fb_params.region_info = &region_info;
1269 
1270 	adev->dm.dmub_fb_info =
1271 		kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
1272 	fb_info = adev->dm.dmub_fb_info;
1273 
1274 	if (!fb_info) {
1275 		DRM_ERROR(
1276 			"Failed to allocate framebuffer info for DMUB service!\n");
1277 		return -ENOMEM;
1278 	}
1279 
1280 	status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info);
1281 	if (status != DMUB_STATUS_OK) {
1282 		DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
1283 		return -EINVAL;
1284 	}
1285 
1286 	return 0;
1287 }
1288 
1289 static int dm_sw_init(void *handle)
1290 {
1291 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1292 	int r;
1293 
1294 	r = dm_dmub_sw_init(adev);
1295 	if (r)
1296 		return r;
1297 
1298 	return load_dmcu_fw(adev);
1299 }
1300 
1301 static int dm_sw_fini(void *handle)
1302 {
1303 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1304 
1305 	kfree(adev->dm.dmub_fb_info);
1306 	adev->dm.dmub_fb_info = NULL;
1307 
1308 	if (adev->dm.dmub_srv) {
1309 		dmub_srv_destroy(adev->dm.dmub_srv);
1310 		adev->dm.dmub_srv = NULL;
1311 	}
1312 
1313 	if (adev->dm.dmub_fw) {
1314 		release_firmware(adev->dm.dmub_fw);
1315 		adev->dm.dmub_fw = NULL;
1316 	}
1317 
1318 	if(adev->dm.fw_dmcu) {
1319 		release_firmware(adev->dm.fw_dmcu);
1320 		adev->dm.fw_dmcu = NULL;
1321 	}
1322 
1323 	return 0;
1324 }
1325 
1326 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
1327 {
1328 	struct amdgpu_dm_connector *aconnector;
1329 	struct drm_connector *connector;
1330 	struct drm_connector_list_iter iter;
1331 	int ret = 0;
1332 
1333 	drm_connector_list_iter_begin(dev, &iter);
1334 	drm_for_each_connector_iter(connector, &iter) {
1335 		aconnector = to_amdgpu_dm_connector(connector);
1336 		if (aconnector->dc_link->type == dc_connection_mst_branch &&
1337 		    aconnector->mst_mgr.aux) {
1338 			DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
1339 					 aconnector,
1340 					 aconnector->base.base.id);
1341 
1342 			ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
1343 			if (ret < 0) {
1344 				DRM_ERROR("DM_MST: Failed to start MST\n");
1345 				aconnector->dc_link->type =
1346 					dc_connection_single;
1347 				break;
1348 			}
1349 		}
1350 	}
1351 	drm_connector_list_iter_end(&iter);
1352 
1353 	return ret;
1354 }
1355 
1356 static int dm_late_init(void *handle)
1357 {
1358 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1359 
1360 	struct dmcu_iram_parameters params;
1361 	unsigned int linear_lut[16];
1362 	int i;
1363 	struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1364 	bool ret = false;
1365 
1366 	for (i = 0; i < 16; i++)
1367 		linear_lut[i] = 0xFFFF * i / 15;
1368 
1369 	params.set = 0;
1370 	params.backlight_ramping_start = 0xCCCC;
1371 	params.backlight_ramping_reduction = 0xCCCCCCCC;
1372 	params.backlight_lut_array_size = 16;
1373 	params.backlight_lut_array = linear_lut;
1374 
1375 	/* Min backlight level after ABM reduction,  Don't allow below 1%
1376 	 * 0xFFFF x 0.01 = 0x28F
1377 	 */
1378 	params.min_abm_backlight = 0x28F;
1379 
1380 	/* todo will enable for navi10 */
1381 	if (adev->asic_type <= CHIP_RAVEN) {
1382 		ret = dmcu_load_iram(dmcu, params);
1383 
1384 		if (!ret)
1385 			return -EINVAL;
1386 	}
1387 
1388 	return detect_mst_link_for_all_connectors(adev->ddev);
1389 }
1390 
1391 static void s3_handle_mst(struct drm_device *dev, bool suspend)
1392 {
1393 	struct amdgpu_dm_connector *aconnector;
1394 	struct drm_connector *connector;
1395 	struct drm_connector_list_iter iter;
1396 	struct drm_dp_mst_topology_mgr *mgr;
1397 	int ret;
1398 	bool need_hotplug = false;
1399 
1400 	drm_connector_list_iter_begin(dev, &iter);
1401 	drm_for_each_connector_iter(connector, &iter) {
1402 		aconnector = to_amdgpu_dm_connector(connector);
1403 		if (aconnector->dc_link->type != dc_connection_mst_branch ||
1404 		    aconnector->mst_port)
1405 			continue;
1406 
1407 		mgr = &aconnector->mst_mgr;
1408 
1409 		if (suspend) {
1410 			drm_dp_mst_topology_mgr_suspend(mgr);
1411 		} else {
1412 			ret = drm_dp_mst_topology_mgr_resume(mgr, true);
1413 			if (ret < 0) {
1414 				drm_dp_mst_topology_mgr_set_mst(mgr, false);
1415 				need_hotplug = true;
1416 			}
1417 		}
1418 	}
1419 	drm_connector_list_iter_end(&iter);
1420 
1421 	if (need_hotplug)
1422 		drm_kms_helper_hotplug_event(dev);
1423 }
1424 
1425 /**
1426  * dm_hw_init() - Initialize DC device
1427  * @handle: The base driver device containing the amdgpu_dm device.
1428  *
1429  * Initialize the &struct amdgpu_display_manager device. This involves calling
1430  * the initializers of each DM component, then populating the struct with them.
1431  *
1432  * Although the function implies hardware initialization, both hardware and
1433  * software are initialized here. Splitting them out to their relevant init
1434  * hooks is a future TODO item.
1435  *
1436  * Some notable things that are initialized here:
1437  *
1438  * - Display Core, both software and hardware
1439  * - DC modules that we need (freesync and color management)
1440  * - DRM software states
1441  * - Interrupt sources and handlers
1442  * - Vblank support
1443  * - Debug FS entries, if enabled
1444  */
1445 static int dm_hw_init(void *handle)
1446 {
1447 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1448 	/* Create DAL display manager */
1449 	amdgpu_dm_init(adev);
1450 	amdgpu_dm_hpd_init(adev);
1451 
1452 	return 0;
1453 }
1454 
1455 /**
1456  * dm_hw_fini() - Teardown DC device
1457  * @handle: The base driver device containing the amdgpu_dm device.
1458  *
1459  * Teardown components within &struct amdgpu_display_manager that require
1460  * cleanup. This involves cleaning up the DRM device, DC, and any modules that
1461  * were loaded. Also flush IRQ workqueues and disable them.
1462  */
1463 static int dm_hw_fini(void *handle)
1464 {
1465 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1466 
1467 	amdgpu_dm_hpd_fini(adev);
1468 
1469 	amdgpu_dm_irq_fini(adev);
1470 	amdgpu_dm_fini(adev);
1471 	return 0;
1472 }
1473 
1474 static int dm_suspend(void *handle)
1475 {
1476 	struct amdgpu_device *adev = handle;
1477 	struct amdgpu_display_manager *dm = &adev->dm;
1478 	int ret = 0;
1479 
1480 	WARN_ON(adev->dm.cached_state);
1481 	adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
1482 
1483 	s3_handle_mst(adev->ddev, true);
1484 
1485 	amdgpu_dm_irq_suspend(adev);
1486 
1487 
1488 	dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
1489 
1490 	return ret;
1491 }
1492 
1493 static struct amdgpu_dm_connector *
1494 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
1495 					     struct drm_crtc *crtc)
1496 {
1497 	uint32_t i;
1498 	struct drm_connector_state *new_con_state;
1499 	struct drm_connector *connector;
1500 	struct drm_crtc *crtc_from_state;
1501 
1502 	for_each_new_connector_in_state(state, connector, new_con_state, i) {
1503 		crtc_from_state = new_con_state->crtc;
1504 
1505 		if (crtc_from_state == crtc)
1506 			return to_amdgpu_dm_connector(connector);
1507 	}
1508 
1509 	return NULL;
1510 }
1511 
1512 static void emulated_link_detect(struct dc_link *link)
1513 {
1514 	struct dc_sink_init_data sink_init_data = { 0 };
1515 	struct display_sink_capability sink_caps = { 0 };
1516 	enum dc_edid_status edid_status;
1517 	struct dc_context *dc_ctx = link->ctx;
1518 	struct dc_sink *sink = NULL;
1519 	struct dc_sink *prev_sink = NULL;
1520 
1521 	link->type = dc_connection_none;
1522 	prev_sink = link->local_sink;
1523 
1524 	if (prev_sink != NULL)
1525 		dc_sink_retain(prev_sink);
1526 
1527 	switch (link->connector_signal) {
1528 	case SIGNAL_TYPE_HDMI_TYPE_A: {
1529 		sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1530 		sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
1531 		break;
1532 	}
1533 
1534 	case SIGNAL_TYPE_DVI_SINGLE_LINK: {
1535 		sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1536 		sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1537 		break;
1538 	}
1539 
1540 	case SIGNAL_TYPE_DVI_DUAL_LINK: {
1541 		sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1542 		sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1543 		break;
1544 	}
1545 
1546 	case SIGNAL_TYPE_LVDS: {
1547 		sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1548 		sink_caps.signal = SIGNAL_TYPE_LVDS;
1549 		break;
1550 	}
1551 
1552 	case SIGNAL_TYPE_EDP: {
1553 		sink_caps.transaction_type =
1554 			DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
1555 		sink_caps.signal = SIGNAL_TYPE_EDP;
1556 		break;
1557 	}
1558 
1559 	case SIGNAL_TYPE_DISPLAY_PORT: {
1560 		sink_caps.transaction_type =
1561 			DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
1562 		sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
1563 		break;
1564 	}
1565 
1566 	default:
1567 		DC_ERROR("Invalid connector type! signal:%d\n",
1568 			link->connector_signal);
1569 		return;
1570 	}
1571 
1572 	sink_init_data.link = link;
1573 	sink_init_data.sink_signal = sink_caps.signal;
1574 
1575 	sink = dc_sink_create(&sink_init_data);
1576 	if (!sink) {
1577 		DC_ERROR("Failed to create sink!\n");
1578 		return;
1579 	}
1580 
1581 	/* dc_sink_create returns a new reference */
1582 	link->local_sink = sink;
1583 
1584 	edid_status = dm_helpers_read_local_edid(
1585 			link->ctx,
1586 			link,
1587 			sink);
1588 
1589 	if (edid_status != EDID_OK)
1590 		DC_ERROR("Failed to read EDID");
1591 
1592 }
1593 
1594 static int dm_resume(void *handle)
1595 {
1596 	struct amdgpu_device *adev = handle;
1597 	struct drm_device *ddev = adev->ddev;
1598 	struct amdgpu_display_manager *dm = &adev->dm;
1599 	struct amdgpu_dm_connector *aconnector;
1600 	struct drm_connector *connector;
1601 	struct drm_connector_list_iter iter;
1602 	struct drm_crtc *crtc;
1603 	struct drm_crtc_state *new_crtc_state;
1604 	struct dm_crtc_state *dm_new_crtc_state;
1605 	struct drm_plane *plane;
1606 	struct drm_plane_state *new_plane_state;
1607 	struct dm_plane_state *dm_new_plane_state;
1608 	struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
1609 	enum dc_connection_type new_connection_type = dc_connection_none;
1610 	int i, r;
1611 
1612 	/* Recreate dc_state - DC invalidates it when setting power state to S3. */
1613 	dc_release_state(dm_state->context);
1614 	dm_state->context = dc_create_state(dm->dc);
1615 	/* TODO: Remove dc_state->dccg, use dc->dccg directly. */
1616 	dc_resource_state_construct(dm->dc, dm_state->context);
1617 
1618 	/* Before powering on DC we need to re-initialize DMUB. */
1619 	r = dm_dmub_hw_init(adev);
1620 	if (r)
1621 		DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1622 
1623 	/* power on hardware */
1624 	dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
1625 
1626 	/* program HPD filter */
1627 	dc_resume(dm->dc);
1628 
1629 	/*
1630 	 * early enable HPD Rx IRQ, should be done before set mode as short
1631 	 * pulse interrupts are used for MST
1632 	 */
1633 	amdgpu_dm_irq_resume_early(adev);
1634 
1635 	/* On resume we need to rewrite the MSTM control bits to enable MST*/
1636 	s3_handle_mst(ddev, false);
1637 
1638 	/* Do detection*/
1639 	drm_connector_list_iter_begin(ddev, &iter);
1640 	drm_for_each_connector_iter(connector, &iter) {
1641 		aconnector = to_amdgpu_dm_connector(connector);
1642 
1643 		/*
1644 		 * this is the case when traversing through already created
1645 		 * MST connectors, should be skipped
1646 		 */
1647 		if (aconnector->mst_port)
1648 			continue;
1649 
1650 		mutex_lock(&aconnector->hpd_lock);
1651 		if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
1652 			DRM_ERROR("KMS: Failed to detect connector\n");
1653 
1654 		if (aconnector->base.force && new_connection_type == dc_connection_none)
1655 			emulated_link_detect(aconnector->dc_link);
1656 		else
1657 			dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
1658 
1659 		if (aconnector->fake_enable && aconnector->dc_link->local_sink)
1660 			aconnector->fake_enable = false;
1661 
1662 		if (aconnector->dc_sink)
1663 			dc_sink_release(aconnector->dc_sink);
1664 		aconnector->dc_sink = NULL;
1665 		amdgpu_dm_update_connector_after_detect(aconnector);
1666 		mutex_unlock(&aconnector->hpd_lock);
1667 	}
1668 	drm_connector_list_iter_end(&iter);
1669 
1670 	/* Force mode set in atomic commit */
1671 	for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
1672 		new_crtc_state->active_changed = true;
1673 
1674 	/*
1675 	 * atomic_check is expected to create the dc states. We need to release
1676 	 * them here, since they were duplicated as part of the suspend
1677 	 * procedure.
1678 	 */
1679 	for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
1680 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1681 		if (dm_new_crtc_state->stream) {
1682 			WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
1683 			dc_stream_release(dm_new_crtc_state->stream);
1684 			dm_new_crtc_state->stream = NULL;
1685 		}
1686 	}
1687 
1688 	for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
1689 		dm_new_plane_state = to_dm_plane_state(new_plane_state);
1690 		if (dm_new_plane_state->dc_state) {
1691 			WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
1692 			dc_plane_state_release(dm_new_plane_state->dc_state);
1693 			dm_new_plane_state->dc_state = NULL;
1694 		}
1695 	}
1696 
1697 	drm_atomic_helper_resume(ddev, dm->cached_state);
1698 
1699 	dm->cached_state = NULL;
1700 
1701 	amdgpu_dm_irq_resume_late(adev);
1702 
1703 	return 0;
1704 }
1705 
1706 /**
1707  * DOC: DM Lifecycle
1708  *
1709  * DM (and consequently DC) is registered in the amdgpu base driver as a IP
1710  * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
1711  * the base driver's device list to be initialized and torn down accordingly.
1712  *
1713  * The functions to do so are provided as hooks in &struct amd_ip_funcs.
1714  */
1715 
1716 static const struct amd_ip_funcs amdgpu_dm_funcs = {
1717 	.name = "dm",
1718 	.early_init = dm_early_init,
1719 	.late_init = dm_late_init,
1720 	.sw_init = dm_sw_init,
1721 	.sw_fini = dm_sw_fini,
1722 	.hw_init = dm_hw_init,
1723 	.hw_fini = dm_hw_fini,
1724 	.suspend = dm_suspend,
1725 	.resume = dm_resume,
1726 	.is_idle = dm_is_idle,
1727 	.wait_for_idle = dm_wait_for_idle,
1728 	.check_soft_reset = dm_check_soft_reset,
1729 	.soft_reset = dm_soft_reset,
1730 	.set_clockgating_state = dm_set_clockgating_state,
1731 	.set_powergating_state = dm_set_powergating_state,
1732 };
1733 
1734 const struct amdgpu_ip_block_version dm_ip_block =
1735 {
1736 	.type = AMD_IP_BLOCK_TYPE_DCE,
1737 	.major = 1,
1738 	.minor = 0,
1739 	.rev = 0,
1740 	.funcs = &amdgpu_dm_funcs,
1741 };
1742 
1743 
1744 /**
1745  * DOC: atomic
1746  *
1747  * *WIP*
1748  */
1749 
1750 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
1751 	.fb_create = amdgpu_display_user_framebuffer_create,
1752 	.output_poll_changed = drm_fb_helper_output_poll_changed,
1753 	.atomic_check = amdgpu_dm_atomic_check,
1754 	.atomic_commit = amdgpu_dm_atomic_commit,
1755 };
1756 
1757 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
1758 	.atomic_commit_tail = amdgpu_dm_atomic_commit_tail
1759 };
1760 
1761 static void
1762 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
1763 {
1764 	struct drm_connector *connector = &aconnector->base;
1765 	struct drm_device *dev = connector->dev;
1766 	struct dc_sink *sink;
1767 
1768 	/* MST handled by drm_mst framework */
1769 	if (aconnector->mst_mgr.mst_state == true)
1770 		return;
1771 
1772 
1773 	sink = aconnector->dc_link->local_sink;
1774 	if (sink)
1775 		dc_sink_retain(sink);
1776 
1777 	/*
1778 	 * Edid mgmt connector gets first update only in mode_valid hook and then
1779 	 * the connector sink is set to either fake or physical sink depends on link status.
1780 	 * Skip if already done during boot.
1781 	 */
1782 	if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
1783 			&& aconnector->dc_em_sink) {
1784 
1785 		/*
1786 		 * For S3 resume with headless use eml_sink to fake stream
1787 		 * because on resume connector->sink is set to NULL
1788 		 */
1789 		mutex_lock(&dev->mode_config.mutex);
1790 
1791 		if (sink) {
1792 			if (aconnector->dc_sink) {
1793 				amdgpu_dm_update_freesync_caps(connector, NULL);
1794 				/*
1795 				 * retain and release below are used to
1796 				 * bump up refcount for sink because the link doesn't point
1797 				 * to it anymore after disconnect, so on next crtc to connector
1798 				 * reshuffle by UMD we will get into unwanted dc_sink release
1799 				 */
1800 				dc_sink_release(aconnector->dc_sink);
1801 			}
1802 			aconnector->dc_sink = sink;
1803 			dc_sink_retain(aconnector->dc_sink);
1804 			amdgpu_dm_update_freesync_caps(connector,
1805 					aconnector->edid);
1806 		} else {
1807 			amdgpu_dm_update_freesync_caps(connector, NULL);
1808 			if (!aconnector->dc_sink) {
1809 				aconnector->dc_sink = aconnector->dc_em_sink;
1810 				dc_sink_retain(aconnector->dc_sink);
1811 			}
1812 		}
1813 
1814 		mutex_unlock(&dev->mode_config.mutex);
1815 
1816 		if (sink)
1817 			dc_sink_release(sink);
1818 		return;
1819 	}
1820 
1821 	/*
1822 	 * TODO: temporary guard to look for proper fix
1823 	 * if this sink is MST sink, we should not do anything
1824 	 */
1825 	if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1826 		dc_sink_release(sink);
1827 		return;
1828 	}
1829 
1830 	if (aconnector->dc_sink == sink) {
1831 		/*
1832 		 * We got a DP short pulse (Link Loss, DP CTS, etc...).
1833 		 * Do nothing!!
1834 		 */
1835 		DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
1836 				aconnector->connector_id);
1837 		if (sink)
1838 			dc_sink_release(sink);
1839 		return;
1840 	}
1841 
1842 	DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
1843 		aconnector->connector_id, aconnector->dc_sink, sink);
1844 
1845 	mutex_lock(&dev->mode_config.mutex);
1846 
1847 	/*
1848 	 * 1. Update status of the drm connector
1849 	 * 2. Send an event and let userspace tell us what to do
1850 	 */
1851 	if (sink) {
1852 		/*
1853 		 * TODO: check if we still need the S3 mode update workaround.
1854 		 * If yes, put it here.
1855 		 */
1856 		if (aconnector->dc_sink)
1857 			amdgpu_dm_update_freesync_caps(connector, NULL);
1858 
1859 		aconnector->dc_sink = sink;
1860 		dc_sink_retain(aconnector->dc_sink);
1861 		if (sink->dc_edid.length == 0) {
1862 			aconnector->edid = NULL;
1863 			drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
1864 		} else {
1865 			aconnector->edid =
1866 				(struct edid *) sink->dc_edid.raw_edid;
1867 
1868 
1869 			drm_connector_update_edid_property(connector,
1870 					aconnector->edid);
1871 			drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
1872 					    aconnector->edid);
1873 		}
1874 		amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
1875 
1876 	} else {
1877 		drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
1878 		amdgpu_dm_update_freesync_caps(connector, NULL);
1879 		drm_connector_update_edid_property(connector, NULL);
1880 		aconnector->num_modes = 0;
1881 		dc_sink_release(aconnector->dc_sink);
1882 		aconnector->dc_sink = NULL;
1883 		aconnector->edid = NULL;
1884 #ifdef CONFIG_DRM_AMD_DC_HDCP
1885 		/* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
1886 		if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
1887 			connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
1888 #endif
1889 	}
1890 
1891 	mutex_unlock(&dev->mode_config.mutex);
1892 
1893 	if (sink)
1894 		dc_sink_release(sink);
1895 }
1896 
1897 static void handle_hpd_irq(void *param)
1898 {
1899 	struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
1900 	struct drm_connector *connector = &aconnector->base;
1901 	struct drm_device *dev = connector->dev;
1902 	enum dc_connection_type new_connection_type = dc_connection_none;
1903 #ifdef CONFIG_DRM_AMD_DC_HDCP
1904 	struct amdgpu_device *adev = dev->dev_private;
1905 #endif
1906 
1907 	/*
1908 	 * In case of failure or MST no need to update connector status or notify the OS
1909 	 * since (for MST case) MST does this in its own context.
1910 	 */
1911 	mutex_lock(&aconnector->hpd_lock);
1912 
1913 #ifdef CONFIG_DRM_AMD_DC_HDCP
1914 	if (adev->asic_type >= CHIP_RAVEN)
1915 		hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
1916 #endif
1917 	if (aconnector->fake_enable)
1918 		aconnector->fake_enable = false;
1919 
1920 	if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
1921 		DRM_ERROR("KMS: Failed to detect connector\n");
1922 
1923 	if (aconnector->base.force && new_connection_type == dc_connection_none) {
1924 		emulated_link_detect(aconnector->dc_link);
1925 
1926 
1927 		drm_modeset_lock_all(dev);
1928 		dm_restore_drm_connector_state(dev, connector);
1929 		drm_modeset_unlock_all(dev);
1930 
1931 		if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1932 			drm_kms_helper_hotplug_event(dev);
1933 
1934 	} else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
1935 		amdgpu_dm_update_connector_after_detect(aconnector);
1936 
1937 
1938 		drm_modeset_lock_all(dev);
1939 		dm_restore_drm_connector_state(dev, connector);
1940 		drm_modeset_unlock_all(dev);
1941 
1942 		if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1943 			drm_kms_helper_hotplug_event(dev);
1944 	}
1945 	mutex_unlock(&aconnector->hpd_lock);
1946 
1947 }
1948 
1949 static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
1950 {
1951 	uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
1952 	uint8_t dret;
1953 	bool new_irq_handled = false;
1954 	int dpcd_addr;
1955 	int dpcd_bytes_to_read;
1956 
1957 	const int max_process_count = 30;
1958 	int process_count = 0;
1959 
1960 	const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
1961 
1962 	if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
1963 		dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
1964 		/* DPCD 0x200 - 0x201 for downstream IRQ */
1965 		dpcd_addr = DP_SINK_COUNT;
1966 	} else {
1967 		dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
1968 		/* DPCD 0x2002 - 0x2005 for downstream IRQ */
1969 		dpcd_addr = DP_SINK_COUNT_ESI;
1970 	}
1971 
1972 	dret = drm_dp_dpcd_read(
1973 		&aconnector->dm_dp_aux.aux,
1974 		dpcd_addr,
1975 		esi,
1976 		dpcd_bytes_to_read);
1977 
1978 	while (dret == dpcd_bytes_to_read &&
1979 		process_count < max_process_count) {
1980 		uint8_t retry;
1981 		dret = 0;
1982 
1983 		process_count++;
1984 
1985 		DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
1986 		/* handle HPD short pulse irq */
1987 		if (aconnector->mst_mgr.mst_state)
1988 			drm_dp_mst_hpd_irq(
1989 				&aconnector->mst_mgr,
1990 				esi,
1991 				&new_irq_handled);
1992 
1993 		if (new_irq_handled) {
1994 			/* ACK at DPCD to notify down stream */
1995 			const int ack_dpcd_bytes_to_write =
1996 				dpcd_bytes_to_read - 1;
1997 
1998 			for (retry = 0; retry < 3; retry++) {
1999 				uint8_t wret;
2000 
2001 				wret = drm_dp_dpcd_write(
2002 					&aconnector->dm_dp_aux.aux,
2003 					dpcd_addr + 1,
2004 					&esi[1],
2005 					ack_dpcd_bytes_to_write);
2006 				if (wret == ack_dpcd_bytes_to_write)
2007 					break;
2008 			}
2009 
2010 			/* check if there is new irq to be handled */
2011 			dret = drm_dp_dpcd_read(
2012 				&aconnector->dm_dp_aux.aux,
2013 				dpcd_addr,
2014 				esi,
2015 				dpcd_bytes_to_read);
2016 
2017 			new_irq_handled = false;
2018 		} else {
2019 			break;
2020 		}
2021 	}
2022 
2023 	if (process_count == max_process_count)
2024 		DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
2025 }
2026 
2027 static void handle_hpd_rx_irq(void *param)
2028 {
2029 	struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
2030 	struct drm_connector *connector = &aconnector->base;
2031 	struct drm_device *dev = connector->dev;
2032 	struct dc_link *dc_link = aconnector->dc_link;
2033 	bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
2034 	enum dc_connection_type new_connection_type = dc_connection_none;
2035 #ifdef CONFIG_DRM_AMD_DC_HDCP
2036 	union hpd_irq_data hpd_irq_data;
2037 	struct amdgpu_device *adev = dev->dev_private;
2038 
2039 	memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
2040 #endif
2041 
2042 	/*
2043 	 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
2044 	 * conflict, after implement i2c helper, this mutex should be
2045 	 * retired.
2046 	 */
2047 	if (dc_link->type != dc_connection_mst_branch)
2048 		mutex_lock(&aconnector->hpd_lock);
2049 
2050 
2051 #ifdef CONFIG_DRM_AMD_DC_HDCP
2052 	if (dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data, NULL) &&
2053 #else
2054 	if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) &&
2055 #endif
2056 			!is_mst_root_connector) {
2057 		/* Downstream Port status changed. */
2058 		if (!dc_link_detect_sink(dc_link, &new_connection_type))
2059 			DRM_ERROR("KMS: Failed to detect connector\n");
2060 
2061 		if (aconnector->base.force && new_connection_type == dc_connection_none) {
2062 			emulated_link_detect(dc_link);
2063 
2064 			if (aconnector->fake_enable)
2065 				aconnector->fake_enable = false;
2066 
2067 			amdgpu_dm_update_connector_after_detect(aconnector);
2068 
2069 
2070 			drm_modeset_lock_all(dev);
2071 			dm_restore_drm_connector_state(dev, connector);
2072 			drm_modeset_unlock_all(dev);
2073 
2074 			drm_kms_helper_hotplug_event(dev);
2075 		} else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
2076 
2077 			if (aconnector->fake_enable)
2078 				aconnector->fake_enable = false;
2079 
2080 			amdgpu_dm_update_connector_after_detect(aconnector);
2081 
2082 
2083 			drm_modeset_lock_all(dev);
2084 			dm_restore_drm_connector_state(dev, connector);
2085 			drm_modeset_unlock_all(dev);
2086 
2087 			drm_kms_helper_hotplug_event(dev);
2088 		}
2089 	}
2090 #ifdef CONFIG_DRM_AMD_DC_HDCP
2091 	if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ)
2092 		hdcp_handle_cpirq(adev->dm.hdcp_workqueue,  aconnector->base.index);
2093 #endif
2094 	if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
2095 	    (dc_link->type == dc_connection_mst_branch))
2096 		dm_handle_hpd_rx_irq(aconnector);
2097 
2098 	if (dc_link->type != dc_connection_mst_branch) {
2099 		drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
2100 		mutex_unlock(&aconnector->hpd_lock);
2101 	}
2102 }
2103 
2104 static void register_hpd_handlers(struct amdgpu_device *adev)
2105 {
2106 	struct drm_device *dev = adev->ddev;
2107 	struct drm_connector *connector;
2108 	struct amdgpu_dm_connector *aconnector;
2109 	const struct dc_link *dc_link;
2110 	struct dc_interrupt_params int_params = {0};
2111 
2112 	int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
2113 	int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
2114 
2115 	list_for_each_entry(connector,
2116 			&dev->mode_config.connector_list, head)	{
2117 
2118 		aconnector = to_amdgpu_dm_connector(connector);
2119 		dc_link = aconnector->dc_link;
2120 
2121 		if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
2122 			int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
2123 			int_params.irq_source = dc_link->irq_source_hpd;
2124 
2125 			amdgpu_dm_irq_register_interrupt(adev, &int_params,
2126 					handle_hpd_irq,
2127 					(void *) aconnector);
2128 		}
2129 
2130 		if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
2131 
2132 			/* Also register for DP short pulse (hpd_rx). */
2133 			int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
2134 			int_params.irq_source =	dc_link->irq_source_hpd_rx;
2135 
2136 			amdgpu_dm_irq_register_interrupt(adev, &int_params,
2137 					handle_hpd_rx_irq,
2138 					(void *) aconnector);
2139 		}
2140 	}
2141 }
2142 
2143 /* Register IRQ sources and initialize IRQ callbacks */
2144 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
2145 {
2146 	struct dc *dc = adev->dm.dc;
2147 	struct common_irq_params *c_irq_params;
2148 	struct dc_interrupt_params int_params = {0};
2149 	int r;
2150 	int i;
2151 	unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
2152 
2153 	if (adev->asic_type >= CHIP_VEGA10)
2154 		client_id = SOC15_IH_CLIENTID_DCE;
2155 
2156 	int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
2157 	int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
2158 
2159 	/*
2160 	 * Actions of amdgpu_irq_add_id():
2161 	 * 1. Register a set() function with base driver.
2162 	 *    Base driver will call set() function to enable/disable an
2163 	 *    interrupt in DC hardware.
2164 	 * 2. Register amdgpu_dm_irq_handler().
2165 	 *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
2166 	 *    coming from DC hardware.
2167 	 *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
2168 	 *    for acknowledging and handling. */
2169 
2170 	/* Use VBLANK interrupt */
2171 	for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
2172 		r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
2173 		if (r) {
2174 			DRM_ERROR("Failed to add crtc irq id!\n");
2175 			return r;
2176 		}
2177 
2178 		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2179 		int_params.irq_source =
2180 			dc_interrupt_to_irq_source(dc, i, 0);
2181 
2182 		c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
2183 
2184 		c_irq_params->adev = adev;
2185 		c_irq_params->irq_src = int_params.irq_source;
2186 
2187 		amdgpu_dm_irq_register_interrupt(adev, &int_params,
2188 				dm_crtc_high_irq, c_irq_params);
2189 	}
2190 
2191 	/* Use VUPDATE interrupt */
2192 	for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
2193 		r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
2194 		if (r) {
2195 			DRM_ERROR("Failed to add vupdate irq id!\n");
2196 			return r;
2197 		}
2198 
2199 		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2200 		int_params.irq_source =
2201 			dc_interrupt_to_irq_source(dc, i, 0);
2202 
2203 		c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
2204 
2205 		c_irq_params->adev = adev;
2206 		c_irq_params->irq_src = int_params.irq_source;
2207 
2208 		amdgpu_dm_irq_register_interrupt(adev, &int_params,
2209 				dm_vupdate_high_irq, c_irq_params);
2210 	}
2211 
2212 	/* Use GRPH_PFLIP interrupt */
2213 	for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
2214 			i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2215 		r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
2216 		if (r) {
2217 			DRM_ERROR("Failed to add page flip irq id!\n");
2218 			return r;
2219 		}
2220 
2221 		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2222 		int_params.irq_source =
2223 			dc_interrupt_to_irq_source(dc, i, 0);
2224 
2225 		c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
2226 
2227 		c_irq_params->adev = adev;
2228 		c_irq_params->irq_src = int_params.irq_source;
2229 
2230 		amdgpu_dm_irq_register_interrupt(adev, &int_params,
2231 				dm_pflip_high_irq, c_irq_params);
2232 
2233 	}
2234 
2235 	/* HPD */
2236 	r = amdgpu_irq_add_id(adev, client_id,
2237 			VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
2238 	if (r) {
2239 		DRM_ERROR("Failed to add hpd irq id!\n");
2240 		return r;
2241 	}
2242 
2243 	register_hpd_handlers(adev);
2244 
2245 	return 0;
2246 }
2247 
2248 #if defined(CONFIG_DRM_AMD_DC_DCN)
2249 /* Register IRQ sources and initialize IRQ callbacks */
2250 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
2251 {
2252 	struct dc *dc = adev->dm.dc;
2253 	struct common_irq_params *c_irq_params;
2254 	struct dc_interrupt_params int_params = {0};
2255 	int r;
2256 	int i;
2257 
2258 	int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
2259 	int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
2260 
2261 	/*
2262 	 * Actions of amdgpu_irq_add_id():
2263 	 * 1. Register a set() function with base driver.
2264 	 *    Base driver will call set() function to enable/disable an
2265 	 *    interrupt in DC hardware.
2266 	 * 2. Register amdgpu_dm_irq_handler().
2267 	 *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
2268 	 *    coming from DC hardware.
2269 	 *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
2270 	 *    for acknowledging and handling.
2271 	 */
2272 
2273 	/* Use VSTARTUP interrupt */
2274 	for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
2275 			i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
2276 			i++) {
2277 		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
2278 
2279 		if (r) {
2280 			DRM_ERROR("Failed to add crtc irq id!\n");
2281 			return r;
2282 		}
2283 
2284 		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2285 		int_params.irq_source =
2286 			dc_interrupt_to_irq_source(dc, i, 0);
2287 
2288 		c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
2289 
2290 		c_irq_params->adev = adev;
2291 		c_irq_params->irq_src = int_params.irq_source;
2292 
2293 		amdgpu_dm_irq_register_interrupt(adev, &int_params,
2294 				dm_dcn_crtc_high_irq, c_irq_params);
2295 	}
2296 
2297 	/* Use GRPH_PFLIP interrupt */
2298 	for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
2299 			i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
2300 			i++) {
2301 		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
2302 		if (r) {
2303 			DRM_ERROR("Failed to add page flip irq id!\n");
2304 			return r;
2305 		}
2306 
2307 		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2308 		int_params.irq_source =
2309 			dc_interrupt_to_irq_source(dc, i, 0);
2310 
2311 		c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
2312 
2313 		c_irq_params->adev = adev;
2314 		c_irq_params->irq_src = int_params.irq_source;
2315 
2316 		amdgpu_dm_irq_register_interrupt(adev, &int_params,
2317 				dm_pflip_high_irq, c_irq_params);
2318 
2319 	}
2320 
2321 	/* HPD */
2322 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
2323 			&adev->hpd_irq);
2324 	if (r) {
2325 		DRM_ERROR("Failed to add hpd irq id!\n");
2326 		return r;
2327 	}
2328 
2329 	register_hpd_handlers(adev);
2330 
2331 	return 0;
2332 }
2333 #endif
2334 
2335 /*
2336  * Acquires the lock for the atomic state object and returns
2337  * the new atomic state.
2338  *
2339  * This should only be called during atomic check.
2340  */
2341 static int dm_atomic_get_state(struct drm_atomic_state *state,
2342 			       struct dm_atomic_state **dm_state)
2343 {
2344 	struct drm_device *dev = state->dev;
2345 	struct amdgpu_device *adev = dev->dev_private;
2346 	struct amdgpu_display_manager *dm = &adev->dm;
2347 	struct drm_private_state *priv_state;
2348 
2349 	if (*dm_state)
2350 		return 0;
2351 
2352 	priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
2353 	if (IS_ERR(priv_state))
2354 		return PTR_ERR(priv_state);
2355 
2356 	*dm_state = to_dm_atomic_state(priv_state);
2357 
2358 	return 0;
2359 }
2360 
2361 struct dm_atomic_state *
2362 dm_atomic_get_new_state(struct drm_atomic_state *state)
2363 {
2364 	struct drm_device *dev = state->dev;
2365 	struct amdgpu_device *adev = dev->dev_private;
2366 	struct amdgpu_display_manager *dm = &adev->dm;
2367 	struct drm_private_obj *obj;
2368 	struct drm_private_state *new_obj_state;
2369 	int i;
2370 
2371 	for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
2372 		if (obj->funcs == dm->atomic_obj.funcs)
2373 			return to_dm_atomic_state(new_obj_state);
2374 	}
2375 
2376 	return NULL;
2377 }
2378 
2379 struct dm_atomic_state *
2380 dm_atomic_get_old_state(struct drm_atomic_state *state)
2381 {
2382 	struct drm_device *dev = state->dev;
2383 	struct amdgpu_device *adev = dev->dev_private;
2384 	struct amdgpu_display_manager *dm = &adev->dm;
2385 	struct drm_private_obj *obj;
2386 	struct drm_private_state *old_obj_state;
2387 	int i;
2388 
2389 	for_each_old_private_obj_in_state(state, obj, old_obj_state, i) {
2390 		if (obj->funcs == dm->atomic_obj.funcs)
2391 			return to_dm_atomic_state(old_obj_state);
2392 	}
2393 
2394 	return NULL;
2395 }
2396 
2397 static struct drm_private_state *
2398 dm_atomic_duplicate_state(struct drm_private_obj *obj)
2399 {
2400 	struct dm_atomic_state *old_state, *new_state;
2401 
2402 	new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
2403 	if (!new_state)
2404 		return NULL;
2405 
2406 	__drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
2407 
2408 	old_state = to_dm_atomic_state(obj->state);
2409 
2410 	if (old_state && old_state->context)
2411 		new_state->context = dc_copy_state(old_state->context);
2412 
2413 	if (!new_state->context) {
2414 		kfree(new_state);
2415 		return NULL;
2416 	}
2417 
2418 	return &new_state->base;
2419 }
2420 
2421 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
2422 				    struct drm_private_state *state)
2423 {
2424 	struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
2425 
2426 	if (dm_state && dm_state->context)
2427 		dc_release_state(dm_state->context);
2428 
2429 	kfree(dm_state);
2430 }
2431 
2432 static struct drm_private_state_funcs dm_atomic_state_funcs = {
2433 	.atomic_duplicate_state = dm_atomic_duplicate_state,
2434 	.atomic_destroy_state = dm_atomic_destroy_state,
2435 };
2436 
2437 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
2438 {
2439 	struct dm_atomic_state *state;
2440 	int r;
2441 
2442 	adev->mode_info.mode_config_initialized = true;
2443 
2444 	adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
2445 	adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
2446 
2447 	adev->ddev->mode_config.max_width = 16384;
2448 	adev->ddev->mode_config.max_height = 16384;
2449 
2450 	adev->ddev->mode_config.preferred_depth = 24;
2451 	adev->ddev->mode_config.prefer_shadow = 1;
2452 	/* indicates support for immediate flip */
2453 	adev->ddev->mode_config.async_page_flip = true;
2454 
2455 	adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
2456 
2457 	state = kzalloc(sizeof(*state), GFP_KERNEL);
2458 	if (!state)
2459 		return -ENOMEM;
2460 
2461 	state->context = dc_create_state(adev->dm.dc);
2462 	if (!state->context) {
2463 		kfree(state);
2464 		return -ENOMEM;
2465 	}
2466 
2467 	dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
2468 
2469 	drm_atomic_private_obj_init(adev->ddev,
2470 				    &adev->dm.atomic_obj,
2471 				    &state->base,
2472 				    &dm_atomic_state_funcs);
2473 
2474 	r = amdgpu_display_modeset_create_props(adev);
2475 	if (r)
2476 		return r;
2477 
2478 	r = amdgpu_dm_audio_init(adev);
2479 	if (r)
2480 		return r;
2481 
2482 	return 0;
2483 }
2484 
2485 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
2486 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
2487 
2488 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2489 	defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2490 
2491 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm)
2492 {
2493 #if defined(CONFIG_ACPI)
2494 	struct amdgpu_dm_backlight_caps caps;
2495 
2496 	if (dm->backlight_caps.caps_valid)
2497 		return;
2498 
2499 	amdgpu_acpi_get_backlight_caps(dm->adev, &caps);
2500 	if (caps.caps_valid) {
2501 		dm->backlight_caps.min_input_signal = caps.min_input_signal;
2502 		dm->backlight_caps.max_input_signal = caps.max_input_signal;
2503 		dm->backlight_caps.caps_valid = true;
2504 	} else {
2505 		dm->backlight_caps.min_input_signal =
2506 				AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
2507 		dm->backlight_caps.max_input_signal =
2508 				AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
2509 	}
2510 #else
2511 	dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
2512 	dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
2513 #endif
2514 }
2515 
2516 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
2517 {
2518 	struct amdgpu_display_manager *dm = bl_get_data(bd);
2519 	struct amdgpu_dm_backlight_caps caps;
2520 	uint32_t brightness = bd->props.brightness;
2521 
2522 	amdgpu_dm_update_backlight_caps(dm);
2523 	caps = dm->backlight_caps;
2524 	/*
2525 	 * The brightness input is in the range 0-255
2526 	 * It needs to be rescaled to be between the
2527 	 * requested min and max input signal
2528 	 *
2529 	 * It also needs to be scaled up by 0x101 to
2530 	 * match the DC interface which has a range of
2531 	 * 0 to 0xffff
2532 	 */
2533 	brightness =
2534 		brightness
2535 		* 0x101
2536 		* (caps.max_input_signal - caps.min_input_signal)
2537 		/ AMDGPU_MAX_BL_LEVEL
2538 		+ caps.min_input_signal * 0x101;
2539 
2540 	if (dc_link_set_backlight_level(dm->backlight_link,
2541 			brightness, 0))
2542 		return 0;
2543 	else
2544 		return 1;
2545 }
2546 
2547 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
2548 {
2549 	struct amdgpu_display_manager *dm = bl_get_data(bd);
2550 	int ret = dc_link_get_backlight_level(dm->backlight_link);
2551 
2552 	if (ret == DC_ERROR_UNEXPECTED)
2553 		return bd->props.brightness;
2554 	return ret;
2555 }
2556 
2557 static const struct backlight_ops amdgpu_dm_backlight_ops = {
2558 	.options = BL_CORE_SUSPENDRESUME,
2559 	.get_brightness = amdgpu_dm_backlight_get_brightness,
2560 	.update_status	= amdgpu_dm_backlight_update_status,
2561 };
2562 
2563 static void
2564 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
2565 {
2566 	char bl_name[16];
2567 	struct backlight_properties props = { 0 };
2568 
2569 	amdgpu_dm_update_backlight_caps(dm);
2570 
2571 	props.max_brightness = AMDGPU_MAX_BL_LEVEL;
2572 	props.brightness = AMDGPU_MAX_BL_LEVEL;
2573 	props.type = BACKLIGHT_RAW;
2574 
2575 	snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
2576 			dm->adev->ddev->primary->index);
2577 
2578 	dm->backlight_dev = backlight_device_register(bl_name,
2579 			dm->adev->ddev->dev,
2580 			dm,
2581 			&amdgpu_dm_backlight_ops,
2582 			&props);
2583 
2584 	if (IS_ERR(dm->backlight_dev))
2585 		DRM_ERROR("DM: Backlight registration failed!\n");
2586 	else
2587 		DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
2588 }
2589 
2590 #endif
2591 
2592 static int initialize_plane(struct amdgpu_display_manager *dm,
2593 			    struct amdgpu_mode_info *mode_info, int plane_id,
2594 			    enum drm_plane_type plane_type,
2595 			    const struct dc_plane_cap *plane_cap)
2596 {
2597 	struct drm_plane *plane;
2598 	unsigned long possible_crtcs;
2599 	int ret = 0;
2600 
2601 	plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
2602 	if (!plane) {
2603 		DRM_ERROR("KMS: Failed to allocate plane\n");
2604 		return -ENOMEM;
2605 	}
2606 	plane->type = plane_type;
2607 
2608 	/*
2609 	 * HACK: IGT tests expect that the primary plane for a CRTC
2610 	 * can only have one possible CRTC. Only expose support for
2611 	 * any CRTC if they're not going to be used as a primary plane
2612 	 * for a CRTC - like overlay or underlay planes.
2613 	 */
2614 	possible_crtcs = 1 << plane_id;
2615 	if (plane_id >= dm->dc->caps.max_streams)
2616 		possible_crtcs = 0xff;
2617 
2618 	ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
2619 
2620 	if (ret) {
2621 		DRM_ERROR("KMS: Failed to initialize plane\n");
2622 		kfree(plane);
2623 		return ret;
2624 	}
2625 
2626 	if (mode_info)
2627 		mode_info->planes[plane_id] = plane;
2628 
2629 	return ret;
2630 }
2631 
2632 
2633 static void register_backlight_device(struct amdgpu_display_manager *dm,
2634 				      struct dc_link *link)
2635 {
2636 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2637 	defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2638 
2639 	if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
2640 	    link->type != dc_connection_none) {
2641 		/*
2642 		 * Event if registration failed, we should continue with
2643 		 * DM initialization because not having a backlight control
2644 		 * is better then a black screen.
2645 		 */
2646 		amdgpu_dm_register_backlight_device(dm);
2647 
2648 		if (dm->backlight_dev)
2649 			dm->backlight_link = link;
2650 	}
2651 #endif
2652 }
2653 
2654 
2655 /*
2656  * In this architecture, the association
2657  * connector -> encoder -> crtc
2658  * id not really requried. The crtc and connector will hold the
2659  * display_index as an abstraction to use with DAL component
2660  *
2661  * Returns 0 on success
2662  */
2663 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
2664 {
2665 	struct amdgpu_display_manager *dm = &adev->dm;
2666 	int32_t i;
2667 	struct amdgpu_dm_connector *aconnector = NULL;
2668 	struct amdgpu_encoder *aencoder = NULL;
2669 	struct amdgpu_mode_info *mode_info = &adev->mode_info;
2670 	uint32_t link_cnt;
2671 	int32_t primary_planes;
2672 	enum dc_connection_type new_connection_type = dc_connection_none;
2673 	const struct dc_plane_cap *plane;
2674 
2675 	link_cnt = dm->dc->caps.max_links;
2676 	if (amdgpu_dm_mode_config_init(dm->adev)) {
2677 		DRM_ERROR("DM: Failed to initialize mode config\n");
2678 		return -EINVAL;
2679 	}
2680 
2681 	/* There is one primary plane per CRTC */
2682 	primary_planes = dm->dc->caps.max_streams;
2683 	ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
2684 
2685 	/*
2686 	 * Initialize primary planes, implicit planes for legacy IOCTLS.
2687 	 * Order is reversed to match iteration order in atomic check.
2688 	 */
2689 	for (i = (primary_planes - 1); i >= 0; i--) {
2690 		plane = &dm->dc->caps.planes[i];
2691 
2692 		if (initialize_plane(dm, mode_info, i,
2693 				     DRM_PLANE_TYPE_PRIMARY, plane)) {
2694 			DRM_ERROR("KMS: Failed to initialize primary plane\n");
2695 			goto fail;
2696 		}
2697 	}
2698 
2699 	/*
2700 	 * Initialize overlay planes, index starting after primary planes.
2701 	 * These planes have a higher DRM index than the primary planes since
2702 	 * they should be considered as having a higher z-order.
2703 	 * Order is reversed to match iteration order in atomic check.
2704 	 *
2705 	 * Only support DCN for now, and only expose one so we don't encourage
2706 	 * userspace to use up all the pipes.
2707 	 */
2708 	for (i = 0; i < dm->dc->caps.max_planes; ++i) {
2709 		struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
2710 
2711 		if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
2712 			continue;
2713 
2714 		if (!plane->blends_with_above || !plane->blends_with_below)
2715 			continue;
2716 
2717 		if (!plane->pixel_format_support.argb8888)
2718 			continue;
2719 
2720 		if (initialize_plane(dm, NULL, primary_planes + i,
2721 				     DRM_PLANE_TYPE_OVERLAY, plane)) {
2722 			DRM_ERROR("KMS: Failed to initialize overlay plane\n");
2723 			goto fail;
2724 		}
2725 
2726 		/* Only create one overlay plane. */
2727 		break;
2728 	}
2729 
2730 	for (i = 0; i < dm->dc->caps.max_streams; i++)
2731 		if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
2732 			DRM_ERROR("KMS: Failed to initialize crtc\n");
2733 			goto fail;
2734 		}
2735 
2736 	dm->display_indexes_num = dm->dc->caps.max_streams;
2737 
2738 	/* loops over all connectors on the board */
2739 	for (i = 0; i < link_cnt; i++) {
2740 		struct dc_link *link = NULL;
2741 
2742 		if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
2743 			DRM_ERROR(
2744 				"KMS: Cannot support more than %d display indexes\n",
2745 					AMDGPU_DM_MAX_DISPLAY_INDEX);
2746 			continue;
2747 		}
2748 
2749 		aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
2750 		if (!aconnector)
2751 			goto fail;
2752 
2753 		aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
2754 		if (!aencoder)
2755 			goto fail;
2756 
2757 		if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
2758 			DRM_ERROR("KMS: Failed to initialize encoder\n");
2759 			goto fail;
2760 		}
2761 
2762 		if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
2763 			DRM_ERROR("KMS: Failed to initialize connector\n");
2764 			goto fail;
2765 		}
2766 
2767 		link = dc_get_link_at_index(dm->dc, i);
2768 
2769 		if (!dc_link_detect_sink(link, &new_connection_type))
2770 			DRM_ERROR("KMS: Failed to detect connector\n");
2771 
2772 		if (aconnector->base.force && new_connection_type == dc_connection_none) {
2773 			emulated_link_detect(link);
2774 			amdgpu_dm_update_connector_after_detect(aconnector);
2775 
2776 		} else if (dc_link_detect(link, DETECT_REASON_BOOT)) {
2777 			amdgpu_dm_update_connector_after_detect(aconnector);
2778 			register_backlight_device(dm, link);
2779 			if (amdgpu_dc_feature_mask & DC_PSR_MASK)
2780 				amdgpu_dm_set_psr_caps(link);
2781 		}
2782 
2783 
2784 	}
2785 
2786 	/* Software is initialized. Now we can register interrupt handlers. */
2787 	switch (adev->asic_type) {
2788 	case CHIP_BONAIRE:
2789 	case CHIP_HAWAII:
2790 	case CHIP_KAVERI:
2791 	case CHIP_KABINI:
2792 	case CHIP_MULLINS:
2793 	case CHIP_TONGA:
2794 	case CHIP_FIJI:
2795 	case CHIP_CARRIZO:
2796 	case CHIP_STONEY:
2797 	case CHIP_POLARIS11:
2798 	case CHIP_POLARIS10:
2799 	case CHIP_POLARIS12:
2800 	case CHIP_VEGAM:
2801 	case CHIP_VEGA10:
2802 	case CHIP_VEGA12:
2803 	case CHIP_VEGA20:
2804 		if (dce110_register_irq_handlers(dm->adev)) {
2805 			DRM_ERROR("DM: Failed to initialize IRQ\n");
2806 			goto fail;
2807 		}
2808 		break;
2809 #if defined(CONFIG_DRM_AMD_DC_DCN)
2810 	case CHIP_RAVEN:
2811 	case CHIP_NAVI12:
2812 	case CHIP_NAVI10:
2813 	case CHIP_NAVI14:
2814 	case CHIP_RENOIR:
2815 		if (dcn10_register_irq_handlers(dm->adev)) {
2816 			DRM_ERROR("DM: Failed to initialize IRQ\n");
2817 			goto fail;
2818 		}
2819 		break;
2820 #endif
2821 	default:
2822 		DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2823 		goto fail;
2824 	}
2825 
2826 	if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
2827 		dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
2828 
2829 	return 0;
2830 fail:
2831 	kfree(aencoder);
2832 	kfree(aconnector);
2833 
2834 	return -EINVAL;
2835 }
2836 
2837 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
2838 {
2839 	drm_mode_config_cleanup(dm->ddev);
2840 	drm_atomic_private_obj_fini(&dm->atomic_obj);
2841 	return;
2842 }
2843 
2844 /******************************************************************************
2845  * amdgpu_display_funcs functions
2846  *****************************************************************************/
2847 
2848 /*
2849  * dm_bandwidth_update - program display watermarks
2850  *
2851  * @adev: amdgpu_device pointer
2852  *
2853  * Calculate and program the display watermarks and line buffer allocation.
2854  */
2855 static void dm_bandwidth_update(struct amdgpu_device *adev)
2856 {
2857 	/* TODO: implement later */
2858 }
2859 
2860 static const struct amdgpu_display_funcs dm_display_funcs = {
2861 	.bandwidth_update = dm_bandwidth_update, /* called unconditionally */
2862 	.vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
2863 	.backlight_set_level = NULL, /* never called for DC */
2864 	.backlight_get_level = NULL, /* never called for DC */
2865 	.hpd_sense = NULL,/* called unconditionally */
2866 	.hpd_set_polarity = NULL, /* called unconditionally */
2867 	.hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
2868 	.page_flip_get_scanoutpos =
2869 		dm_crtc_get_scanoutpos,/* called unconditionally */
2870 	.add_encoder = NULL, /* VBIOS parsing. DAL does it. */
2871 	.add_connector = NULL, /* VBIOS parsing. DAL does it. */
2872 };
2873 
2874 #if defined(CONFIG_DEBUG_KERNEL_DC)
2875 
2876 static ssize_t s3_debug_store(struct device *device,
2877 			      struct device_attribute *attr,
2878 			      const char *buf,
2879 			      size_t count)
2880 {
2881 	int ret;
2882 	int s3_state;
2883 	struct drm_device *drm_dev = dev_get_drvdata(device);
2884 	struct amdgpu_device *adev = drm_dev->dev_private;
2885 
2886 	ret = kstrtoint(buf, 0, &s3_state);
2887 
2888 	if (ret == 0) {
2889 		if (s3_state) {
2890 			dm_resume(adev);
2891 			drm_kms_helper_hotplug_event(adev->ddev);
2892 		} else
2893 			dm_suspend(adev);
2894 	}
2895 
2896 	return ret == 0 ? count : 0;
2897 }
2898 
2899 DEVICE_ATTR_WO(s3_debug);
2900 
2901 #endif
2902 
2903 static int dm_early_init(void *handle)
2904 {
2905 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2906 
2907 	switch (adev->asic_type) {
2908 	case CHIP_BONAIRE:
2909 	case CHIP_HAWAII:
2910 		adev->mode_info.num_crtc = 6;
2911 		adev->mode_info.num_hpd = 6;
2912 		adev->mode_info.num_dig = 6;
2913 		break;
2914 	case CHIP_KAVERI:
2915 		adev->mode_info.num_crtc = 4;
2916 		adev->mode_info.num_hpd = 6;
2917 		adev->mode_info.num_dig = 7;
2918 		break;
2919 	case CHIP_KABINI:
2920 	case CHIP_MULLINS:
2921 		adev->mode_info.num_crtc = 2;
2922 		adev->mode_info.num_hpd = 6;
2923 		adev->mode_info.num_dig = 6;
2924 		break;
2925 	case CHIP_FIJI:
2926 	case CHIP_TONGA:
2927 		adev->mode_info.num_crtc = 6;
2928 		adev->mode_info.num_hpd = 6;
2929 		adev->mode_info.num_dig = 7;
2930 		break;
2931 	case CHIP_CARRIZO:
2932 		adev->mode_info.num_crtc = 3;
2933 		adev->mode_info.num_hpd = 6;
2934 		adev->mode_info.num_dig = 9;
2935 		break;
2936 	case CHIP_STONEY:
2937 		adev->mode_info.num_crtc = 2;
2938 		adev->mode_info.num_hpd = 6;
2939 		adev->mode_info.num_dig = 9;
2940 		break;
2941 	case CHIP_POLARIS11:
2942 	case CHIP_POLARIS12:
2943 		adev->mode_info.num_crtc = 5;
2944 		adev->mode_info.num_hpd = 5;
2945 		adev->mode_info.num_dig = 5;
2946 		break;
2947 	case CHIP_POLARIS10:
2948 	case CHIP_VEGAM:
2949 		adev->mode_info.num_crtc = 6;
2950 		adev->mode_info.num_hpd = 6;
2951 		adev->mode_info.num_dig = 6;
2952 		break;
2953 	case CHIP_VEGA10:
2954 	case CHIP_VEGA12:
2955 	case CHIP_VEGA20:
2956 		adev->mode_info.num_crtc = 6;
2957 		adev->mode_info.num_hpd = 6;
2958 		adev->mode_info.num_dig = 6;
2959 		break;
2960 #if defined(CONFIG_DRM_AMD_DC_DCN)
2961 	case CHIP_RAVEN:
2962 		adev->mode_info.num_crtc = 4;
2963 		adev->mode_info.num_hpd = 4;
2964 		adev->mode_info.num_dig = 4;
2965 		break;
2966 #endif
2967 	case CHIP_NAVI10:
2968 	case CHIP_NAVI12:
2969 		adev->mode_info.num_crtc = 6;
2970 		adev->mode_info.num_hpd = 6;
2971 		adev->mode_info.num_dig = 6;
2972 		break;
2973 	case CHIP_NAVI14:
2974 		adev->mode_info.num_crtc = 5;
2975 		adev->mode_info.num_hpd = 5;
2976 		adev->mode_info.num_dig = 5;
2977 		break;
2978 	case CHIP_RENOIR:
2979 		adev->mode_info.num_crtc = 4;
2980 		adev->mode_info.num_hpd = 4;
2981 		adev->mode_info.num_dig = 4;
2982 		break;
2983 	default:
2984 		DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2985 		return -EINVAL;
2986 	}
2987 
2988 	amdgpu_dm_set_irq_funcs(adev);
2989 
2990 	if (adev->mode_info.funcs == NULL)
2991 		adev->mode_info.funcs = &dm_display_funcs;
2992 
2993 	/*
2994 	 * Note: Do NOT change adev->audio_endpt_rreg and
2995 	 * adev->audio_endpt_wreg because they are initialised in
2996 	 * amdgpu_device_init()
2997 	 */
2998 #if defined(CONFIG_DEBUG_KERNEL_DC)
2999 	device_create_file(
3000 		adev->ddev->dev,
3001 		&dev_attr_s3_debug);
3002 #endif
3003 
3004 	return 0;
3005 }
3006 
3007 static bool modeset_required(struct drm_crtc_state *crtc_state,
3008 			     struct dc_stream_state *new_stream,
3009 			     struct dc_stream_state *old_stream)
3010 {
3011 	if (!drm_atomic_crtc_needs_modeset(crtc_state))
3012 		return false;
3013 
3014 	if (!crtc_state->enable)
3015 		return false;
3016 
3017 	return crtc_state->active;
3018 }
3019 
3020 static bool modereset_required(struct drm_crtc_state *crtc_state)
3021 {
3022 	if (!drm_atomic_crtc_needs_modeset(crtc_state))
3023 		return false;
3024 
3025 	return !crtc_state->enable || !crtc_state->active;
3026 }
3027 
3028 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
3029 {
3030 	drm_encoder_cleanup(encoder);
3031 	kfree(encoder);
3032 }
3033 
3034 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
3035 	.destroy = amdgpu_dm_encoder_destroy,
3036 };
3037 
3038 
3039 static int fill_dc_scaling_info(const struct drm_plane_state *state,
3040 				struct dc_scaling_info *scaling_info)
3041 {
3042 	int scale_w, scale_h;
3043 
3044 	memset(scaling_info, 0, sizeof(*scaling_info));
3045 
3046 	/* Source is fixed 16.16 but we ignore mantissa for now... */
3047 	scaling_info->src_rect.x = state->src_x >> 16;
3048 	scaling_info->src_rect.y = state->src_y >> 16;
3049 
3050 	scaling_info->src_rect.width = state->src_w >> 16;
3051 	if (scaling_info->src_rect.width == 0)
3052 		return -EINVAL;
3053 
3054 	scaling_info->src_rect.height = state->src_h >> 16;
3055 	if (scaling_info->src_rect.height == 0)
3056 		return -EINVAL;
3057 
3058 	scaling_info->dst_rect.x = state->crtc_x;
3059 	scaling_info->dst_rect.y = state->crtc_y;
3060 
3061 	if (state->crtc_w == 0)
3062 		return -EINVAL;
3063 
3064 	scaling_info->dst_rect.width = state->crtc_w;
3065 
3066 	if (state->crtc_h == 0)
3067 		return -EINVAL;
3068 
3069 	scaling_info->dst_rect.height = state->crtc_h;
3070 
3071 	/* DRM doesn't specify clipping on destination output. */
3072 	scaling_info->clip_rect = scaling_info->dst_rect;
3073 
3074 	/* TODO: Validate scaling per-format with DC plane caps */
3075 	scale_w = scaling_info->dst_rect.width * 1000 /
3076 		  scaling_info->src_rect.width;
3077 
3078 	if (scale_w < 250 || scale_w > 16000)
3079 		return -EINVAL;
3080 
3081 	scale_h = scaling_info->dst_rect.height * 1000 /
3082 		  scaling_info->src_rect.height;
3083 
3084 	if (scale_h < 250 || scale_h > 16000)
3085 		return -EINVAL;
3086 
3087 	/*
3088 	 * The "scaling_quality" can be ignored for now, quality = 0 has DC
3089 	 * assume reasonable defaults based on the format.
3090 	 */
3091 
3092 	return 0;
3093 }
3094 
3095 static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
3096 		       uint64_t *tiling_flags)
3097 {
3098 	struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
3099 	int r = amdgpu_bo_reserve(rbo, false);
3100 
3101 	if (unlikely(r)) {
3102 		/* Don't show error message when returning -ERESTARTSYS */
3103 		if (r != -ERESTARTSYS)
3104 			DRM_ERROR("Unable to reserve buffer: %d\n", r);
3105 		return r;
3106 	}
3107 
3108 	if (tiling_flags)
3109 		amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
3110 
3111 	amdgpu_bo_unreserve(rbo);
3112 
3113 	return r;
3114 }
3115 
3116 static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags)
3117 {
3118 	uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B);
3119 
3120 	return offset ? (address + offset * 256) : 0;
3121 }
3122 
3123 static int
3124 fill_plane_dcc_attributes(struct amdgpu_device *adev,
3125 			  const struct amdgpu_framebuffer *afb,
3126 			  const enum surface_pixel_format format,
3127 			  const enum dc_rotation_angle rotation,
3128 			  const struct plane_size *plane_size,
3129 			  const union dc_tiling_info *tiling_info,
3130 			  const uint64_t info,
3131 			  struct dc_plane_dcc_param *dcc,
3132 			  struct dc_plane_address *address)
3133 {
3134 	struct dc *dc = adev->dm.dc;
3135 	struct dc_dcc_surface_param input;
3136 	struct dc_surface_dcc_cap output;
3137 	uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B);
3138 	uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0;
3139 	uint64_t dcc_address;
3140 
3141 	memset(&input, 0, sizeof(input));
3142 	memset(&output, 0, sizeof(output));
3143 
3144 	if (!offset)
3145 		return 0;
3146 
3147 	if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
3148 		return 0;
3149 
3150 	if (!dc->cap_funcs.get_dcc_compression_cap)
3151 		return -EINVAL;
3152 
3153 	input.format = format;
3154 	input.surface_size.width = plane_size->surface_size.width;
3155 	input.surface_size.height = plane_size->surface_size.height;
3156 	input.swizzle_mode = tiling_info->gfx9.swizzle;
3157 
3158 	if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180)
3159 		input.scan = SCAN_DIRECTION_HORIZONTAL;
3160 	else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270)
3161 		input.scan = SCAN_DIRECTION_VERTICAL;
3162 
3163 	if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output))
3164 		return -EINVAL;
3165 
3166 	if (!output.capable)
3167 		return -EINVAL;
3168 
3169 	if (i64b == 0 && output.grph.rgb.independent_64b_blks != 0)
3170 		return -EINVAL;
3171 
3172 	dcc->enable = 1;
3173 	dcc->meta_pitch =
3174 		AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1;
3175 	dcc->independent_64b_blks = i64b;
3176 
3177 	dcc_address = get_dcc_address(afb->address, info);
3178 	address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
3179 	address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
3180 
3181 	return 0;
3182 }
3183 
3184 static int
3185 fill_plane_buffer_attributes(struct amdgpu_device *adev,
3186 			     const struct amdgpu_framebuffer *afb,
3187 			     const enum surface_pixel_format format,
3188 			     const enum dc_rotation_angle rotation,
3189 			     const uint64_t tiling_flags,
3190 			     union dc_tiling_info *tiling_info,
3191 			     struct plane_size *plane_size,
3192 			     struct dc_plane_dcc_param *dcc,
3193 			     struct dc_plane_address *address)
3194 {
3195 	const struct drm_framebuffer *fb = &afb->base;
3196 	int ret;
3197 
3198 	memset(tiling_info, 0, sizeof(*tiling_info));
3199 	memset(plane_size, 0, sizeof(*plane_size));
3200 	memset(dcc, 0, sizeof(*dcc));
3201 	memset(address, 0, sizeof(*address));
3202 
3203 	if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
3204 		plane_size->surface_size.x = 0;
3205 		plane_size->surface_size.y = 0;
3206 		plane_size->surface_size.width = fb->width;
3207 		plane_size->surface_size.height = fb->height;
3208 		plane_size->surface_pitch =
3209 			fb->pitches[0] / fb->format->cpp[0];
3210 
3211 		address->type = PLN_ADDR_TYPE_GRAPHICS;
3212 		address->grph.addr.low_part = lower_32_bits(afb->address);
3213 		address->grph.addr.high_part = upper_32_bits(afb->address);
3214 	} else if (format < SURFACE_PIXEL_FORMAT_INVALID) {
3215 		uint64_t chroma_addr = afb->address + fb->offsets[1];
3216 
3217 		plane_size->surface_size.x = 0;
3218 		plane_size->surface_size.y = 0;
3219 		plane_size->surface_size.width = fb->width;
3220 		plane_size->surface_size.height = fb->height;
3221 		plane_size->surface_pitch =
3222 			fb->pitches[0] / fb->format->cpp[0];
3223 
3224 		plane_size->chroma_size.x = 0;
3225 		plane_size->chroma_size.y = 0;
3226 		/* TODO: set these based on surface format */
3227 		plane_size->chroma_size.width = fb->width / 2;
3228 		plane_size->chroma_size.height = fb->height / 2;
3229 
3230 		plane_size->chroma_pitch =
3231 			fb->pitches[1] / fb->format->cpp[1];
3232 
3233 		address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3234 		address->video_progressive.luma_addr.low_part =
3235 			lower_32_bits(afb->address);
3236 		address->video_progressive.luma_addr.high_part =
3237 			upper_32_bits(afb->address);
3238 		address->video_progressive.chroma_addr.low_part =
3239 			lower_32_bits(chroma_addr);
3240 		address->video_progressive.chroma_addr.high_part =
3241 			upper_32_bits(chroma_addr);
3242 	}
3243 
3244 	/* Fill GFX8 params */
3245 	if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
3246 		unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
3247 
3248 		bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
3249 		bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
3250 		mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
3251 		tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
3252 		num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
3253 
3254 		/* XXX fix me for VI */
3255 		tiling_info->gfx8.num_banks = num_banks;
3256 		tiling_info->gfx8.array_mode =
3257 				DC_ARRAY_2D_TILED_THIN1;
3258 		tiling_info->gfx8.tile_split = tile_split;
3259 		tiling_info->gfx8.bank_width = bankw;
3260 		tiling_info->gfx8.bank_height = bankh;
3261 		tiling_info->gfx8.tile_aspect = mtaspect;
3262 		tiling_info->gfx8.tile_mode =
3263 				DC_ADDR_SURF_MICRO_TILING_DISPLAY;
3264 	} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
3265 			== DC_ARRAY_1D_TILED_THIN1) {
3266 		tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
3267 	}
3268 
3269 	tiling_info->gfx8.pipe_config =
3270 			AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
3271 
3272 	if (adev->asic_type == CHIP_VEGA10 ||
3273 	    adev->asic_type == CHIP_VEGA12 ||
3274 	    adev->asic_type == CHIP_VEGA20 ||
3275 	    adev->asic_type == CHIP_NAVI10 ||
3276 	    adev->asic_type == CHIP_NAVI14 ||
3277 	    adev->asic_type == CHIP_NAVI12 ||
3278 	    adev->asic_type == CHIP_RENOIR ||
3279 	    adev->asic_type == CHIP_RAVEN) {
3280 		/* Fill GFX9 params */
3281 		tiling_info->gfx9.num_pipes =
3282 			adev->gfx.config.gb_addr_config_fields.num_pipes;
3283 		tiling_info->gfx9.num_banks =
3284 			adev->gfx.config.gb_addr_config_fields.num_banks;
3285 		tiling_info->gfx9.pipe_interleave =
3286 			adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
3287 		tiling_info->gfx9.num_shader_engines =
3288 			adev->gfx.config.gb_addr_config_fields.num_se;
3289 		tiling_info->gfx9.max_compressed_frags =
3290 			adev->gfx.config.gb_addr_config_fields.max_compress_frags;
3291 		tiling_info->gfx9.num_rb_per_se =
3292 			adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
3293 		tiling_info->gfx9.swizzle =
3294 			AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
3295 		tiling_info->gfx9.shaderEnable = 1;
3296 
3297 		ret = fill_plane_dcc_attributes(adev, afb, format, rotation,
3298 						plane_size, tiling_info,
3299 						tiling_flags, dcc, address);
3300 		if (ret)
3301 			return ret;
3302 	}
3303 
3304 	return 0;
3305 }
3306 
3307 static void
3308 fill_blending_from_plane_state(const struct drm_plane_state *plane_state,
3309 			       bool *per_pixel_alpha, bool *global_alpha,
3310 			       int *global_alpha_value)
3311 {
3312 	*per_pixel_alpha = false;
3313 	*global_alpha = false;
3314 	*global_alpha_value = 0xff;
3315 
3316 	if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY)
3317 		return;
3318 
3319 	if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
3320 		static const uint32_t alpha_formats[] = {
3321 			DRM_FORMAT_ARGB8888,
3322 			DRM_FORMAT_RGBA8888,
3323 			DRM_FORMAT_ABGR8888,
3324 		};
3325 		uint32_t format = plane_state->fb->format->format;
3326 		unsigned int i;
3327 
3328 		for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) {
3329 			if (format == alpha_formats[i]) {
3330 				*per_pixel_alpha = true;
3331 				break;
3332 			}
3333 		}
3334 	}
3335 
3336 	if (plane_state->alpha < 0xffff) {
3337 		*global_alpha = true;
3338 		*global_alpha_value = plane_state->alpha >> 8;
3339 	}
3340 }
3341 
3342 static int
3343 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
3344 			    const enum surface_pixel_format format,
3345 			    enum dc_color_space *color_space)
3346 {
3347 	bool full_range;
3348 
3349 	*color_space = COLOR_SPACE_SRGB;
3350 
3351 	/* DRM color properties only affect non-RGB formats. */
3352 	if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
3353 		return 0;
3354 
3355 	full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
3356 
3357 	switch (plane_state->color_encoding) {
3358 	case DRM_COLOR_YCBCR_BT601:
3359 		if (full_range)
3360 			*color_space = COLOR_SPACE_YCBCR601;
3361 		else
3362 			*color_space = COLOR_SPACE_YCBCR601_LIMITED;
3363 		break;
3364 
3365 	case DRM_COLOR_YCBCR_BT709:
3366 		if (full_range)
3367 			*color_space = COLOR_SPACE_YCBCR709;
3368 		else
3369 			*color_space = COLOR_SPACE_YCBCR709_LIMITED;
3370 		break;
3371 
3372 	case DRM_COLOR_YCBCR_BT2020:
3373 		if (full_range)
3374 			*color_space = COLOR_SPACE_2020_YCBCR;
3375 		else
3376 			return -EINVAL;
3377 		break;
3378 
3379 	default:
3380 		return -EINVAL;
3381 	}
3382 
3383 	return 0;
3384 }
3385 
3386 static int
3387 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
3388 			    const struct drm_plane_state *plane_state,
3389 			    const uint64_t tiling_flags,
3390 			    struct dc_plane_info *plane_info,
3391 			    struct dc_plane_address *address)
3392 {
3393 	const struct drm_framebuffer *fb = plane_state->fb;
3394 	const struct amdgpu_framebuffer *afb =
3395 		to_amdgpu_framebuffer(plane_state->fb);
3396 	struct drm_format_name_buf format_name;
3397 	int ret;
3398 
3399 	memset(plane_info, 0, sizeof(*plane_info));
3400 
3401 	switch (fb->format->format) {
3402 	case DRM_FORMAT_C8:
3403 		plane_info->format =
3404 			SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
3405 		break;
3406 	case DRM_FORMAT_RGB565:
3407 		plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
3408 		break;
3409 	case DRM_FORMAT_XRGB8888:
3410 	case DRM_FORMAT_ARGB8888:
3411 		plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
3412 		break;
3413 	case DRM_FORMAT_XRGB2101010:
3414 	case DRM_FORMAT_ARGB2101010:
3415 		plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
3416 		break;
3417 	case DRM_FORMAT_XBGR2101010:
3418 	case DRM_FORMAT_ABGR2101010:
3419 		plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
3420 		break;
3421 	case DRM_FORMAT_XBGR8888:
3422 	case DRM_FORMAT_ABGR8888:
3423 		plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
3424 		break;
3425 	case DRM_FORMAT_NV21:
3426 		plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
3427 		break;
3428 	case DRM_FORMAT_NV12:
3429 		plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
3430 		break;
3431 	default:
3432 		DRM_ERROR(
3433 			"Unsupported screen format %s\n",
3434 			drm_get_format_name(fb->format->format, &format_name));
3435 		return -EINVAL;
3436 	}
3437 
3438 	switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
3439 	case DRM_MODE_ROTATE_0:
3440 		plane_info->rotation = ROTATION_ANGLE_0;
3441 		break;
3442 	case DRM_MODE_ROTATE_90:
3443 		plane_info->rotation = ROTATION_ANGLE_90;
3444 		break;
3445 	case DRM_MODE_ROTATE_180:
3446 		plane_info->rotation = ROTATION_ANGLE_180;
3447 		break;
3448 	case DRM_MODE_ROTATE_270:
3449 		plane_info->rotation = ROTATION_ANGLE_270;
3450 		break;
3451 	default:
3452 		plane_info->rotation = ROTATION_ANGLE_0;
3453 		break;
3454 	}
3455 
3456 	plane_info->visible = true;
3457 	plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
3458 
3459 	plane_info->layer_index = 0;
3460 
3461 	ret = fill_plane_color_attributes(plane_state, plane_info->format,
3462 					  &plane_info->color_space);
3463 	if (ret)
3464 		return ret;
3465 
3466 	ret = fill_plane_buffer_attributes(adev, afb, plane_info->format,
3467 					   plane_info->rotation, tiling_flags,
3468 					   &plane_info->tiling_info,
3469 					   &plane_info->plane_size,
3470 					   &plane_info->dcc, address);
3471 	if (ret)
3472 		return ret;
3473 
3474 	fill_blending_from_plane_state(
3475 		plane_state, &plane_info->per_pixel_alpha,
3476 		&plane_info->global_alpha, &plane_info->global_alpha_value);
3477 
3478 	return 0;
3479 }
3480 
3481 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
3482 				    struct dc_plane_state *dc_plane_state,
3483 				    struct drm_plane_state *plane_state,
3484 				    struct drm_crtc_state *crtc_state)
3485 {
3486 	struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
3487 	const struct amdgpu_framebuffer *amdgpu_fb =
3488 		to_amdgpu_framebuffer(plane_state->fb);
3489 	struct dc_scaling_info scaling_info;
3490 	struct dc_plane_info plane_info;
3491 	uint64_t tiling_flags;
3492 	int ret;
3493 
3494 	ret = fill_dc_scaling_info(plane_state, &scaling_info);
3495 	if (ret)
3496 		return ret;
3497 
3498 	dc_plane_state->src_rect = scaling_info.src_rect;
3499 	dc_plane_state->dst_rect = scaling_info.dst_rect;
3500 	dc_plane_state->clip_rect = scaling_info.clip_rect;
3501 	dc_plane_state->scaling_quality = scaling_info.scaling_quality;
3502 
3503 	ret = get_fb_info(amdgpu_fb, &tiling_flags);
3504 	if (ret)
3505 		return ret;
3506 
3507 	ret = fill_dc_plane_info_and_addr(adev, plane_state, tiling_flags,
3508 					  &plane_info,
3509 					  &dc_plane_state->address);
3510 	if (ret)
3511 		return ret;
3512 
3513 	dc_plane_state->format = plane_info.format;
3514 	dc_plane_state->color_space = plane_info.color_space;
3515 	dc_plane_state->format = plane_info.format;
3516 	dc_plane_state->plane_size = plane_info.plane_size;
3517 	dc_plane_state->rotation = plane_info.rotation;
3518 	dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
3519 	dc_plane_state->stereo_format = plane_info.stereo_format;
3520 	dc_plane_state->tiling_info = plane_info.tiling_info;
3521 	dc_plane_state->visible = plane_info.visible;
3522 	dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
3523 	dc_plane_state->global_alpha = plane_info.global_alpha;
3524 	dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
3525 	dc_plane_state->dcc = plane_info.dcc;
3526 	dc_plane_state->layer_index = plane_info.layer_index; // Always returns 0
3527 
3528 	/*
3529 	 * Always set input transfer function, since plane state is refreshed
3530 	 * every time.
3531 	 */
3532 	ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
3533 	if (ret)
3534 		return ret;
3535 
3536 	return 0;
3537 }
3538 
3539 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
3540 					   const struct dm_connector_state *dm_state,
3541 					   struct dc_stream_state *stream)
3542 {
3543 	enum amdgpu_rmx_type rmx_type;
3544 
3545 	struct rect src = { 0 }; /* viewport in composition space*/
3546 	struct rect dst = { 0 }; /* stream addressable area */
3547 
3548 	/* no mode. nothing to be done */
3549 	if (!mode)
3550 		return;
3551 
3552 	/* Full screen scaling by default */
3553 	src.width = mode->hdisplay;
3554 	src.height = mode->vdisplay;
3555 	dst.width = stream->timing.h_addressable;
3556 	dst.height = stream->timing.v_addressable;
3557 
3558 	if (dm_state) {
3559 		rmx_type = dm_state->scaling;
3560 		if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
3561 			if (src.width * dst.height <
3562 					src.height * dst.width) {
3563 				/* height needs less upscaling/more downscaling */
3564 				dst.width = src.width *
3565 						dst.height / src.height;
3566 			} else {
3567 				/* width needs less upscaling/more downscaling */
3568 				dst.height = src.height *
3569 						dst.width / src.width;
3570 			}
3571 		} else if (rmx_type == RMX_CENTER) {
3572 			dst = src;
3573 		}
3574 
3575 		dst.x = (stream->timing.h_addressable - dst.width) / 2;
3576 		dst.y = (stream->timing.v_addressable - dst.height) / 2;
3577 
3578 		if (dm_state->underscan_enable) {
3579 			dst.x += dm_state->underscan_hborder / 2;
3580 			dst.y += dm_state->underscan_vborder / 2;
3581 			dst.width -= dm_state->underscan_hborder;
3582 			dst.height -= dm_state->underscan_vborder;
3583 		}
3584 	}
3585 
3586 	stream->src = src;
3587 	stream->dst = dst;
3588 
3589 	DRM_DEBUG_DRIVER("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
3590 			dst.x, dst.y, dst.width, dst.height);
3591 
3592 }
3593 
3594 static enum dc_color_depth
3595 convert_color_depth_from_display_info(const struct drm_connector *connector,
3596 				      const struct drm_connector_state *state,
3597 				      bool is_y420)
3598 {
3599 	uint8_t bpc;
3600 
3601 	if (is_y420) {
3602 		bpc = 8;
3603 
3604 		/* Cap display bpc based on HDMI 2.0 HF-VSDB */
3605 		if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
3606 			bpc = 16;
3607 		else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
3608 			bpc = 12;
3609 		else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
3610 			bpc = 10;
3611 	} else {
3612 		bpc = (uint8_t)connector->display_info.bpc;
3613 		/* Assume 8 bpc by default if no bpc is specified. */
3614 		bpc = bpc ? bpc : 8;
3615 	}
3616 
3617 	if (!state)
3618 		state = connector->state;
3619 
3620 	if (state) {
3621 		/*
3622 		 * Cap display bpc based on the user requested value.
3623 		 *
3624 		 * The value for state->max_bpc may not correctly updated
3625 		 * depending on when the connector gets added to the state
3626 		 * or if this was called outside of atomic check, so it
3627 		 * can't be used directly.
3628 		 */
3629 		bpc = min(bpc, state->max_requested_bpc);
3630 
3631 		/* Round down to the nearest even number. */
3632 		bpc = bpc - (bpc & 1);
3633 	}
3634 
3635 	switch (bpc) {
3636 	case 0:
3637 		/*
3638 		 * Temporary Work around, DRM doesn't parse color depth for
3639 		 * EDID revision before 1.4
3640 		 * TODO: Fix edid parsing
3641 		 */
3642 		return COLOR_DEPTH_888;
3643 	case 6:
3644 		return COLOR_DEPTH_666;
3645 	case 8:
3646 		return COLOR_DEPTH_888;
3647 	case 10:
3648 		return COLOR_DEPTH_101010;
3649 	case 12:
3650 		return COLOR_DEPTH_121212;
3651 	case 14:
3652 		return COLOR_DEPTH_141414;
3653 	case 16:
3654 		return COLOR_DEPTH_161616;
3655 	default:
3656 		return COLOR_DEPTH_UNDEFINED;
3657 	}
3658 }
3659 
3660 static enum dc_aspect_ratio
3661 get_aspect_ratio(const struct drm_display_mode *mode_in)
3662 {
3663 	/* 1-1 mapping, since both enums follow the HDMI spec. */
3664 	return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
3665 }
3666 
3667 static enum dc_color_space
3668 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
3669 {
3670 	enum dc_color_space color_space = COLOR_SPACE_SRGB;
3671 
3672 	switch (dc_crtc_timing->pixel_encoding)	{
3673 	case PIXEL_ENCODING_YCBCR422:
3674 	case PIXEL_ENCODING_YCBCR444:
3675 	case PIXEL_ENCODING_YCBCR420:
3676 	{
3677 		/*
3678 		 * 27030khz is the separation point between HDTV and SDTV
3679 		 * according to HDMI spec, we use YCbCr709 and YCbCr601
3680 		 * respectively
3681 		 */
3682 		if (dc_crtc_timing->pix_clk_100hz > 270300) {
3683 			if (dc_crtc_timing->flags.Y_ONLY)
3684 				color_space =
3685 					COLOR_SPACE_YCBCR709_LIMITED;
3686 			else
3687 				color_space = COLOR_SPACE_YCBCR709;
3688 		} else {
3689 			if (dc_crtc_timing->flags.Y_ONLY)
3690 				color_space =
3691 					COLOR_SPACE_YCBCR601_LIMITED;
3692 			else
3693 				color_space = COLOR_SPACE_YCBCR601;
3694 		}
3695 
3696 	}
3697 	break;
3698 	case PIXEL_ENCODING_RGB:
3699 		color_space = COLOR_SPACE_SRGB;
3700 		break;
3701 
3702 	default:
3703 		WARN_ON(1);
3704 		break;
3705 	}
3706 
3707 	return color_space;
3708 }
3709 
3710 static bool adjust_colour_depth_from_display_info(
3711 	struct dc_crtc_timing *timing_out,
3712 	const struct drm_display_info *info)
3713 {
3714 	enum dc_color_depth depth = timing_out->display_color_depth;
3715 	int normalized_clk;
3716 	do {
3717 		normalized_clk = timing_out->pix_clk_100hz / 10;
3718 		/* YCbCr 4:2:0 requires additional adjustment of 1/2 */
3719 		if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
3720 			normalized_clk /= 2;
3721 		/* Adjusting pix clock following on HDMI spec based on colour depth */
3722 		switch (depth) {
3723 		case COLOR_DEPTH_888:
3724 			break;
3725 		case COLOR_DEPTH_101010:
3726 			normalized_clk = (normalized_clk * 30) / 24;
3727 			break;
3728 		case COLOR_DEPTH_121212:
3729 			normalized_clk = (normalized_clk * 36) / 24;
3730 			break;
3731 		case COLOR_DEPTH_161616:
3732 			normalized_clk = (normalized_clk * 48) / 24;
3733 			break;
3734 		default:
3735 			/* The above depths are the only ones valid for HDMI. */
3736 			return false;
3737 		}
3738 		if (normalized_clk <= info->max_tmds_clock) {
3739 			timing_out->display_color_depth = depth;
3740 			return true;
3741 		}
3742 	} while (--depth > COLOR_DEPTH_666);
3743 	return false;
3744 }
3745 
3746 static void fill_stream_properties_from_drm_display_mode(
3747 	struct dc_stream_state *stream,
3748 	const struct drm_display_mode *mode_in,
3749 	const struct drm_connector *connector,
3750 	const struct drm_connector_state *connector_state,
3751 	const struct dc_stream_state *old_stream)
3752 {
3753 	struct dc_crtc_timing *timing_out = &stream->timing;
3754 	const struct drm_display_info *info = &connector->display_info;
3755 	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
3756 	struct hdmi_vendor_infoframe hv_frame;
3757 	struct hdmi_avi_infoframe avi_frame;
3758 
3759 	memset(&hv_frame, 0, sizeof(hv_frame));
3760 	memset(&avi_frame, 0, sizeof(avi_frame));
3761 
3762 	timing_out->h_border_left = 0;
3763 	timing_out->h_border_right = 0;
3764 	timing_out->v_border_top = 0;
3765 	timing_out->v_border_bottom = 0;
3766 	/* TODO: un-hardcode */
3767 	if (drm_mode_is_420_only(info, mode_in)
3768 			&& stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
3769 		timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
3770 	else if (drm_mode_is_420_also(info, mode_in)
3771 			&& aconnector->force_yuv420_output)
3772 		timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
3773 	else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
3774 			&& stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
3775 		timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
3776 	else
3777 		timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
3778 
3779 	timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
3780 	timing_out->display_color_depth = convert_color_depth_from_display_info(
3781 		connector, connector_state,
3782 		(timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420));
3783 	timing_out->scan_type = SCANNING_TYPE_NODATA;
3784 	timing_out->hdmi_vic = 0;
3785 
3786 	if(old_stream) {
3787 		timing_out->vic = old_stream->timing.vic;
3788 		timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
3789 		timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
3790 	} else {
3791 		timing_out->vic = drm_match_cea_mode(mode_in);
3792 		if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
3793 			timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
3794 		if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
3795 			timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
3796 	}
3797 
3798 	if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
3799 		drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
3800 		timing_out->vic = avi_frame.video_code;
3801 		drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
3802 		timing_out->hdmi_vic = hv_frame.vic;
3803 	}
3804 
3805 	timing_out->h_addressable = mode_in->crtc_hdisplay;
3806 	timing_out->h_total = mode_in->crtc_htotal;
3807 	timing_out->h_sync_width =
3808 		mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
3809 	timing_out->h_front_porch =
3810 		mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
3811 	timing_out->v_total = mode_in->crtc_vtotal;
3812 	timing_out->v_addressable = mode_in->crtc_vdisplay;
3813 	timing_out->v_front_porch =
3814 		mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
3815 	timing_out->v_sync_width =
3816 		mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
3817 	timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
3818 	timing_out->aspect_ratio = get_aspect_ratio(mode_in);
3819 
3820 	stream->output_color_space = get_output_color_space(timing_out);
3821 
3822 	stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
3823 	stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
3824 	if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
3825 		if (!adjust_colour_depth_from_display_info(timing_out, info) &&
3826 		    drm_mode_is_420_also(info, mode_in) &&
3827 		    timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
3828 			timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
3829 			adjust_colour_depth_from_display_info(timing_out, info);
3830 		}
3831 	}
3832 }
3833 
3834 static void fill_audio_info(struct audio_info *audio_info,
3835 			    const struct drm_connector *drm_connector,
3836 			    const struct dc_sink *dc_sink)
3837 {
3838 	int i = 0;
3839 	int cea_revision = 0;
3840 	const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
3841 
3842 	audio_info->manufacture_id = edid_caps->manufacturer_id;
3843 	audio_info->product_id = edid_caps->product_id;
3844 
3845 	cea_revision = drm_connector->display_info.cea_rev;
3846 
3847 	strscpy(audio_info->display_name,
3848 		edid_caps->display_name,
3849 		AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
3850 
3851 	if (cea_revision >= 3) {
3852 		audio_info->mode_count = edid_caps->audio_mode_count;
3853 
3854 		for (i = 0; i < audio_info->mode_count; ++i) {
3855 			audio_info->modes[i].format_code =
3856 					(enum audio_format_code)
3857 					(edid_caps->audio_modes[i].format_code);
3858 			audio_info->modes[i].channel_count =
3859 					edid_caps->audio_modes[i].channel_count;
3860 			audio_info->modes[i].sample_rates.all =
3861 					edid_caps->audio_modes[i].sample_rate;
3862 			audio_info->modes[i].sample_size =
3863 					edid_caps->audio_modes[i].sample_size;
3864 		}
3865 	}
3866 
3867 	audio_info->flags.all = edid_caps->speaker_flags;
3868 
3869 	/* TODO: We only check for the progressive mode, check for interlace mode too */
3870 	if (drm_connector->latency_present[0]) {
3871 		audio_info->video_latency = drm_connector->video_latency[0];
3872 		audio_info->audio_latency = drm_connector->audio_latency[0];
3873 	}
3874 
3875 	/* TODO: For DP, video and audio latency should be calculated from DPCD caps */
3876 
3877 }
3878 
3879 static void
3880 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
3881 				      struct drm_display_mode *dst_mode)
3882 {
3883 	dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
3884 	dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
3885 	dst_mode->crtc_clock = src_mode->crtc_clock;
3886 	dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
3887 	dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
3888 	dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
3889 	dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
3890 	dst_mode->crtc_htotal = src_mode->crtc_htotal;
3891 	dst_mode->crtc_hskew = src_mode->crtc_hskew;
3892 	dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
3893 	dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
3894 	dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
3895 	dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
3896 	dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
3897 }
3898 
3899 static void
3900 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
3901 					const struct drm_display_mode *native_mode,
3902 					bool scale_enabled)
3903 {
3904 	if (scale_enabled) {
3905 		copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
3906 	} else if (native_mode->clock == drm_mode->clock &&
3907 			native_mode->htotal == drm_mode->htotal &&
3908 			native_mode->vtotal == drm_mode->vtotal) {
3909 		copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
3910 	} else {
3911 		/* no scaling nor amdgpu inserted, no need to patch */
3912 	}
3913 }
3914 
3915 static struct dc_sink *
3916 create_fake_sink(struct amdgpu_dm_connector *aconnector)
3917 {
3918 	struct dc_sink_init_data sink_init_data = { 0 };
3919 	struct dc_sink *sink = NULL;
3920 	sink_init_data.link = aconnector->dc_link;
3921 	sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
3922 
3923 	sink = dc_sink_create(&sink_init_data);
3924 	if (!sink) {
3925 		DRM_ERROR("Failed to create sink!\n");
3926 		return NULL;
3927 	}
3928 	sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
3929 
3930 	return sink;
3931 }
3932 
3933 static void set_multisync_trigger_params(
3934 		struct dc_stream_state *stream)
3935 {
3936 	if (stream->triggered_crtc_reset.enabled) {
3937 		stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
3938 		stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
3939 	}
3940 }
3941 
3942 static void set_master_stream(struct dc_stream_state *stream_set[],
3943 			      int stream_count)
3944 {
3945 	int j, highest_rfr = 0, master_stream = 0;
3946 
3947 	for (j = 0;  j < stream_count; j++) {
3948 		if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
3949 			int refresh_rate = 0;
3950 
3951 			refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
3952 				(stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
3953 			if (refresh_rate > highest_rfr) {
3954 				highest_rfr = refresh_rate;
3955 				master_stream = j;
3956 			}
3957 		}
3958 	}
3959 	for (j = 0;  j < stream_count; j++) {
3960 		if (stream_set[j])
3961 			stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
3962 	}
3963 }
3964 
3965 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
3966 {
3967 	int i = 0;
3968 
3969 	if (context->stream_count < 2)
3970 		return;
3971 	for (i = 0; i < context->stream_count ; i++) {
3972 		if (!context->streams[i])
3973 			continue;
3974 		/*
3975 		 * TODO: add a function to read AMD VSDB bits and set
3976 		 * crtc_sync_master.multi_sync_enabled flag
3977 		 * For now it's set to false
3978 		 */
3979 		set_multisync_trigger_params(context->streams[i]);
3980 	}
3981 	set_master_stream(context->streams, context->stream_count);
3982 }
3983 
3984 static struct dc_stream_state *
3985 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
3986 		       const struct drm_display_mode *drm_mode,
3987 		       const struct dm_connector_state *dm_state,
3988 		       const struct dc_stream_state *old_stream)
3989 {
3990 	struct drm_display_mode *preferred_mode = NULL;
3991 	struct drm_connector *drm_connector;
3992 	const struct drm_connector_state *con_state =
3993 		dm_state ? &dm_state->base : NULL;
3994 	struct dc_stream_state *stream = NULL;
3995 	struct drm_display_mode mode = *drm_mode;
3996 	bool native_mode_found = false;
3997 	bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
3998 	int mode_refresh;
3999 	int preferred_refresh = 0;
4000 #if defined(CONFIG_DRM_AMD_DC_DCN)
4001 	struct dsc_dec_dpcd_caps dsc_caps;
4002 #endif
4003 	uint32_t link_bandwidth_kbps;
4004 
4005 	struct dc_sink *sink = NULL;
4006 	if (aconnector == NULL) {
4007 		DRM_ERROR("aconnector is NULL!\n");
4008 		return stream;
4009 	}
4010 
4011 	drm_connector = &aconnector->base;
4012 
4013 	if (!aconnector->dc_sink) {
4014 		sink = create_fake_sink(aconnector);
4015 		if (!sink)
4016 			return stream;
4017 	} else {
4018 		sink = aconnector->dc_sink;
4019 		dc_sink_retain(sink);
4020 	}
4021 
4022 	stream = dc_create_stream_for_sink(sink);
4023 
4024 	if (stream == NULL) {
4025 		DRM_ERROR("Failed to create stream for sink!\n");
4026 		goto finish;
4027 	}
4028 
4029 	stream->dm_stream_context = aconnector;
4030 
4031 	stream->timing.flags.LTE_340MCSC_SCRAMBLE =
4032 		drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
4033 
4034 	list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
4035 		/* Search for preferred mode */
4036 		if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
4037 			native_mode_found = true;
4038 			break;
4039 		}
4040 	}
4041 	if (!native_mode_found)
4042 		preferred_mode = list_first_entry_or_null(
4043 				&aconnector->base.modes,
4044 				struct drm_display_mode,
4045 				head);
4046 
4047 	mode_refresh = drm_mode_vrefresh(&mode);
4048 
4049 	if (preferred_mode == NULL) {
4050 		/*
4051 		 * This may not be an error, the use case is when we have no
4052 		 * usermode calls to reset and set mode upon hotplug. In this
4053 		 * case, we call set mode ourselves to restore the previous mode
4054 		 * and the modelist may not be filled in in time.
4055 		 */
4056 		DRM_DEBUG_DRIVER("No preferred mode found\n");
4057 	} else {
4058 		decide_crtc_timing_for_drm_display_mode(
4059 				&mode, preferred_mode,
4060 				dm_state ? (dm_state->scaling != RMX_OFF) : false);
4061 		preferred_refresh = drm_mode_vrefresh(preferred_mode);
4062 	}
4063 
4064 	if (!dm_state)
4065 		drm_mode_set_crtcinfo(&mode, 0);
4066 
4067 	/*
4068 	* If scaling is enabled and refresh rate didn't change
4069 	* we copy the vic and polarities of the old timings
4070 	*/
4071 	if (!scale || mode_refresh != preferred_refresh)
4072 		fill_stream_properties_from_drm_display_mode(stream,
4073 			&mode, &aconnector->base, con_state, NULL);
4074 	else
4075 		fill_stream_properties_from_drm_display_mode(stream,
4076 			&mode, &aconnector->base, con_state, old_stream);
4077 
4078 	stream->timing.flags.DSC = 0;
4079 
4080 	if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
4081 #if defined(CONFIG_DRM_AMD_DC_DCN)
4082 		dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
4083 				      aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
4084 				      aconnector->dc_link->dpcd_caps.dsc_caps.dsc_ext_caps.raw,
4085 				      &dsc_caps);
4086 #endif
4087 		link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
4088 							     dc_link_get_link_cap(aconnector->dc_link));
4089 
4090 #if defined(CONFIG_DRM_AMD_DC_DCN)
4091 		if (dsc_caps.is_dsc_supported)
4092 			if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
4093 						  &dsc_caps,
4094 						  aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
4095 						  link_bandwidth_kbps,
4096 						  &stream->timing,
4097 						  &stream->timing.dsc_cfg))
4098 				stream->timing.flags.DSC = 1;
4099 #endif
4100 	}
4101 
4102 	update_stream_scaling_settings(&mode, dm_state, stream);
4103 
4104 	fill_audio_info(
4105 		&stream->audio_info,
4106 		drm_connector,
4107 		sink);
4108 
4109 	update_stream_signal(stream, sink);
4110 
4111 	if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
4112 		mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket, false, false);
4113 	if (stream->link->psr_feature_enabled)	{
4114 		struct dc  *core_dc = stream->link->ctx->dc;
4115 
4116 		if (dc_is_dmcu_initialized(core_dc)) {
4117 			struct dmcu *dmcu = core_dc->res_pool->dmcu;
4118 
4119 			stream->psr_version = dmcu->dmcu_version.psr_version;
4120 			mod_build_vsc_infopacket(stream,
4121 					&stream->vsc_infopacket,
4122 					&stream->use_vsc_sdp_for_colorimetry);
4123 		}
4124 	}
4125 finish:
4126 	dc_sink_release(sink);
4127 
4128 	return stream;
4129 }
4130 
4131 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
4132 {
4133 	drm_crtc_cleanup(crtc);
4134 	kfree(crtc);
4135 }
4136 
4137 static void dm_crtc_destroy_state(struct drm_crtc *crtc,
4138 				  struct drm_crtc_state *state)
4139 {
4140 	struct dm_crtc_state *cur = to_dm_crtc_state(state);
4141 
4142 	/* TODO Destroy dc_stream objects are stream object is flattened */
4143 	if (cur->stream)
4144 		dc_stream_release(cur->stream);
4145 
4146 
4147 	__drm_atomic_helper_crtc_destroy_state(state);
4148 
4149 
4150 	kfree(state);
4151 }
4152 
4153 static void dm_crtc_reset_state(struct drm_crtc *crtc)
4154 {
4155 	struct dm_crtc_state *state;
4156 
4157 	if (crtc->state)
4158 		dm_crtc_destroy_state(crtc, crtc->state);
4159 
4160 	state = kzalloc(sizeof(*state), GFP_KERNEL);
4161 	if (WARN_ON(!state))
4162 		return;
4163 
4164 	crtc->state = &state->base;
4165 	crtc->state->crtc = crtc;
4166 
4167 }
4168 
4169 static struct drm_crtc_state *
4170 dm_crtc_duplicate_state(struct drm_crtc *crtc)
4171 {
4172 	struct dm_crtc_state *state, *cur;
4173 
4174 	cur = to_dm_crtc_state(crtc->state);
4175 
4176 	if (WARN_ON(!crtc->state))
4177 		return NULL;
4178 
4179 	state = kzalloc(sizeof(*state), GFP_KERNEL);
4180 	if (!state)
4181 		return NULL;
4182 
4183 	__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
4184 
4185 	if (cur->stream) {
4186 		state->stream = cur->stream;
4187 		dc_stream_retain(state->stream);
4188 	}
4189 
4190 	state->active_planes = cur->active_planes;
4191 	state->interrupts_enabled = cur->interrupts_enabled;
4192 	state->vrr_params = cur->vrr_params;
4193 	state->vrr_infopacket = cur->vrr_infopacket;
4194 	state->abm_level = cur->abm_level;
4195 	state->vrr_supported = cur->vrr_supported;
4196 	state->freesync_config = cur->freesync_config;
4197 	state->crc_src = cur->crc_src;
4198 	state->cm_has_degamma = cur->cm_has_degamma;
4199 	state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
4200 
4201 	/* TODO Duplicate dc_stream after objects are stream object is flattened */
4202 
4203 	return &state->base;
4204 }
4205 
4206 static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
4207 {
4208 	enum dc_irq_source irq_source;
4209 	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4210 	struct amdgpu_device *adev = crtc->dev->dev_private;
4211 	int rc;
4212 
4213 	/* Do not set vupdate for DCN hardware */
4214 	if (adev->family > AMDGPU_FAMILY_AI)
4215 		return 0;
4216 
4217 	irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
4218 
4219 	rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
4220 
4221 	DRM_DEBUG_DRIVER("crtc %d - vupdate irq %sabling: r=%d\n",
4222 			 acrtc->crtc_id, enable ? "en" : "dis", rc);
4223 	return rc;
4224 }
4225 
4226 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
4227 {
4228 	enum dc_irq_source irq_source;
4229 	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4230 	struct amdgpu_device *adev = crtc->dev->dev_private;
4231 	struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
4232 	int rc = 0;
4233 
4234 	if (enable) {
4235 		/* vblank irq on -> Only need vupdate irq in vrr mode */
4236 		if (amdgpu_dm_vrr_active(acrtc_state))
4237 			rc = dm_set_vupdate_irq(crtc, true);
4238 	} else {
4239 		/* vblank irq off -> vupdate irq off */
4240 		rc = dm_set_vupdate_irq(crtc, false);
4241 	}
4242 
4243 	if (rc)
4244 		return rc;
4245 
4246 	irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
4247 	return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
4248 }
4249 
4250 static int dm_enable_vblank(struct drm_crtc *crtc)
4251 {
4252 	return dm_set_vblank(crtc, true);
4253 }
4254 
4255 static void dm_disable_vblank(struct drm_crtc *crtc)
4256 {
4257 	dm_set_vblank(crtc, false);
4258 }
4259 
4260 /* Implemented only the options currently availible for the driver */
4261 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
4262 	.reset = dm_crtc_reset_state,
4263 	.destroy = amdgpu_dm_crtc_destroy,
4264 	.gamma_set = drm_atomic_helper_legacy_gamma_set,
4265 	.set_config = drm_atomic_helper_set_config,
4266 	.page_flip = drm_atomic_helper_page_flip,
4267 	.atomic_duplicate_state = dm_crtc_duplicate_state,
4268 	.atomic_destroy_state = dm_crtc_destroy_state,
4269 	.set_crc_source = amdgpu_dm_crtc_set_crc_source,
4270 	.verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
4271 	.get_crc_sources = amdgpu_dm_crtc_get_crc_sources,
4272 	.enable_vblank = dm_enable_vblank,
4273 	.disable_vblank = dm_disable_vblank,
4274 };
4275 
4276 static enum drm_connector_status
4277 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
4278 {
4279 	bool connected;
4280 	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
4281 
4282 	/*
4283 	 * Notes:
4284 	 * 1. This interface is NOT called in context of HPD irq.
4285 	 * 2. This interface *is called* in context of user-mode ioctl. Which
4286 	 * makes it a bad place for *any* MST-related activity.
4287 	 */
4288 
4289 	if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
4290 	    !aconnector->fake_enable)
4291 		connected = (aconnector->dc_sink != NULL);
4292 	else
4293 		connected = (aconnector->base.force == DRM_FORCE_ON);
4294 
4295 	return (connected ? connector_status_connected :
4296 			connector_status_disconnected);
4297 }
4298 
4299 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
4300 					    struct drm_connector_state *connector_state,
4301 					    struct drm_property *property,
4302 					    uint64_t val)
4303 {
4304 	struct drm_device *dev = connector->dev;
4305 	struct amdgpu_device *adev = dev->dev_private;
4306 	struct dm_connector_state *dm_old_state =
4307 		to_dm_connector_state(connector->state);
4308 	struct dm_connector_state *dm_new_state =
4309 		to_dm_connector_state(connector_state);
4310 
4311 	int ret = -EINVAL;
4312 
4313 	if (property == dev->mode_config.scaling_mode_property) {
4314 		enum amdgpu_rmx_type rmx_type;
4315 
4316 		switch (val) {
4317 		case DRM_MODE_SCALE_CENTER:
4318 			rmx_type = RMX_CENTER;
4319 			break;
4320 		case DRM_MODE_SCALE_ASPECT:
4321 			rmx_type = RMX_ASPECT;
4322 			break;
4323 		case DRM_MODE_SCALE_FULLSCREEN:
4324 			rmx_type = RMX_FULL;
4325 			break;
4326 		case DRM_MODE_SCALE_NONE:
4327 		default:
4328 			rmx_type = RMX_OFF;
4329 			break;
4330 		}
4331 
4332 		if (dm_old_state->scaling == rmx_type)
4333 			return 0;
4334 
4335 		dm_new_state->scaling = rmx_type;
4336 		ret = 0;
4337 	} else if (property == adev->mode_info.underscan_hborder_property) {
4338 		dm_new_state->underscan_hborder = val;
4339 		ret = 0;
4340 	} else if (property == adev->mode_info.underscan_vborder_property) {
4341 		dm_new_state->underscan_vborder = val;
4342 		ret = 0;
4343 	} else if (property == adev->mode_info.underscan_property) {
4344 		dm_new_state->underscan_enable = val;
4345 		ret = 0;
4346 	} else if (property == adev->mode_info.abm_level_property) {
4347 		dm_new_state->abm_level = val;
4348 		ret = 0;
4349 	}
4350 
4351 	return ret;
4352 }
4353 
4354 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
4355 					    const struct drm_connector_state *state,
4356 					    struct drm_property *property,
4357 					    uint64_t *val)
4358 {
4359 	struct drm_device *dev = connector->dev;
4360 	struct amdgpu_device *adev = dev->dev_private;
4361 	struct dm_connector_state *dm_state =
4362 		to_dm_connector_state(state);
4363 	int ret = -EINVAL;
4364 
4365 	if (property == dev->mode_config.scaling_mode_property) {
4366 		switch (dm_state->scaling) {
4367 		case RMX_CENTER:
4368 			*val = DRM_MODE_SCALE_CENTER;
4369 			break;
4370 		case RMX_ASPECT:
4371 			*val = DRM_MODE_SCALE_ASPECT;
4372 			break;
4373 		case RMX_FULL:
4374 			*val = DRM_MODE_SCALE_FULLSCREEN;
4375 			break;
4376 		case RMX_OFF:
4377 		default:
4378 			*val = DRM_MODE_SCALE_NONE;
4379 			break;
4380 		}
4381 		ret = 0;
4382 	} else if (property == adev->mode_info.underscan_hborder_property) {
4383 		*val = dm_state->underscan_hborder;
4384 		ret = 0;
4385 	} else if (property == adev->mode_info.underscan_vborder_property) {
4386 		*val = dm_state->underscan_vborder;
4387 		ret = 0;
4388 	} else if (property == adev->mode_info.underscan_property) {
4389 		*val = dm_state->underscan_enable;
4390 		ret = 0;
4391 	} else if (property == adev->mode_info.abm_level_property) {
4392 		*val = dm_state->abm_level;
4393 		ret = 0;
4394 	}
4395 
4396 	return ret;
4397 }
4398 
4399 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
4400 {
4401 	struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
4402 
4403 	drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
4404 }
4405 
4406 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
4407 {
4408 	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
4409 	const struct dc_link *link = aconnector->dc_link;
4410 	struct amdgpu_device *adev = connector->dev->dev_private;
4411 	struct amdgpu_display_manager *dm = &adev->dm;
4412 
4413 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
4414 	defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
4415 
4416 	if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
4417 	    link->type != dc_connection_none &&
4418 	    dm->backlight_dev) {
4419 		backlight_device_unregister(dm->backlight_dev);
4420 		dm->backlight_dev = NULL;
4421 	}
4422 #endif
4423 
4424 	if (aconnector->dc_em_sink)
4425 		dc_sink_release(aconnector->dc_em_sink);
4426 	aconnector->dc_em_sink = NULL;
4427 	if (aconnector->dc_sink)
4428 		dc_sink_release(aconnector->dc_sink);
4429 	aconnector->dc_sink = NULL;
4430 
4431 	drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
4432 	drm_connector_unregister(connector);
4433 	drm_connector_cleanup(connector);
4434 	if (aconnector->i2c) {
4435 		i2c_del_adapter(&aconnector->i2c->base);
4436 		kfree(aconnector->i2c);
4437 	}
4438 
4439 	kfree(connector);
4440 }
4441 
4442 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
4443 {
4444 	struct dm_connector_state *state =
4445 		to_dm_connector_state(connector->state);
4446 
4447 	if (connector->state)
4448 		__drm_atomic_helper_connector_destroy_state(connector->state);
4449 
4450 	kfree(state);
4451 
4452 	state = kzalloc(sizeof(*state), GFP_KERNEL);
4453 
4454 	if (state) {
4455 		state->scaling = RMX_OFF;
4456 		state->underscan_enable = false;
4457 		state->underscan_hborder = 0;
4458 		state->underscan_vborder = 0;
4459 		state->base.max_requested_bpc = 8;
4460 		state->vcpi_slots = 0;
4461 		state->pbn = 0;
4462 		if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4463 			state->abm_level = amdgpu_dm_abm_level;
4464 
4465 		__drm_atomic_helper_connector_reset(connector, &state->base);
4466 	}
4467 }
4468 
4469 struct drm_connector_state *
4470 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
4471 {
4472 	struct dm_connector_state *state =
4473 		to_dm_connector_state(connector->state);
4474 
4475 	struct dm_connector_state *new_state =
4476 			kmemdup(state, sizeof(*state), GFP_KERNEL);
4477 
4478 	if (!new_state)
4479 		return NULL;
4480 
4481 	__drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
4482 
4483 	new_state->freesync_capable = state->freesync_capable;
4484 	new_state->abm_level = state->abm_level;
4485 	new_state->scaling = state->scaling;
4486 	new_state->underscan_enable = state->underscan_enable;
4487 	new_state->underscan_hborder = state->underscan_hborder;
4488 	new_state->underscan_vborder = state->underscan_vborder;
4489 	new_state->vcpi_slots = state->vcpi_slots;
4490 	new_state->pbn = state->pbn;
4491 	return &new_state->base;
4492 }
4493 
4494 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
4495 	.reset = amdgpu_dm_connector_funcs_reset,
4496 	.detect = amdgpu_dm_connector_detect,
4497 	.fill_modes = drm_helper_probe_single_connector_modes,
4498 	.destroy = amdgpu_dm_connector_destroy,
4499 	.atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
4500 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4501 	.atomic_set_property = amdgpu_dm_connector_atomic_set_property,
4502 	.atomic_get_property = amdgpu_dm_connector_atomic_get_property,
4503 	.early_unregister = amdgpu_dm_connector_unregister
4504 };
4505 
4506 static int get_modes(struct drm_connector *connector)
4507 {
4508 	return amdgpu_dm_connector_get_modes(connector);
4509 }
4510 
4511 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
4512 {
4513 	struct dc_sink_init_data init_params = {
4514 			.link = aconnector->dc_link,
4515 			.sink_signal = SIGNAL_TYPE_VIRTUAL
4516 	};
4517 	struct edid *edid;
4518 
4519 	if (!aconnector->base.edid_blob_ptr) {
4520 		DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
4521 				aconnector->base.name);
4522 
4523 		aconnector->base.force = DRM_FORCE_OFF;
4524 		aconnector->base.override_edid = false;
4525 		return;
4526 	}
4527 
4528 	edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
4529 
4530 	aconnector->edid = edid;
4531 
4532 	aconnector->dc_em_sink = dc_link_add_remote_sink(
4533 		aconnector->dc_link,
4534 		(uint8_t *)edid,
4535 		(edid->extensions + 1) * EDID_LENGTH,
4536 		&init_params);
4537 
4538 	if (aconnector->base.force == DRM_FORCE_ON) {
4539 		aconnector->dc_sink = aconnector->dc_link->local_sink ?
4540 		aconnector->dc_link->local_sink :
4541 		aconnector->dc_em_sink;
4542 		dc_sink_retain(aconnector->dc_sink);
4543 	}
4544 }
4545 
4546 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
4547 {
4548 	struct dc_link *link = (struct dc_link *)aconnector->dc_link;
4549 
4550 	/*
4551 	 * In case of headless boot with force on for DP managed connector
4552 	 * Those settings have to be != 0 to get initial modeset
4553 	 */
4554 	if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
4555 		link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
4556 		link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
4557 	}
4558 
4559 
4560 	aconnector->base.override_edid = true;
4561 	create_eml_sink(aconnector);
4562 }
4563 
4564 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
4565 				   struct drm_display_mode *mode)
4566 {
4567 	int result = MODE_ERROR;
4568 	struct dc_sink *dc_sink;
4569 	struct amdgpu_device *adev = connector->dev->dev_private;
4570 	/* TODO: Unhardcode stream count */
4571 	struct dc_stream_state *stream;
4572 	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
4573 	enum dc_status dc_result = DC_OK;
4574 
4575 	if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
4576 			(mode->flags & DRM_MODE_FLAG_DBLSCAN))
4577 		return result;
4578 
4579 	/*
4580 	 * Only run this the first time mode_valid is called to initilialize
4581 	 * EDID mgmt
4582 	 */
4583 	if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
4584 		!aconnector->dc_em_sink)
4585 		handle_edid_mgmt(aconnector);
4586 
4587 	dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
4588 
4589 	if (dc_sink == NULL) {
4590 		DRM_ERROR("dc_sink is NULL!\n");
4591 		goto fail;
4592 	}
4593 
4594 	stream = create_stream_for_sink(aconnector, mode, NULL, NULL);
4595 	if (stream == NULL) {
4596 		DRM_ERROR("Failed to create stream for sink!\n");
4597 		goto fail;
4598 	}
4599 
4600 	dc_result = dc_validate_stream(adev->dm.dc, stream);
4601 
4602 	if (dc_result == DC_OK)
4603 		result = MODE_OK;
4604 	else
4605 		DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
4606 			      mode->hdisplay,
4607 			      mode->vdisplay,
4608 			      mode->clock,
4609 			      dc_result);
4610 
4611 	dc_stream_release(stream);
4612 
4613 fail:
4614 	/* TODO: error handling*/
4615 	return result;
4616 }
4617 
4618 static int fill_hdr_info_packet(const struct drm_connector_state *state,
4619 				struct dc_info_packet *out)
4620 {
4621 	struct hdmi_drm_infoframe frame;
4622 	unsigned char buf[30]; /* 26 + 4 */
4623 	ssize_t len;
4624 	int ret, i;
4625 
4626 	memset(out, 0, sizeof(*out));
4627 
4628 	if (!state->hdr_output_metadata)
4629 		return 0;
4630 
4631 	ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
4632 	if (ret)
4633 		return ret;
4634 
4635 	len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
4636 	if (len < 0)
4637 		return (int)len;
4638 
4639 	/* Static metadata is a fixed 26 bytes + 4 byte header. */
4640 	if (len != 30)
4641 		return -EINVAL;
4642 
4643 	/* Prepare the infopacket for DC. */
4644 	switch (state->connector->connector_type) {
4645 	case DRM_MODE_CONNECTOR_HDMIA:
4646 		out->hb0 = 0x87; /* type */
4647 		out->hb1 = 0x01; /* version */
4648 		out->hb2 = 0x1A; /* length */
4649 		out->sb[0] = buf[3]; /* checksum */
4650 		i = 1;
4651 		break;
4652 
4653 	case DRM_MODE_CONNECTOR_DisplayPort:
4654 	case DRM_MODE_CONNECTOR_eDP:
4655 		out->hb0 = 0x00; /* sdp id, zero */
4656 		out->hb1 = 0x87; /* type */
4657 		out->hb2 = 0x1D; /* payload len - 1 */
4658 		out->hb3 = (0x13 << 2); /* sdp version */
4659 		out->sb[0] = 0x01; /* version */
4660 		out->sb[1] = 0x1A; /* length */
4661 		i = 2;
4662 		break;
4663 
4664 	default:
4665 		return -EINVAL;
4666 	}
4667 
4668 	memcpy(&out->sb[i], &buf[4], 26);
4669 	out->valid = true;
4670 
4671 	print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
4672 		       sizeof(out->sb), false);
4673 
4674 	return 0;
4675 }
4676 
4677 static bool
4678 is_hdr_metadata_different(const struct drm_connector_state *old_state,
4679 			  const struct drm_connector_state *new_state)
4680 {
4681 	struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
4682 	struct drm_property_blob *new_blob = new_state->hdr_output_metadata;
4683 
4684 	if (old_blob != new_blob) {
4685 		if (old_blob && new_blob &&
4686 		    old_blob->length == new_blob->length)
4687 			return memcmp(old_blob->data, new_blob->data,
4688 				      old_blob->length);
4689 
4690 		return true;
4691 	}
4692 
4693 	return false;
4694 }
4695 
4696 static int
4697 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
4698 				 struct drm_atomic_state *state)
4699 {
4700 	struct drm_connector_state *new_con_state =
4701 		drm_atomic_get_new_connector_state(state, conn);
4702 	struct drm_connector_state *old_con_state =
4703 		drm_atomic_get_old_connector_state(state, conn);
4704 	struct drm_crtc *crtc = new_con_state->crtc;
4705 	struct drm_crtc_state *new_crtc_state;
4706 	int ret;
4707 
4708 	if (!crtc)
4709 		return 0;
4710 
4711 	if (is_hdr_metadata_different(old_con_state, new_con_state)) {
4712 		struct dc_info_packet hdr_infopacket;
4713 
4714 		ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
4715 		if (ret)
4716 			return ret;
4717 
4718 		new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
4719 		if (IS_ERR(new_crtc_state))
4720 			return PTR_ERR(new_crtc_state);
4721 
4722 		/*
4723 		 * DC considers the stream backends changed if the
4724 		 * static metadata changes. Forcing the modeset also
4725 		 * gives a simple way for userspace to switch from
4726 		 * 8bpc to 10bpc when setting the metadata to enter
4727 		 * or exit HDR.
4728 		 *
4729 		 * Changing the static metadata after it's been
4730 		 * set is permissible, however. So only force a
4731 		 * modeset if we're entering or exiting HDR.
4732 		 */
4733 		new_crtc_state->mode_changed =
4734 			!old_con_state->hdr_output_metadata ||
4735 			!new_con_state->hdr_output_metadata;
4736 	}
4737 
4738 	return 0;
4739 }
4740 
4741 static const struct drm_connector_helper_funcs
4742 amdgpu_dm_connector_helper_funcs = {
4743 	/*
4744 	 * If hotplugging a second bigger display in FB Con mode, bigger resolution
4745 	 * modes will be filtered by drm_mode_validate_size(), and those modes
4746 	 * are missing after user start lightdm. So we need to renew modes list.
4747 	 * in get_modes call back, not just return the modes count
4748 	 */
4749 	.get_modes = get_modes,
4750 	.mode_valid = amdgpu_dm_connector_mode_valid,
4751 	.atomic_check = amdgpu_dm_connector_atomic_check,
4752 };
4753 
4754 static void dm_crtc_helper_disable(struct drm_crtc *crtc)
4755 {
4756 }
4757 
4758 static bool does_crtc_have_active_cursor(struct drm_crtc_state *new_crtc_state)
4759 {
4760 	struct drm_device *dev = new_crtc_state->crtc->dev;
4761 	struct drm_plane *plane;
4762 
4763 	drm_for_each_plane_mask(plane, dev, new_crtc_state->plane_mask) {
4764 		if (plane->type == DRM_PLANE_TYPE_CURSOR)
4765 			return true;
4766 	}
4767 
4768 	return false;
4769 }
4770 
4771 static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
4772 {
4773 	struct drm_atomic_state *state = new_crtc_state->state;
4774 	struct drm_plane *plane;
4775 	int num_active = 0;
4776 
4777 	drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) {
4778 		struct drm_plane_state *new_plane_state;
4779 
4780 		/* Cursor planes are "fake". */
4781 		if (plane->type == DRM_PLANE_TYPE_CURSOR)
4782 			continue;
4783 
4784 		new_plane_state = drm_atomic_get_new_plane_state(state, plane);
4785 
4786 		if (!new_plane_state) {
4787 			/*
4788 			 * The plane is enable on the CRTC and hasn't changed
4789 			 * state. This means that it previously passed
4790 			 * validation and is therefore enabled.
4791 			 */
4792 			num_active += 1;
4793 			continue;
4794 		}
4795 
4796 		/* We need a framebuffer to be considered enabled. */
4797 		num_active += (new_plane_state->fb != NULL);
4798 	}
4799 
4800 	return num_active;
4801 }
4802 
4803 /*
4804  * Sets whether interrupts should be enabled on a specific CRTC.
4805  * We require that the stream be enabled and that there exist active
4806  * DC planes on the stream.
4807  */
4808 static void
4809 dm_update_crtc_interrupt_state(struct drm_crtc *crtc,
4810 			       struct drm_crtc_state *new_crtc_state)
4811 {
4812 	struct dm_crtc_state *dm_new_crtc_state =
4813 		to_dm_crtc_state(new_crtc_state);
4814 
4815 	dm_new_crtc_state->active_planes = 0;
4816 	dm_new_crtc_state->interrupts_enabled = false;
4817 
4818 	if (!dm_new_crtc_state->stream)
4819 		return;
4820 
4821 	dm_new_crtc_state->active_planes =
4822 		count_crtc_active_planes(new_crtc_state);
4823 
4824 	dm_new_crtc_state->interrupts_enabled =
4825 		dm_new_crtc_state->active_planes > 0;
4826 }
4827 
4828 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
4829 				       struct drm_crtc_state *state)
4830 {
4831 	struct amdgpu_device *adev = crtc->dev->dev_private;
4832 	struct dc *dc = adev->dm.dc;
4833 	struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
4834 	int ret = -EINVAL;
4835 
4836 	/*
4837 	 * Update interrupt state for the CRTC. This needs to happen whenever
4838 	 * the CRTC has changed or whenever any of its planes have changed.
4839 	 * Atomic check satisfies both of these requirements since the CRTC
4840 	 * is added to the state by DRM during drm_atomic_helper_check_planes.
4841 	 */
4842 	dm_update_crtc_interrupt_state(crtc, state);
4843 
4844 	if (unlikely(!dm_crtc_state->stream &&
4845 		     modeset_required(state, NULL, dm_crtc_state->stream))) {
4846 		WARN_ON(1);
4847 		return ret;
4848 	}
4849 
4850 	/* In some use cases, like reset, no stream is attached */
4851 	if (!dm_crtc_state->stream)
4852 		return 0;
4853 
4854 	/*
4855 	 * We want at least one hardware plane enabled to use
4856 	 * the stream with a cursor enabled.
4857 	 */
4858 	if (state->enable && state->active &&
4859 	    does_crtc_have_active_cursor(state) &&
4860 	    dm_crtc_state->active_planes == 0)
4861 		return -EINVAL;
4862 
4863 	if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
4864 		return 0;
4865 
4866 	return ret;
4867 }
4868 
4869 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
4870 				      const struct drm_display_mode *mode,
4871 				      struct drm_display_mode *adjusted_mode)
4872 {
4873 	return true;
4874 }
4875 
4876 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
4877 	.disable = dm_crtc_helper_disable,
4878 	.atomic_check = dm_crtc_helper_atomic_check,
4879 	.mode_fixup = dm_crtc_helper_mode_fixup
4880 };
4881 
4882 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
4883 {
4884 
4885 }
4886 
4887 static int convert_dc_color_depth_into_bpc (enum dc_color_depth display_color_depth)
4888 {
4889 	switch (display_color_depth) {
4890 		case COLOR_DEPTH_666:
4891 			return 6;
4892 		case COLOR_DEPTH_888:
4893 			return 8;
4894 		case COLOR_DEPTH_101010:
4895 			return 10;
4896 		case COLOR_DEPTH_121212:
4897 			return 12;
4898 		case COLOR_DEPTH_141414:
4899 			return 14;
4900 		case COLOR_DEPTH_161616:
4901 			return 16;
4902 		default:
4903 			break;
4904 		}
4905 	return 0;
4906 }
4907 
4908 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
4909 					  struct drm_crtc_state *crtc_state,
4910 					  struct drm_connector_state *conn_state)
4911 {
4912 	struct drm_atomic_state *state = crtc_state->state;
4913 	struct drm_connector *connector = conn_state->connector;
4914 	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
4915 	struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
4916 	const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
4917 	struct drm_dp_mst_topology_mgr *mst_mgr;
4918 	struct drm_dp_mst_port *mst_port;
4919 	enum dc_color_depth color_depth;
4920 	int clock, bpp = 0;
4921 	bool is_y420 = false;
4922 
4923 	if (!aconnector->port || !aconnector->dc_sink)
4924 		return 0;
4925 
4926 	mst_port = aconnector->port;
4927 	mst_mgr = &aconnector->mst_port->mst_mgr;
4928 
4929 	if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
4930 		return 0;
4931 
4932 	if (!state->duplicated) {
4933 		is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
4934 				aconnector->force_yuv420_output;
4935 		color_depth = convert_color_depth_from_display_info(connector, conn_state,
4936 								    is_y420);
4937 		bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
4938 		clock = adjusted_mode->clock;
4939 		dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
4940 	}
4941 	dm_new_connector_state->vcpi_slots = drm_dp_atomic_find_vcpi_slots(state,
4942 									   mst_mgr,
4943 									   mst_port,
4944 									   dm_new_connector_state->pbn,
4945 									   0);
4946 	if (dm_new_connector_state->vcpi_slots < 0) {
4947 		DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
4948 		return dm_new_connector_state->vcpi_slots;
4949 	}
4950 	return 0;
4951 }
4952 
4953 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
4954 	.disable = dm_encoder_helper_disable,
4955 	.atomic_check = dm_encoder_helper_atomic_check
4956 };
4957 
4958 #if defined(CONFIG_DRM_AMD_DC_DCN)
4959 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
4960 					    struct dc_state *dc_state)
4961 {
4962 	struct dc_stream_state *stream = NULL;
4963 	struct drm_connector *connector;
4964 	struct drm_connector_state *new_con_state, *old_con_state;
4965 	struct amdgpu_dm_connector *aconnector;
4966 	struct dm_connector_state *dm_conn_state;
4967 	int i, j, clock, bpp;
4968 	int vcpi, pbn_div, pbn = 0;
4969 
4970 	for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
4971 
4972 		aconnector = to_amdgpu_dm_connector(connector);
4973 
4974 		if (!aconnector->port)
4975 			continue;
4976 
4977 		if (!new_con_state || !new_con_state->crtc)
4978 			continue;
4979 
4980 		dm_conn_state = to_dm_connector_state(new_con_state);
4981 
4982 		for (j = 0; j < dc_state->stream_count; j++) {
4983 			stream = dc_state->streams[j];
4984 			if (!stream)
4985 				continue;
4986 
4987 			if ((struct amdgpu_dm_connector*)stream->dm_stream_context == aconnector)
4988 				break;
4989 
4990 			stream = NULL;
4991 		}
4992 
4993 		if (!stream)
4994 			continue;
4995 
4996 		if (stream->timing.flags.DSC != 1) {
4997 			drm_dp_mst_atomic_enable_dsc(state,
4998 						     aconnector->port,
4999 						     dm_conn_state->pbn,
5000 						     0,
5001 						     false);
5002 			continue;
5003 		}
5004 
5005 		pbn_div = dm_mst_get_pbn_divider(stream->link);
5006 		bpp = stream->timing.dsc_cfg.bits_per_pixel;
5007 		clock = stream->timing.pix_clk_100hz / 10;
5008 		pbn = drm_dp_calc_pbn_mode(clock, bpp, true);
5009 		vcpi = drm_dp_mst_atomic_enable_dsc(state,
5010 						    aconnector->port,
5011 						    pbn, pbn_div,
5012 						    true);
5013 		if (vcpi < 0)
5014 			return vcpi;
5015 
5016 		dm_conn_state->pbn = pbn;
5017 		dm_conn_state->vcpi_slots = vcpi;
5018 	}
5019 	return 0;
5020 }
5021 #endif
5022 
5023 static void dm_drm_plane_reset(struct drm_plane *plane)
5024 {
5025 	struct dm_plane_state *amdgpu_state = NULL;
5026 
5027 	if (plane->state)
5028 		plane->funcs->atomic_destroy_state(plane, plane->state);
5029 
5030 	amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
5031 	WARN_ON(amdgpu_state == NULL);
5032 
5033 	if (amdgpu_state)
5034 		__drm_atomic_helper_plane_reset(plane, &amdgpu_state->base);
5035 }
5036 
5037 static struct drm_plane_state *
5038 dm_drm_plane_duplicate_state(struct drm_plane *plane)
5039 {
5040 	struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
5041 
5042 	old_dm_plane_state = to_dm_plane_state(plane->state);
5043 	dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
5044 	if (!dm_plane_state)
5045 		return NULL;
5046 
5047 	__drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
5048 
5049 	if (old_dm_plane_state->dc_state) {
5050 		dm_plane_state->dc_state = old_dm_plane_state->dc_state;
5051 		dc_plane_state_retain(dm_plane_state->dc_state);
5052 	}
5053 
5054 	return &dm_plane_state->base;
5055 }
5056 
5057 void dm_drm_plane_destroy_state(struct drm_plane *plane,
5058 				struct drm_plane_state *state)
5059 {
5060 	struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
5061 
5062 	if (dm_plane_state->dc_state)
5063 		dc_plane_state_release(dm_plane_state->dc_state);
5064 
5065 	drm_atomic_helper_plane_destroy_state(plane, state);
5066 }
5067 
5068 static const struct drm_plane_funcs dm_plane_funcs = {
5069 	.update_plane	= drm_atomic_helper_update_plane,
5070 	.disable_plane	= drm_atomic_helper_disable_plane,
5071 	.destroy	= drm_primary_helper_destroy,
5072 	.reset = dm_drm_plane_reset,
5073 	.atomic_duplicate_state = dm_drm_plane_duplicate_state,
5074 	.atomic_destroy_state = dm_drm_plane_destroy_state,
5075 };
5076 
5077 static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
5078 				      struct drm_plane_state *new_state)
5079 {
5080 	struct amdgpu_framebuffer *afb;
5081 	struct drm_gem_object *obj;
5082 	struct amdgpu_device *adev;
5083 	struct amdgpu_bo *rbo;
5084 	struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
5085 	struct list_head list;
5086 	struct ttm_validate_buffer tv;
5087 	struct ww_acquire_ctx ticket;
5088 	uint64_t tiling_flags;
5089 	uint32_t domain;
5090 	int r;
5091 
5092 	dm_plane_state_old = to_dm_plane_state(plane->state);
5093 	dm_plane_state_new = to_dm_plane_state(new_state);
5094 
5095 	if (!new_state->fb) {
5096 		DRM_DEBUG_DRIVER("No FB bound\n");
5097 		return 0;
5098 	}
5099 
5100 	afb = to_amdgpu_framebuffer(new_state->fb);
5101 	obj = new_state->fb->obj[0];
5102 	rbo = gem_to_amdgpu_bo(obj);
5103 	adev = amdgpu_ttm_adev(rbo->tbo.bdev);
5104 	INIT_LIST_HEAD(&list);
5105 
5106 	tv.bo = &rbo->tbo;
5107 	tv.num_shared = 1;
5108 	list_add(&tv.head, &list);
5109 
5110 	r = ttm_eu_reserve_buffers(&ticket, &list, false, NULL);
5111 	if (r) {
5112 		dev_err(adev->dev, "fail to reserve bo (%d)\n", r);
5113 		return r;
5114 	}
5115 
5116 	if (plane->type != DRM_PLANE_TYPE_CURSOR)
5117 		domain = amdgpu_display_supported_domains(adev, rbo->flags);
5118 	else
5119 		domain = AMDGPU_GEM_DOMAIN_VRAM;
5120 
5121 	r = amdgpu_bo_pin(rbo, domain);
5122 	if (unlikely(r != 0)) {
5123 		if (r != -ERESTARTSYS)
5124 			DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
5125 		ttm_eu_backoff_reservation(&ticket, &list);
5126 		return r;
5127 	}
5128 
5129 	r = amdgpu_ttm_alloc_gart(&rbo->tbo);
5130 	if (unlikely(r != 0)) {
5131 		amdgpu_bo_unpin(rbo);
5132 		ttm_eu_backoff_reservation(&ticket, &list);
5133 		DRM_ERROR("%p bind failed\n", rbo);
5134 		return r;
5135 	}
5136 
5137 	amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
5138 
5139 	ttm_eu_backoff_reservation(&ticket, &list);
5140 
5141 	afb->address = amdgpu_bo_gpu_offset(rbo);
5142 
5143 	amdgpu_bo_ref(rbo);
5144 
5145 	if (dm_plane_state_new->dc_state &&
5146 			dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
5147 		struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
5148 
5149 		fill_plane_buffer_attributes(
5150 			adev, afb, plane_state->format, plane_state->rotation,
5151 			tiling_flags, &plane_state->tiling_info,
5152 			&plane_state->plane_size, &plane_state->dcc,
5153 			&plane_state->address);
5154 	}
5155 
5156 	return 0;
5157 }
5158 
5159 static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
5160 				       struct drm_plane_state *old_state)
5161 {
5162 	struct amdgpu_bo *rbo;
5163 	int r;
5164 
5165 	if (!old_state->fb)
5166 		return;
5167 
5168 	rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
5169 	r = amdgpu_bo_reserve(rbo, false);
5170 	if (unlikely(r)) {
5171 		DRM_ERROR("failed to reserve rbo before unpin\n");
5172 		return;
5173 	}
5174 
5175 	amdgpu_bo_unpin(rbo);
5176 	amdgpu_bo_unreserve(rbo);
5177 	amdgpu_bo_unref(&rbo);
5178 }
5179 
5180 static int dm_plane_atomic_check(struct drm_plane *plane,
5181 				 struct drm_plane_state *state)
5182 {
5183 	struct amdgpu_device *adev = plane->dev->dev_private;
5184 	struct dc *dc = adev->dm.dc;
5185 	struct dm_plane_state *dm_plane_state;
5186 	struct dc_scaling_info scaling_info;
5187 	int ret;
5188 
5189 	dm_plane_state = to_dm_plane_state(state);
5190 
5191 	if (!dm_plane_state->dc_state)
5192 		return 0;
5193 
5194 	ret = fill_dc_scaling_info(state, &scaling_info);
5195 	if (ret)
5196 		return ret;
5197 
5198 	if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
5199 		return 0;
5200 
5201 	return -EINVAL;
5202 }
5203 
5204 static int dm_plane_atomic_async_check(struct drm_plane *plane,
5205 				       struct drm_plane_state *new_plane_state)
5206 {
5207 	/* Only support async updates on cursor planes. */
5208 	if (plane->type != DRM_PLANE_TYPE_CURSOR)
5209 		return -EINVAL;
5210 
5211 	return 0;
5212 }
5213 
5214 static void dm_plane_atomic_async_update(struct drm_plane *plane,
5215 					 struct drm_plane_state *new_state)
5216 {
5217 	struct drm_plane_state *old_state =
5218 		drm_atomic_get_old_plane_state(new_state->state, plane);
5219 
5220 	swap(plane->state->fb, new_state->fb);
5221 
5222 	plane->state->src_x = new_state->src_x;
5223 	plane->state->src_y = new_state->src_y;
5224 	plane->state->src_w = new_state->src_w;
5225 	plane->state->src_h = new_state->src_h;
5226 	plane->state->crtc_x = new_state->crtc_x;
5227 	plane->state->crtc_y = new_state->crtc_y;
5228 	plane->state->crtc_w = new_state->crtc_w;
5229 	plane->state->crtc_h = new_state->crtc_h;
5230 
5231 	handle_cursor_update(plane, old_state);
5232 }
5233 
5234 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
5235 	.prepare_fb = dm_plane_helper_prepare_fb,
5236 	.cleanup_fb = dm_plane_helper_cleanup_fb,
5237 	.atomic_check = dm_plane_atomic_check,
5238 	.atomic_async_check = dm_plane_atomic_async_check,
5239 	.atomic_async_update = dm_plane_atomic_async_update
5240 };
5241 
5242 /*
5243  * TODO: these are currently initialized to rgb formats only.
5244  * For future use cases we should either initialize them dynamically based on
5245  * plane capabilities, or initialize this array to all formats, so internal drm
5246  * check will succeed, and let DC implement proper check
5247  */
5248 static const uint32_t rgb_formats[] = {
5249 	DRM_FORMAT_XRGB8888,
5250 	DRM_FORMAT_ARGB8888,
5251 	DRM_FORMAT_RGBA8888,
5252 	DRM_FORMAT_XRGB2101010,
5253 	DRM_FORMAT_XBGR2101010,
5254 	DRM_FORMAT_ARGB2101010,
5255 	DRM_FORMAT_ABGR2101010,
5256 	DRM_FORMAT_XBGR8888,
5257 	DRM_FORMAT_ABGR8888,
5258 	DRM_FORMAT_RGB565,
5259 };
5260 
5261 static const uint32_t overlay_formats[] = {
5262 	DRM_FORMAT_XRGB8888,
5263 	DRM_FORMAT_ARGB8888,
5264 	DRM_FORMAT_RGBA8888,
5265 	DRM_FORMAT_XBGR8888,
5266 	DRM_FORMAT_ABGR8888,
5267 	DRM_FORMAT_RGB565
5268 };
5269 
5270 static const u32 cursor_formats[] = {
5271 	DRM_FORMAT_ARGB8888
5272 };
5273 
5274 static int get_plane_formats(const struct drm_plane *plane,
5275 			     const struct dc_plane_cap *plane_cap,
5276 			     uint32_t *formats, int max_formats)
5277 {
5278 	int i, num_formats = 0;
5279 
5280 	/*
5281 	 * TODO: Query support for each group of formats directly from
5282 	 * DC plane caps. This will require adding more formats to the
5283 	 * caps list.
5284 	 */
5285 
5286 	switch (plane->type) {
5287 	case DRM_PLANE_TYPE_PRIMARY:
5288 		for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) {
5289 			if (num_formats >= max_formats)
5290 				break;
5291 
5292 			formats[num_formats++] = rgb_formats[i];
5293 		}
5294 
5295 		if (plane_cap && plane_cap->pixel_format_support.nv12)
5296 			formats[num_formats++] = DRM_FORMAT_NV12;
5297 		break;
5298 
5299 	case DRM_PLANE_TYPE_OVERLAY:
5300 		for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) {
5301 			if (num_formats >= max_formats)
5302 				break;
5303 
5304 			formats[num_formats++] = overlay_formats[i];
5305 		}
5306 		break;
5307 
5308 	case DRM_PLANE_TYPE_CURSOR:
5309 		for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) {
5310 			if (num_formats >= max_formats)
5311 				break;
5312 
5313 			formats[num_formats++] = cursor_formats[i];
5314 		}
5315 		break;
5316 	}
5317 
5318 	return num_formats;
5319 }
5320 
5321 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
5322 				struct drm_plane *plane,
5323 				unsigned long possible_crtcs,
5324 				const struct dc_plane_cap *plane_cap)
5325 {
5326 	uint32_t formats[32];
5327 	int num_formats;
5328 	int res = -EPERM;
5329 
5330 	num_formats = get_plane_formats(plane, plane_cap, formats,
5331 					ARRAY_SIZE(formats));
5332 
5333 	res = drm_universal_plane_init(dm->adev->ddev, plane, possible_crtcs,
5334 				       &dm_plane_funcs, formats, num_formats,
5335 				       NULL, plane->type, NULL);
5336 	if (res)
5337 		return res;
5338 
5339 	if (plane->type == DRM_PLANE_TYPE_OVERLAY &&
5340 	    plane_cap && plane_cap->per_pixel_alpha) {
5341 		unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
5342 					  BIT(DRM_MODE_BLEND_PREMULTI);
5343 
5344 		drm_plane_create_alpha_property(plane);
5345 		drm_plane_create_blend_mode_property(plane, blend_caps);
5346 	}
5347 
5348 	if (plane->type == DRM_PLANE_TYPE_PRIMARY &&
5349 	    plane_cap && plane_cap->pixel_format_support.nv12) {
5350 		/* This only affects YUV formats. */
5351 		drm_plane_create_color_properties(
5352 			plane,
5353 			BIT(DRM_COLOR_YCBCR_BT601) |
5354 			BIT(DRM_COLOR_YCBCR_BT709),
5355 			BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
5356 			BIT(DRM_COLOR_YCBCR_FULL_RANGE),
5357 			DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE);
5358 	}
5359 
5360 	drm_plane_helper_add(plane, &dm_plane_helper_funcs);
5361 
5362 	/* Create (reset) the plane state */
5363 	if (plane->funcs->reset)
5364 		plane->funcs->reset(plane);
5365 
5366 	return 0;
5367 }
5368 
5369 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
5370 			       struct drm_plane *plane,
5371 			       uint32_t crtc_index)
5372 {
5373 	struct amdgpu_crtc *acrtc = NULL;
5374 	struct drm_plane *cursor_plane;
5375 
5376 	int res = -ENOMEM;
5377 
5378 	cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
5379 	if (!cursor_plane)
5380 		goto fail;
5381 
5382 	cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
5383 	res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL);
5384 
5385 	acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
5386 	if (!acrtc)
5387 		goto fail;
5388 
5389 	res = drm_crtc_init_with_planes(
5390 			dm->ddev,
5391 			&acrtc->base,
5392 			plane,
5393 			cursor_plane,
5394 			&amdgpu_dm_crtc_funcs, NULL);
5395 
5396 	if (res)
5397 		goto fail;
5398 
5399 	drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
5400 
5401 	/* Create (reset) the plane state */
5402 	if (acrtc->base.funcs->reset)
5403 		acrtc->base.funcs->reset(&acrtc->base);
5404 
5405 	acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
5406 	acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
5407 
5408 	acrtc->crtc_id = crtc_index;
5409 	acrtc->base.enabled = false;
5410 	acrtc->otg_inst = -1;
5411 
5412 	dm->adev->mode_info.crtcs[crtc_index] = acrtc;
5413 	drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
5414 				   true, MAX_COLOR_LUT_ENTRIES);
5415 	drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
5416 
5417 	return 0;
5418 
5419 fail:
5420 	kfree(acrtc);
5421 	kfree(cursor_plane);
5422 	return res;
5423 }
5424 
5425 
5426 static int to_drm_connector_type(enum signal_type st)
5427 {
5428 	switch (st) {
5429 	case SIGNAL_TYPE_HDMI_TYPE_A:
5430 		return DRM_MODE_CONNECTOR_HDMIA;
5431 	case SIGNAL_TYPE_EDP:
5432 		return DRM_MODE_CONNECTOR_eDP;
5433 	case SIGNAL_TYPE_LVDS:
5434 		return DRM_MODE_CONNECTOR_LVDS;
5435 	case SIGNAL_TYPE_RGB:
5436 		return DRM_MODE_CONNECTOR_VGA;
5437 	case SIGNAL_TYPE_DISPLAY_PORT:
5438 	case SIGNAL_TYPE_DISPLAY_PORT_MST:
5439 		return DRM_MODE_CONNECTOR_DisplayPort;
5440 	case SIGNAL_TYPE_DVI_DUAL_LINK:
5441 	case SIGNAL_TYPE_DVI_SINGLE_LINK:
5442 		return DRM_MODE_CONNECTOR_DVID;
5443 	case SIGNAL_TYPE_VIRTUAL:
5444 		return DRM_MODE_CONNECTOR_VIRTUAL;
5445 
5446 	default:
5447 		return DRM_MODE_CONNECTOR_Unknown;
5448 	}
5449 }
5450 
5451 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
5452 {
5453 	struct drm_encoder *encoder;
5454 
5455 	/* There is only one encoder per connector */
5456 	drm_connector_for_each_possible_encoder(connector, encoder)
5457 		return encoder;
5458 
5459 	return NULL;
5460 }
5461 
5462 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
5463 {
5464 	struct drm_encoder *encoder;
5465 	struct amdgpu_encoder *amdgpu_encoder;
5466 
5467 	encoder = amdgpu_dm_connector_to_encoder(connector);
5468 
5469 	if (encoder == NULL)
5470 		return;
5471 
5472 	amdgpu_encoder = to_amdgpu_encoder(encoder);
5473 
5474 	amdgpu_encoder->native_mode.clock = 0;
5475 
5476 	if (!list_empty(&connector->probed_modes)) {
5477 		struct drm_display_mode *preferred_mode = NULL;
5478 
5479 		list_for_each_entry(preferred_mode,
5480 				    &connector->probed_modes,
5481 				    head) {
5482 			if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
5483 				amdgpu_encoder->native_mode = *preferred_mode;
5484 
5485 			break;
5486 		}
5487 
5488 	}
5489 }
5490 
5491 static struct drm_display_mode *
5492 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
5493 			     char *name,
5494 			     int hdisplay, int vdisplay)
5495 {
5496 	struct drm_device *dev = encoder->dev;
5497 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
5498 	struct drm_display_mode *mode = NULL;
5499 	struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
5500 
5501 	mode = drm_mode_duplicate(dev, native_mode);
5502 
5503 	if (mode == NULL)
5504 		return NULL;
5505 
5506 	mode->hdisplay = hdisplay;
5507 	mode->vdisplay = vdisplay;
5508 	mode->type &= ~DRM_MODE_TYPE_PREFERRED;
5509 	strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
5510 
5511 	return mode;
5512 
5513 }
5514 
5515 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
5516 						 struct drm_connector *connector)
5517 {
5518 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
5519 	struct drm_display_mode *mode = NULL;
5520 	struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
5521 	struct amdgpu_dm_connector *amdgpu_dm_connector =
5522 				to_amdgpu_dm_connector(connector);
5523 	int i;
5524 	int n;
5525 	struct mode_size {
5526 		char name[DRM_DISPLAY_MODE_LEN];
5527 		int w;
5528 		int h;
5529 	} common_modes[] = {
5530 		{  "640x480",  640,  480},
5531 		{  "800x600",  800,  600},
5532 		{ "1024x768", 1024,  768},
5533 		{ "1280x720", 1280,  720},
5534 		{ "1280x800", 1280,  800},
5535 		{"1280x1024", 1280, 1024},
5536 		{ "1440x900", 1440,  900},
5537 		{"1680x1050", 1680, 1050},
5538 		{"1600x1200", 1600, 1200},
5539 		{"1920x1080", 1920, 1080},
5540 		{"1920x1200", 1920, 1200}
5541 	};
5542 
5543 	n = ARRAY_SIZE(common_modes);
5544 
5545 	for (i = 0; i < n; i++) {
5546 		struct drm_display_mode *curmode = NULL;
5547 		bool mode_existed = false;
5548 
5549 		if (common_modes[i].w > native_mode->hdisplay ||
5550 		    common_modes[i].h > native_mode->vdisplay ||
5551 		   (common_modes[i].w == native_mode->hdisplay &&
5552 		    common_modes[i].h == native_mode->vdisplay))
5553 			continue;
5554 
5555 		list_for_each_entry(curmode, &connector->probed_modes, head) {
5556 			if (common_modes[i].w == curmode->hdisplay &&
5557 			    common_modes[i].h == curmode->vdisplay) {
5558 				mode_existed = true;
5559 				break;
5560 			}
5561 		}
5562 
5563 		if (mode_existed)
5564 			continue;
5565 
5566 		mode = amdgpu_dm_create_common_mode(encoder,
5567 				common_modes[i].name, common_modes[i].w,
5568 				common_modes[i].h);
5569 		drm_mode_probed_add(connector, mode);
5570 		amdgpu_dm_connector->num_modes++;
5571 	}
5572 }
5573 
5574 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
5575 					      struct edid *edid)
5576 {
5577 	struct amdgpu_dm_connector *amdgpu_dm_connector =
5578 			to_amdgpu_dm_connector(connector);
5579 
5580 	if (edid) {
5581 		/* empty probed_modes */
5582 		INIT_LIST_HEAD(&connector->probed_modes);
5583 		amdgpu_dm_connector->num_modes =
5584 				drm_add_edid_modes(connector, edid);
5585 
5586 		/* sorting the probed modes before calling function
5587 		 * amdgpu_dm_get_native_mode() since EDID can have
5588 		 * more than one preferred mode. The modes that are
5589 		 * later in the probed mode list could be of higher
5590 		 * and preferred resolution. For example, 3840x2160
5591 		 * resolution in base EDID preferred timing and 4096x2160
5592 		 * preferred resolution in DID extension block later.
5593 		 */
5594 		drm_mode_sort(&connector->probed_modes);
5595 		amdgpu_dm_get_native_mode(connector);
5596 	} else {
5597 		amdgpu_dm_connector->num_modes = 0;
5598 	}
5599 }
5600 
5601 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
5602 {
5603 	struct amdgpu_dm_connector *amdgpu_dm_connector =
5604 			to_amdgpu_dm_connector(connector);
5605 	struct drm_encoder *encoder;
5606 	struct edid *edid = amdgpu_dm_connector->edid;
5607 
5608 	encoder = amdgpu_dm_connector_to_encoder(connector);
5609 
5610 	if (!edid || !drm_edid_is_valid(edid)) {
5611 		amdgpu_dm_connector->num_modes =
5612 				drm_add_modes_noedid(connector, 640, 480);
5613 	} else {
5614 		amdgpu_dm_connector_ddc_get_modes(connector, edid);
5615 		amdgpu_dm_connector_add_common_modes(encoder, connector);
5616 	}
5617 	amdgpu_dm_fbc_init(connector);
5618 
5619 	return amdgpu_dm_connector->num_modes;
5620 }
5621 
5622 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
5623 				     struct amdgpu_dm_connector *aconnector,
5624 				     int connector_type,
5625 				     struct dc_link *link,
5626 				     int link_index)
5627 {
5628 	struct amdgpu_device *adev = dm->ddev->dev_private;
5629 
5630 	/*
5631 	 * Some of the properties below require access to state, like bpc.
5632 	 * Allocate some default initial connector state with our reset helper.
5633 	 */
5634 	if (aconnector->base.funcs->reset)
5635 		aconnector->base.funcs->reset(&aconnector->base);
5636 
5637 	aconnector->connector_id = link_index;
5638 	aconnector->dc_link = link;
5639 	aconnector->base.interlace_allowed = false;
5640 	aconnector->base.doublescan_allowed = false;
5641 	aconnector->base.stereo_allowed = false;
5642 	aconnector->base.dpms = DRM_MODE_DPMS_OFF;
5643 	aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
5644 	aconnector->audio_inst = -1;
5645 	mutex_init(&aconnector->hpd_lock);
5646 
5647 	/*
5648 	 * configure support HPD hot plug connector_>polled default value is 0
5649 	 * which means HPD hot plug not supported
5650 	 */
5651 	switch (connector_type) {
5652 	case DRM_MODE_CONNECTOR_HDMIA:
5653 		aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
5654 		aconnector->base.ycbcr_420_allowed =
5655 			link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
5656 		break;
5657 	case DRM_MODE_CONNECTOR_DisplayPort:
5658 		aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
5659 		aconnector->base.ycbcr_420_allowed =
5660 			link->link_enc->features.dp_ycbcr420_supported ? true : false;
5661 		break;
5662 	case DRM_MODE_CONNECTOR_DVID:
5663 		aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
5664 		break;
5665 	default:
5666 		break;
5667 	}
5668 
5669 	drm_object_attach_property(&aconnector->base.base,
5670 				dm->ddev->mode_config.scaling_mode_property,
5671 				DRM_MODE_SCALE_NONE);
5672 
5673 	drm_object_attach_property(&aconnector->base.base,
5674 				adev->mode_info.underscan_property,
5675 				UNDERSCAN_OFF);
5676 	drm_object_attach_property(&aconnector->base.base,
5677 				adev->mode_info.underscan_hborder_property,
5678 				0);
5679 	drm_object_attach_property(&aconnector->base.base,
5680 				adev->mode_info.underscan_vborder_property,
5681 				0);
5682 
5683 	drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
5684 
5685 	/* This defaults to the max in the range, but we want 8bpc for non-edp. */
5686 	aconnector->base.state->max_bpc = (connector_type == DRM_MODE_CONNECTOR_eDP) ? 16 : 8;
5687 	aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
5688 
5689 	if (connector_type == DRM_MODE_CONNECTOR_eDP &&
5690 	    dc_is_dmcu_initialized(adev->dm.dc)) {
5691 		drm_object_attach_property(&aconnector->base.base,
5692 				adev->mode_info.abm_level_property, 0);
5693 	}
5694 
5695 	if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
5696 	    connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5697 	    connector_type == DRM_MODE_CONNECTOR_eDP) {
5698 		drm_object_attach_property(
5699 			&aconnector->base.base,
5700 			dm->ddev->mode_config.hdr_output_metadata_property, 0);
5701 
5702 		drm_connector_attach_vrr_capable_property(
5703 			&aconnector->base);
5704 #ifdef CONFIG_DRM_AMD_DC_HDCP
5705 		if (adev->asic_type >= CHIP_RAVEN)
5706 			drm_connector_attach_content_protection_property(&aconnector->base, true);
5707 #endif
5708 	}
5709 }
5710 
5711 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
5712 			      struct i2c_msg *msgs, int num)
5713 {
5714 	struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
5715 	struct ddc_service *ddc_service = i2c->ddc_service;
5716 	struct i2c_command cmd;
5717 	int i;
5718 	int result = -EIO;
5719 
5720 	cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
5721 
5722 	if (!cmd.payloads)
5723 		return result;
5724 
5725 	cmd.number_of_payloads = num;
5726 	cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
5727 	cmd.speed = 100;
5728 
5729 	for (i = 0; i < num; i++) {
5730 		cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
5731 		cmd.payloads[i].address = msgs[i].addr;
5732 		cmd.payloads[i].length = msgs[i].len;
5733 		cmd.payloads[i].data = msgs[i].buf;
5734 	}
5735 
5736 	if (dc_submit_i2c(
5737 			ddc_service->ctx->dc,
5738 			ddc_service->ddc_pin->hw_info.ddc_channel,
5739 			&cmd))
5740 		result = num;
5741 
5742 	kfree(cmd.payloads);
5743 	return result;
5744 }
5745 
5746 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
5747 {
5748 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
5749 }
5750 
5751 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
5752 	.master_xfer = amdgpu_dm_i2c_xfer,
5753 	.functionality = amdgpu_dm_i2c_func,
5754 };
5755 
5756 static struct amdgpu_i2c_adapter *
5757 create_i2c(struct ddc_service *ddc_service,
5758 	   int link_index,
5759 	   int *res)
5760 {
5761 	struct amdgpu_device *adev = ddc_service->ctx->driver_context;
5762 	struct amdgpu_i2c_adapter *i2c;
5763 
5764 	i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
5765 	if (!i2c)
5766 		return NULL;
5767 	i2c->base.owner = THIS_MODULE;
5768 	i2c->base.class = I2C_CLASS_DDC;
5769 	i2c->base.dev.parent = &adev->pdev->dev;
5770 	i2c->base.algo = &amdgpu_dm_i2c_algo;
5771 	snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
5772 	i2c_set_adapdata(&i2c->base, i2c);
5773 	i2c->ddc_service = ddc_service;
5774 	i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index;
5775 
5776 	return i2c;
5777 }
5778 
5779 
5780 /*
5781  * Note: this function assumes that dc_link_detect() was called for the
5782  * dc_link which will be represented by this aconnector.
5783  */
5784 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
5785 				    struct amdgpu_dm_connector *aconnector,
5786 				    uint32_t link_index,
5787 				    struct amdgpu_encoder *aencoder)
5788 {
5789 	int res = 0;
5790 	int connector_type;
5791 	struct dc *dc = dm->dc;
5792 	struct dc_link *link = dc_get_link_at_index(dc, link_index);
5793 	struct amdgpu_i2c_adapter *i2c;
5794 
5795 	link->priv = aconnector;
5796 
5797 	DRM_DEBUG_DRIVER("%s()\n", __func__);
5798 
5799 	i2c = create_i2c(link->ddc, link->link_index, &res);
5800 	if (!i2c) {
5801 		DRM_ERROR("Failed to create i2c adapter data\n");
5802 		return -ENOMEM;
5803 	}
5804 
5805 	aconnector->i2c = i2c;
5806 	res = i2c_add_adapter(&i2c->base);
5807 
5808 	if (res) {
5809 		DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
5810 		goto out_free;
5811 	}
5812 
5813 	connector_type = to_drm_connector_type(link->connector_signal);
5814 
5815 	res = drm_connector_init_with_ddc(
5816 			dm->ddev,
5817 			&aconnector->base,
5818 			&amdgpu_dm_connector_funcs,
5819 			connector_type,
5820 			&i2c->base);
5821 
5822 	if (res) {
5823 		DRM_ERROR("connector_init failed\n");
5824 		aconnector->connector_id = -1;
5825 		goto out_free;
5826 	}
5827 
5828 	drm_connector_helper_add(
5829 			&aconnector->base,
5830 			&amdgpu_dm_connector_helper_funcs);
5831 
5832 	amdgpu_dm_connector_init_helper(
5833 		dm,
5834 		aconnector,
5835 		connector_type,
5836 		link,
5837 		link_index);
5838 
5839 	drm_connector_attach_encoder(
5840 		&aconnector->base, &aencoder->base);
5841 
5842 	drm_connector_register(&aconnector->base);
5843 #if defined(CONFIG_DEBUG_FS)
5844 	connector_debugfs_init(aconnector);
5845 	aconnector->debugfs_dpcd_address = 0;
5846 	aconnector->debugfs_dpcd_size = 0;
5847 #endif
5848 
5849 	if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
5850 		|| connector_type == DRM_MODE_CONNECTOR_eDP)
5851 		amdgpu_dm_initialize_dp_connector(dm, aconnector);
5852 
5853 out_free:
5854 	if (res) {
5855 		kfree(i2c);
5856 		aconnector->i2c = NULL;
5857 	}
5858 	return res;
5859 }
5860 
5861 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
5862 {
5863 	switch (adev->mode_info.num_crtc) {
5864 	case 1:
5865 		return 0x1;
5866 	case 2:
5867 		return 0x3;
5868 	case 3:
5869 		return 0x7;
5870 	case 4:
5871 		return 0xf;
5872 	case 5:
5873 		return 0x1f;
5874 	case 6:
5875 	default:
5876 		return 0x3f;
5877 	}
5878 }
5879 
5880 static int amdgpu_dm_encoder_init(struct drm_device *dev,
5881 				  struct amdgpu_encoder *aencoder,
5882 				  uint32_t link_index)
5883 {
5884 	struct amdgpu_device *adev = dev->dev_private;
5885 
5886 	int res = drm_encoder_init(dev,
5887 				   &aencoder->base,
5888 				   &amdgpu_dm_encoder_funcs,
5889 				   DRM_MODE_ENCODER_TMDS,
5890 				   NULL);
5891 
5892 	aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
5893 
5894 	if (!res)
5895 		aencoder->encoder_id = link_index;
5896 	else
5897 		aencoder->encoder_id = -1;
5898 
5899 	drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
5900 
5901 	return res;
5902 }
5903 
5904 static void manage_dm_interrupts(struct amdgpu_device *adev,
5905 				 struct amdgpu_crtc *acrtc,
5906 				 bool enable)
5907 {
5908 	/*
5909 	 * this is not correct translation but will work as soon as VBLANK
5910 	 * constant is the same as PFLIP
5911 	 */
5912 	int irq_type =
5913 		amdgpu_display_crtc_idx_to_irq_type(
5914 			adev,
5915 			acrtc->crtc_id);
5916 
5917 	if (enable) {
5918 		drm_crtc_vblank_on(&acrtc->base);
5919 		amdgpu_irq_get(
5920 			adev,
5921 			&adev->pageflip_irq,
5922 			irq_type);
5923 	} else {
5924 
5925 		amdgpu_irq_put(
5926 			adev,
5927 			&adev->pageflip_irq,
5928 			irq_type);
5929 		drm_crtc_vblank_off(&acrtc->base);
5930 	}
5931 }
5932 
5933 static bool
5934 is_scaling_state_different(const struct dm_connector_state *dm_state,
5935 			   const struct dm_connector_state *old_dm_state)
5936 {
5937 	if (dm_state->scaling != old_dm_state->scaling)
5938 		return true;
5939 	if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
5940 		if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
5941 			return true;
5942 	} else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
5943 		if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
5944 			return true;
5945 	} else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
5946 		   dm_state->underscan_vborder != old_dm_state->underscan_vborder)
5947 		return true;
5948 	return false;
5949 }
5950 
5951 #ifdef CONFIG_DRM_AMD_DC_HDCP
5952 static bool is_content_protection_different(struct drm_connector_state *state,
5953 					    const struct drm_connector_state *old_state,
5954 					    const struct drm_connector *connector, struct hdcp_workqueue *hdcp_w)
5955 {
5956 	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5957 
5958 	if (old_state->hdcp_content_type != state->hdcp_content_type &&
5959 	    state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
5960 		state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
5961 		return true;
5962 	}
5963 
5964 	/* CP is being re enabled, ignore this */
5965 	if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
5966 	    state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
5967 		state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
5968 		return false;
5969 	}
5970 
5971 	/* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED */
5972 	if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
5973 	    state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
5974 		state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
5975 
5976 	/* Check if something is connected/enabled, otherwise we start hdcp but nothing is connected/enabled
5977 	 * hot-plug, headless s3, dpms
5978 	 */
5979 	if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED && connector->dpms == DRM_MODE_DPMS_ON &&
5980 	    aconnector->dc_sink != NULL)
5981 		return true;
5982 
5983 	if (old_state->content_protection == state->content_protection)
5984 		return false;
5985 
5986 	if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
5987 		return true;
5988 
5989 	return false;
5990 }
5991 
5992 #endif
5993 static void remove_stream(struct amdgpu_device *adev,
5994 			  struct amdgpu_crtc *acrtc,
5995 			  struct dc_stream_state *stream)
5996 {
5997 	/* this is the update mode case */
5998 
5999 	acrtc->otg_inst = -1;
6000 	acrtc->enabled = false;
6001 }
6002 
6003 static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
6004 			       struct dc_cursor_position *position)
6005 {
6006 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
6007 	int x, y;
6008 	int xorigin = 0, yorigin = 0;
6009 
6010 	position->enable = false;
6011 	position->x = 0;
6012 	position->y = 0;
6013 
6014 	if (!crtc || !plane->state->fb)
6015 		return 0;
6016 
6017 	if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
6018 	    (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
6019 		DRM_ERROR("%s: bad cursor width or height %d x %d\n",
6020 			  __func__,
6021 			  plane->state->crtc_w,
6022 			  plane->state->crtc_h);
6023 		return -EINVAL;
6024 	}
6025 
6026 	x = plane->state->crtc_x;
6027 	y = plane->state->crtc_y;
6028 
6029 	if (x <= -amdgpu_crtc->max_cursor_width ||
6030 	    y <= -amdgpu_crtc->max_cursor_height)
6031 		return 0;
6032 
6033 	if (crtc->primary->state) {
6034 		/* avivo cursor are offset into the total surface */
6035 		x += crtc->primary->state->src_x >> 16;
6036 		y += crtc->primary->state->src_y >> 16;
6037 	}
6038 
6039 	if (x < 0) {
6040 		xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
6041 		x = 0;
6042 	}
6043 	if (y < 0) {
6044 		yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
6045 		y = 0;
6046 	}
6047 	position->enable = true;
6048 	position->x = x;
6049 	position->y = y;
6050 	position->x_hotspot = xorigin;
6051 	position->y_hotspot = yorigin;
6052 
6053 	return 0;
6054 }
6055 
6056 static void handle_cursor_update(struct drm_plane *plane,
6057 				 struct drm_plane_state *old_plane_state)
6058 {
6059 	struct amdgpu_device *adev = plane->dev->dev_private;
6060 	struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
6061 	struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
6062 	struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
6063 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
6064 	uint64_t address = afb ? afb->address : 0;
6065 	struct dc_cursor_position position;
6066 	struct dc_cursor_attributes attributes;
6067 	int ret;
6068 
6069 	if (!plane->state->fb && !old_plane_state->fb)
6070 		return;
6071 
6072 	DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
6073 			 __func__,
6074 			 amdgpu_crtc->crtc_id,
6075 			 plane->state->crtc_w,
6076 			 plane->state->crtc_h);
6077 
6078 	ret = get_cursor_position(plane, crtc, &position);
6079 	if (ret)
6080 		return;
6081 
6082 	if (!position.enable) {
6083 		/* turn off cursor */
6084 		if (crtc_state && crtc_state->stream) {
6085 			mutex_lock(&adev->dm.dc_lock);
6086 			dc_stream_set_cursor_position(crtc_state->stream,
6087 						      &position);
6088 			mutex_unlock(&adev->dm.dc_lock);
6089 		}
6090 		return;
6091 	}
6092 
6093 	amdgpu_crtc->cursor_width = plane->state->crtc_w;
6094 	amdgpu_crtc->cursor_height = plane->state->crtc_h;
6095 
6096 	memset(&attributes, 0, sizeof(attributes));
6097 	attributes.address.high_part = upper_32_bits(address);
6098 	attributes.address.low_part  = lower_32_bits(address);
6099 	attributes.width             = plane->state->crtc_w;
6100 	attributes.height            = plane->state->crtc_h;
6101 	attributes.color_format      = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
6102 	attributes.rotation_angle    = 0;
6103 	attributes.attribute_flags.value = 0;
6104 
6105 	attributes.pitch = attributes.width;
6106 
6107 	if (crtc_state->stream) {
6108 		mutex_lock(&adev->dm.dc_lock);
6109 		if (!dc_stream_set_cursor_attributes(crtc_state->stream,
6110 							 &attributes))
6111 			DRM_ERROR("DC failed to set cursor attributes\n");
6112 
6113 		if (!dc_stream_set_cursor_position(crtc_state->stream,
6114 						   &position))
6115 			DRM_ERROR("DC failed to set cursor position\n");
6116 		mutex_unlock(&adev->dm.dc_lock);
6117 	}
6118 }
6119 
6120 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
6121 {
6122 
6123 	assert_spin_locked(&acrtc->base.dev->event_lock);
6124 	WARN_ON(acrtc->event);
6125 
6126 	acrtc->event = acrtc->base.state->event;
6127 
6128 	/* Set the flip status */
6129 	acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
6130 
6131 	/* Mark this event as consumed */
6132 	acrtc->base.state->event = NULL;
6133 
6134 	DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
6135 						 acrtc->crtc_id);
6136 }
6137 
6138 static void update_freesync_state_on_stream(
6139 	struct amdgpu_display_manager *dm,
6140 	struct dm_crtc_state *new_crtc_state,
6141 	struct dc_stream_state *new_stream,
6142 	struct dc_plane_state *surface,
6143 	u32 flip_timestamp_in_us)
6144 {
6145 	struct mod_vrr_params vrr_params;
6146 	struct dc_info_packet vrr_infopacket = {0};
6147 	struct amdgpu_device *adev = dm->adev;
6148 	unsigned long flags;
6149 
6150 	if (!new_stream)
6151 		return;
6152 
6153 	/*
6154 	 * TODO: Determine why min/max totals and vrefresh can be 0 here.
6155 	 * For now it's sufficient to just guard against these conditions.
6156 	 */
6157 
6158 	if (!new_stream->timing.h_total || !new_stream->timing.v_total)
6159 		return;
6160 
6161 	spin_lock_irqsave(&adev->ddev->event_lock, flags);
6162 	vrr_params = new_crtc_state->vrr_params;
6163 
6164 	if (surface) {
6165 		mod_freesync_handle_preflip(
6166 			dm->freesync_module,
6167 			surface,
6168 			new_stream,
6169 			flip_timestamp_in_us,
6170 			&vrr_params);
6171 
6172 		if (adev->family < AMDGPU_FAMILY_AI &&
6173 		    amdgpu_dm_vrr_active(new_crtc_state)) {
6174 			mod_freesync_handle_v_update(dm->freesync_module,
6175 						     new_stream, &vrr_params);
6176 
6177 			/* Need to call this before the frame ends. */
6178 			dc_stream_adjust_vmin_vmax(dm->dc,
6179 						   new_crtc_state->stream,
6180 						   &vrr_params.adjust);
6181 		}
6182 	}
6183 
6184 	mod_freesync_build_vrr_infopacket(
6185 		dm->freesync_module,
6186 		new_stream,
6187 		&vrr_params,
6188 		PACKET_TYPE_VRR,
6189 		TRANSFER_FUNC_UNKNOWN,
6190 		&vrr_infopacket);
6191 
6192 	new_crtc_state->freesync_timing_changed |=
6193 		(memcmp(&new_crtc_state->vrr_params.adjust,
6194 			&vrr_params.adjust,
6195 			sizeof(vrr_params.adjust)) != 0);
6196 
6197 	new_crtc_state->freesync_vrr_info_changed |=
6198 		(memcmp(&new_crtc_state->vrr_infopacket,
6199 			&vrr_infopacket,
6200 			sizeof(vrr_infopacket)) != 0);
6201 
6202 	new_crtc_state->vrr_params = vrr_params;
6203 	new_crtc_state->vrr_infopacket = vrr_infopacket;
6204 
6205 	new_stream->adjust = new_crtc_state->vrr_params.adjust;
6206 	new_stream->vrr_infopacket = vrr_infopacket;
6207 
6208 	if (new_crtc_state->freesync_vrr_info_changed)
6209 		DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
6210 			      new_crtc_state->base.crtc->base.id,
6211 			      (int)new_crtc_state->base.vrr_enabled,
6212 			      (int)vrr_params.state);
6213 
6214 	spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
6215 }
6216 
6217 static void pre_update_freesync_state_on_stream(
6218 	struct amdgpu_display_manager *dm,
6219 	struct dm_crtc_state *new_crtc_state)
6220 {
6221 	struct dc_stream_state *new_stream = new_crtc_state->stream;
6222 	struct mod_vrr_params vrr_params;
6223 	struct mod_freesync_config config = new_crtc_state->freesync_config;
6224 	struct amdgpu_device *adev = dm->adev;
6225 	unsigned long flags;
6226 
6227 	if (!new_stream)
6228 		return;
6229 
6230 	/*
6231 	 * TODO: Determine why min/max totals and vrefresh can be 0 here.
6232 	 * For now it's sufficient to just guard against these conditions.
6233 	 */
6234 	if (!new_stream->timing.h_total || !new_stream->timing.v_total)
6235 		return;
6236 
6237 	spin_lock_irqsave(&adev->ddev->event_lock, flags);
6238 	vrr_params = new_crtc_state->vrr_params;
6239 
6240 	if (new_crtc_state->vrr_supported &&
6241 	    config.min_refresh_in_uhz &&
6242 	    config.max_refresh_in_uhz) {
6243 		config.state = new_crtc_state->base.vrr_enabled ?
6244 			VRR_STATE_ACTIVE_VARIABLE :
6245 			VRR_STATE_INACTIVE;
6246 	} else {
6247 		config.state = VRR_STATE_UNSUPPORTED;
6248 	}
6249 
6250 	mod_freesync_build_vrr_params(dm->freesync_module,
6251 				      new_stream,
6252 				      &config, &vrr_params);
6253 
6254 	new_crtc_state->freesync_timing_changed |=
6255 		(memcmp(&new_crtc_state->vrr_params.adjust,
6256 			&vrr_params.adjust,
6257 			sizeof(vrr_params.adjust)) != 0);
6258 
6259 	new_crtc_state->vrr_params = vrr_params;
6260 	spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
6261 }
6262 
6263 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
6264 					    struct dm_crtc_state *new_state)
6265 {
6266 	bool old_vrr_active = amdgpu_dm_vrr_active(old_state);
6267 	bool new_vrr_active = amdgpu_dm_vrr_active(new_state);
6268 
6269 	if (!old_vrr_active && new_vrr_active) {
6270 		/* Transition VRR inactive -> active:
6271 		 * While VRR is active, we must not disable vblank irq, as a
6272 		 * reenable after disable would compute bogus vblank/pflip
6273 		 * timestamps if it likely happened inside display front-porch.
6274 		 *
6275 		 * We also need vupdate irq for the actual core vblank handling
6276 		 * at end of vblank.
6277 		 */
6278 		dm_set_vupdate_irq(new_state->base.crtc, true);
6279 		drm_crtc_vblank_get(new_state->base.crtc);
6280 		DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
6281 				 __func__, new_state->base.crtc->base.id);
6282 	} else if (old_vrr_active && !new_vrr_active) {
6283 		/* Transition VRR active -> inactive:
6284 		 * Allow vblank irq disable again for fixed refresh rate.
6285 		 */
6286 		dm_set_vupdate_irq(new_state->base.crtc, false);
6287 		drm_crtc_vblank_put(new_state->base.crtc);
6288 		DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
6289 				 __func__, new_state->base.crtc->base.id);
6290 	}
6291 }
6292 
6293 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
6294 {
6295 	struct drm_plane *plane;
6296 	struct drm_plane_state *old_plane_state, *new_plane_state;
6297 	int i;
6298 
6299 	/*
6300 	 * TODO: Make this per-stream so we don't issue redundant updates for
6301 	 * commits with multiple streams.
6302 	 */
6303 	for_each_oldnew_plane_in_state(state, plane, old_plane_state,
6304 				       new_plane_state, i)
6305 		if (plane->type == DRM_PLANE_TYPE_CURSOR)
6306 			handle_cursor_update(plane, old_plane_state);
6307 }
6308 
6309 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
6310 				    struct dc_state *dc_state,
6311 				    struct drm_device *dev,
6312 				    struct amdgpu_display_manager *dm,
6313 				    struct drm_crtc *pcrtc,
6314 				    bool wait_for_vblank)
6315 {
6316 	uint32_t i;
6317 	uint64_t timestamp_ns;
6318 	struct drm_plane *plane;
6319 	struct drm_plane_state *old_plane_state, *new_plane_state;
6320 	struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
6321 	struct drm_crtc_state *new_pcrtc_state =
6322 			drm_atomic_get_new_crtc_state(state, pcrtc);
6323 	struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
6324 	struct dm_crtc_state *dm_old_crtc_state =
6325 			to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
6326 	int planes_count = 0, vpos, hpos;
6327 	long r;
6328 	unsigned long flags;
6329 	struct amdgpu_bo *abo;
6330 	uint64_t tiling_flags;
6331 	uint32_t target_vblank, last_flip_vblank;
6332 	bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
6333 	bool pflip_present = false;
6334 	bool swizzle = true;
6335 	struct {
6336 		struct dc_surface_update surface_updates[MAX_SURFACES];
6337 		struct dc_plane_info plane_infos[MAX_SURFACES];
6338 		struct dc_scaling_info scaling_infos[MAX_SURFACES];
6339 		struct dc_flip_addrs flip_addrs[MAX_SURFACES];
6340 		struct dc_stream_update stream_update;
6341 	} *bundle;
6342 
6343 	bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
6344 
6345 	if (!bundle) {
6346 		dm_error("Failed to allocate update bundle\n");
6347 		goto cleanup;
6348 	}
6349 
6350 	/*
6351 	 * Disable the cursor first if we're disabling all the planes.
6352 	 * It'll remain on the screen after the planes are re-enabled
6353 	 * if we don't.
6354 	 */
6355 	if (acrtc_state->active_planes == 0)
6356 		amdgpu_dm_commit_cursors(state);
6357 
6358 	/* update planes when needed */
6359 	for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
6360 		struct drm_crtc *crtc = new_plane_state->crtc;
6361 		struct drm_crtc_state *new_crtc_state;
6362 		struct drm_framebuffer *fb = new_plane_state->fb;
6363 		bool plane_needs_flip;
6364 		struct dc_plane_state *dc_plane;
6365 		struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
6366 
6367 		/* Cursor plane is handled after stream updates */
6368 		if (plane->type == DRM_PLANE_TYPE_CURSOR)
6369 			continue;
6370 
6371 		if (!fb || !crtc || pcrtc != crtc)
6372 			continue;
6373 
6374 		new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
6375 		if (!new_crtc_state->active)
6376 			continue;
6377 
6378 		dc_plane = dm_new_plane_state->dc_state;
6379 
6380 		if (dc_plane && !dc_plane->tiling_info.gfx9.swizzle)
6381 			swizzle = false;
6382 
6383 		bundle->surface_updates[planes_count].surface = dc_plane;
6384 		if (new_pcrtc_state->color_mgmt_changed) {
6385 			bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
6386 			bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
6387 		}
6388 
6389 		fill_dc_scaling_info(new_plane_state,
6390 				     &bundle->scaling_infos[planes_count]);
6391 
6392 		bundle->surface_updates[planes_count].scaling_info =
6393 			&bundle->scaling_infos[planes_count];
6394 
6395 		plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
6396 
6397 		pflip_present = pflip_present || plane_needs_flip;
6398 
6399 		if (!plane_needs_flip) {
6400 			planes_count += 1;
6401 			continue;
6402 		}
6403 
6404 		abo = gem_to_amdgpu_bo(fb->obj[0]);
6405 
6406 		/*
6407 		 * Wait for all fences on this FB. Do limited wait to avoid
6408 		 * deadlock during GPU reset when this fence will not signal
6409 		 * but we hold reservation lock for the BO.
6410 		 */
6411 		r = dma_resv_wait_timeout_rcu(abo->tbo.base.resv, true,
6412 							false,
6413 							msecs_to_jiffies(5000));
6414 		if (unlikely(r <= 0))
6415 			DRM_ERROR("Waiting for fences timed out!");
6416 
6417 		/*
6418 		 * TODO This might fail and hence better not used, wait
6419 		 * explicitly on fences instead
6420 		 * and in general should be called for
6421 		 * blocking commit to as per framework helpers
6422 		 */
6423 		r = amdgpu_bo_reserve(abo, true);
6424 		if (unlikely(r != 0))
6425 			DRM_ERROR("failed to reserve buffer before flip\n");
6426 
6427 		amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
6428 
6429 		amdgpu_bo_unreserve(abo);
6430 
6431 		fill_dc_plane_info_and_addr(
6432 			dm->adev, new_plane_state, tiling_flags,
6433 			&bundle->plane_infos[planes_count],
6434 			&bundle->flip_addrs[planes_count].address);
6435 
6436 		bundle->surface_updates[planes_count].plane_info =
6437 			&bundle->plane_infos[planes_count];
6438 
6439 		/*
6440 		 * Only allow immediate flips for fast updates that don't
6441 		 * change FB pitch, DCC state, rotation or mirroing.
6442 		 */
6443 		bundle->flip_addrs[planes_count].flip_immediate =
6444 			crtc->state->async_flip &&
6445 			acrtc_state->update_type == UPDATE_TYPE_FAST;
6446 
6447 		timestamp_ns = ktime_get_ns();
6448 		bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
6449 		bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
6450 		bundle->surface_updates[planes_count].surface = dc_plane;
6451 
6452 		if (!bundle->surface_updates[planes_count].surface) {
6453 			DRM_ERROR("No surface for CRTC: id=%d\n",
6454 					acrtc_attach->crtc_id);
6455 			continue;
6456 		}
6457 
6458 		if (plane == pcrtc->primary)
6459 			update_freesync_state_on_stream(
6460 				dm,
6461 				acrtc_state,
6462 				acrtc_state->stream,
6463 				dc_plane,
6464 				bundle->flip_addrs[planes_count].flip_timestamp_in_us);
6465 
6466 		DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x\n",
6467 				 __func__,
6468 				 bundle->flip_addrs[planes_count].address.grph.addr.high_part,
6469 				 bundle->flip_addrs[planes_count].address.grph.addr.low_part);
6470 
6471 		planes_count += 1;
6472 
6473 	}
6474 
6475 	if (pflip_present) {
6476 		if (!vrr_active) {
6477 			/* Use old throttling in non-vrr fixed refresh rate mode
6478 			 * to keep flip scheduling based on target vblank counts
6479 			 * working in a backwards compatible way, e.g., for
6480 			 * clients using the GLX_OML_sync_control extension or
6481 			 * DRI3/Present extension with defined target_msc.
6482 			 */
6483 			last_flip_vblank = amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id);
6484 		}
6485 		else {
6486 			/* For variable refresh rate mode only:
6487 			 * Get vblank of last completed flip to avoid > 1 vrr
6488 			 * flips per video frame by use of throttling, but allow
6489 			 * flip programming anywhere in the possibly large
6490 			 * variable vrr vblank interval for fine-grained flip
6491 			 * timing control and more opportunity to avoid stutter
6492 			 * on late submission of flips.
6493 			 */
6494 			spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
6495 			last_flip_vblank = acrtc_attach->last_flip_vblank;
6496 			spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
6497 		}
6498 
6499 		target_vblank = last_flip_vblank + wait_for_vblank;
6500 
6501 		/*
6502 		 * Wait until we're out of the vertical blank period before the one
6503 		 * targeted by the flip
6504 		 */
6505 		while ((acrtc_attach->enabled &&
6506 			(amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
6507 							    0, &vpos, &hpos, NULL,
6508 							    NULL, &pcrtc->hwmode)
6509 			 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
6510 			(DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
6511 			(int)(target_vblank -
6512 			  amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id)) > 0)) {
6513 			usleep_range(1000, 1100);
6514 		}
6515 
6516 		if (acrtc_attach->base.state->event) {
6517 			drm_crtc_vblank_get(pcrtc);
6518 
6519 			spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
6520 
6521 			WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
6522 			prepare_flip_isr(acrtc_attach);
6523 
6524 			spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
6525 		}
6526 
6527 		if (acrtc_state->stream) {
6528 			if (acrtc_state->freesync_vrr_info_changed)
6529 				bundle->stream_update.vrr_infopacket =
6530 					&acrtc_state->stream->vrr_infopacket;
6531 		}
6532 	}
6533 
6534 	/* Update the planes if changed or disable if we don't have any. */
6535 	if ((planes_count || acrtc_state->active_planes == 0) &&
6536 		acrtc_state->stream) {
6537 		bundle->stream_update.stream = acrtc_state->stream;
6538 		if (new_pcrtc_state->mode_changed) {
6539 			bundle->stream_update.src = acrtc_state->stream->src;
6540 			bundle->stream_update.dst = acrtc_state->stream->dst;
6541 		}
6542 
6543 		if (new_pcrtc_state->color_mgmt_changed) {
6544 			/*
6545 			 * TODO: This isn't fully correct since we've actually
6546 			 * already modified the stream in place.
6547 			 */
6548 			bundle->stream_update.gamut_remap =
6549 				&acrtc_state->stream->gamut_remap_matrix;
6550 			bundle->stream_update.output_csc_transform =
6551 				&acrtc_state->stream->csc_color_matrix;
6552 			bundle->stream_update.out_transfer_func =
6553 				acrtc_state->stream->out_transfer_func;
6554 		}
6555 
6556 		acrtc_state->stream->abm_level = acrtc_state->abm_level;
6557 		if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
6558 			bundle->stream_update.abm_level = &acrtc_state->abm_level;
6559 
6560 		/*
6561 		 * If FreeSync state on the stream has changed then we need to
6562 		 * re-adjust the min/max bounds now that DC doesn't handle this
6563 		 * as part of commit.
6564 		 */
6565 		if (amdgpu_dm_vrr_active(dm_old_crtc_state) !=
6566 		    amdgpu_dm_vrr_active(acrtc_state)) {
6567 			spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
6568 			dc_stream_adjust_vmin_vmax(
6569 				dm->dc, acrtc_state->stream,
6570 				&acrtc_state->vrr_params.adjust);
6571 			spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
6572 		}
6573 		mutex_lock(&dm->dc_lock);
6574 		if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
6575 				acrtc_state->stream->link->psr_allow_active)
6576 			amdgpu_dm_psr_disable(acrtc_state->stream);
6577 
6578 		dc_commit_updates_for_stream(dm->dc,
6579 						     bundle->surface_updates,
6580 						     planes_count,
6581 						     acrtc_state->stream,
6582 						     &bundle->stream_update,
6583 						     dc_state);
6584 
6585 		if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
6586 						acrtc_state->stream->psr_version &&
6587 						!acrtc_state->stream->link->psr_feature_enabled)
6588 			amdgpu_dm_link_setup_psr(acrtc_state->stream);
6589 		else if ((acrtc_state->update_type == UPDATE_TYPE_FAST) &&
6590 						acrtc_state->stream->link->psr_feature_enabled &&
6591 						!acrtc_state->stream->link->psr_allow_active &&
6592 						swizzle) {
6593 			amdgpu_dm_psr_enable(acrtc_state->stream);
6594 		}
6595 
6596 		mutex_unlock(&dm->dc_lock);
6597 	}
6598 
6599 	/*
6600 	 * Update cursor state *after* programming all the planes.
6601 	 * This avoids redundant programming in the case where we're going
6602 	 * to be disabling a single plane - those pipes are being disabled.
6603 	 */
6604 	if (acrtc_state->active_planes)
6605 		amdgpu_dm_commit_cursors(state);
6606 
6607 cleanup:
6608 	kfree(bundle);
6609 }
6610 
6611 static void amdgpu_dm_commit_audio(struct drm_device *dev,
6612 				   struct drm_atomic_state *state)
6613 {
6614 	struct amdgpu_device *adev = dev->dev_private;
6615 	struct amdgpu_dm_connector *aconnector;
6616 	struct drm_connector *connector;
6617 	struct drm_connector_state *old_con_state, *new_con_state;
6618 	struct drm_crtc_state *new_crtc_state;
6619 	struct dm_crtc_state *new_dm_crtc_state;
6620 	const struct dc_stream_status *status;
6621 	int i, inst;
6622 
6623 	/* Notify device removals. */
6624 	for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
6625 		if (old_con_state->crtc != new_con_state->crtc) {
6626 			/* CRTC changes require notification. */
6627 			goto notify;
6628 		}
6629 
6630 		if (!new_con_state->crtc)
6631 			continue;
6632 
6633 		new_crtc_state = drm_atomic_get_new_crtc_state(
6634 			state, new_con_state->crtc);
6635 
6636 		if (!new_crtc_state)
6637 			continue;
6638 
6639 		if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
6640 			continue;
6641 
6642 	notify:
6643 		aconnector = to_amdgpu_dm_connector(connector);
6644 
6645 		mutex_lock(&adev->dm.audio_lock);
6646 		inst = aconnector->audio_inst;
6647 		aconnector->audio_inst = -1;
6648 		mutex_unlock(&adev->dm.audio_lock);
6649 
6650 		amdgpu_dm_audio_eld_notify(adev, inst);
6651 	}
6652 
6653 	/* Notify audio device additions. */
6654 	for_each_new_connector_in_state(state, connector, new_con_state, i) {
6655 		if (!new_con_state->crtc)
6656 			continue;
6657 
6658 		new_crtc_state = drm_atomic_get_new_crtc_state(
6659 			state, new_con_state->crtc);
6660 
6661 		if (!new_crtc_state)
6662 			continue;
6663 
6664 		if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
6665 			continue;
6666 
6667 		new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
6668 		if (!new_dm_crtc_state->stream)
6669 			continue;
6670 
6671 		status = dc_stream_get_status(new_dm_crtc_state->stream);
6672 		if (!status)
6673 			continue;
6674 
6675 		aconnector = to_amdgpu_dm_connector(connector);
6676 
6677 		mutex_lock(&adev->dm.audio_lock);
6678 		inst = status->audio_inst;
6679 		aconnector->audio_inst = inst;
6680 		mutex_unlock(&adev->dm.audio_lock);
6681 
6682 		amdgpu_dm_audio_eld_notify(adev, inst);
6683 	}
6684 }
6685 
6686 /*
6687  * Enable interrupts on CRTCs that are newly active, undergone
6688  * a modeset, or have active planes again.
6689  *
6690  * Done in two passes, based on the for_modeset flag:
6691  * Pass 1: For CRTCs going through modeset
6692  * Pass 2: For CRTCs going from 0 to n active planes
6693  *
6694  * Interrupts can only be enabled after the planes are programmed,
6695  * so this requires a two-pass approach since we don't want to
6696  * just defer the interrupts until after commit planes every time.
6697  */
6698 static void amdgpu_dm_enable_crtc_interrupts(struct drm_device *dev,
6699 					     struct drm_atomic_state *state,
6700 					     bool for_modeset)
6701 {
6702 	struct amdgpu_device *adev = dev->dev_private;
6703 	struct drm_crtc *crtc;
6704 	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
6705 	int i;
6706 #ifdef CONFIG_DEBUG_FS
6707 	enum amdgpu_dm_pipe_crc_source source;
6708 #endif
6709 
6710 	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
6711 				      new_crtc_state, i) {
6712 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
6713 		struct dm_crtc_state *dm_new_crtc_state =
6714 			to_dm_crtc_state(new_crtc_state);
6715 		struct dm_crtc_state *dm_old_crtc_state =
6716 			to_dm_crtc_state(old_crtc_state);
6717 		bool modeset = drm_atomic_crtc_needs_modeset(new_crtc_state);
6718 		bool run_pass;
6719 
6720 		run_pass = (for_modeset && modeset) ||
6721 			   (!for_modeset && !modeset &&
6722 			    !dm_old_crtc_state->interrupts_enabled);
6723 
6724 		if (!run_pass)
6725 			continue;
6726 
6727 		if (!dm_new_crtc_state->interrupts_enabled)
6728 			continue;
6729 
6730 		manage_dm_interrupts(adev, acrtc, true);
6731 
6732 #ifdef CONFIG_DEBUG_FS
6733 		/* The stream has changed so CRC capture needs to re-enabled. */
6734 		source = dm_new_crtc_state->crc_src;
6735 		if (amdgpu_dm_is_valid_crc_source(source)) {
6736 			amdgpu_dm_crtc_configure_crc_source(
6737 				crtc, dm_new_crtc_state,
6738 				dm_new_crtc_state->crc_src);
6739 		}
6740 #endif
6741 	}
6742 }
6743 
6744 /*
6745  * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
6746  * @crtc_state: the DRM CRTC state
6747  * @stream_state: the DC stream state.
6748  *
6749  * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
6750  * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
6751  */
6752 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
6753 						struct dc_stream_state *stream_state)
6754 {
6755 	stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
6756 }
6757 
6758 static int amdgpu_dm_atomic_commit(struct drm_device *dev,
6759 				   struct drm_atomic_state *state,
6760 				   bool nonblock)
6761 {
6762 	struct drm_crtc *crtc;
6763 	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
6764 	struct amdgpu_device *adev = dev->dev_private;
6765 	int i;
6766 
6767 	/*
6768 	 * We evade vblank and pflip interrupts on CRTCs that are undergoing
6769 	 * a modeset, being disabled, or have no active planes.
6770 	 *
6771 	 * It's done in atomic commit rather than commit tail for now since
6772 	 * some of these interrupt handlers access the current CRTC state and
6773 	 * potentially the stream pointer itself.
6774 	 *
6775 	 * Since the atomic state is swapped within atomic commit and not within
6776 	 * commit tail this would leave to new state (that hasn't been committed yet)
6777 	 * being accesssed from within the handlers.
6778 	 *
6779 	 * TODO: Fix this so we can do this in commit tail and not have to block
6780 	 * in atomic check.
6781 	 */
6782 	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6783 		struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
6784 		struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6785 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
6786 
6787 		if (dm_old_crtc_state->interrupts_enabled &&
6788 		    (!dm_new_crtc_state->interrupts_enabled ||
6789 		     drm_atomic_crtc_needs_modeset(new_crtc_state)))
6790 			manage_dm_interrupts(adev, acrtc, false);
6791 	}
6792 	/*
6793 	 * Add check here for SoC's that support hardware cursor plane, to
6794 	 * unset legacy_cursor_update
6795 	 */
6796 
6797 	return drm_atomic_helper_commit(dev, state, nonblock);
6798 
6799 	/*TODO Handle EINTR, reenable IRQ*/
6800 }
6801 
6802 /**
6803  * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
6804  * @state: The atomic state to commit
6805  *
6806  * This will tell DC to commit the constructed DC state from atomic_check,
6807  * programming the hardware. Any failures here implies a hardware failure, since
6808  * atomic check should have filtered anything non-kosher.
6809  */
6810 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
6811 {
6812 	struct drm_device *dev = state->dev;
6813 	struct amdgpu_device *adev = dev->dev_private;
6814 	struct amdgpu_display_manager *dm = &adev->dm;
6815 	struct dm_atomic_state *dm_state;
6816 	struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
6817 	uint32_t i, j;
6818 	struct drm_crtc *crtc;
6819 	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
6820 	unsigned long flags;
6821 	bool wait_for_vblank = true;
6822 	struct drm_connector *connector;
6823 	struct drm_connector_state *old_con_state, *new_con_state;
6824 	struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
6825 	int crtc_disable_count = 0;
6826 
6827 	drm_atomic_helper_update_legacy_modeset_state(dev, state);
6828 
6829 	dm_state = dm_atomic_get_new_state(state);
6830 	if (dm_state && dm_state->context) {
6831 		dc_state = dm_state->context;
6832 	} else {
6833 		/* No state changes, retain current state. */
6834 		dc_state_temp = dc_create_state(dm->dc);
6835 		ASSERT(dc_state_temp);
6836 		dc_state = dc_state_temp;
6837 		dc_resource_state_copy_construct_current(dm->dc, dc_state);
6838 	}
6839 
6840 	/* update changed items */
6841 	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6842 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
6843 
6844 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6845 		dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
6846 
6847 		DRM_DEBUG_DRIVER(
6848 			"amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
6849 			"planes_changed:%d, mode_changed:%d,active_changed:%d,"
6850 			"connectors_changed:%d\n",
6851 			acrtc->crtc_id,
6852 			new_crtc_state->enable,
6853 			new_crtc_state->active,
6854 			new_crtc_state->planes_changed,
6855 			new_crtc_state->mode_changed,
6856 			new_crtc_state->active_changed,
6857 			new_crtc_state->connectors_changed);
6858 
6859 		/* Copy all transient state flags into dc state */
6860 		if (dm_new_crtc_state->stream) {
6861 			amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
6862 							    dm_new_crtc_state->stream);
6863 		}
6864 
6865 		/* handles headless hotplug case, updating new_state and
6866 		 * aconnector as needed
6867 		 */
6868 
6869 		if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
6870 
6871 			DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
6872 
6873 			if (!dm_new_crtc_state->stream) {
6874 				/*
6875 				 * this could happen because of issues with
6876 				 * userspace notifications delivery.
6877 				 * In this case userspace tries to set mode on
6878 				 * display which is disconnected in fact.
6879 				 * dc_sink is NULL in this case on aconnector.
6880 				 * We expect reset mode will come soon.
6881 				 *
6882 				 * This can also happen when unplug is done
6883 				 * during resume sequence ended
6884 				 *
6885 				 * In this case, we want to pretend we still
6886 				 * have a sink to keep the pipe running so that
6887 				 * hw state is consistent with the sw state
6888 				 */
6889 				DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
6890 						__func__, acrtc->base.base.id);
6891 				continue;
6892 			}
6893 
6894 			if (dm_old_crtc_state->stream)
6895 				remove_stream(adev, acrtc, dm_old_crtc_state->stream);
6896 
6897 			pm_runtime_get_noresume(dev->dev);
6898 
6899 			acrtc->enabled = true;
6900 			acrtc->hw_mode = new_crtc_state->mode;
6901 			crtc->hwmode = new_crtc_state->mode;
6902 		} else if (modereset_required(new_crtc_state)) {
6903 			DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
6904 			/* i.e. reset mode */
6905 			if (dm_old_crtc_state->stream) {
6906 				if (dm_old_crtc_state->stream->link->psr_allow_active)
6907 					amdgpu_dm_psr_disable(dm_old_crtc_state->stream);
6908 
6909 				remove_stream(adev, acrtc, dm_old_crtc_state->stream);
6910 			}
6911 		}
6912 	} /* for_each_crtc_in_state() */
6913 
6914 	if (dc_state) {
6915 		dm_enable_per_frame_crtc_master_sync(dc_state);
6916 		mutex_lock(&dm->dc_lock);
6917 		WARN_ON(!dc_commit_state(dm->dc, dc_state));
6918 		mutex_unlock(&dm->dc_lock);
6919 	}
6920 
6921 	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
6922 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
6923 
6924 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6925 
6926 		if (dm_new_crtc_state->stream != NULL) {
6927 			const struct dc_stream_status *status =
6928 					dc_stream_get_status(dm_new_crtc_state->stream);
6929 
6930 			if (!status)
6931 				status = dc_stream_get_status_from_state(dc_state,
6932 									 dm_new_crtc_state->stream);
6933 
6934 			if (!status)
6935 				DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
6936 			else
6937 				acrtc->otg_inst = status->primary_otg_inst;
6938 		}
6939 	}
6940 #ifdef CONFIG_DRM_AMD_DC_HDCP
6941 	for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
6942 		struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
6943 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
6944 		struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6945 
6946 		new_crtc_state = NULL;
6947 
6948 		if (acrtc)
6949 			new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
6950 
6951 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6952 
6953 		if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
6954 		    connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
6955 			hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
6956 			new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
6957 			continue;
6958 		}
6959 
6960 		if (is_content_protection_different(new_con_state, old_con_state, connector, adev->dm.hdcp_workqueue))
6961 			hdcp_update_display(
6962 				adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
6963 				new_con_state->hdcp_content_type,
6964 				new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED ? true
6965 													 : false);
6966 	}
6967 #endif
6968 
6969 	/* Handle connector state changes */
6970 	for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
6971 		struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
6972 		struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
6973 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
6974 		struct dc_surface_update dummy_updates[MAX_SURFACES];
6975 		struct dc_stream_update stream_update;
6976 		struct dc_info_packet hdr_packet;
6977 		struct dc_stream_status *status = NULL;
6978 		bool abm_changed, hdr_changed, scaling_changed;
6979 
6980 		memset(&dummy_updates, 0, sizeof(dummy_updates));
6981 		memset(&stream_update, 0, sizeof(stream_update));
6982 
6983 		if (acrtc) {
6984 			new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
6985 			old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
6986 		}
6987 
6988 		/* Skip any modesets/resets */
6989 		if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
6990 			continue;
6991 
6992 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6993 		dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
6994 
6995 		scaling_changed = is_scaling_state_different(dm_new_con_state,
6996 							     dm_old_con_state);
6997 
6998 		abm_changed = dm_new_crtc_state->abm_level !=
6999 			      dm_old_crtc_state->abm_level;
7000 
7001 		hdr_changed =
7002 			is_hdr_metadata_different(old_con_state, new_con_state);
7003 
7004 		if (!scaling_changed && !abm_changed && !hdr_changed)
7005 			continue;
7006 
7007 		stream_update.stream = dm_new_crtc_state->stream;
7008 		if (scaling_changed) {
7009 			update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
7010 					dm_new_con_state, dm_new_crtc_state->stream);
7011 
7012 			stream_update.src = dm_new_crtc_state->stream->src;
7013 			stream_update.dst = dm_new_crtc_state->stream->dst;
7014 		}
7015 
7016 		if (abm_changed) {
7017 			dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
7018 
7019 			stream_update.abm_level = &dm_new_crtc_state->abm_level;
7020 		}
7021 
7022 		if (hdr_changed) {
7023 			fill_hdr_info_packet(new_con_state, &hdr_packet);
7024 			stream_update.hdr_static_metadata = &hdr_packet;
7025 		}
7026 
7027 		status = dc_stream_get_status(dm_new_crtc_state->stream);
7028 		WARN_ON(!status);
7029 		WARN_ON(!status->plane_count);
7030 
7031 		/*
7032 		 * TODO: DC refuses to perform stream updates without a dc_surface_update.
7033 		 * Here we create an empty update on each plane.
7034 		 * To fix this, DC should permit updating only stream properties.
7035 		 */
7036 		for (j = 0; j < status->plane_count; j++)
7037 			dummy_updates[j].surface = status->plane_states[0];
7038 
7039 
7040 		mutex_lock(&dm->dc_lock);
7041 		dc_commit_updates_for_stream(dm->dc,
7042 						     dummy_updates,
7043 						     status->plane_count,
7044 						     dm_new_crtc_state->stream,
7045 						     &stream_update,
7046 						     dc_state);
7047 		mutex_unlock(&dm->dc_lock);
7048 	}
7049 
7050 	/* Count number of newly disabled CRTCs for dropping PM refs later. */
7051 	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
7052 				      new_crtc_state, i) {
7053 		if (old_crtc_state->active && !new_crtc_state->active)
7054 			crtc_disable_count++;
7055 
7056 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
7057 		dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
7058 
7059 		/* Update freesync active state. */
7060 		pre_update_freesync_state_on_stream(dm, dm_new_crtc_state);
7061 
7062 		/* Handle vrr on->off / off->on transitions */
7063 		amdgpu_dm_handle_vrr_transition(dm_old_crtc_state,
7064 						dm_new_crtc_state);
7065 	}
7066 
7067 	/* Enable interrupts for CRTCs going through a modeset. */
7068 	amdgpu_dm_enable_crtc_interrupts(dev, state, true);
7069 
7070 	for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
7071 		if (new_crtc_state->async_flip)
7072 			wait_for_vblank = false;
7073 
7074 	/* update planes when needed per crtc*/
7075 	for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
7076 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
7077 
7078 		if (dm_new_crtc_state->stream)
7079 			amdgpu_dm_commit_planes(state, dc_state, dev,
7080 						dm, crtc, wait_for_vblank);
7081 	}
7082 
7083 	/* Enable interrupts for CRTCs going from 0 to n active planes. */
7084 	amdgpu_dm_enable_crtc_interrupts(dev, state, false);
7085 
7086 	/* Update audio instances for each connector. */
7087 	amdgpu_dm_commit_audio(dev, state);
7088 
7089 	/*
7090 	 * send vblank event on all events not handled in flip and
7091 	 * mark consumed event for drm_atomic_helper_commit_hw_done
7092 	 */
7093 	spin_lock_irqsave(&adev->ddev->event_lock, flags);
7094 	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
7095 
7096 		if (new_crtc_state->event)
7097 			drm_send_event_locked(dev, &new_crtc_state->event->base);
7098 
7099 		new_crtc_state->event = NULL;
7100 	}
7101 	spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
7102 
7103 	/* Signal HW programming completion */
7104 	drm_atomic_helper_commit_hw_done(state);
7105 
7106 	if (wait_for_vblank)
7107 		drm_atomic_helper_wait_for_flip_done(dev, state);
7108 
7109 	drm_atomic_helper_cleanup_planes(dev, state);
7110 
7111 	/*
7112 	 * Finally, drop a runtime PM reference for each newly disabled CRTC,
7113 	 * so we can put the GPU into runtime suspend if we're not driving any
7114 	 * displays anymore
7115 	 */
7116 	for (i = 0; i < crtc_disable_count; i++)
7117 		pm_runtime_put_autosuspend(dev->dev);
7118 	pm_runtime_mark_last_busy(dev->dev);
7119 
7120 	if (dc_state_temp)
7121 		dc_release_state(dc_state_temp);
7122 }
7123 
7124 
7125 static int dm_force_atomic_commit(struct drm_connector *connector)
7126 {
7127 	int ret = 0;
7128 	struct drm_device *ddev = connector->dev;
7129 	struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
7130 	struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
7131 	struct drm_plane *plane = disconnected_acrtc->base.primary;
7132 	struct drm_connector_state *conn_state;
7133 	struct drm_crtc_state *crtc_state;
7134 	struct drm_plane_state *plane_state;
7135 
7136 	if (!state)
7137 		return -ENOMEM;
7138 
7139 	state->acquire_ctx = ddev->mode_config.acquire_ctx;
7140 
7141 	/* Construct an atomic state to restore previous display setting */
7142 
7143 	/*
7144 	 * Attach connectors to drm_atomic_state
7145 	 */
7146 	conn_state = drm_atomic_get_connector_state(state, connector);
7147 
7148 	ret = PTR_ERR_OR_ZERO(conn_state);
7149 	if (ret)
7150 		goto err;
7151 
7152 	/* Attach crtc to drm_atomic_state*/
7153 	crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
7154 
7155 	ret = PTR_ERR_OR_ZERO(crtc_state);
7156 	if (ret)
7157 		goto err;
7158 
7159 	/* force a restore */
7160 	crtc_state->mode_changed = true;
7161 
7162 	/* Attach plane to drm_atomic_state */
7163 	plane_state = drm_atomic_get_plane_state(state, plane);
7164 
7165 	ret = PTR_ERR_OR_ZERO(plane_state);
7166 	if (ret)
7167 		goto err;
7168 
7169 
7170 	/* Call commit internally with the state we just constructed */
7171 	ret = drm_atomic_commit(state);
7172 	if (!ret)
7173 		return 0;
7174 
7175 err:
7176 	DRM_ERROR("Restoring old state failed with %i\n", ret);
7177 	drm_atomic_state_put(state);
7178 
7179 	return ret;
7180 }
7181 
7182 /*
7183  * This function handles all cases when set mode does not come upon hotplug.
7184  * This includes when a display is unplugged then plugged back into the
7185  * same port and when running without usermode desktop manager supprot
7186  */
7187 void dm_restore_drm_connector_state(struct drm_device *dev,
7188 				    struct drm_connector *connector)
7189 {
7190 	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7191 	struct amdgpu_crtc *disconnected_acrtc;
7192 	struct dm_crtc_state *acrtc_state;
7193 
7194 	if (!aconnector->dc_sink || !connector->state || !connector->encoder)
7195 		return;
7196 
7197 	disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
7198 	if (!disconnected_acrtc)
7199 		return;
7200 
7201 	acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
7202 	if (!acrtc_state->stream)
7203 		return;
7204 
7205 	/*
7206 	 * If the previous sink is not released and different from the current,
7207 	 * we deduce we are in a state where we can not rely on usermode call
7208 	 * to turn on the display, so we do it here
7209 	 */
7210 	if (acrtc_state->stream->sink != aconnector->dc_sink)
7211 		dm_force_atomic_commit(&aconnector->base);
7212 }
7213 
7214 /*
7215  * Grabs all modesetting locks to serialize against any blocking commits,
7216  * Waits for completion of all non blocking commits.
7217  */
7218 static int do_aquire_global_lock(struct drm_device *dev,
7219 				 struct drm_atomic_state *state)
7220 {
7221 	struct drm_crtc *crtc;
7222 	struct drm_crtc_commit *commit;
7223 	long ret;
7224 
7225 	/*
7226 	 * Adding all modeset locks to aquire_ctx will
7227 	 * ensure that when the framework release it the
7228 	 * extra locks we are locking here will get released to
7229 	 */
7230 	ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
7231 	if (ret)
7232 		return ret;
7233 
7234 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7235 		spin_lock(&crtc->commit_lock);
7236 		commit = list_first_entry_or_null(&crtc->commit_list,
7237 				struct drm_crtc_commit, commit_entry);
7238 		if (commit)
7239 			drm_crtc_commit_get(commit);
7240 		spin_unlock(&crtc->commit_lock);
7241 
7242 		if (!commit)
7243 			continue;
7244 
7245 		/*
7246 		 * Make sure all pending HW programming completed and
7247 		 * page flips done
7248 		 */
7249 		ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
7250 
7251 		if (ret > 0)
7252 			ret = wait_for_completion_interruptible_timeout(
7253 					&commit->flip_done, 10*HZ);
7254 
7255 		if (ret == 0)
7256 			DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
7257 				  "timed out\n", crtc->base.id, crtc->name);
7258 
7259 		drm_crtc_commit_put(commit);
7260 	}
7261 
7262 	return ret < 0 ? ret : 0;
7263 }
7264 
7265 static void get_freesync_config_for_crtc(
7266 	struct dm_crtc_state *new_crtc_state,
7267 	struct dm_connector_state *new_con_state)
7268 {
7269 	struct mod_freesync_config config = {0};
7270 	struct amdgpu_dm_connector *aconnector =
7271 			to_amdgpu_dm_connector(new_con_state->base.connector);
7272 	struct drm_display_mode *mode = &new_crtc_state->base.mode;
7273 	int vrefresh = drm_mode_vrefresh(mode);
7274 
7275 	new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
7276 					vrefresh >= aconnector->min_vfreq &&
7277 					vrefresh <= aconnector->max_vfreq;
7278 
7279 	if (new_crtc_state->vrr_supported) {
7280 		new_crtc_state->stream->ignore_msa_timing_param = true;
7281 		config.state = new_crtc_state->base.vrr_enabled ?
7282 				VRR_STATE_ACTIVE_VARIABLE :
7283 				VRR_STATE_INACTIVE;
7284 		config.min_refresh_in_uhz =
7285 				aconnector->min_vfreq * 1000000;
7286 		config.max_refresh_in_uhz =
7287 				aconnector->max_vfreq * 1000000;
7288 		config.vsif_supported = true;
7289 		config.btr = true;
7290 	}
7291 
7292 	new_crtc_state->freesync_config = config;
7293 }
7294 
7295 static void reset_freesync_config_for_crtc(
7296 	struct dm_crtc_state *new_crtc_state)
7297 {
7298 	new_crtc_state->vrr_supported = false;
7299 
7300 	memset(&new_crtc_state->vrr_params, 0,
7301 	       sizeof(new_crtc_state->vrr_params));
7302 	memset(&new_crtc_state->vrr_infopacket, 0,
7303 	       sizeof(new_crtc_state->vrr_infopacket));
7304 }
7305 
7306 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
7307 				struct drm_atomic_state *state,
7308 				struct drm_crtc *crtc,
7309 				struct drm_crtc_state *old_crtc_state,
7310 				struct drm_crtc_state *new_crtc_state,
7311 				bool enable,
7312 				bool *lock_and_validation_needed)
7313 {
7314 	struct dm_atomic_state *dm_state = NULL;
7315 	struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
7316 	struct dc_stream_state *new_stream;
7317 	int ret = 0;
7318 
7319 	/*
7320 	 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
7321 	 * update changed items
7322 	 */
7323 	struct amdgpu_crtc *acrtc = NULL;
7324 	struct amdgpu_dm_connector *aconnector = NULL;
7325 	struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
7326 	struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
7327 
7328 	new_stream = NULL;
7329 
7330 	dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
7331 	dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
7332 	acrtc = to_amdgpu_crtc(crtc);
7333 	aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
7334 
7335 	/* TODO This hack should go away */
7336 	if (aconnector && enable) {
7337 		/* Make sure fake sink is created in plug-in scenario */
7338 		drm_new_conn_state = drm_atomic_get_new_connector_state(state,
7339 							    &aconnector->base);
7340 		drm_old_conn_state = drm_atomic_get_old_connector_state(state,
7341 							    &aconnector->base);
7342 
7343 		if (IS_ERR(drm_new_conn_state)) {
7344 			ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
7345 			goto fail;
7346 		}
7347 
7348 		dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
7349 		dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
7350 
7351 		if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
7352 			goto skip_modeset;
7353 
7354 		new_stream = create_stream_for_sink(aconnector,
7355 						     &new_crtc_state->mode,
7356 						    dm_new_conn_state,
7357 						    dm_old_crtc_state->stream);
7358 
7359 		/*
7360 		 * we can have no stream on ACTION_SET if a display
7361 		 * was disconnected during S3, in this case it is not an
7362 		 * error, the OS will be updated after detection, and
7363 		 * will do the right thing on next atomic commit
7364 		 */
7365 
7366 		if (!new_stream) {
7367 			DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
7368 					__func__, acrtc->base.base.id);
7369 			ret = -ENOMEM;
7370 			goto fail;
7371 		}
7372 
7373 		dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
7374 
7375 		ret = fill_hdr_info_packet(drm_new_conn_state,
7376 					   &new_stream->hdr_static_metadata);
7377 		if (ret)
7378 			goto fail;
7379 
7380 		/*
7381 		 * If we already removed the old stream from the context
7382 		 * (and set the new stream to NULL) then we can't reuse
7383 		 * the old stream even if the stream and scaling are unchanged.
7384 		 * We'll hit the BUG_ON and black screen.
7385 		 *
7386 		 * TODO: Refactor this function to allow this check to work
7387 		 * in all conditions.
7388 		 */
7389 		if (dm_new_crtc_state->stream &&
7390 		    dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
7391 		    dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
7392 			new_crtc_state->mode_changed = false;
7393 			DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
7394 					 new_crtc_state->mode_changed);
7395 		}
7396 	}
7397 
7398 	/* mode_changed flag may get updated above, need to check again */
7399 	if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
7400 		goto skip_modeset;
7401 
7402 	DRM_DEBUG_DRIVER(
7403 		"amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
7404 		"planes_changed:%d, mode_changed:%d,active_changed:%d,"
7405 		"connectors_changed:%d\n",
7406 		acrtc->crtc_id,
7407 		new_crtc_state->enable,
7408 		new_crtc_state->active,
7409 		new_crtc_state->planes_changed,
7410 		new_crtc_state->mode_changed,
7411 		new_crtc_state->active_changed,
7412 		new_crtc_state->connectors_changed);
7413 
7414 	/* Remove stream for any changed/disabled CRTC */
7415 	if (!enable) {
7416 
7417 		if (!dm_old_crtc_state->stream)
7418 			goto skip_modeset;
7419 
7420 		ret = dm_atomic_get_state(state, &dm_state);
7421 		if (ret)
7422 			goto fail;
7423 
7424 		DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
7425 				crtc->base.id);
7426 
7427 		/* i.e. reset mode */
7428 		if (dc_remove_stream_from_ctx(
7429 				dm->dc,
7430 				dm_state->context,
7431 				dm_old_crtc_state->stream) != DC_OK) {
7432 			ret = -EINVAL;
7433 			goto fail;
7434 		}
7435 
7436 		dc_stream_release(dm_old_crtc_state->stream);
7437 		dm_new_crtc_state->stream = NULL;
7438 
7439 		reset_freesync_config_for_crtc(dm_new_crtc_state);
7440 
7441 		*lock_and_validation_needed = true;
7442 
7443 	} else {/* Add stream for any updated/enabled CRTC */
7444 		/*
7445 		 * Quick fix to prevent NULL pointer on new_stream when
7446 		 * added MST connectors not found in existing crtc_state in the chained mode
7447 		 * TODO: need to dig out the root cause of that
7448 		 */
7449 		if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
7450 			goto skip_modeset;
7451 
7452 		if (modereset_required(new_crtc_state))
7453 			goto skip_modeset;
7454 
7455 		if (modeset_required(new_crtc_state, new_stream,
7456 				     dm_old_crtc_state->stream)) {
7457 
7458 			WARN_ON(dm_new_crtc_state->stream);
7459 
7460 			ret = dm_atomic_get_state(state, &dm_state);
7461 			if (ret)
7462 				goto fail;
7463 
7464 			dm_new_crtc_state->stream = new_stream;
7465 
7466 			dc_stream_retain(new_stream);
7467 
7468 			DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
7469 						crtc->base.id);
7470 
7471 			if (dc_add_stream_to_ctx(
7472 					dm->dc,
7473 					dm_state->context,
7474 					dm_new_crtc_state->stream) != DC_OK) {
7475 				ret = -EINVAL;
7476 				goto fail;
7477 			}
7478 
7479 			*lock_and_validation_needed = true;
7480 		}
7481 	}
7482 
7483 skip_modeset:
7484 	/* Release extra reference */
7485 	if (new_stream)
7486 		 dc_stream_release(new_stream);
7487 
7488 	/*
7489 	 * We want to do dc stream updates that do not require a
7490 	 * full modeset below.
7491 	 */
7492 	if (!(enable && aconnector && new_crtc_state->enable &&
7493 	      new_crtc_state->active))
7494 		return 0;
7495 	/*
7496 	 * Given above conditions, the dc state cannot be NULL because:
7497 	 * 1. We're in the process of enabling CRTCs (just been added
7498 	 *    to the dc context, or already is on the context)
7499 	 * 2. Has a valid connector attached, and
7500 	 * 3. Is currently active and enabled.
7501 	 * => The dc stream state currently exists.
7502 	 */
7503 	BUG_ON(dm_new_crtc_state->stream == NULL);
7504 
7505 	/* Scaling or underscan settings */
7506 	if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
7507 		update_stream_scaling_settings(
7508 			&new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
7509 
7510 	/* ABM settings */
7511 	dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
7512 
7513 	/*
7514 	 * Color management settings. We also update color properties
7515 	 * when a modeset is needed, to ensure it gets reprogrammed.
7516 	 */
7517 	if (dm_new_crtc_state->base.color_mgmt_changed ||
7518 	    drm_atomic_crtc_needs_modeset(new_crtc_state)) {
7519 		ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
7520 		if (ret)
7521 			goto fail;
7522 	}
7523 
7524 	/* Update Freesync settings. */
7525 	get_freesync_config_for_crtc(dm_new_crtc_state,
7526 				     dm_new_conn_state);
7527 
7528 	return ret;
7529 
7530 fail:
7531 	if (new_stream)
7532 		dc_stream_release(new_stream);
7533 	return ret;
7534 }
7535 
7536 static bool should_reset_plane(struct drm_atomic_state *state,
7537 			       struct drm_plane *plane,
7538 			       struct drm_plane_state *old_plane_state,
7539 			       struct drm_plane_state *new_plane_state)
7540 {
7541 	struct drm_plane *other;
7542 	struct drm_plane_state *old_other_state, *new_other_state;
7543 	struct drm_crtc_state *new_crtc_state;
7544 	int i;
7545 
7546 	/*
7547 	 * TODO: Remove this hack once the checks below are sufficient
7548 	 * enough to determine when we need to reset all the planes on
7549 	 * the stream.
7550 	 */
7551 	if (state->allow_modeset)
7552 		return true;
7553 
7554 	/* Exit early if we know that we're adding or removing the plane. */
7555 	if (old_plane_state->crtc != new_plane_state->crtc)
7556 		return true;
7557 
7558 	/* old crtc == new_crtc == NULL, plane not in context. */
7559 	if (!new_plane_state->crtc)
7560 		return false;
7561 
7562 	new_crtc_state =
7563 		drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
7564 
7565 	if (!new_crtc_state)
7566 		return true;
7567 
7568 	/* CRTC Degamma changes currently require us to recreate planes. */
7569 	if (new_crtc_state->color_mgmt_changed)
7570 		return true;
7571 
7572 	if (drm_atomic_crtc_needs_modeset(new_crtc_state))
7573 		return true;
7574 
7575 	/*
7576 	 * If there are any new primary or overlay planes being added or
7577 	 * removed then the z-order can potentially change. To ensure
7578 	 * correct z-order and pipe acquisition the current DC architecture
7579 	 * requires us to remove and recreate all existing planes.
7580 	 *
7581 	 * TODO: Come up with a more elegant solution for this.
7582 	 */
7583 	for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
7584 		if (other->type == DRM_PLANE_TYPE_CURSOR)
7585 			continue;
7586 
7587 		if (old_other_state->crtc != new_plane_state->crtc &&
7588 		    new_other_state->crtc != new_plane_state->crtc)
7589 			continue;
7590 
7591 		if (old_other_state->crtc != new_other_state->crtc)
7592 			return true;
7593 
7594 		/* TODO: Remove this once we can handle fast format changes. */
7595 		if (old_other_state->fb && new_other_state->fb &&
7596 		    old_other_state->fb->format != new_other_state->fb->format)
7597 			return true;
7598 	}
7599 
7600 	return false;
7601 }
7602 
7603 static int dm_update_plane_state(struct dc *dc,
7604 				 struct drm_atomic_state *state,
7605 				 struct drm_plane *plane,
7606 				 struct drm_plane_state *old_plane_state,
7607 				 struct drm_plane_state *new_plane_state,
7608 				 bool enable,
7609 				 bool *lock_and_validation_needed)
7610 {
7611 
7612 	struct dm_atomic_state *dm_state = NULL;
7613 	struct drm_crtc *new_plane_crtc, *old_plane_crtc;
7614 	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
7615 	struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
7616 	struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
7617 	bool needs_reset;
7618 	int ret = 0;
7619 
7620 
7621 	new_plane_crtc = new_plane_state->crtc;
7622 	old_plane_crtc = old_plane_state->crtc;
7623 	dm_new_plane_state = to_dm_plane_state(new_plane_state);
7624 	dm_old_plane_state = to_dm_plane_state(old_plane_state);
7625 
7626 	/*TODO Implement atomic check for cursor plane */
7627 	if (plane->type == DRM_PLANE_TYPE_CURSOR)
7628 		return 0;
7629 
7630 	needs_reset = should_reset_plane(state, plane, old_plane_state,
7631 					 new_plane_state);
7632 
7633 	/* Remove any changed/removed planes */
7634 	if (!enable) {
7635 		if (!needs_reset)
7636 			return 0;
7637 
7638 		if (!old_plane_crtc)
7639 			return 0;
7640 
7641 		old_crtc_state = drm_atomic_get_old_crtc_state(
7642 				state, old_plane_crtc);
7643 		dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
7644 
7645 		if (!dm_old_crtc_state->stream)
7646 			return 0;
7647 
7648 		DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
7649 				plane->base.id, old_plane_crtc->base.id);
7650 
7651 		ret = dm_atomic_get_state(state, &dm_state);
7652 		if (ret)
7653 			return ret;
7654 
7655 		if (!dc_remove_plane_from_context(
7656 				dc,
7657 				dm_old_crtc_state->stream,
7658 				dm_old_plane_state->dc_state,
7659 				dm_state->context)) {
7660 
7661 			ret = EINVAL;
7662 			return ret;
7663 		}
7664 
7665 
7666 		dc_plane_state_release(dm_old_plane_state->dc_state);
7667 		dm_new_plane_state->dc_state = NULL;
7668 
7669 		*lock_and_validation_needed = true;
7670 
7671 	} else { /* Add new planes */
7672 		struct dc_plane_state *dc_new_plane_state;
7673 
7674 		if (drm_atomic_plane_disabling(plane->state, new_plane_state))
7675 			return 0;
7676 
7677 		if (!new_plane_crtc)
7678 			return 0;
7679 
7680 		new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
7681 		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
7682 
7683 		if (!dm_new_crtc_state->stream)
7684 			return 0;
7685 
7686 		if (!needs_reset)
7687 			return 0;
7688 
7689 		WARN_ON(dm_new_plane_state->dc_state);
7690 
7691 		dc_new_plane_state = dc_create_plane_state(dc);
7692 		if (!dc_new_plane_state)
7693 			return -ENOMEM;
7694 
7695 		DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
7696 				plane->base.id, new_plane_crtc->base.id);
7697 
7698 		ret = fill_dc_plane_attributes(
7699 			new_plane_crtc->dev->dev_private,
7700 			dc_new_plane_state,
7701 			new_plane_state,
7702 			new_crtc_state);
7703 		if (ret) {
7704 			dc_plane_state_release(dc_new_plane_state);
7705 			return ret;
7706 		}
7707 
7708 		ret = dm_atomic_get_state(state, &dm_state);
7709 		if (ret) {
7710 			dc_plane_state_release(dc_new_plane_state);
7711 			return ret;
7712 		}
7713 
7714 		/*
7715 		 * Any atomic check errors that occur after this will
7716 		 * not need a release. The plane state will be attached
7717 		 * to the stream, and therefore part of the atomic
7718 		 * state. It'll be released when the atomic state is
7719 		 * cleaned.
7720 		 */
7721 		if (!dc_add_plane_to_context(
7722 				dc,
7723 				dm_new_crtc_state->stream,
7724 				dc_new_plane_state,
7725 				dm_state->context)) {
7726 
7727 			dc_plane_state_release(dc_new_plane_state);
7728 			return -EINVAL;
7729 		}
7730 
7731 		dm_new_plane_state->dc_state = dc_new_plane_state;
7732 
7733 		/* Tell DC to do a full surface update every time there
7734 		 * is a plane change. Inefficient, but works for now.
7735 		 */
7736 		dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
7737 
7738 		*lock_and_validation_needed = true;
7739 	}
7740 
7741 
7742 	return ret;
7743 }
7744 
7745 static int
7746 dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm,
7747 				    struct drm_atomic_state *state,
7748 				    enum surface_update_type *out_type)
7749 {
7750 	struct dc *dc = dm->dc;
7751 	struct dm_atomic_state *dm_state = NULL, *old_dm_state = NULL;
7752 	int i, j, num_plane, ret = 0;
7753 	struct drm_plane_state *old_plane_state, *new_plane_state;
7754 	struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state;
7755 	struct drm_crtc *new_plane_crtc;
7756 	struct drm_plane *plane;
7757 
7758 	struct drm_crtc *crtc;
7759 	struct drm_crtc_state *new_crtc_state, *old_crtc_state;
7760 	struct dm_crtc_state *new_dm_crtc_state, *old_dm_crtc_state;
7761 	struct dc_stream_status *status = NULL;
7762 	enum surface_update_type update_type = UPDATE_TYPE_FAST;
7763 	struct surface_info_bundle {
7764 		struct dc_surface_update surface_updates[MAX_SURFACES];
7765 		struct dc_plane_info plane_infos[MAX_SURFACES];
7766 		struct dc_scaling_info scaling_infos[MAX_SURFACES];
7767 		struct dc_flip_addrs flip_addrs[MAX_SURFACES];
7768 		struct dc_stream_update stream_update;
7769 	} *bundle;
7770 
7771 	bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
7772 
7773 	if (!bundle) {
7774 		DRM_ERROR("Failed to allocate update bundle\n");
7775 		/* Set type to FULL to avoid crashing in DC*/
7776 		update_type = UPDATE_TYPE_FULL;
7777 		goto cleanup;
7778 	}
7779 
7780 	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7781 
7782 		memset(bundle, 0, sizeof(struct surface_info_bundle));
7783 
7784 		new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
7785 		old_dm_crtc_state = to_dm_crtc_state(old_crtc_state);
7786 		num_plane = 0;
7787 
7788 		if (new_dm_crtc_state->stream != old_dm_crtc_state->stream) {
7789 			update_type = UPDATE_TYPE_FULL;
7790 			goto cleanup;
7791 		}
7792 
7793 		if (!new_dm_crtc_state->stream)
7794 			continue;
7795 
7796 		for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) {
7797 			const struct amdgpu_framebuffer *amdgpu_fb =
7798 				to_amdgpu_framebuffer(new_plane_state->fb);
7799 			struct dc_plane_info *plane_info = &bundle->plane_infos[num_plane];
7800 			struct dc_flip_addrs *flip_addr = &bundle->flip_addrs[num_plane];
7801 			struct dc_scaling_info *scaling_info = &bundle->scaling_infos[num_plane];
7802 			uint64_t tiling_flags;
7803 
7804 			new_plane_crtc = new_plane_state->crtc;
7805 			new_dm_plane_state = to_dm_plane_state(new_plane_state);
7806 			old_dm_plane_state = to_dm_plane_state(old_plane_state);
7807 
7808 			if (plane->type == DRM_PLANE_TYPE_CURSOR)
7809 				continue;
7810 
7811 			if (new_dm_plane_state->dc_state != old_dm_plane_state->dc_state) {
7812 				update_type = UPDATE_TYPE_FULL;
7813 				goto cleanup;
7814 			}
7815 
7816 			if (crtc != new_plane_crtc)
7817 				continue;
7818 
7819 			bundle->surface_updates[num_plane].surface =
7820 					new_dm_plane_state->dc_state;
7821 
7822 			if (new_crtc_state->mode_changed) {
7823 				bundle->stream_update.dst = new_dm_crtc_state->stream->dst;
7824 				bundle->stream_update.src = new_dm_crtc_state->stream->src;
7825 			}
7826 
7827 			if (new_crtc_state->color_mgmt_changed) {
7828 				bundle->surface_updates[num_plane].gamma =
7829 						new_dm_plane_state->dc_state->gamma_correction;
7830 				bundle->surface_updates[num_plane].in_transfer_func =
7831 						new_dm_plane_state->dc_state->in_transfer_func;
7832 				bundle->stream_update.gamut_remap =
7833 						&new_dm_crtc_state->stream->gamut_remap_matrix;
7834 				bundle->stream_update.output_csc_transform =
7835 						&new_dm_crtc_state->stream->csc_color_matrix;
7836 				bundle->stream_update.out_transfer_func =
7837 						new_dm_crtc_state->stream->out_transfer_func;
7838 			}
7839 
7840 			ret = fill_dc_scaling_info(new_plane_state,
7841 						   scaling_info);
7842 			if (ret)
7843 				goto cleanup;
7844 
7845 			bundle->surface_updates[num_plane].scaling_info = scaling_info;
7846 
7847 			if (amdgpu_fb) {
7848 				ret = get_fb_info(amdgpu_fb, &tiling_flags);
7849 				if (ret)
7850 					goto cleanup;
7851 
7852 				ret = fill_dc_plane_info_and_addr(
7853 					dm->adev, new_plane_state, tiling_flags,
7854 					plane_info,
7855 					&flip_addr->address);
7856 				if (ret)
7857 					goto cleanup;
7858 
7859 				bundle->surface_updates[num_plane].plane_info = plane_info;
7860 				bundle->surface_updates[num_plane].flip_addr = flip_addr;
7861 			}
7862 
7863 			num_plane++;
7864 		}
7865 
7866 		if (num_plane == 0)
7867 			continue;
7868 
7869 		ret = dm_atomic_get_state(state, &dm_state);
7870 		if (ret)
7871 			goto cleanup;
7872 
7873 		old_dm_state = dm_atomic_get_old_state(state);
7874 		if (!old_dm_state) {
7875 			ret = -EINVAL;
7876 			goto cleanup;
7877 		}
7878 
7879 		status = dc_stream_get_status_from_state(old_dm_state->context,
7880 							 new_dm_crtc_state->stream);
7881 		bundle->stream_update.stream = new_dm_crtc_state->stream;
7882 		/*
7883 		 * TODO: DC modifies the surface during this call so we need
7884 		 * to lock here - find a way to do this without locking.
7885 		 */
7886 		mutex_lock(&dm->dc_lock);
7887 		update_type = dc_check_update_surfaces_for_stream(
7888 				dc,	bundle->surface_updates, num_plane,
7889 				&bundle->stream_update, status);
7890 		mutex_unlock(&dm->dc_lock);
7891 
7892 		if (update_type > UPDATE_TYPE_MED) {
7893 			update_type = UPDATE_TYPE_FULL;
7894 			goto cleanup;
7895 		}
7896 	}
7897 
7898 cleanup:
7899 	kfree(bundle);
7900 
7901 	*out_type = update_type;
7902 	return ret;
7903 }
7904 
7905 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
7906 {
7907 	struct drm_connector *connector;
7908 	struct drm_connector_state *conn_state;
7909 	struct amdgpu_dm_connector *aconnector = NULL;
7910 	int i;
7911 	for_each_new_connector_in_state(state, connector, conn_state, i) {
7912 		if (conn_state->crtc != crtc)
7913 			continue;
7914 
7915 		aconnector = to_amdgpu_dm_connector(connector);
7916 		if (!aconnector->port || !aconnector->mst_port)
7917 			aconnector = NULL;
7918 		else
7919 			break;
7920 	}
7921 
7922 	if (!aconnector)
7923 		return 0;
7924 
7925 	return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_port->mst_mgr);
7926 }
7927 
7928 /**
7929  * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
7930  * @dev: The DRM device
7931  * @state: The atomic state to commit
7932  *
7933  * Validate that the given atomic state is programmable by DC into hardware.
7934  * This involves constructing a &struct dc_state reflecting the new hardware
7935  * state we wish to commit, then querying DC to see if it is programmable. It's
7936  * important not to modify the existing DC state. Otherwise, atomic_check
7937  * may unexpectedly commit hardware changes.
7938  *
7939  * When validating the DC state, it's important that the right locks are
7940  * acquired. For full updates case which removes/adds/updates streams on one
7941  * CRTC while flipping on another CRTC, acquiring global lock will guarantee
7942  * that any such full update commit will wait for completion of any outstanding
7943  * flip using DRMs synchronization events. See
7944  * dm_determine_update_type_for_commit()
7945  *
7946  * Note that DM adds the affected connectors for all CRTCs in state, when that
7947  * might not seem necessary. This is because DC stream creation requires the
7948  * DC sink, which is tied to the DRM connector state. Cleaning this up should
7949  * be possible but non-trivial - a possible TODO item.
7950  *
7951  * Return: -Error code if validation failed.
7952  */
7953 static int amdgpu_dm_atomic_check(struct drm_device *dev,
7954 				  struct drm_atomic_state *state)
7955 {
7956 	struct amdgpu_device *adev = dev->dev_private;
7957 	struct dm_atomic_state *dm_state = NULL;
7958 	struct dc *dc = adev->dm.dc;
7959 	struct drm_connector *connector;
7960 	struct drm_connector_state *old_con_state, *new_con_state;
7961 	struct drm_crtc *crtc;
7962 	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
7963 	struct drm_plane *plane;
7964 	struct drm_plane_state *old_plane_state, *new_plane_state;
7965 	enum surface_update_type update_type = UPDATE_TYPE_FAST;
7966 	enum surface_update_type overall_update_type = UPDATE_TYPE_FAST;
7967 
7968 	int ret, i;
7969 
7970 	/*
7971 	 * This bool will be set for true for any modeset/reset
7972 	 * or plane update which implies non fast surface update.
7973 	 */
7974 	bool lock_and_validation_needed = false;
7975 
7976 	ret = drm_atomic_helper_check_modeset(dev, state);
7977 	if (ret)
7978 		goto fail;
7979 
7980 	if (adev->asic_type >= CHIP_NAVI10) {
7981 		for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7982 			if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
7983 				ret = add_affected_mst_dsc_crtcs(state, crtc);
7984 				if (ret)
7985 					goto fail;
7986 			}
7987 		}
7988 	}
7989 
7990 	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7991 		if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
7992 		    !new_crtc_state->color_mgmt_changed &&
7993 		    old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled)
7994 			continue;
7995 
7996 		if (!new_crtc_state->enable)
7997 			continue;
7998 
7999 		ret = drm_atomic_add_affected_connectors(state, crtc);
8000 		if (ret)
8001 			return ret;
8002 
8003 		ret = drm_atomic_add_affected_planes(state, crtc);
8004 		if (ret)
8005 			goto fail;
8006 	}
8007 
8008 	/*
8009 	 * Add all primary and overlay planes on the CRTC to the state
8010 	 * whenever a plane is enabled to maintain correct z-ordering
8011 	 * and to enable fast surface updates.
8012 	 */
8013 	drm_for_each_crtc(crtc, dev) {
8014 		bool modified = false;
8015 
8016 		for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
8017 			if (plane->type == DRM_PLANE_TYPE_CURSOR)
8018 				continue;
8019 
8020 			if (new_plane_state->crtc == crtc ||
8021 			    old_plane_state->crtc == crtc) {
8022 				modified = true;
8023 				break;
8024 			}
8025 		}
8026 
8027 		if (!modified)
8028 			continue;
8029 
8030 		drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
8031 			if (plane->type == DRM_PLANE_TYPE_CURSOR)
8032 				continue;
8033 
8034 			new_plane_state =
8035 				drm_atomic_get_plane_state(state, plane);
8036 
8037 			if (IS_ERR(new_plane_state)) {
8038 				ret = PTR_ERR(new_plane_state);
8039 				goto fail;
8040 			}
8041 		}
8042 	}
8043 
8044 	/* Remove exiting planes if they are modified */
8045 	for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
8046 		ret = dm_update_plane_state(dc, state, plane,
8047 					    old_plane_state,
8048 					    new_plane_state,
8049 					    false,
8050 					    &lock_and_validation_needed);
8051 		if (ret)
8052 			goto fail;
8053 	}
8054 
8055 	/* Disable all crtcs which require disable */
8056 	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8057 		ret = dm_update_crtc_state(&adev->dm, state, crtc,
8058 					   old_crtc_state,
8059 					   new_crtc_state,
8060 					   false,
8061 					   &lock_and_validation_needed);
8062 		if (ret)
8063 			goto fail;
8064 	}
8065 
8066 	/* Enable all crtcs which require enable */
8067 	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8068 		ret = dm_update_crtc_state(&adev->dm, state, crtc,
8069 					   old_crtc_state,
8070 					   new_crtc_state,
8071 					   true,
8072 					   &lock_and_validation_needed);
8073 		if (ret)
8074 			goto fail;
8075 	}
8076 
8077 	/* Add new/modified planes */
8078 	for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
8079 		ret = dm_update_plane_state(dc, state, plane,
8080 					    old_plane_state,
8081 					    new_plane_state,
8082 					    true,
8083 					    &lock_and_validation_needed);
8084 		if (ret)
8085 			goto fail;
8086 	}
8087 
8088 	/* Run this here since we want to validate the streams we created */
8089 	ret = drm_atomic_helper_check_planes(dev, state);
8090 	if (ret)
8091 		goto fail;
8092 
8093 	if (state->legacy_cursor_update) {
8094 		/*
8095 		 * This is a fast cursor update coming from the plane update
8096 		 * helper, check if it can be done asynchronously for better
8097 		 * performance.
8098 		 */
8099 		state->async_update =
8100 			!drm_atomic_helper_async_check(dev, state);
8101 
8102 		/*
8103 		 * Skip the remaining global validation if this is an async
8104 		 * update. Cursor updates can be done without affecting
8105 		 * state or bandwidth calcs and this avoids the performance
8106 		 * penalty of locking the private state object and
8107 		 * allocating a new dc_state.
8108 		 */
8109 		if (state->async_update)
8110 			return 0;
8111 	}
8112 
8113 	/* Check scaling and underscan changes*/
8114 	/* TODO Removed scaling changes validation due to inability to commit
8115 	 * new stream into context w\o causing full reset. Need to
8116 	 * decide how to handle.
8117 	 */
8118 	for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8119 		struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8120 		struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8121 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8122 
8123 		/* Skip any modesets/resets */
8124 		if (!acrtc || drm_atomic_crtc_needs_modeset(
8125 				drm_atomic_get_new_crtc_state(state, &acrtc->base)))
8126 			continue;
8127 
8128 		/* Skip any thing not scale or underscan changes */
8129 		if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
8130 			continue;
8131 
8132 		overall_update_type = UPDATE_TYPE_FULL;
8133 		lock_and_validation_needed = true;
8134 	}
8135 
8136 	ret = dm_determine_update_type_for_commit(&adev->dm, state, &update_type);
8137 	if (ret)
8138 		goto fail;
8139 
8140 	if (overall_update_type < update_type)
8141 		overall_update_type = update_type;
8142 
8143 	/*
8144 	 * lock_and_validation_needed was an old way to determine if we need to set
8145 	 * the global lock. Leaving it in to check if we broke any corner cases
8146 	 * lock_and_validation_needed true = UPDATE_TYPE_FULL or UPDATE_TYPE_MED
8147 	 * lock_and_validation_needed false = UPDATE_TYPE_FAST
8148 	 */
8149 	if (lock_and_validation_needed && overall_update_type <= UPDATE_TYPE_FAST)
8150 		WARN(1, "Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL");
8151 
8152 	if (overall_update_type > UPDATE_TYPE_FAST) {
8153 		ret = dm_atomic_get_state(state, &dm_state);
8154 		if (ret)
8155 			goto fail;
8156 
8157 		ret = do_aquire_global_lock(dev, state);
8158 		if (ret)
8159 			goto fail;
8160 
8161 #if defined(CONFIG_DRM_AMD_DC_DCN)
8162 		if (!compute_mst_dsc_configs_for_state(state, dm_state->context))
8163 			goto fail;
8164 
8165 		ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context);
8166 		if (ret)
8167 			goto fail;
8168 #endif
8169 
8170 		/*
8171 		 * Perform validation of MST topology in the state:
8172 		 * We need to perform MST atomic check before calling
8173 		 * dc_validate_global_state(), or there is a chance
8174 		 * to get stuck in an infinite loop and hang eventually.
8175 		 */
8176 		ret = drm_dp_mst_atomic_check(state);
8177 		if (ret)
8178 			goto fail;
8179 
8180 		if (dc_validate_global_state(dc, dm_state->context, false) != DC_OK) {
8181 			ret = -EINVAL;
8182 			goto fail;
8183 		}
8184 	} else {
8185 		/*
8186 		 * The commit is a fast update. Fast updates shouldn't change
8187 		 * the DC context, affect global validation, and can have their
8188 		 * commit work done in parallel with other commits not touching
8189 		 * the same resource. If we have a new DC context as part of
8190 		 * the DM atomic state from validation we need to free it and
8191 		 * retain the existing one instead.
8192 		 */
8193 		struct dm_atomic_state *new_dm_state, *old_dm_state;
8194 
8195 		new_dm_state = dm_atomic_get_new_state(state);
8196 		old_dm_state = dm_atomic_get_old_state(state);
8197 
8198 		if (new_dm_state && old_dm_state) {
8199 			if (new_dm_state->context)
8200 				dc_release_state(new_dm_state->context);
8201 
8202 			new_dm_state->context = old_dm_state->context;
8203 
8204 			if (old_dm_state->context)
8205 				dc_retain_state(old_dm_state->context);
8206 		}
8207 	}
8208 
8209 	/* Store the overall update type for use later in atomic check. */
8210 	for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
8211 		struct dm_crtc_state *dm_new_crtc_state =
8212 			to_dm_crtc_state(new_crtc_state);
8213 
8214 		dm_new_crtc_state->update_type = (int)overall_update_type;
8215 	}
8216 
8217 	/* Must be success */
8218 	WARN_ON(ret);
8219 	return ret;
8220 
8221 fail:
8222 	if (ret == -EDEADLK)
8223 		DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
8224 	else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
8225 		DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
8226 	else
8227 		DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
8228 
8229 	return ret;
8230 }
8231 
8232 static bool is_dp_capable_without_timing_msa(struct dc *dc,
8233 					     struct amdgpu_dm_connector *amdgpu_dm_connector)
8234 {
8235 	uint8_t dpcd_data;
8236 	bool capable = false;
8237 
8238 	if (amdgpu_dm_connector->dc_link &&
8239 		dm_helpers_dp_read_dpcd(
8240 				NULL,
8241 				amdgpu_dm_connector->dc_link,
8242 				DP_DOWN_STREAM_PORT_COUNT,
8243 				&dpcd_data,
8244 				sizeof(dpcd_data))) {
8245 		capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
8246 	}
8247 
8248 	return capable;
8249 }
8250 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
8251 					struct edid *edid)
8252 {
8253 	int i;
8254 	bool edid_check_required;
8255 	struct detailed_timing *timing;
8256 	struct detailed_non_pixel *data;
8257 	struct detailed_data_monitor_range *range;
8258 	struct amdgpu_dm_connector *amdgpu_dm_connector =
8259 			to_amdgpu_dm_connector(connector);
8260 	struct dm_connector_state *dm_con_state = NULL;
8261 
8262 	struct drm_device *dev = connector->dev;
8263 	struct amdgpu_device *adev = dev->dev_private;
8264 	bool freesync_capable = false;
8265 
8266 	if (!connector->state) {
8267 		DRM_ERROR("%s - Connector has no state", __func__);
8268 		goto update;
8269 	}
8270 
8271 	if (!edid) {
8272 		dm_con_state = to_dm_connector_state(connector->state);
8273 
8274 		amdgpu_dm_connector->min_vfreq = 0;
8275 		amdgpu_dm_connector->max_vfreq = 0;
8276 		amdgpu_dm_connector->pixel_clock_mhz = 0;
8277 
8278 		goto update;
8279 	}
8280 
8281 	dm_con_state = to_dm_connector_state(connector->state);
8282 
8283 	edid_check_required = false;
8284 	if (!amdgpu_dm_connector->dc_sink) {
8285 		DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
8286 		goto update;
8287 	}
8288 	if (!adev->dm.freesync_module)
8289 		goto update;
8290 	/*
8291 	 * if edid non zero restrict freesync only for dp and edp
8292 	 */
8293 	if (edid) {
8294 		if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
8295 			|| amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
8296 			edid_check_required = is_dp_capable_without_timing_msa(
8297 						adev->dm.dc,
8298 						amdgpu_dm_connector);
8299 		}
8300 	}
8301 	if (edid_check_required == true && (edid->version > 1 ||
8302 	   (edid->version == 1 && edid->revision > 1))) {
8303 		for (i = 0; i < 4; i++) {
8304 
8305 			timing	= &edid->detailed_timings[i];
8306 			data	= &timing->data.other_data;
8307 			range	= &data->data.range;
8308 			/*
8309 			 * Check if monitor has continuous frequency mode
8310 			 */
8311 			if (data->type != EDID_DETAIL_MONITOR_RANGE)
8312 				continue;
8313 			/*
8314 			 * Check for flag range limits only. If flag == 1 then
8315 			 * no additional timing information provided.
8316 			 * Default GTF, GTF Secondary curve and CVT are not
8317 			 * supported
8318 			 */
8319 			if (range->flags != 1)
8320 				continue;
8321 
8322 			amdgpu_dm_connector->min_vfreq = range->min_vfreq;
8323 			amdgpu_dm_connector->max_vfreq = range->max_vfreq;
8324 			amdgpu_dm_connector->pixel_clock_mhz =
8325 				range->pixel_clock_mhz * 10;
8326 			break;
8327 		}
8328 
8329 		if (amdgpu_dm_connector->max_vfreq -
8330 		    amdgpu_dm_connector->min_vfreq > 10) {
8331 
8332 			freesync_capable = true;
8333 		}
8334 	}
8335 
8336 update:
8337 	if (dm_con_state)
8338 		dm_con_state->freesync_capable = freesync_capable;
8339 
8340 	if (connector->vrr_capable_property)
8341 		drm_connector_set_vrr_capable_property(connector,
8342 						       freesync_capable);
8343 }
8344 
8345 static void amdgpu_dm_set_psr_caps(struct dc_link *link)
8346 {
8347 	uint8_t dpcd_data[EDP_PSR_RECEIVER_CAP_SIZE];
8348 
8349 	if (!(link->connector_signal & SIGNAL_TYPE_EDP))
8350 		return;
8351 	if (link->type == dc_connection_none)
8352 		return;
8353 	if (dm_helpers_dp_read_dpcd(NULL, link, DP_PSR_SUPPORT,
8354 					dpcd_data, sizeof(dpcd_data))) {
8355 		link->psr_feature_enabled = dpcd_data[0] ? true:false;
8356 		DRM_INFO("PSR support:%d\n", link->psr_feature_enabled);
8357 	}
8358 }
8359 
8360 /*
8361  * amdgpu_dm_link_setup_psr() - configure psr link
8362  * @stream: stream state
8363  *
8364  * Return: true if success
8365  */
8366 static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)
8367 {
8368 	struct dc_link *link = NULL;
8369 	struct psr_config psr_config = {0};
8370 	struct psr_context psr_context = {0};
8371 	struct dc *dc = NULL;
8372 	bool ret = false;
8373 
8374 	if (stream == NULL)
8375 		return false;
8376 
8377 	link = stream->link;
8378 	dc = link->ctx->dc;
8379 
8380 	psr_config.psr_version = dc->res_pool->dmcu->dmcu_version.psr_version;
8381 
8382 	if (psr_config.psr_version > 0) {
8383 		psr_config.psr_exit_link_training_required = 0x1;
8384 		psr_config.psr_frame_capture_indication_req = 0;
8385 		psr_config.psr_rfb_setup_time = 0x37;
8386 		psr_config.psr_sdp_transmit_line_num_deadline = 0x20;
8387 		psr_config.allow_smu_optimizations = 0x0;
8388 
8389 		ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context);
8390 
8391 	}
8392 	DRM_DEBUG_DRIVER("PSR link: %d\n",	link->psr_feature_enabled);
8393 
8394 	return ret;
8395 }
8396 
8397 /*
8398  * amdgpu_dm_psr_enable() - enable psr f/w
8399  * @stream: stream state
8400  *
8401  * Return: true if success
8402  */
8403 bool amdgpu_dm_psr_enable(struct dc_stream_state *stream)
8404 {
8405 	struct dc_link *link = stream->link;
8406 	unsigned int vsync_rate_hz = 0;
8407 	struct dc_static_screen_params params = {0};
8408 	/* Calculate number of static frames before generating interrupt to
8409 	 * enter PSR.
8410 	 */
8411 	unsigned int frame_time_microsec = 1000000 / vsync_rate_hz;
8412 	// Init fail safe of 2 frames static
8413 	unsigned int num_frames_static = 2;
8414 
8415 	DRM_DEBUG_DRIVER("Enabling psr...\n");
8416 
8417 	vsync_rate_hz = div64_u64(div64_u64((
8418 			stream->timing.pix_clk_100hz * 100),
8419 			stream->timing.v_total),
8420 			stream->timing.h_total);
8421 
8422 	/* Round up
8423 	 * Calculate number of frames such that at least 30 ms of time has
8424 	 * passed.
8425 	 */
8426 	if (vsync_rate_hz != 0)
8427 		num_frames_static = (30000 / frame_time_microsec) + 1;
8428 
8429 	params.triggers.cursor_update = true;
8430 	params.triggers.overlay_update = true;
8431 	params.triggers.surface_update = true;
8432 	params.num_frames = num_frames_static;
8433 
8434 	dc_stream_set_static_screen_params(link->ctx->dc,
8435 					   &stream, 1,
8436 					   &params);
8437 
8438 	return dc_link_set_psr_allow_active(link, true, false);
8439 }
8440 
8441 /*
8442  * amdgpu_dm_psr_disable() - disable psr f/w
8443  * @stream:  stream state
8444  *
8445  * Return: true if success
8446  */
8447 static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream)
8448 {
8449 
8450 	DRM_DEBUG_DRIVER("Disabling psr...\n");
8451 
8452 	return dc_link_set_psr_allow_active(stream->link, false, true);
8453 }
8454