1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Huawei HiNIC PCI Express Linux driver 4 * Copyright(c) 2017 Huawei Technologies Co., Ltd 5 */ 6 7 #ifndef HINIC_HW_DEV_H 8 #define HINIC_HW_DEV_H 9 10 #include <linux/pci.h> 11 #include <linux/types.h> 12 #include <linux/bitops.h> 13 #include <net/devlink.h> 14 15 #include "hinic_hw_if.h" 16 #include "hinic_hw_eqs.h" 17 #include "hinic_hw_mgmt.h" 18 #include "hinic_hw_qp.h" 19 #include "hinic_hw_io.h" 20 #include "hinic_hw_mbox.h" 21 22 #define HINIC_MAX_QPS 32 23 24 #define HINIC_MGMT_NUM_MSG_CMD (HINIC_MGMT_MSG_CMD_MAX - \ 25 HINIC_MGMT_MSG_CMD_BASE) 26 27 #define HINIC_PF_SET_VF_ALREADY 0x4 28 #define HINIC_MGMT_STATUS_EXIST 0x6 29 #define HINIC_MGMT_CMD_UNSUPPORTED 0xFF 30 31 #define HINIC_CMD_VER_FUNC_ID 2 32 33 struct hinic_cap { 34 u16 max_qps; 35 u16 num_qps; 36 u8 max_vf; 37 u16 max_vf_qps; 38 }; 39 40 enum hw_ioctxt_set_cmdq_depth { 41 HW_IOCTXT_SET_CMDQ_DEPTH_DEFAULT, 42 HW_IOCTXT_SET_CMDQ_DEPTH_ENABLE, 43 }; 44 45 enum hinic_port_cmd { 46 HINIC_PORT_CMD_VF_REGISTER = 0x0, 47 HINIC_PORT_CMD_VF_UNREGISTER = 0x1, 48 49 HINIC_PORT_CMD_CHANGE_MTU = 2, 50 51 HINIC_PORT_CMD_ADD_VLAN = 3, 52 HINIC_PORT_CMD_DEL_VLAN = 4, 53 54 HINIC_PORT_CMD_SET_PFC = 5, 55 56 HINIC_PORT_CMD_SET_MAC = 9, 57 HINIC_PORT_CMD_GET_MAC = 10, 58 HINIC_PORT_CMD_DEL_MAC = 11, 59 60 HINIC_PORT_CMD_SET_RX_MODE = 12, 61 62 HINIC_PORT_CMD_GET_PAUSE_INFO = 20, 63 HINIC_PORT_CMD_SET_PAUSE_INFO = 21, 64 65 HINIC_PORT_CMD_GET_LINK_STATE = 24, 66 67 HINIC_PORT_CMD_SET_LRO = 25, 68 69 HINIC_PORT_CMD_SET_RX_CSUM = 26, 70 71 HINIC_PORT_CMD_SET_RX_VLAN_OFFLOAD = 27, 72 73 HINIC_PORT_CMD_GET_PORT_STATISTICS = 28, 74 75 HINIC_PORT_CMD_CLEAR_PORT_STATISTICS = 29, 76 77 HINIC_PORT_CMD_GET_VPORT_STAT = 30, 78 79 HINIC_PORT_CMD_CLEAN_VPORT_STAT = 31, 80 81 HINIC_PORT_CMD_GET_RSS_TEMPLATE_INDIR_TBL = 37, 82 83 HINIC_PORT_CMD_SET_PORT_STATE = 41, 84 85 HINIC_PORT_CMD_SET_RSS_TEMPLATE_TBL = 43, 86 87 HINIC_PORT_CMD_GET_RSS_TEMPLATE_TBL = 44, 88 89 HINIC_PORT_CMD_SET_RSS_HASH_ENGINE = 45, 90 91 HINIC_PORT_CMD_GET_RSS_HASH_ENGINE = 46, 92 93 HINIC_PORT_CMD_GET_RSS_CTX_TBL = 47, 94 95 HINIC_PORT_CMD_SET_RSS_CTX_TBL = 48, 96 97 HINIC_PORT_CMD_RSS_TEMP_MGR = 49, 98 99 HINIC_PORT_CMD_RSS_CFG = 66, 100 101 HINIC_PORT_CMD_FWCTXT_INIT = 69, 102 103 HINIC_PORT_CMD_GET_LOOPBACK_MODE = 72, 104 HINIC_PORT_CMD_SET_LOOPBACK_MODE, 105 106 HINIC_PORT_CMD_ENABLE_SPOOFCHK = 78, 107 108 HINIC_PORT_CMD_GET_MGMT_VERSION = 88, 109 110 HINIC_PORT_CMD_SET_FUNC_STATE = 93, 111 112 HINIC_PORT_CMD_GET_GLOBAL_QPN = 102, 113 114 HINIC_PORT_CMD_SET_VF_RATE = 105, 115 116 HINIC_PORT_CMD_SET_VF_VLAN = 106, 117 118 HINIC_PORT_CMD_CLR_VF_VLAN, 119 120 HINIC_PORT_CMD_SET_TSO = 112, 121 122 HINIC_PORT_CMD_UPDATE_FW = 114, 123 124 HINIC_PORT_CMD_SET_RQ_IQ_MAP = 115, 125 126 HINIC_PORT_CMD_LINK_STATUS_REPORT = 160, 127 128 HINIC_PORT_CMD_UPDATE_MAC = 164, 129 130 HINIC_PORT_CMD_GET_CAP = 170, 131 132 HINIC_PORT_CMD_GET_LINK_MODE = 217, 133 134 HINIC_PORT_CMD_SET_SPEED = 218, 135 136 HINIC_PORT_CMD_SET_AUTONEG = 219, 137 138 HINIC_PORT_CMD_GET_STD_SFP_INFO = 240, 139 140 HINIC_PORT_CMD_SET_LRO_TIMER = 244, 141 142 HINIC_PORT_CMD_SET_VF_MAX_MIN_RATE = 249, 143 144 HINIC_PORT_CMD_GET_SFP_ABS = 251, 145 }; 146 147 /* cmd of mgmt CPU message for HILINK module */ 148 enum hinic_hilink_cmd { 149 HINIC_HILINK_CMD_GET_LINK_INFO = 0x3, 150 HINIC_HILINK_CMD_SET_LINK_SETTINGS = 0x8, 151 }; 152 153 enum hinic_ucode_cmd { 154 HINIC_UCODE_CMD_MODIFY_QUEUE_CONTEXT = 0, 155 HINIC_UCODE_CMD_CLEAN_QUEUE_CONTEXT, 156 HINIC_UCODE_CMD_ARM_SQ, 157 HINIC_UCODE_CMD_ARM_RQ, 158 HINIC_UCODE_CMD_SET_RSS_INDIR_TABLE, 159 HINIC_UCODE_CMD_SET_RSS_CONTEXT_TABLE, 160 HINIC_UCODE_CMD_GET_RSS_INDIR_TABLE, 161 HINIC_UCODE_CMD_GET_RSS_CONTEXT_TABLE, 162 HINIC_UCODE_CMD_SET_IQ_ENABLE, 163 HINIC_UCODE_CMD_SET_RQ_FLUSH = 10 164 }; 165 166 #define NIC_RSS_CMD_TEMP_ALLOC 0x01 167 #define NIC_RSS_CMD_TEMP_FREE 0x02 168 169 enum hinic_mgmt_msg_cmd { 170 HINIC_MGMT_MSG_CMD_BASE = 0xA0, 171 172 HINIC_MGMT_MSG_CMD_LINK_STATUS = 0xA0, 173 174 HINIC_MGMT_MSG_CMD_CABLE_PLUG_EVENT = 0xE5, 175 HINIC_MGMT_MSG_CMD_LINK_ERR_EVENT = 0xE6, 176 177 HINIC_MGMT_MSG_CMD_MAX, 178 }; 179 180 enum hinic_cb_state { 181 HINIC_CB_ENABLED = BIT(0), 182 HINIC_CB_RUNNING = BIT(1), 183 }; 184 185 enum hinic_res_state { 186 HINIC_RES_CLEAN = 0, 187 HINIC_RES_ACTIVE = 1, 188 }; 189 190 struct hinic_cmd_fw_ctxt { 191 u8 status; 192 u8 version; 193 u8 rsvd0[6]; 194 195 u16 func_idx; 196 u16 rx_buf_sz; 197 198 u32 rsvd1; 199 }; 200 201 struct hinic_cmd_hw_ioctxt { 202 u8 status; 203 u8 version; 204 u8 rsvd0[6]; 205 206 u16 func_idx; 207 208 u16 rsvd1; 209 210 u8 set_cmdq_depth; 211 u8 cmdq_depth; 212 213 u8 lro_en; 214 u8 rsvd3; 215 u8 ppf_idx; 216 u8 rsvd4; 217 218 u16 rq_depth; 219 u16 rx_buf_sz_idx; 220 u16 sq_depth; 221 }; 222 223 struct hinic_cmd_io_status { 224 u8 status; 225 u8 version; 226 u8 rsvd0[6]; 227 228 u16 func_idx; 229 u8 rsvd1; 230 u8 rsvd2; 231 u32 io_status; 232 }; 233 234 struct hinic_cmd_clear_io_res { 235 u8 status; 236 u8 version; 237 u8 rsvd0[6]; 238 239 u16 func_idx; 240 u8 rsvd1; 241 u8 rsvd2; 242 }; 243 244 struct hinic_cmd_set_res_state { 245 u8 status; 246 u8 version; 247 u8 rsvd0[6]; 248 249 u16 func_idx; 250 u8 state; 251 u8 rsvd1; 252 u32 rsvd2; 253 }; 254 255 struct hinic_ceq_ctrl_reg { 256 u8 status; 257 u8 version; 258 u8 rsvd0[6]; 259 260 u16 func_id; 261 u16 q_id; 262 u32 ctrl0; 263 u32 ctrl1; 264 }; 265 266 struct hinic_cmd_base_qpn { 267 u8 status; 268 u8 version; 269 u8 rsvd0[6]; 270 271 u16 func_idx; 272 u16 qpn; 273 }; 274 275 struct hinic_cmd_hw_ci { 276 u8 status; 277 u8 version; 278 u8 rsvd0[6]; 279 280 u16 func_idx; 281 282 u8 dma_attr_off; 283 u8 pending_limit; 284 u8 coalesc_timer; 285 286 u8 msix_en; 287 u16 msix_entry_idx; 288 289 u32 sq_id; 290 u32 rsvd1; 291 u64 ci_addr; 292 }; 293 294 struct hinic_cmd_l2nic_reset { 295 u8 status; 296 u8 version; 297 u8 rsvd0[6]; 298 299 u16 func_id; 300 u16 reset_flag; 301 }; 302 303 struct hinic_msix_config { 304 u8 status; 305 u8 version; 306 u8 rsvd0[6]; 307 308 u16 func_id; 309 u16 msix_index; 310 u8 pending_cnt; 311 u8 coalesce_timer_cnt; 312 u8 lli_timer_cnt; 313 u8 lli_credit_cnt; 314 u8 resend_timer_cnt; 315 u8 rsvd1[3]; 316 }; 317 318 struct hinic_set_random_id { 319 u8 status; 320 u8 version; 321 u8 rsvd0[6]; 322 323 u8 vf_in_pf; 324 u8 rsvd1; 325 u16 func_idx; 326 u32 random_id; 327 }; 328 329 struct hinic_board_info { 330 u32 board_type; 331 u32 port_num; 332 u32 port_speed; 333 u32 pcie_width; 334 u32 host_num; 335 u32 pf_num; 336 u32 vf_total_num; 337 u32 tile_num; 338 u32 qcm_num; 339 u32 core_num; 340 u32 work_mode; 341 u32 service_mode; 342 u32 pcie_mode; 343 u32 cfg_addr; 344 u32 boot_sel; 345 u32 board_id; 346 }; 347 348 struct hinic_comm_board_info { 349 u8 status; 350 u8 version; 351 u8 rsvd0[6]; 352 353 struct hinic_board_info info; 354 355 u32 rsvd1[4]; 356 }; 357 358 struct hinic_hwdev { 359 struct hinic_hwif *hwif; 360 struct msix_entry *msix_entries; 361 362 struct hinic_aeqs aeqs; 363 struct hinic_func_to_io func_to_io; 364 struct hinic_mbox_func_to_func *func_to_func; 365 366 struct hinic_cap nic_cap; 367 u8 port_id; 368 struct hinic_devlink_priv *devlink_dev; 369 }; 370 371 struct hinic_nic_cb { 372 void (*handler)(void *handle, void *buf_in, 373 u16 in_size, void *buf_out, 374 u16 *out_size); 375 376 void *handle; 377 unsigned long cb_state; 378 }; 379 380 #define HINIC_COMM_SELF_CMD_MAX 4 381 382 typedef void (*comm_mgmt_self_msg_proc)(void *handle, void *buf_in, u16 in_size, 383 void *buf_out, u16 *out_size); 384 385 struct comm_mgmt_self_msg_sub_info { 386 u8 cmd; 387 comm_mgmt_self_msg_proc proc; 388 }; 389 390 struct comm_mgmt_self_msg_info { 391 u8 cmd_num; 392 struct comm_mgmt_self_msg_sub_info info[HINIC_COMM_SELF_CMD_MAX]; 393 }; 394 395 struct hinic_pfhwdev { 396 struct hinic_hwdev hwdev; 397 398 struct hinic_pf_to_mgmt pf_to_mgmt; 399 400 struct hinic_nic_cb nic_cb[HINIC_MGMT_NUM_MSG_CMD]; 401 402 struct comm_mgmt_self_msg_info proc; 403 }; 404 405 struct hinic_dev_cap { 406 u8 status; 407 u8 version; 408 u8 rsvd0[6]; 409 410 u8 rsvd1[5]; 411 u8 intr_type; 412 u8 max_cos_id; 413 u8 er_id; 414 u8 port_id; 415 u8 max_vf; 416 u8 rsvd2[62]; 417 u16 max_sqs; 418 u16 max_rqs; 419 u16 max_vf_sqs; 420 u16 max_vf_rqs; 421 u8 rsvd3[204]; 422 }; 423 424 union hinic_fault_hw_mgmt { 425 u32 val[4]; 426 /* valid only type == FAULT_TYPE_CHIP */ 427 struct { 428 u8 node_id; 429 u8 err_level; 430 u16 err_type; 431 u32 err_csr_addr; 432 u32 err_csr_value; 433 /* func_id valid only if err_level == FAULT_LEVEL_SERIOUS_FLR */ 434 u16 func_id; 435 u16 rsvd2; 436 } chip; 437 438 /* valid only if type == FAULT_TYPE_UCODE */ 439 struct { 440 u8 cause_id; 441 u8 core_id; 442 u8 c_id; 443 u8 rsvd3; 444 u32 epc; 445 u32 rsvd4; 446 u32 rsvd5; 447 } ucode; 448 449 /* valid only if type == FAULT_TYPE_MEM_RD_TIMEOUT || 450 * FAULT_TYPE_MEM_WR_TIMEOUT 451 */ 452 struct { 453 u32 err_csr_ctrl; 454 u32 err_csr_data; 455 u32 ctrl_tab; 456 u32 mem_index; 457 } mem_timeout; 458 459 /* valid only if type == FAULT_TYPE_REG_RD_TIMEOUT || 460 * FAULT_TYPE_REG_WR_TIMEOUT 461 */ 462 struct { 463 u32 err_csr; 464 u32 rsvd6; 465 u32 rsvd7; 466 u32 rsvd8; 467 } reg_timeout; 468 469 struct { 470 /* 0: read; 1: write */ 471 u8 op_type; 472 u8 port_id; 473 u8 dev_ad; 474 u8 rsvd9; 475 u32 csr_addr; 476 u32 op_data; 477 u32 rsvd10; 478 } phy_fault; 479 }; 480 481 struct hinic_fault_event { 482 u8 type; 483 u8 fault_level; 484 u8 rsvd0[2]; 485 union hinic_fault_hw_mgmt event; 486 }; 487 488 struct hinic_cmd_fault_event { 489 u8 status; 490 u8 version; 491 u8 rsvd0[6]; 492 493 struct hinic_fault_event event; 494 }; 495 496 enum hinic_fault_type { 497 FAULT_TYPE_CHIP, 498 FAULT_TYPE_UCODE, 499 FAULT_TYPE_MEM_RD_TIMEOUT, 500 FAULT_TYPE_MEM_WR_TIMEOUT, 501 FAULT_TYPE_REG_RD_TIMEOUT, 502 FAULT_TYPE_REG_WR_TIMEOUT, 503 FAULT_TYPE_PHY_FAULT, 504 FAULT_TYPE_MAX, 505 }; 506 507 enum hinic_fault_err_level { 508 FAULT_LEVEL_FATAL, 509 FAULT_LEVEL_SERIOUS_RESET, 510 FAULT_LEVEL_SERIOUS_FLR, 511 FAULT_LEVEL_GENERAL, 512 FAULT_LEVEL_SUGGESTION, 513 FAULT_LEVEL_MAX 514 }; 515 516 struct hinic_mgmt_watchdog_info { 517 u8 status; 518 u8 version; 519 u8 rsvd0[6]; 520 521 u32 curr_time_h; 522 u32 curr_time_l; 523 u32 task_id; 524 u32 rsv; 525 526 u32 reg[13]; 527 u32 pc; 528 u32 lr; 529 u32 cpsr; 530 531 u32 stack_top; 532 u32 stack_bottom; 533 u32 sp; 534 u32 curr_used; 535 u32 peak_used; 536 u32 is_overflow; 537 538 u32 stack_actlen; 539 u8 data[1024]; 540 }; 541 542 void hinic_hwdev_cb_register(struct hinic_hwdev *hwdev, 543 enum hinic_mgmt_msg_cmd cmd, void *handle, 544 void (*handler)(void *handle, void *buf_in, 545 u16 in_size, void *buf_out, 546 u16 *out_size)); 547 548 void hinic_hwdev_cb_unregister(struct hinic_hwdev *hwdev, 549 enum hinic_mgmt_msg_cmd cmd); 550 551 int hinic_port_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_port_cmd cmd, 552 void *buf_in, u16 in_size, void *buf_out, 553 u16 *out_size); 554 555 int hinic_hilink_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_hilink_cmd cmd, 556 void *buf_in, u16 in_size, void *buf_out, 557 u16 *out_size); 558 559 int hinic_hwdev_ifup(struct hinic_hwdev *hwdev, u16 sq_depth, u16 rq_depth); 560 561 void hinic_hwdev_ifdown(struct hinic_hwdev *hwdev); 562 563 struct hinic_hwdev *hinic_init_hwdev(struct pci_dev *pdev, struct devlink *devlink); 564 565 void hinic_free_hwdev(struct hinic_hwdev *hwdev); 566 567 int hinic_hwdev_max_num_qps(struct hinic_hwdev *hwdev); 568 569 int hinic_hwdev_num_qps(struct hinic_hwdev *hwdev); 570 571 struct hinic_sq *hinic_hwdev_get_sq(struct hinic_hwdev *hwdev, int i); 572 573 struct hinic_rq *hinic_hwdev_get_rq(struct hinic_hwdev *hwdev, int i); 574 575 int hinic_hwdev_msix_cnt_set(struct hinic_hwdev *hwdev, u16 msix_index); 576 577 int hinic_hwdev_msix_set(struct hinic_hwdev *hwdev, u16 msix_index, 578 u8 pending_limit, u8 coalesc_timer, 579 u8 lli_timer_cfg, u8 lli_credit_limit, 580 u8 resend_timer); 581 582 int hinic_hwdev_hw_ci_addr_set(struct hinic_hwdev *hwdev, struct hinic_sq *sq, 583 u8 pending_limit, u8 coalesc_timer); 584 585 void hinic_hwdev_set_msix_state(struct hinic_hwdev *hwdev, u16 msix_index, 586 enum hinic_msix_state flag); 587 588 int hinic_get_interrupt_cfg(struct hinic_hwdev *hwdev, 589 struct hinic_msix_config *interrupt_info); 590 591 int hinic_set_interrupt_cfg(struct hinic_hwdev *hwdev, 592 struct hinic_msix_config *interrupt_info); 593 594 int hinic_get_board_info(struct hinic_hwdev *hwdev, 595 struct hinic_comm_board_info *board_info); 596 597 #endif 598