1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Huawei HiNIC PCI Express Linux driver 4 * Copyright(c) 2017 Huawei Technologies Co., Ltd 5 */ 6 7 #include <linux/kernel.h> 8 #include <linux/types.h> 9 #include <linux/pci.h> 10 #include <linux/device.h> 11 #include <linux/errno.h> 12 #include <linux/slab.h> 13 #include <linux/bitops.h> 14 #include <linux/delay.h> 15 #include <linux/jiffies.h> 16 #include <linux/log2.h> 17 #include <linux/err.h> 18 #include <linux/netdevice.h> 19 #include <net/devlink.h> 20 21 #include "hinic_devlink.h" 22 #include "hinic_sriov.h" 23 #include "hinic_dev.h" 24 #include "hinic_hw_if.h" 25 #include "hinic_hw_eqs.h" 26 #include "hinic_hw_mgmt.h" 27 #include "hinic_hw_qp_ctxt.h" 28 #include "hinic_hw_qp.h" 29 #include "hinic_hw_io.h" 30 #include "hinic_hw_dev.h" 31 32 #define IO_STATUS_TIMEOUT 100 33 #define OUTBOUND_STATE_TIMEOUT 100 34 #define DB_STATE_TIMEOUT 100 35 36 #define MAX_IRQS(max_qps, num_aeqs, num_ceqs) \ 37 (2 * (max_qps) + (num_aeqs) + (num_ceqs)) 38 39 #define ADDR_IN_4BYTES(addr) ((addr) >> 2) 40 41 enum intr_type { 42 INTR_MSIX_TYPE, 43 }; 44 45 enum io_status { 46 IO_STOPPED = 0, 47 IO_RUNNING = 1, 48 }; 49 50 /** 51 * get_capability - convert device capabilities to NIC capabilities 52 * @hwdev: the HW device to set and convert device capabilities for 53 * @dev_cap: device capabilities from FW 54 * 55 * Return 0 - Success, negative - Failure 56 **/ 57 static int parse_capability(struct hinic_hwdev *hwdev, 58 struct hinic_dev_cap *dev_cap) 59 { 60 struct hinic_cap *nic_cap = &hwdev->nic_cap; 61 int num_aeqs, num_ceqs, num_irqs; 62 63 if (!HINIC_IS_VF(hwdev->hwif) && dev_cap->intr_type != INTR_MSIX_TYPE) 64 return -EFAULT; 65 66 num_aeqs = HINIC_HWIF_NUM_AEQS(hwdev->hwif); 67 num_ceqs = HINIC_HWIF_NUM_CEQS(hwdev->hwif); 68 num_irqs = HINIC_HWIF_NUM_IRQS(hwdev->hwif); 69 70 /* Each QP has its own (SQ + RQ) interrupts */ 71 nic_cap->num_qps = (num_irqs - (num_aeqs + num_ceqs)) / 2; 72 73 if (nic_cap->num_qps > HINIC_Q_CTXT_MAX) 74 nic_cap->num_qps = HINIC_Q_CTXT_MAX; 75 76 if (!HINIC_IS_VF(hwdev->hwif)) 77 nic_cap->max_qps = dev_cap->max_sqs + 1; 78 else 79 nic_cap->max_qps = dev_cap->max_sqs; 80 81 if (nic_cap->num_qps > nic_cap->max_qps) 82 nic_cap->num_qps = nic_cap->max_qps; 83 84 if (!HINIC_IS_VF(hwdev->hwif)) { 85 nic_cap->max_vf = dev_cap->max_vf; 86 nic_cap->max_vf_qps = dev_cap->max_vf_sqs + 1; 87 } 88 89 hwdev->port_id = dev_cap->port_id; 90 91 return 0; 92 } 93 94 /** 95 * get_cap_from_fw - get device capabilities from FW 96 * @pfhwdev: the PF HW device to get capabilities for 97 * 98 * Return 0 - Success, negative - Failure 99 **/ 100 static int get_capability(struct hinic_pfhwdev *pfhwdev) 101 { 102 struct hinic_hwdev *hwdev = &pfhwdev->hwdev; 103 struct hinic_hwif *hwif = hwdev->hwif; 104 struct pci_dev *pdev = hwif->pdev; 105 struct hinic_dev_cap dev_cap; 106 u16 out_len; 107 int err; 108 109 out_len = sizeof(dev_cap); 110 111 err = hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_CFGM, 112 HINIC_CFG_NIC_CAP, &dev_cap, sizeof(dev_cap), 113 &dev_cap, &out_len, HINIC_MGMT_MSG_SYNC); 114 if (err) { 115 dev_err(&pdev->dev, "Failed to get capability from FW\n"); 116 return err; 117 } 118 119 return parse_capability(hwdev, &dev_cap); 120 } 121 122 /** 123 * get_dev_cap - get device capabilities 124 * @hwdev: the NIC HW device to get capabilities for 125 * 126 * Return 0 - Success, negative - Failure 127 **/ 128 static int get_dev_cap(struct hinic_hwdev *hwdev) 129 { 130 struct hinic_hwif *hwif = hwdev->hwif; 131 struct pci_dev *pdev = hwif->pdev; 132 struct hinic_pfhwdev *pfhwdev; 133 int err; 134 135 switch (HINIC_FUNC_TYPE(hwif)) { 136 case HINIC_PPF: 137 case HINIC_PF: 138 case HINIC_VF: 139 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 140 err = get_capability(pfhwdev); 141 if (err) { 142 dev_err(&pdev->dev, "Failed to get capability\n"); 143 return err; 144 } 145 break; 146 default: 147 dev_err(&pdev->dev, "Unsupported PCI Function type\n"); 148 return -EINVAL; 149 } 150 151 return 0; 152 } 153 154 /** 155 * init_msix - enable the msix and save the entries 156 * @hwdev: the NIC HW device 157 * 158 * Return 0 - Success, negative - Failure 159 **/ 160 static int init_msix(struct hinic_hwdev *hwdev) 161 { 162 struct hinic_hwif *hwif = hwdev->hwif; 163 struct pci_dev *pdev = hwif->pdev; 164 int nr_irqs, num_aeqs, num_ceqs; 165 size_t msix_entries_size; 166 int i, err; 167 168 num_aeqs = HINIC_HWIF_NUM_AEQS(hwif); 169 num_ceqs = HINIC_HWIF_NUM_CEQS(hwif); 170 nr_irqs = MAX_IRQS(HINIC_MAX_QPS, num_aeqs, num_ceqs); 171 if (nr_irqs > HINIC_HWIF_NUM_IRQS(hwif)) 172 nr_irqs = HINIC_HWIF_NUM_IRQS(hwif); 173 174 msix_entries_size = nr_irqs * sizeof(*hwdev->msix_entries); 175 hwdev->msix_entries = devm_kzalloc(&pdev->dev, msix_entries_size, 176 GFP_KERNEL); 177 if (!hwdev->msix_entries) 178 return -ENOMEM; 179 180 for (i = 0; i < nr_irqs; i++) 181 hwdev->msix_entries[i].entry = i; 182 183 err = pci_enable_msix_exact(pdev, hwdev->msix_entries, nr_irqs); 184 if (err) { 185 dev_err(&pdev->dev, "Failed to enable pci msix\n"); 186 return err; 187 } 188 189 return 0; 190 } 191 192 /** 193 * disable_msix - disable the msix 194 * @hwdev: the NIC HW device 195 **/ 196 static void disable_msix(struct hinic_hwdev *hwdev) 197 { 198 struct hinic_hwif *hwif = hwdev->hwif; 199 struct pci_dev *pdev = hwif->pdev; 200 201 pci_disable_msix(pdev); 202 } 203 204 /** 205 * hinic_port_msg_cmd - send port msg to mgmt 206 * @hwdev: the NIC HW device 207 * @cmd: the port command 208 * @buf_in: input buffer 209 * @in_size: input size 210 * @buf_out: output buffer 211 * @out_size: returned output size 212 * 213 * Return 0 - Success, negative - Failure 214 **/ 215 int hinic_port_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_port_cmd cmd, 216 void *buf_in, u16 in_size, void *buf_out, u16 *out_size) 217 { 218 struct hinic_pfhwdev *pfhwdev; 219 220 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 221 222 return hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_L2NIC, cmd, 223 buf_in, in_size, buf_out, out_size, 224 HINIC_MGMT_MSG_SYNC); 225 } 226 227 int hinic_hilink_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_hilink_cmd cmd, 228 void *buf_in, u16 in_size, void *buf_out, 229 u16 *out_size) 230 { 231 struct hinic_pfhwdev *pfhwdev; 232 233 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 234 235 return hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_HILINK, cmd, 236 buf_in, in_size, buf_out, out_size, 237 HINIC_MGMT_MSG_SYNC); 238 } 239 240 /** 241 * init_fw_ctxt- Init Firmware tables before network mgmt and io operations 242 * @hwdev: the NIC HW device 243 * 244 * Return 0 - Success, negative - Failure 245 **/ 246 static int init_fw_ctxt(struct hinic_hwdev *hwdev) 247 { 248 struct hinic_hwif *hwif = hwdev->hwif; 249 struct pci_dev *pdev = hwif->pdev; 250 struct hinic_cmd_fw_ctxt fw_ctxt; 251 u16 out_size = sizeof(fw_ctxt); 252 int err; 253 254 fw_ctxt.func_idx = HINIC_HWIF_FUNC_IDX(hwif); 255 fw_ctxt.rx_buf_sz = HINIC_RX_BUF_SZ; 256 257 err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_FWCTXT_INIT, 258 &fw_ctxt, sizeof(fw_ctxt), 259 &fw_ctxt, &out_size); 260 if (err || (out_size != sizeof(fw_ctxt)) || fw_ctxt.status) { 261 dev_err(&pdev->dev, "Failed to init FW ctxt, err: %d, status: 0x%x, out size: 0x%x\n", 262 err, fw_ctxt.status, out_size); 263 return -EIO; 264 } 265 266 return 0; 267 } 268 269 /** 270 * set_hw_ioctxt - set the shape of the IO queues in FW 271 * @hwdev: the NIC HW device 272 * @rq_depth: rq depth 273 * @sq_depth: sq depth 274 * 275 * Return 0 - Success, negative - Failure 276 **/ 277 static int set_hw_ioctxt(struct hinic_hwdev *hwdev, unsigned int sq_depth, 278 unsigned int rq_depth) 279 { 280 struct hinic_hwif *hwif = hwdev->hwif; 281 struct hinic_cmd_hw_ioctxt hw_ioctxt; 282 struct hinic_pfhwdev *pfhwdev; 283 284 hw_ioctxt.func_idx = HINIC_HWIF_FUNC_IDX(hwif); 285 hw_ioctxt.ppf_idx = HINIC_HWIF_PPF_IDX(hwif); 286 287 hw_ioctxt.set_cmdq_depth = HW_IOCTXT_SET_CMDQ_DEPTH_DEFAULT; 288 hw_ioctxt.cmdq_depth = 0; 289 290 hw_ioctxt.lro_en = 1; 291 292 hw_ioctxt.rq_depth = ilog2(rq_depth); 293 294 hw_ioctxt.rx_buf_sz_idx = HINIC_RX_BUF_SZ_IDX; 295 296 hw_ioctxt.sq_depth = ilog2(sq_depth); 297 298 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 299 300 return hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_COMM, 301 HINIC_COMM_CMD_HWCTXT_SET, 302 &hw_ioctxt, sizeof(hw_ioctxt), NULL, 303 NULL, HINIC_MGMT_MSG_SYNC); 304 } 305 306 static int wait_for_outbound_state(struct hinic_hwdev *hwdev) 307 { 308 enum hinic_outbound_state outbound_state; 309 struct hinic_hwif *hwif = hwdev->hwif; 310 struct pci_dev *pdev = hwif->pdev; 311 unsigned long end; 312 313 end = jiffies + msecs_to_jiffies(OUTBOUND_STATE_TIMEOUT); 314 do { 315 outbound_state = hinic_outbound_state_get(hwif); 316 317 if (outbound_state == HINIC_OUTBOUND_ENABLE) 318 return 0; 319 320 msleep(20); 321 } while (time_before(jiffies, end)); 322 323 dev_err(&pdev->dev, "Wait for OUTBOUND - Timeout\n"); 324 return -EFAULT; 325 } 326 327 static int wait_for_db_state(struct hinic_hwdev *hwdev) 328 { 329 struct hinic_hwif *hwif = hwdev->hwif; 330 struct pci_dev *pdev = hwif->pdev; 331 enum hinic_db_state db_state; 332 unsigned long end; 333 334 end = jiffies + msecs_to_jiffies(DB_STATE_TIMEOUT); 335 do { 336 db_state = hinic_db_state_get(hwif); 337 338 if (db_state == HINIC_DB_ENABLE) 339 return 0; 340 341 msleep(20); 342 } while (time_before(jiffies, end)); 343 344 dev_err(&pdev->dev, "Wait for DB - Timeout\n"); 345 return -EFAULT; 346 } 347 348 /** 349 * clear_io_resource - set the IO resources as not active in the NIC 350 * @hwdev: the NIC HW device 351 * 352 * Return 0 - Success, negative - Failure 353 **/ 354 static int clear_io_resources(struct hinic_hwdev *hwdev) 355 { 356 struct hinic_cmd_clear_io_res cmd_clear_io_res; 357 struct hinic_hwif *hwif = hwdev->hwif; 358 struct pci_dev *pdev = hwif->pdev; 359 struct hinic_pfhwdev *pfhwdev; 360 int err; 361 362 /* sleep 100ms to wait for firmware stopping I/O */ 363 msleep(100); 364 365 cmd_clear_io_res.func_idx = HINIC_HWIF_FUNC_IDX(hwif); 366 367 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 368 369 err = hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_COMM, 370 HINIC_COMM_CMD_IO_RES_CLEAR, &cmd_clear_io_res, 371 sizeof(cmd_clear_io_res), NULL, NULL, 372 HINIC_MGMT_MSG_SYNC); 373 if (err) { 374 dev_err(&pdev->dev, "Failed to clear IO resources\n"); 375 return err; 376 } 377 378 return 0; 379 } 380 381 /** 382 * set_resources_state - set the state of the resources in the NIC 383 * @hwdev: the NIC HW device 384 * @state: the state to set 385 * 386 * Return 0 - Success, negative - Failure 387 **/ 388 static int set_resources_state(struct hinic_hwdev *hwdev, 389 enum hinic_res_state state) 390 { 391 struct hinic_cmd_set_res_state res_state; 392 struct hinic_hwif *hwif = hwdev->hwif; 393 struct hinic_pfhwdev *pfhwdev; 394 395 res_state.func_idx = HINIC_HWIF_FUNC_IDX(hwif); 396 res_state.state = state; 397 398 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 399 400 return hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, 401 HINIC_MOD_COMM, 402 HINIC_COMM_CMD_RES_STATE_SET, 403 &res_state, sizeof(res_state), NULL, 404 NULL, HINIC_MGMT_MSG_SYNC); 405 } 406 407 /** 408 * get_base_qpn - get the first qp number 409 * @hwdev: the NIC HW device 410 * @base_qpn: returned qp number 411 * 412 * Return 0 - Success, negative - Failure 413 **/ 414 static int get_base_qpn(struct hinic_hwdev *hwdev, u16 *base_qpn) 415 { 416 struct hinic_cmd_base_qpn cmd_base_qpn; 417 struct hinic_hwif *hwif = hwdev->hwif; 418 u16 out_size = sizeof(cmd_base_qpn); 419 struct pci_dev *pdev = hwif->pdev; 420 int err; 421 422 cmd_base_qpn.func_idx = HINIC_HWIF_FUNC_IDX(hwif); 423 424 err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_GET_GLOBAL_QPN, 425 &cmd_base_qpn, sizeof(cmd_base_qpn), 426 &cmd_base_qpn, &out_size); 427 if (err || (out_size != sizeof(cmd_base_qpn)) || cmd_base_qpn.status) { 428 dev_err(&pdev->dev, "Failed to get base qpn, err: %d, status: 0x%x, out size: 0x%x\n", 429 err, cmd_base_qpn.status, out_size); 430 return -EIO; 431 } 432 433 *base_qpn = cmd_base_qpn.qpn; 434 return 0; 435 } 436 437 /** 438 * hinic_hwdev_ifup - Preparing the HW for passing IO 439 * @hwdev: the NIC HW device 440 * 441 * Return 0 - Success, negative - Failure 442 **/ 443 int hinic_hwdev_ifup(struct hinic_hwdev *hwdev, u16 sq_depth, u16 rq_depth) 444 { 445 struct hinic_func_to_io *func_to_io = &hwdev->func_to_io; 446 struct hinic_cap *nic_cap = &hwdev->nic_cap; 447 struct hinic_hwif *hwif = hwdev->hwif; 448 int err, num_aeqs, num_ceqs, num_qps; 449 struct msix_entry *ceq_msix_entries; 450 struct msix_entry *sq_msix_entries; 451 struct msix_entry *rq_msix_entries; 452 struct pci_dev *pdev = hwif->pdev; 453 u16 base_qpn; 454 455 err = get_base_qpn(hwdev, &base_qpn); 456 if (err) { 457 dev_err(&pdev->dev, "Failed to get global base qp number\n"); 458 return err; 459 } 460 461 num_aeqs = HINIC_HWIF_NUM_AEQS(hwif); 462 num_ceqs = HINIC_HWIF_NUM_CEQS(hwif); 463 464 ceq_msix_entries = &hwdev->msix_entries[num_aeqs]; 465 func_to_io->hwdev = hwdev; 466 func_to_io->sq_depth = sq_depth; 467 func_to_io->rq_depth = rq_depth; 468 469 err = hinic_io_init(func_to_io, hwif, nic_cap->max_qps, num_ceqs, 470 ceq_msix_entries); 471 if (err) { 472 dev_err(&pdev->dev, "Failed to init IO channel\n"); 473 return err; 474 } 475 476 num_qps = nic_cap->num_qps; 477 sq_msix_entries = &hwdev->msix_entries[num_aeqs + num_ceqs]; 478 rq_msix_entries = &hwdev->msix_entries[num_aeqs + num_ceqs + num_qps]; 479 480 err = hinic_io_create_qps(func_to_io, base_qpn, num_qps, 481 sq_msix_entries, rq_msix_entries); 482 if (err) { 483 dev_err(&pdev->dev, "Failed to create QPs\n"); 484 goto err_create_qps; 485 } 486 487 err = wait_for_db_state(hwdev); 488 if (err) { 489 dev_warn(&pdev->dev, "db - disabled, try again\n"); 490 hinic_db_state_set(hwif, HINIC_DB_ENABLE); 491 } 492 493 err = set_hw_ioctxt(hwdev, sq_depth, rq_depth); 494 if (err) { 495 dev_err(&pdev->dev, "Failed to set HW IO ctxt\n"); 496 goto err_hw_ioctxt; 497 } 498 499 return 0; 500 501 err_hw_ioctxt: 502 hinic_io_destroy_qps(func_to_io, num_qps); 503 504 err_create_qps: 505 hinic_io_free(func_to_io); 506 return err; 507 } 508 509 /** 510 * hinic_hwdev_ifdown - Closing the HW for passing IO 511 * @hwdev: the NIC HW device 512 * 513 **/ 514 void hinic_hwdev_ifdown(struct hinic_hwdev *hwdev) 515 { 516 struct hinic_func_to_io *func_to_io = &hwdev->func_to_io; 517 struct hinic_cap *nic_cap = &hwdev->nic_cap; 518 519 clear_io_resources(hwdev); 520 521 hinic_io_destroy_qps(func_to_io, nic_cap->num_qps); 522 hinic_io_free(func_to_io); 523 } 524 525 /** 526 * hinic_hwdev_cb_register - register callback handler for MGMT events 527 * @hwdev: the NIC HW device 528 * @cmd: the mgmt event 529 * @handle: private data for the handler 530 * @handler: event handler 531 **/ 532 void hinic_hwdev_cb_register(struct hinic_hwdev *hwdev, 533 enum hinic_mgmt_msg_cmd cmd, void *handle, 534 void (*handler)(void *handle, void *buf_in, 535 u16 in_size, void *buf_out, 536 u16 *out_size)) 537 { 538 struct hinic_pfhwdev *pfhwdev; 539 struct hinic_nic_cb *nic_cb; 540 u8 cmd_cb; 541 542 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 543 544 cmd_cb = cmd - HINIC_MGMT_MSG_CMD_BASE; 545 nic_cb = &pfhwdev->nic_cb[cmd_cb]; 546 547 nic_cb->handler = handler; 548 nic_cb->handle = handle; 549 nic_cb->cb_state = HINIC_CB_ENABLED; 550 } 551 552 /** 553 * hinic_hwdev_cb_unregister - unregister callback handler for MGMT events 554 * @hwdev: the NIC HW device 555 * @cmd: the mgmt event 556 **/ 557 void hinic_hwdev_cb_unregister(struct hinic_hwdev *hwdev, 558 enum hinic_mgmt_msg_cmd cmd) 559 { 560 struct hinic_hwif *hwif = hwdev->hwif; 561 struct hinic_pfhwdev *pfhwdev; 562 struct hinic_nic_cb *nic_cb; 563 u8 cmd_cb; 564 565 if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) 566 return; 567 568 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 569 570 cmd_cb = cmd - HINIC_MGMT_MSG_CMD_BASE; 571 nic_cb = &pfhwdev->nic_cb[cmd_cb]; 572 573 nic_cb->cb_state &= ~HINIC_CB_ENABLED; 574 575 while (nic_cb->cb_state & HINIC_CB_RUNNING) 576 schedule(); 577 578 nic_cb->handler = NULL; 579 } 580 581 /** 582 * nic_mgmt_msg_handler - nic mgmt event handler 583 * @handle: private data for the handler 584 * @buf_in: input buffer 585 * @in_size: input size 586 * @buf_out: output buffer 587 * @out_size: returned output size 588 **/ 589 static void nic_mgmt_msg_handler(void *handle, u8 cmd, void *buf_in, 590 u16 in_size, void *buf_out, u16 *out_size) 591 { 592 struct hinic_pfhwdev *pfhwdev = handle; 593 enum hinic_cb_state cb_state; 594 struct hinic_nic_cb *nic_cb; 595 struct hinic_hwdev *hwdev; 596 struct hinic_hwif *hwif; 597 struct pci_dev *pdev; 598 u8 cmd_cb; 599 600 hwdev = &pfhwdev->hwdev; 601 hwif = hwdev->hwif; 602 pdev = hwif->pdev; 603 604 if ((cmd < HINIC_MGMT_MSG_CMD_BASE) || 605 (cmd >= HINIC_MGMT_MSG_CMD_MAX)) { 606 dev_err(&pdev->dev, "unknown L2NIC event, cmd = %d\n", cmd); 607 return; 608 } 609 610 cmd_cb = cmd - HINIC_MGMT_MSG_CMD_BASE; 611 612 nic_cb = &pfhwdev->nic_cb[cmd_cb]; 613 614 cb_state = cmpxchg(&nic_cb->cb_state, 615 HINIC_CB_ENABLED, 616 HINIC_CB_ENABLED | HINIC_CB_RUNNING); 617 618 if ((cb_state == HINIC_CB_ENABLED) && (nic_cb->handler)) 619 nic_cb->handler(nic_cb->handle, buf_in, 620 in_size, buf_out, out_size); 621 else 622 dev_err(&pdev->dev, "Unhandled NIC Event %d\n", cmd); 623 624 nic_cb->cb_state &= ~HINIC_CB_RUNNING; 625 } 626 627 static void hinic_comm_recv_mgmt_self_cmd_reg(struct hinic_pfhwdev *pfhwdev, 628 u8 cmd, 629 comm_mgmt_self_msg_proc proc) 630 { 631 u8 cmd_idx; 632 633 cmd_idx = pfhwdev->proc.cmd_num; 634 if (cmd_idx >= HINIC_COMM_SELF_CMD_MAX) { 635 dev_err(&pfhwdev->hwdev.hwif->pdev->dev, 636 "Register recv mgmt process failed, cmd: 0x%x\n", cmd); 637 return; 638 } 639 640 pfhwdev->proc.info[cmd_idx].cmd = cmd; 641 pfhwdev->proc.info[cmd_idx].proc = proc; 642 pfhwdev->proc.cmd_num++; 643 } 644 645 static void hinic_comm_recv_mgmt_self_cmd_unreg(struct hinic_pfhwdev *pfhwdev, 646 u8 cmd) 647 { 648 u8 cmd_idx; 649 650 cmd_idx = pfhwdev->proc.cmd_num; 651 if (cmd_idx >= HINIC_COMM_SELF_CMD_MAX) { 652 dev_err(&pfhwdev->hwdev.hwif->pdev->dev, "Unregister recv mgmt process failed, cmd: 0x%x\n", 653 cmd); 654 return; 655 } 656 657 for (cmd_idx = 0; cmd_idx < HINIC_COMM_SELF_CMD_MAX; cmd_idx++) { 658 if (cmd == pfhwdev->proc.info[cmd_idx].cmd) { 659 pfhwdev->proc.info[cmd_idx].cmd = 0; 660 pfhwdev->proc.info[cmd_idx].proc = NULL; 661 pfhwdev->proc.cmd_num--; 662 } 663 } 664 } 665 666 static void comm_mgmt_msg_handler(void *handle, u8 cmd, void *buf_in, 667 u16 in_size, void *buf_out, u16 *out_size) 668 { 669 struct hinic_pfhwdev *pfhwdev = handle; 670 u8 cmd_idx; 671 672 for (cmd_idx = 0; cmd_idx < pfhwdev->proc.cmd_num; cmd_idx++) { 673 if (cmd == pfhwdev->proc.info[cmd_idx].cmd) { 674 if (!pfhwdev->proc.info[cmd_idx].proc) { 675 dev_warn(&pfhwdev->hwdev.hwif->pdev->dev, 676 "PF recv mgmt comm msg handle null, cmd: 0x%x\n", 677 cmd); 678 } else { 679 pfhwdev->proc.info[cmd_idx].proc 680 (&pfhwdev->hwdev, buf_in, in_size, 681 buf_out, out_size); 682 } 683 684 return; 685 } 686 } 687 688 dev_warn(&pfhwdev->hwdev.hwif->pdev->dev, "Received unknown mgmt cpu event: 0x%x\n", 689 cmd); 690 691 *out_size = 0; 692 } 693 694 /* pf fault report event */ 695 static void pf_fault_event_handler(void *dev, void *buf_in, u16 in_size, 696 void *buf_out, u16 *out_size) 697 { 698 struct hinic_cmd_fault_event *fault_event = buf_in; 699 struct hinic_hwdev *hwdev = dev; 700 701 if (in_size != sizeof(*fault_event)) { 702 dev_err(&hwdev->hwif->pdev->dev, "Invalid fault event report, length: %d, should be %zu\n", 703 in_size, sizeof(*fault_event)); 704 return; 705 } 706 707 if (!hwdev->devlink_dev || IS_ERR_OR_NULL(hwdev->devlink_dev->hw_fault_reporter)) 708 return; 709 710 devlink_health_report(hwdev->devlink_dev->hw_fault_reporter, 711 "HW fatal error reported", &fault_event->event); 712 } 713 714 static void mgmt_watchdog_timeout_event_handler(void *dev, 715 void *buf_in, u16 in_size, 716 void *buf_out, u16 *out_size) 717 { 718 struct hinic_mgmt_watchdog_info *watchdog_info = buf_in; 719 struct hinic_hwdev *hwdev = dev; 720 721 if (in_size != sizeof(*watchdog_info)) { 722 dev_err(&hwdev->hwif->pdev->dev, "Invalid mgmt watchdog report, length: %d, should be %zu\n", 723 in_size, sizeof(*watchdog_info)); 724 return; 725 } 726 727 if (!hwdev->devlink_dev || IS_ERR_OR_NULL(hwdev->devlink_dev->fw_fault_reporter)) 728 return; 729 730 devlink_health_report(hwdev->devlink_dev->fw_fault_reporter, 731 "FW fatal error reported", watchdog_info); 732 } 733 734 /** 735 * init_pfhwdev - Initialize the extended components of PF 736 * @pfhwdev: the HW device for PF 737 * 738 * Return 0 - success, negative - failure 739 **/ 740 static int init_pfhwdev(struct hinic_pfhwdev *pfhwdev) 741 { 742 struct hinic_hwdev *hwdev = &pfhwdev->hwdev; 743 struct hinic_hwif *hwif = hwdev->hwif; 744 struct pci_dev *pdev = hwif->pdev; 745 int err; 746 747 err = hinic_pf_to_mgmt_init(&pfhwdev->pf_to_mgmt, hwif); 748 if (err) { 749 dev_err(&pdev->dev, "Failed to initialize PF to MGMT channel\n"); 750 return err; 751 } 752 753 err = hinic_devlink_register(hwdev->devlink_dev, &pdev->dev); 754 if (err) { 755 dev_err(&hwif->pdev->dev, "Failed to register devlink\n"); 756 hinic_pf_to_mgmt_free(&pfhwdev->pf_to_mgmt); 757 return err; 758 } 759 760 err = hinic_func_to_func_init(hwdev); 761 if (err) { 762 dev_err(&hwif->pdev->dev, "Failed to init mailbox\n"); 763 hinic_devlink_unregister(hwdev->devlink_dev); 764 hinic_pf_to_mgmt_free(&pfhwdev->pf_to_mgmt); 765 return err; 766 } 767 768 if (!HINIC_IS_VF(hwif)) { 769 hinic_register_mgmt_msg_cb(&pfhwdev->pf_to_mgmt, 770 HINIC_MOD_L2NIC, pfhwdev, 771 nic_mgmt_msg_handler); 772 hinic_register_mgmt_msg_cb(&pfhwdev->pf_to_mgmt, HINIC_MOD_COMM, 773 pfhwdev, comm_mgmt_msg_handler); 774 hinic_comm_recv_mgmt_self_cmd_reg(pfhwdev, 775 HINIC_COMM_CMD_FAULT_REPORT, 776 pf_fault_event_handler); 777 hinic_comm_recv_mgmt_self_cmd_reg 778 (pfhwdev, HINIC_COMM_CMD_WATCHDOG_INFO, 779 mgmt_watchdog_timeout_event_handler); 780 } else { 781 hinic_register_vf_mbox_cb(hwdev, HINIC_MOD_L2NIC, 782 nic_mgmt_msg_handler); 783 } 784 785 hinic_set_pf_action(hwif, HINIC_PF_MGMT_ACTIVE); 786 787 return 0; 788 } 789 790 /** 791 * free_pfhwdev - Free the extended components of PF 792 * @pfhwdev: the HW device for PF 793 **/ 794 static void free_pfhwdev(struct hinic_pfhwdev *pfhwdev) 795 { 796 struct hinic_hwdev *hwdev = &pfhwdev->hwdev; 797 798 hinic_set_pf_action(hwdev->hwif, HINIC_PF_MGMT_INIT); 799 800 if (!HINIC_IS_VF(hwdev->hwif)) { 801 hinic_comm_recv_mgmt_self_cmd_unreg(pfhwdev, 802 HINIC_COMM_CMD_WATCHDOG_INFO); 803 hinic_comm_recv_mgmt_self_cmd_unreg(pfhwdev, 804 HINIC_COMM_CMD_FAULT_REPORT); 805 hinic_unregister_mgmt_msg_cb(&pfhwdev->pf_to_mgmt, 806 HINIC_MOD_COMM); 807 hinic_unregister_mgmt_msg_cb(&pfhwdev->pf_to_mgmt, 808 HINIC_MOD_L2NIC); 809 } else { 810 hinic_unregister_vf_mbox_cb(hwdev, HINIC_MOD_L2NIC); 811 } 812 813 hinic_func_to_func_free(hwdev); 814 815 hinic_devlink_unregister(hwdev->devlink_dev); 816 817 hinic_pf_to_mgmt_free(&pfhwdev->pf_to_mgmt); 818 } 819 820 static int hinic_l2nic_reset(struct hinic_hwdev *hwdev) 821 { 822 struct hinic_cmd_l2nic_reset l2nic_reset = {0}; 823 u16 out_size = sizeof(l2nic_reset); 824 struct hinic_pfhwdev *pfhwdev; 825 int err; 826 827 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 828 829 l2nic_reset.func_id = HINIC_HWIF_FUNC_IDX(hwdev->hwif); 830 /* 0 represents standard l2nic reset flow */ 831 l2nic_reset.reset_flag = 0; 832 833 err = hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_COMM, 834 HINIC_COMM_CMD_L2NIC_RESET, &l2nic_reset, 835 sizeof(l2nic_reset), &l2nic_reset, 836 &out_size, HINIC_MGMT_MSG_SYNC); 837 if (err || !out_size || l2nic_reset.status) { 838 dev_err(&hwdev->hwif->pdev->dev, "Failed to reset L2NIC resources, err: %d, status: 0x%x, out_size: 0x%x\n", 839 err, l2nic_reset.status, out_size); 840 return -EIO; 841 } 842 843 return 0; 844 } 845 846 int hinic_get_interrupt_cfg(struct hinic_hwdev *hwdev, 847 struct hinic_msix_config *interrupt_info) 848 { 849 u16 out_size = sizeof(*interrupt_info); 850 struct hinic_pfhwdev *pfhwdev; 851 int err; 852 853 if (!hwdev || !interrupt_info) 854 return -EINVAL; 855 856 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 857 858 interrupt_info->func_id = HINIC_HWIF_FUNC_IDX(hwdev->hwif); 859 860 err = hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_COMM, 861 HINIC_COMM_CMD_MSI_CTRL_REG_RD_BY_UP, 862 interrupt_info, sizeof(*interrupt_info), 863 interrupt_info, &out_size, HINIC_MGMT_MSG_SYNC); 864 if (err || !out_size || interrupt_info->status) { 865 dev_err(&hwdev->hwif->pdev->dev, "Failed to get interrupt config, err: %d, status: 0x%x, out size: 0x%x\n", 866 err, interrupt_info->status, out_size); 867 return -EIO; 868 } 869 870 return 0; 871 } 872 873 int hinic_set_interrupt_cfg(struct hinic_hwdev *hwdev, 874 struct hinic_msix_config *interrupt_info) 875 { 876 u16 out_size = sizeof(*interrupt_info); 877 struct hinic_msix_config temp_info; 878 struct hinic_pfhwdev *pfhwdev; 879 int err; 880 881 if (!hwdev) 882 return -EINVAL; 883 884 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 885 886 interrupt_info->func_id = HINIC_HWIF_FUNC_IDX(hwdev->hwif); 887 888 err = hinic_get_interrupt_cfg(hwdev, &temp_info); 889 if (err) 890 return -EINVAL; 891 892 interrupt_info->lli_credit_cnt = temp_info.lli_timer_cnt; 893 interrupt_info->lli_timer_cnt = temp_info.lli_timer_cnt; 894 895 err = hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_COMM, 896 HINIC_COMM_CMD_MSI_CTRL_REG_WR_BY_UP, 897 interrupt_info, sizeof(*interrupt_info), 898 interrupt_info, &out_size, HINIC_MGMT_MSG_SYNC); 899 if (err || !out_size || interrupt_info->status) { 900 dev_err(&hwdev->hwif->pdev->dev, "Failed to get interrupt config, err: %d, status: 0x%x, out size: 0x%x\n", 901 err, interrupt_info->status, out_size); 902 return -EIO; 903 } 904 905 return 0; 906 } 907 908 /** 909 * hinic_init_hwdev - Initialize the NIC HW 910 * @pdev: the NIC pci device 911 * 912 * Return initialized NIC HW device 913 * 914 * Initialize the NIC HW device and return a pointer to it 915 **/ 916 struct hinic_hwdev *hinic_init_hwdev(struct pci_dev *pdev, struct devlink *devlink) 917 { 918 struct hinic_pfhwdev *pfhwdev; 919 struct hinic_hwdev *hwdev; 920 struct hinic_hwif *hwif; 921 int err, num_aeqs; 922 923 hwif = devm_kzalloc(&pdev->dev, sizeof(*hwif), GFP_KERNEL); 924 if (!hwif) 925 return ERR_PTR(-ENOMEM); 926 927 err = hinic_init_hwif(hwif, pdev); 928 if (err) { 929 dev_err(&pdev->dev, "Failed to init HW interface\n"); 930 return ERR_PTR(err); 931 } 932 933 pfhwdev = devm_kzalloc(&pdev->dev, sizeof(*pfhwdev), GFP_KERNEL); 934 if (!pfhwdev) { 935 err = -ENOMEM; 936 goto err_pfhwdev_alloc; 937 } 938 939 hwdev = &pfhwdev->hwdev; 940 hwdev->hwif = hwif; 941 hwdev->devlink_dev = devlink_priv(devlink); 942 hwdev->devlink_dev->hwdev = hwdev; 943 944 err = init_msix(hwdev); 945 if (err) { 946 dev_err(&pdev->dev, "Failed to init msix\n"); 947 goto err_init_msix; 948 } 949 950 err = wait_for_outbound_state(hwdev); 951 if (err) { 952 dev_warn(&pdev->dev, "outbound - disabled, try again\n"); 953 hinic_outbound_state_set(hwif, HINIC_OUTBOUND_ENABLE); 954 } 955 956 num_aeqs = HINIC_HWIF_NUM_AEQS(hwif); 957 958 err = hinic_aeqs_init(&hwdev->aeqs, hwif, num_aeqs, 959 HINIC_DEFAULT_AEQ_LEN, HINIC_EQ_PAGE_SIZE, 960 hwdev->msix_entries); 961 if (err) { 962 dev_err(&pdev->dev, "Failed to init async event queues\n"); 963 goto err_aeqs_init; 964 } 965 966 err = init_pfhwdev(pfhwdev); 967 if (err) { 968 dev_err(&pdev->dev, "Failed to init PF HW device\n"); 969 goto err_init_pfhwdev; 970 } 971 972 err = hinic_l2nic_reset(hwdev); 973 if (err) 974 goto err_l2nic_reset; 975 976 err = get_dev_cap(hwdev); 977 if (err) { 978 dev_err(&pdev->dev, "Failed to get device capabilities\n"); 979 goto err_dev_cap; 980 } 981 982 mutex_init(&hwdev->func_to_io.nic_cfg.cfg_mutex); 983 984 err = hinic_vf_func_init(hwdev); 985 if (err) { 986 dev_err(&pdev->dev, "Failed to init nic mbox\n"); 987 goto err_vf_func_init; 988 } 989 990 err = init_fw_ctxt(hwdev); 991 if (err) { 992 dev_err(&pdev->dev, "Failed to init function table\n"); 993 goto err_init_fw_ctxt; 994 } 995 996 err = set_resources_state(hwdev, HINIC_RES_ACTIVE); 997 if (err) { 998 dev_err(&pdev->dev, "Failed to set resources state\n"); 999 goto err_resources_state; 1000 } 1001 1002 return hwdev; 1003 1004 err_resources_state: 1005 err_init_fw_ctxt: 1006 hinic_vf_func_free(hwdev); 1007 err_vf_func_init: 1008 err_l2nic_reset: 1009 err_dev_cap: 1010 free_pfhwdev(pfhwdev); 1011 1012 err_init_pfhwdev: 1013 hinic_aeqs_free(&hwdev->aeqs); 1014 1015 err_aeqs_init: 1016 disable_msix(hwdev); 1017 1018 err_init_msix: 1019 err_pfhwdev_alloc: 1020 hinic_free_hwif(hwif); 1021 if (err > 0) 1022 err = -EIO; 1023 return ERR_PTR(err); 1024 } 1025 1026 /** 1027 * hinic_free_hwdev - Free the NIC HW device 1028 * @hwdev: the NIC HW device 1029 **/ 1030 void hinic_free_hwdev(struct hinic_hwdev *hwdev) 1031 { 1032 struct hinic_pfhwdev *pfhwdev = container_of(hwdev, 1033 struct hinic_pfhwdev, 1034 hwdev); 1035 1036 set_resources_state(hwdev, HINIC_RES_CLEAN); 1037 1038 hinic_vf_func_free(hwdev); 1039 1040 free_pfhwdev(pfhwdev); 1041 1042 hinic_aeqs_free(&hwdev->aeqs); 1043 1044 disable_msix(hwdev); 1045 1046 hinic_free_hwif(hwdev->hwif); 1047 } 1048 1049 int hinic_hwdev_max_num_qps(struct hinic_hwdev *hwdev) 1050 { 1051 struct hinic_cap *nic_cap = &hwdev->nic_cap; 1052 1053 return nic_cap->max_qps; 1054 } 1055 1056 /** 1057 * hinic_hwdev_num_qps - return the number QPs available for use 1058 * @hwdev: the NIC HW device 1059 * 1060 * Return number QPs available for use 1061 **/ 1062 int hinic_hwdev_num_qps(struct hinic_hwdev *hwdev) 1063 { 1064 struct hinic_cap *nic_cap = &hwdev->nic_cap; 1065 1066 return nic_cap->num_qps; 1067 } 1068 1069 /** 1070 * hinic_hwdev_get_sq - get SQ 1071 * @hwdev: the NIC HW device 1072 * @i: the position of the SQ 1073 * 1074 * Return: the SQ in the i position 1075 **/ 1076 struct hinic_sq *hinic_hwdev_get_sq(struct hinic_hwdev *hwdev, int i) 1077 { 1078 struct hinic_func_to_io *func_to_io = &hwdev->func_to_io; 1079 struct hinic_qp *qp = &func_to_io->qps[i]; 1080 1081 if (i >= hinic_hwdev_num_qps(hwdev)) 1082 return NULL; 1083 1084 return &qp->sq; 1085 } 1086 1087 /** 1088 * hinic_hwdev_get_sq - get RQ 1089 * @hwdev: the NIC HW device 1090 * @i: the position of the RQ 1091 * 1092 * Return: the RQ in the i position 1093 **/ 1094 struct hinic_rq *hinic_hwdev_get_rq(struct hinic_hwdev *hwdev, int i) 1095 { 1096 struct hinic_func_to_io *func_to_io = &hwdev->func_to_io; 1097 struct hinic_qp *qp = &func_to_io->qps[i]; 1098 1099 if (i >= hinic_hwdev_num_qps(hwdev)) 1100 return NULL; 1101 1102 return &qp->rq; 1103 } 1104 1105 /** 1106 * hinic_hwdev_msix_cnt_set - clear message attribute counters for msix entry 1107 * @hwdev: the NIC HW device 1108 * @msix_index: msix_index 1109 * 1110 * Return 0 - Success, negative - Failure 1111 **/ 1112 int hinic_hwdev_msix_cnt_set(struct hinic_hwdev *hwdev, u16 msix_index) 1113 { 1114 return hinic_msix_attr_cnt_clear(hwdev->hwif, msix_index); 1115 } 1116 1117 /** 1118 * hinic_hwdev_msix_set - set message attribute for msix entry 1119 * @hwdev: the NIC HW device 1120 * @msix_index: msix_index 1121 * @pending_limit: the maximum pending interrupt events (unit 8) 1122 * @coalesc_timer: coalesc period for interrupt (unit 8 us) 1123 * @lli_timer: replenishing period for low latency credit (unit 8 us) 1124 * @lli_credit_limit: maximum credits for low latency msix messages (unit 8) 1125 * @resend_timer: maximum wait for resending msix (unit coalesc period) 1126 * 1127 * Return 0 - Success, negative - Failure 1128 **/ 1129 int hinic_hwdev_msix_set(struct hinic_hwdev *hwdev, u16 msix_index, 1130 u8 pending_limit, u8 coalesc_timer, 1131 u8 lli_timer_cfg, u8 lli_credit_limit, 1132 u8 resend_timer) 1133 { 1134 return hinic_msix_attr_set(hwdev->hwif, msix_index, 1135 pending_limit, coalesc_timer, 1136 lli_timer_cfg, lli_credit_limit, 1137 resend_timer); 1138 } 1139 1140 /** 1141 * hinic_hwdev_hw_ci_addr_set - set cons idx addr and attributes in HW for sq 1142 * @hwdev: the NIC HW device 1143 * @sq: send queue 1144 * @pending_limit: the maximum pending update ci events (unit 8) 1145 * @coalesc_timer: coalesc period for update ci (unit 8 us) 1146 * 1147 * Return 0 - Success, negative - Failure 1148 **/ 1149 int hinic_hwdev_hw_ci_addr_set(struct hinic_hwdev *hwdev, struct hinic_sq *sq, 1150 u8 pending_limit, u8 coalesc_timer) 1151 { 1152 struct hinic_qp *qp = container_of(sq, struct hinic_qp, sq); 1153 struct hinic_hwif *hwif = hwdev->hwif; 1154 struct hinic_pfhwdev *pfhwdev; 1155 struct hinic_cmd_hw_ci hw_ci; 1156 1157 hw_ci.dma_attr_off = 0; 1158 hw_ci.pending_limit = pending_limit; 1159 hw_ci.coalesc_timer = coalesc_timer; 1160 1161 hw_ci.msix_en = 1; 1162 hw_ci.msix_entry_idx = sq->msix_entry; 1163 1164 hw_ci.func_idx = HINIC_HWIF_FUNC_IDX(hwif); 1165 1166 hw_ci.sq_id = qp->q_id; 1167 1168 hw_ci.ci_addr = ADDR_IN_4BYTES(sq->hw_ci_dma_addr); 1169 1170 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 1171 return hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, 1172 HINIC_MOD_COMM, 1173 HINIC_COMM_CMD_SQ_HI_CI_SET, 1174 &hw_ci, sizeof(hw_ci), NULL, 1175 NULL, HINIC_MGMT_MSG_SYNC); 1176 } 1177 1178 /** 1179 * hinic_hwdev_set_msix_state- set msix state 1180 * @hwdev: the NIC HW device 1181 * @msix_index: IRQ corresponding index number 1182 * @flag: msix state 1183 * 1184 **/ 1185 void hinic_hwdev_set_msix_state(struct hinic_hwdev *hwdev, u16 msix_index, 1186 enum hinic_msix_state flag) 1187 { 1188 hinic_set_msix_state(hwdev->hwif, msix_index, flag); 1189 } 1190 1191 int hinic_get_board_info(struct hinic_hwdev *hwdev, 1192 struct hinic_comm_board_info *board_info) 1193 { 1194 u16 out_size = sizeof(*board_info); 1195 struct hinic_pfhwdev *pfhwdev; 1196 int err; 1197 1198 if (!hwdev || !board_info) 1199 return -EINVAL; 1200 1201 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 1202 1203 err = hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_COMM, 1204 HINIC_COMM_CMD_GET_BOARD_INFO, 1205 board_info, sizeof(*board_info), 1206 board_info, &out_size, HINIC_MGMT_MSG_SYNC); 1207 if (err || board_info->status || !out_size) { 1208 dev_err(&hwdev->hwif->pdev->dev, 1209 "Failed to get board info, err: %d, status: 0x%x, out size: 0x%x\n", 1210 err, board_info->status, out_size); 1211 return -EIO; 1212 } 1213 1214 return 0; 1215 } 1216