1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2014-2018 Broadcom Limited 5 * Copyright (c) 2018-2020 Broadcom Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation. 10 * 11 * DO NOT MODIFY!!! This file is automatically generated. 12 */ 13 14 #ifndef _BNXT_HSI_H_ 15 #define _BNXT_HSI_H_ 16 17 /* hwrm_cmd_hdr (size:128b/16B) */ 18 struct hwrm_cmd_hdr { 19 __le16 req_type; 20 __le16 cmpl_ring; 21 __le16 seq_id; 22 __le16 target_id; 23 __le64 resp_addr; 24 }; 25 26 /* hwrm_resp_hdr (size:64b/8B) */ 27 struct hwrm_resp_hdr { 28 __le16 error_code; 29 __le16 req_type; 30 __le16 seq_id; 31 __le16 resp_len; 32 }; 33 34 #define CMD_DISCR_TLV_ENCAP 0x8000UL 35 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP 36 37 38 #define TLV_TYPE_HWRM_REQUEST 0x1UL 39 #define TLV_TYPE_HWRM_RESPONSE 0x2UL 40 #define TLV_TYPE_ROCE_SP_COMMAND 0x3UL 41 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 0x4UL 42 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL 43 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY 0x8001UL 44 #define TLV_TYPE_ENGINE_CKV_IV 0x8003UL 45 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL 46 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL 47 #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS 0x8006UL 48 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY 0x8007UL 49 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL 50 #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY 0x8009UL 51 #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 0x800aUL 52 #define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 53 54 55 /* tlv (size:64b/8B) */ 56 struct tlv { 57 __le16 cmd_discr; 58 u8 reserved_8b; 59 u8 flags; 60 #define TLV_FLAGS_MORE 0x1UL 61 #define TLV_FLAGS_MORE_LAST 0x0UL 62 #define TLV_FLAGS_MORE_NOT_LAST 0x1UL 63 #define TLV_FLAGS_REQUIRED 0x2UL 64 #define TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 65 #define TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 66 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES 67 __le16 tlv_type; 68 __le16 length; 69 }; 70 71 /* input (size:128b/16B) */ 72 struct input { 73 __le16 req_type; 74 __le16 cmpl_ring; 75 __le16 seq_id; 76 __le16 target_id; 77 __le64 resp_addr; 78 }; 79 80 /* output (size:64b/8B) */ 81 struct output { 82 __le16 error_code; 83 __le16 req_type; 84 __le16 seq_id; 85 __le16 resp_len; 86 }; 87 88 /* hwrm_short_input (size:128b/16B) */ 89 struct hwrm_short_input { 90 __le16 req_type; 91 __le16 signature; 92 #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL 93 #define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD 94 __le16 target_id; 95 #define SHORT_REQ_TARGET_ID_DEFAULT 0x0UL 96 #define SHORT_REQ_TARGET_ID_TOOLS 0xfffdUL 97 #define SHORT_REQ_TARGET_ID_LAST SHORT_REQ_TARGET_ID_TOOLS 98 __le16 size; 99 __le64 req_addr; 100 }; 101 102 /* cmd_nums (size:64b/8B) */ 103 struct cmd_nums { 104 __le16 req_type; 105 #define HWRM_VER_GET 0x0UL 106 #define HWRM_ERROR_RECOVERY_QCFG 0xcUL 107 #define HWRM_FUNC_DRV_IF_CHANGE 0xdUL 108 #define HWRM_FUNC_BUF_UNRGTR 0xeUL 109 #define HWRM_FUNC_VF_CFG 0xfUL 110 #define HWRM_RESERVED1 0x10UL 111 #define HWRM_FUNC_RESET 0x11UL 112 #define HWRM_FUNC_GETFID 0x12UL 113 #define HWRM_FUNC_VF_ALLOC 0x13UL 114 #define HWRM_FUNC_VF_FREE 0x14UL 115 #define HWRM_FUNC_QCAPS 0x15UL 116 #define HWRM_FUNC_QCFG 0x16UL 117 #define HWRM_FUNC_CFG 0x17UL 118 #define HWRM_FUNC_QSTATS 0x18UL 119 #define HWRM_FUNC_CLR_STATS 0x19UL 120 #define HWRM_FUNC_DRV_UNRGTR 0x1aUL 121 #define HWRM_FUNC_VF_RESC_FREE 0x1bUL 122 #define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL 123 #define HWRM_FUNC_DRV_RGTR 0x1dUL 124 #define HWRM_FUNC_DRV_QVER 0x1eUL 125 #define HWRM_FUNC_BUF_RGTR 0x1fUL 126 #define HWRM_PORT_PHY_CFG 0x20UL 127 #define HWRM_PORT_MAC_CFG 0x21UL 128 #define HWRM_PORT_TS_QUERY 0x22UL 129 #define HWRM_PORT_QSTATS 0x23UL 130 #define HWRM_PORT_LPBK_QSTATS 0x24UL 131 #define HWRM_PORT_CLR_STATS 0x25UL 132 #define HWRM_PORT_LPBK_CLR_STATS 0x26UL 133 #define HWRM_PORT_PHY_QCFG 0x27UL 134 #define HWRM_PORT_MAC_QCFG 0x28UL 135 #define HWRM_PORT_MAC_PTP_QCFG 0x29UL 136 #define HWRM_PORT_PHY_QCAPS 0x2aUL 137 #define HWRM_PORT_PHY_I2C_WRITE 0x2bUL 138 #define HWRM_PORT_PHY_I2C_READ 0x2cUL 139 #define HWRM_PORT_LED_CFG 0x2dUL 140 #define HWRM_PORT_LED_QCFG 0x2eUL 141 #define HWRM_PORT_LED_QCAPS 0x2fUL 142 #define HWRM_QUEUE_QPORTCFG 0x30UL 143 #define HWRM_QUEUE_QCFG 0x31UL 144 #define HWRM_QUEUE_CFG 0x32UL 145 #define HWRM_FUNC_VLAN_CFG 0x33UL 146 #define HWRM_FUNC_VLAN_QCFG 0x34UL 147 #define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL 148 #define HWRM_QUEUE_PFCENABLE_CFG 0x36UL 149 #define HWRM_QUEUE_PRI2COS_QCFG 0x37UL 150 #define HWRM_QUEUE_PRI2COS_CFG 0x38UL 151 #define HWRM_QUEUE_COS2BW_QCFG 0x39UL 152 #define HWRM_QUEUE_COS2BW_CFG 0x3aUL 153 #define HWRM_QUEUE_DSCP_QCAPS 0x3bUL 154 #define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL 155 #define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL 156 #define HWRM_VNIC_ALLOC 0x40UL 157 #define HWRM_VNIC_FREE 0x41UL 158 #define HWRM_VNIC_CFG 0x42UL 159 #define HWRM_VNIC_QCFG 0x43UL 160 #define HWRM_VNIC_TPA_CFG 0x44UL 161 #define HWRM_VNIC_TPA_QCFG 0x45UL 162 #define HWRM_VNIC_RSS_CFG 0x46UL 163 #define HWRM_VNIC_RSS_QCFG 0x47UL 164 #define HWRM_VNIC_PLCMODES_CFG 0x48UL 165 #define HWRM_VNIC_PLCMODES_QCFG 0x49UL 166 #define HWRM_VNIC_QCAPS 0x4aUL 167 #define HWRM_RING_ALLOC 0x50UL 168 #define HWRM_RING_FREE 0x51UL 169 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL 170 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL 171 #define HWRM_RING_AGGINT_QCAPS 0x54UL 172 #define HWRM_RING_RESET 0x5eUL 173 #define HWRM_RING_GRP_ALLOC 0x60UL 174 #define HWRM_RING_GRP_FREE 0x61UL 175 #define HWRM_RESERVED5 0x64UL 176 #define HWRM_RESERVED6 0x65UL 177 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL 178 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL 179 #define HWRM_QUEUE_MPLS_QCAPS 0x80UL 180 #define HWRM_QUEUE_MPLSTC2PRI_QCFG 0x81UL 181 #define HWRM_QUEUE_MPLSTC2PRI_CFG 0x82UL 182 #define HWRM_CFA_L2_FILTER_ALLOC 0x90UL 183 #define HWRM_CFA_L2_FILTER_FREE 0x91UL 184 #define HWRM_CFA_L2_FILTER_CFG 0x92UL 185 #define HWRM_CFA_L2_SET_RX_MASK 0x93UL 186 #define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL 187 #define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL 188 #define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL 189 #define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL 190 #define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL 191 #define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL 192 #define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL 193 #define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL 194 #define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL 195 #define HWRM_CFA_EM_FLOW_FREE 0x9dUL 196 #define HWRM_CFA_EM_FLOW_CFG 0x9eUL 197 #define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL 198 #define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL 199 #define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL 200 #define HWRM_STAT_CTX_ENG_QUERY 0xafUL 201 #define HWRM_STAT_CTX_ALLOC 0xb0UL 202 #define HWRM_STAT_CTX_FREE 0xb1UL 203 #define HWRM_STAT_CTX_QUERY 0xb2UL 204 #define HWRM_STAT_CTX_CLR_STATS 0xb3UL 205 #define HWRM_PORT_QSTATS_EXT 0xb4UL 206 #define HWRM_PORT_PHY_MDIO_WRITE 0xb5UL 207 #define HWRM_PORT_PHY_MDIO_READ 0xb6UL 208 #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE 0xb7UL 209 #define HWRM_PORT_PHY_MDIO_BUS_RELEASE 0xb8UL 210 #define HWRM_PORT_QSTATS_EXT_PFC_WD 0xb9UL 211 #define HWRM_PORT_ECN_QSTATS 0xbaUL 212 #define HWRM_FW_RESET 0xc0UL 213 #define HWRM_FW_QSTATUS 0xc1UL 214 #define HWRM_FW_HEALTH_CHECK 0xc2UL 215 #define HWRM_FW_SYNC 0xc3UL 216 #define HWRM_FW_STATE_QCAPS 0xc4UL 217 #define HWRM_FW_STATE_QUIESCE 0xc5UL 218 #define HWRM_FW_STATE_BACKUP 0xc6UL 219 #define HWRM_FW_STATE_RESTORE 0xc7UL 220 #define HWRM_FW_SET_TIME 0xc8UL 221 #define HWRM_FW_GET_TIME 0xc9UL 222 #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL 223 #define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL 224 #define HWRM_FW_IPC_MAILBOX 0xccUL 225 #define HWRM_FW_ECN_CFG 0xcdUL 226 #define HWRM_FW_ECN_QCFG 0xceUL 227 #define HWRM_EXEC_FWD_RESP 0xd0UL 228 #define HWRM_REJECT_FWD_RESP 0xd1UL 229 #define HWRM_FWD_RESP 0xd2UL 230 #define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL 231 #define HWRM_OEM_CMD 0xd4UL 232 #define HWRM_PORT_PRBS_TEST 0xd5UL 233 #define HWRM_PORT_SFP_SIDEBAND_CFG 0xd6UL 234 #define HWRM_PORT_SFP_SIDEBAND_QCFG 0xd7UL 235 #define HWRM_FW_STATE_UNQUIESCE 0xd8UL 236 #define HWRM_PORT_DSC_DUMP 0xd9UL 237 #define HWRM_TEMP_MONITOR_QUERY 0xe0UL 238 #define HWRM_REG_POWER_QUERY 0xe1UL 239 #define HWRM_CORE_FREQUENCY_QUERY 0xe2UL 240 #define HWRM_REG_POWER_HISTOGRAM 0xe3UL 241 #define HWRM_WOL_FILTER_ALLOC 0xf0UL 242 #define HWRM_WOL_FILTER_FREE 0xf1UL 243 #define HWRM_WOL_FILTER_QCFG 0xf2UL 244 #define HWRM_WOL_REASON_QCFG 0xf3UL 245 #define HWRM_CFA_METER_QCAPS 0xf4UL 246 #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL 247 #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL 248 #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL 249 #define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL 250 #define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL 251 #define HWRM_CFA_METER_INSTANCE_CFG 0xfaUL 252 #define HWRM_CFA_VFR_ALLOC 0xfdUL 253 #define HWRM_CFA_VFR_FREE 0xfeUL 254 #define HWRM_CFA_VF_PAIR_ALLOC 0x100UL 255 #define HWRM_CFA_VF_PAIR_FREE 0x101UL 256 #define HWRM_CFA_VF_PAIR_INFO 0x102UL 257 #define HWRM_CFA_FLOW_ALLOC 0x103UL 258 #define HWRM_CFA_FLOW_FREE 0x104UL 259 #define HWRM_CFA_FLOW_FLUSH 0x105UL 260 #define HWRM_CFA_FLOW_STATS 0x106UL 261 #define HWRM_CFA_FLOW_INFO 0x107UL 262 #define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL 263 #define HWRM_CFA_DECAP_FILTER_FREE 0x109UL 264 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL 265 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL 266 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL 267 #define HWRM_CFA_PAIR_ALLOC 0x10dUL 268 #define HWRM_CFA_PAIR_FREE 0x10eUL 269 #define HWRM_CFA_PAIR_INFO 0x10fUL 270 #define HWRM_FW_IPC_MSG 0x110UL 271 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL 272 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL 273 #define HWRM_CFA_FLOW_AGING_TIMER_RESET 0x113UL 274 #define HWRM_CFA_FLOW_AGING_CFG 0x114UL 275 #define HWRM_CFA_FLOW_AGING_QCFG 0x115UL 276 #define HWRM_CFA_FLOW_AGING_QCAPS 0x116UL 277 #define HWRM_CFA_CTX_MEM_RGTR 0x117UL 278 #define HWRM_CFA_CTX_MEM_UNRGTR 0x118UL 279 #define HWRM_CFA_CTX_MEM_QCTX 0x119UL 280 #define HWRM_CFA_CTX_MEM_QCAPS 0x11aUL 281 #define HWRM_CFA_COUNTER_QCAPS 0x11bUL 282 #define HWRM_CFA_COUNTER_CFG 0x11cUL 283 #define HWRM_CFA_COUNTER_QCFG 0x11dUL 284 #define HWRM_CFA_COUNTER_QSTATS 0x11eUL 285 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG 0x11fUL 286 #define HWRM_CFA_EEM_QCAPS 0x120UL 287 #define HWRM_CFA_EEM_CFG 0x121UL 288 #define HWRM_CFA_EEM_QCFG 0x122UL 289 #define HWRM_CFA_EEM_OP 0x123UL 290 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS 0x124UL 291 #define HWRM_CFA_TFLIB 0x125UL 292 #define HWRM_ENGINE_CKV_STATUS 0x12eUL 293 #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL 294 #define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL 295 #define HWRM_ENGINE_CKV_KEY_ADD 0x131UL 296 #define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL 297 #define HWRM_ENGINE_CKV_FLUSH 0x133UL 298 #define HWRM_ENGINE_CKV_RNG_GET 0x134UL 299 #define HWRM_ENGINE_CKV_KEY_GEN 0x135UL 300 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG 0x136UL 301 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG 0x137UL 302 #define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL 303 #define HWRM_ENGINE_QG_QUERY 0x13dUL 304 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL 305 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL 306 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL 307 #define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL 308 #define HWRM_ENGINE_QG_METER_QUERY 0x142UL 309 #define HWRM_ENGINE_QG_METER_BIND 0x143UL 310 #define HWRM_ENGINE_QG_METER_UNBIND 0x144UL 311 #define HWRM_ENGINE_QG_FUNC_BIND 0x145UL 312 #define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL 313 #define HWRM_ENGINE_SG_QUERY 0x147UL 314 #define HWRM_ENGINE_SG_METER_QUERY 0x148UL 315 #define HWRM_ENGINE_SG_METER_CONFIG 0x149UL 316 #define HWRM_ENGINE_SG_QG_BIND 0x14aUL 317 #define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL 318 #define HWRM_ENGINE_CONFIG_QUERY 0x154UL 319 #define HWRM_ENGINE_STATS_CONFIG 0x155UL 320 #define HWRM_ENGINE_STATS_CLEAR 0x156UL 321 #define HWRM_ENGINE_STATS_QUERY 0x157UL 322 #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR 0x158UL 323 #define HWRM_ENGINE_RQ_ALLOC 0x15eUL 324 #define HWRM_ENGINE_RQ_FREE 0x15fUL 325 #define HWRM_ENGINE_CQ_ALLOC 0x160UL 326 #define HWRM_ENGINE_CQ_FREE 0x161UL 327 #define HWRM_ENGINE_NQ_ALLOC 0x162UL 328 #define HWRM_ENGINE_NQ_FREE 0x163UL 329 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL 330 #define HWRM_ENGINE_FUNC_QCFG 0x165UL 331 #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL 332 #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL 333 #define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL 334 #define HWRM_FUNC_BACKING_STORE_CFG 0x193UL 335 #define HWRM_FUNC_BACKING_STORE_QCFG 0x194UL 336 #define HWRM_FUNC_VF_BW_CFG 0x195UL 337 #define HWRM_FUNC_VF_BW_QCFG 0x196UL 338 #define HWRM_FUNC_HOST_PF_IDS_QUERY 0x197UL 339 #define HWRM_FUNC_QSTATS_EXT 0x198UL 340 #define HWRM_SELFTEST_QLIST 0x200UL 341 #define HWRM_SELFTEST_EXEC 0x201UL 342 #define HWRM_SELFTEST_IRQ 0x202UL 343 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL 344 #define HWRM_PCIE_QSTATS 0x204UL 345 #define HWRM_MFG_FRU_WRITE_CONTROL 0x205UL 346 #define HWRM_MFG_TIMERS_QUERY 0x206UL 347 #define HWRM_MFG_OTP_CFG 0x207UL 348 #define HWRM_MFG_OTP_QCFG 0x208UL 349 #define HWRM_MFG_HDMA_TEST 0x209UL 350 #define HWRM_MFG_FRU_EEPROM_WRITE 0x20aUL 351 #define HWRM_MFG_FRU_EEPROM_READ 0x20bUL 352 #define HWRM_TF 0x2bcUL 353 #define HWRM_TF_VERSION_GET 0x2bdUL 354 #define HWRM_TF_SESSION_OPEN 0x2c6UL 355 #define HWRM_TF_SESSION_ATTACH 0x2c7UL 356 #define HWRM_TF_SESSION_CLOSE 0x2c8UL 357 #define HWRM_TF_SESSION_QCFG 0x2c9UL 358 #define HWRM_TF_SESSION_RESC_QCAPS 0x2caUL 359 #define HWRM_TF_SESSION_RESC_ALLOC 0x2cbUL 360 #define HWRM_TF_SESSION_RESC_FREE 0x2ccUL 361 #define HWRM_TF_SESSION_RESC_FLUSH 0x2cdUL 362 #define HWRM_TF_TBL_TYPE_GET 0x2d0UL 363 #define HWRM_TF_TBL_TYPE_SET 0x2d1UL 364 #define HWRM_TF_CTXT_MEM_RGTR 0x2daUL 365 #define HWRM_TF_CTXT_MEM_UNRGTR 0x2dbUL 366 #define HWRM_TF_EXT_EM_QCAPS 0x2dcUL 367 #define HWRM_TF_EXT_EM_OP 0x2ddUL 368 #define HWRM_TF_EXT_EM_CFG 0x2deUL 369 #define HWRM_TF_EXT_EM_QCFG 0x2dfUL 370 #define HWRM_TF_TCAM_SET 0x2eeUL 371 #define HWRM_TF_TCAM_GET 0x2efUL 372 #define HWRM_TF_TCAM_MOVE 0x2f0UL 373 #define HWRM_TF_TCAM_FREE 0x2f1UL 374 #define HWRM_SV 0x400UL 375 #define HWRM_DBG_READ_DIRECT 0xff10UL 376 #define HWRM_DBG_READ_INDIRECT 0xff11UL 377 #define HWRM_DBG_WRITE_DIRECT 0xff12UL 378 #define HWRM_DBG_WRITE_INDIRECT 0xff13UL 379 #define HWRM_DBG_DUMP 0xff14UL 380 #define HWRM_DBG_ERASE_NVM 0xff15UL 381 #define HWRM_DBG_CFG 0xff16UL 382 #define HWRM_DBG_COREDUMP_LIST 0xff17UL 383 #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL 384 #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL 385 #define HWRM_DBG_FW_CLI 0xff1aUL 386 #define HWRM_DBG_I2C_CMD 0xff1bUL 387 #define HWRM_DBG_RING_INFO_GET 0xff1cUL 388 #define HWRM_DBG_CRASHDUMP_HEADER 0xff1dUL 389 #define HWRM_DBG_CRASHDUMP_ERASE 0xff1eUL 390 #define HWRM_DBG_DRV_TRACE 0xff1fUL 391 #define HWRM_DBG_QCAPS 0xff20UL 392 #define HWRM_DBG_QCFG 0xff21UL 393 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG 0xff22UL 394 #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL 395 #define HWRM_NVM_VALIDATE_OPTION 0xffefUL 396 #define HWRM_NVM_FLUSH 0xfff0UL 397 #define HWRM_NVM_GET_VARIABLE 0xfff1UL 398 #define HWRM_NVM_SET_VARIABLE 0xfff2UL 399 #define HWRM_NVM_INSTALL_UPDATE 0xfff3UL 400 #define HWRM_NVM_MODIFY 0xfff4UL 401 #define HWRM_NVM_VERIFY_UPDATE 0xfff5UL 402 #define HWRM_NVM_GET_DEV_INFO 0xfff6UL 403 #define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL 404 #define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL 405 #define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL 406 #define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL 407 #define HWRM_NVM_GET_DIR_INFO 0xfffbUL 408 #define HWRM_NVM_RAW_DUMP 0xfffcUL 409 #define HWRM_NVM_READ 0xfffdUL 410 #define HWRM_NVM_WRITE 0xfffeUL 411 #define HWRM_NVM_RAW_WRITE_BLK 0xffffUL 412 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK 413 __le16 unused_0[3]; 414 }; 415 416 /* ret_codes (size:64b/8B) */ 417 struct ret_codes { 418 __le16 error_code; 419 #define HWRM_ERR_CODE_SUCCESS 0x0UL 420 #define HWRM_ERR_CODE_FAIL 0x1UL 421 #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL 422 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL 423 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL 424 #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL 425 #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL 426 #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL 427 #define HWRM_ERR_CODE_NO_BUFFER 0x8UL 428 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL 429 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS 0xaUL 430 #define HWRM_ERR_CODE_HOT_RESET_FAIL 0xbUL 431 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC 0xcUL 432 #define HWRM_ERR_CODE_KEY_HASH_COLLISION 0xdUL 433 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS 0xeUL 434 #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL 435 #define HWRM_ERR_CODE_BUSY 0x10UL 436 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL 437 #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL 438 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL 439 #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED 440 __le16 unused_0[3]; 441 }; 442 443 /* hwrm_err_output (size:128b/16B) */ 444 struct hwrm_err_output { 445 __le16 error_code; 446 __le16 req_type; 447 __le16 seq_id; 448 __le16 resp_len; 449 __le32 opaque_0; 450 __le16 opaque_1; 451 u8 cmd_err; 452 u8 valid; 453 }; 454 #define HWRM_NA_SIGNATURE ((__le32)(-1)) 455 #define HWRM_MAX_REQ_LEN 128 456 #define HWRM_MAX_RESP_LEN 704 457 #define HW_HASH_INDEX_SIZE 0x80 458 #define HW_HASH_KEY_SIZE 40 459 #define HWRM_RESP_VALID_KEY 1 460 #define HWRM_TARGET_ID_BONO 0xFFF8 461 #define HWRM_TARGET_ID_KONG 0xFFF9 462 #define HWRM_TARGET_ID_APE 0xFFFA 463 #define HWRM_TARGET_ID_TOOLS 0xFFFD 464 #define HWRM_VERSION_MAJOR 1 465 #define HWRM_VERSION_MINOR 10 466 #define HWRM_VERSION_UPDATE 1 467 #define HWRM_VERSION_RSVD 33 468 #define HWRM_VERSION_STR "1.10.1.33" 469 470 /* hwrm_ver_get_input (size:192b/24B) */ 471 struct hwrm_ver_get_input { 472 __le16 req_type; 473 __le16 cmpl_ring; 474 __le16 seq_id; 475 __le16 target_id; 476 __le64 resp_addr; 477 u8 hwrm_intf_maj; 478 u8 hwrm_intf_min; 479 u8 hwrm_intf_upd; 480 u8 unused_0[5]; 481 }; 482 483 /* hwrm_ver_get_output (size:1408b/176B) */ 484 struct hwrm_ver_get_output { 485 __le16 error_code; 486 __le16 req_type; 487 __le16 seq_id; 488 __le16 resp_len; 489 u8 hwrm_intf_maj_8b; 490 u8 hwrm_intf_min_8b; 491 u8 hwrm_intf_upd_8b; 492 u8 hwrm_intf_rsvd_8b; 493 u8 hwrm_fw_maj_8b; 494 u8 hwrm_fw_min_8b; 495 u8 hwrm_fw_bld_8b; 496 u8 hwrm_fw_rsvd_8b; 497 u8 mgmt_fw_maj_8b; 498 u8 mgmt_fw_min_8b; 499 u8 mgmt_fw_bld_8b; 500 u8 mgmt_fw_rsvd_8b; 501 u8 netctrl_fw_maj_8b; 502 u8 netctrl_fw_min_8b; 503 u8 netctrl_fw_bld_8b; 504 u8 netctrl_fw_rsvd_8b; 505 __le32 dev_caps_cfg; 506 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL 507 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL 508 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL 509 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL 510 #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED 0x10UL 511 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED 0x20UL 512 #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL 513 #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL 514 #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL 515 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED 0x200UL 516 #define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED 0x400UL 517 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED 0x800UL 518 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED 0x1000UL 519 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED 0x2000UL 520 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED 0x4000UL 521 u8 roce_fw_maj_8b; 522 u8 roce_fw_min_8b; 523 u8 roce_fw_bld_8b; 524 u8 roce_fw_rsvd_8b; 525 char hwrm_fw_name[16]; 526 char mgmt_fw_name[16]; 527 char netctrl_fw_name[16]; 528 char active_pkg_name[16]; 529 char roce_fw_name[16]; 530 __le16 chip_num; 531 u8 chip_rev; 532 u8 chip_metal; 533 u8 chip_bond_id; 534 u8 chip_platform_type; 535 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL 536 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL 537 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL 538 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 539 __le16 max_req_win_len; 540 __le16 max_resp_len; 541 __le16 def_req_timeout; 542 u8 flags; 543 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL 544 #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL 545 u8 unused_0[2]; 546 u8 always_1; 547 __le16 hwrm_intf_major; 548 __le16 hwrm_intf_minor; 549 __le16 hwrm_intf_build; 550 __le16 hwrm_intf_patch; 551 __le16 hwrm_fw_major; 552 __le16 hwrm_fw_minor; 553 __le16 hwrm_fw_build; 554 __le16 hwrm_fw_patch; 555 __le16 mgmt_fw_major; 556 __le16 mgmt_fw_minor; 557 __le16 mgmt_fw_build; 558 __le16 mgmt_fw_patch; 559 __le16 netctrl_fw_major; 560 __le16 netctrl_fw_minor; 561 __le16 netctrl_fw_build; 562 __le16 netctrl_fw_patch; 563 __le16 roce_fw_major; 564 __le16 roce_fw_minor; 565 __le16 roce_fw_build; 566 __le16 roce_fw_patch; 567 __le16 max_ext_req_len; 568 u8 unused_1[5]; 569 u8 valid; 570 }; 571 572 /* eject_cmpl (size:128b/16B) */ 573 struct eject_cmpl { 574 __le16 type; 575 #define EJECT_CMPL_TYPE_MASK 0x3fUL 576 #define EJECT_CMPL_TYPE_SFT 0 577 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 578 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT 579 #define EJECT_CMPL_FLAGS_MASK 0xffc0UL 580 #define EJECT_CMPL_FLAGS_SFT 6 581 #define EJECT_CMPL_FLAGS_ERROR 0x40UL 582 __le16 len; 583 __le32 opaque; 584 __le16 v; 585 #define EJECT_CMPL_V 0x1UL 586 #define EJECT_CMPL_ERRORS_MASK 0xfffeUL 587 #define EJECT_CMPL_ERRORS_SFT 1 588 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK 0xeUL 589 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1 590 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1) 591 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1) 592 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1) 593 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (0x5UL << 1) 594 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH 595 __le16 reserved16; 596 __le32 unused_2; 597 }; 598 599 /* hwrm_cmpl (size:128b/16B) */ 600 struct hwrm_cmpl { 601 __le16 type; 602 #define CMPL_TYPE_MASK 0x3fUL 603 #define CMPL_TYPE_SFT 0 604 #define CMPL_TYPE_HWRM_DONE 0x20UL 605 #define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE 606 __le16 sequence_id; 607 __le32 unused_1; 608 __le32 v; 609 #define CMPL_V 0x1UL 610 __le32 unused_3; 611 }; 612 613 /* hwrm_fwd_req_cmpl (size:128b/16B) */ 614 struct hwrm_fwd_req_cmpl { 615 __le16 req_len_type; 616 #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL 617 #define FWD_REQ_CMPL_TYPE_SFT 0 618 #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL 619 #define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 620 #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 621 #define FWD_REQ_CMPL_REQ_LEN_SFT 6 622 __le16 source_id; 623 __le32 unused0; 624 __le32 req_buf_addr_v[2]; 625 #define FWD_REQ_CMPL_V 0x1UL 626 #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 627 #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 628 }; 629 630 /* hwrm_fwd_resp_cmpl (size:128b/16B) */ 631 struct hwrm_fwd_resp_cmpl { 632 __le16 type; 633 #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL 634 #define FWD_RESP_CMPL_TYPE_SFT 0 635 #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL 636 #define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 637 __le16 source_id; 638 __le16 resp_len; 639 __le16 unused_1; 640 __le32 resp_buf_addr_v[2]; 641 #define FWD_RESP_CMPL_V 0x1UL 642 #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 643 #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 644 }; 645 646 /* hwrm_async_event_cmpl (size:128b/16B) */ 647 struct hwrm_async_event_cmpl { 648 __le16 type; 649 #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 650 #define ASYNC_EVENT_CMPL_TYPE_SFT 0 651 #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 652 #define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 653 __le16 event_id; 654 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 655 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL 656 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 657 #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 658 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 659 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 660 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 661 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL 662 #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 0x8UL 663 #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY 0x9UL 664 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 665 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 666 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 667 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 668 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL 669 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL 670 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 671 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 672 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 673 #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL 674 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL 675 #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL 676 #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION 0x37UL 677 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 678 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 679 #define ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE 0x3aUL 680 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE 0x3bUL 681 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE 0x3cUL 682 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE 0x3dUL 683 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE 0x3eUL 684 #define ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE 0x3fUL 685 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE 0x40UL 686 #define ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE 0x41UL 687 #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL 688 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 689 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 690 __le32 event_data2; 691 u8 opaque_v; 692 #define ASYNC_EVENT_CMPL_V 0x1UL 693 #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 694 #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1 695 u8 timestamp_lo; 696 __le16 timestamp_hi; 697 __le32 event_data1; 698 }; 699 700 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */ 701 struct hwrm_async_event_cmpl_link_status_change { 702 __le16 type; 703 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 704 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 705 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 706 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 707 __le16 event_id; 708 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 709 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 710 __le32 event_data2; 711 u8 opaque_v; 712 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 713 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 714 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 715 u8 timestamp_lo; 716 __le16 timestamp_hi; 717 __le32 event_data1; 718 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 719 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL 720 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL 721 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 722 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 723 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 724 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 725 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 726 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK 0xff00000UL 727 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT 20 728 }; 729 730 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */ 731 struct hwrm_async_event_cmpl_port_conn_not_allowed { 732 __le16 type; 733 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 734 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 735 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 736 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 737 __le16 event_id; 738 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 739 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 740 __le32 event_data2; 741 u8 opaque_v; 742 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 743 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 744 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 745 u8 timestamp_lo; 746 __le16 timestamp_hi; 747 __le32 event_data1; 748 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 749 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 750 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 751 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 752 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 753 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 754 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 755 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 756 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 757 }; 758 759 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */ 760 struct hwrm_async_event_cmpl_link_speed_cfg_change { 761 __le16 type; 762 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 763 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 764 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 765 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 766 __le16 event_id; 767 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 768 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 769 __le32 event_data2; 770 u8 opaque_v; 771 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 772 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 773 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 774 u8 timestamp_lo; 775 __le16 timestamp_hi; 776 __le32 event_data1; 777 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 778 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 779 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 780 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 781 }; 782 783 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */ 784 struct hwrm_async_event_cmpl_reset_notify { 785 __le16 type; 786 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK 0x3fUL 787 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0 788 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 789 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 790 __le16 event_id; 791 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL 792 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 793 __le32 event_data2; 794 u8 opaque_v; 795 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V 0x1UL 796 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL 797 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1 798 u8 timestamp_lo; 799 __le16 timestamp_hi; 800 __le32 event_data1; 801 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK 0xffUL 802 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT 0 803 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE 0x1UL 804 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 0x2UL 805 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 806 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK 0xff00UL 807 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT 8 808 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (0x1UL << 8) 809 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (0x2UL << 8) 810 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (0x3UL << 8) 811 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL 812 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK 0xffff0000UL 813 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT 16 814 }; 815 816 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */ 817 struct hwrm_async_event_cmpl_error_recovery { 818 __le16 type; 819 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK 0x3fUL 820 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0 821 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 822 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 823 __le16 event_id; 824 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 0x9UL 825 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 826 __le32 event_data2; 827 u8 opaque_v; 828 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_V 0x1UL 829 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK 0xfeUL 830 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1 831 u8 timestamp_lo; 832 __le16 timestamp_hi; 833 __le32 event_data1; 834 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK 0xffUL 835 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT 0 836 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC 0x1UL 837 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED 0x2UL 838 }; 839 840 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */ 841 struct hwrm_async_event_cmpl_vf_cfg_change { 842 __le16 type; 843 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 844 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 845 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 846 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 847 __le16 event_id; 848 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL 849 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 850 __le32 event_data2; 851 u8 opaque_v; 852 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 853 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 854 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 855 u8 timestamp_lo; 856 __le16 timestamp_hi; 857 __le32 event_data1; 858 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 859 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 860 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 861 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 862 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL 863 }; 864 865 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */ 866 struct hwrm_async_event_cmpl_default_vnic_change { 867 __le16 type; 868 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK 0x3fUL 869 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT 0 870 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 871 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 872 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK 0xffc0UL 873 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT 6 874 __le16 event_id; 875 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 0x35UL 876 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 877 __le32 event_data2; 878 u8 opaque_v; 879 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V 0x1UL 880 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK 0xfeUL 881 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1 882 u8 timestamp_lo; 883 __le16 timestamp_hi; 884 __le32 event_data1; 885 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK 0x3UL 886 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 0 887 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC 0x1UL 888 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 0x2UL 889 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 890 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK 0x3fcUL 891 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT 2 892 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK 0x3fffc00UL 893 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT 10 894 }; 895 896 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */ 897 struct hwrm_async_event_cmpl_hw_flow_aged { 898 __le16 type; 899 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK 0x3fUL 900 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0 901 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 902 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 903 __le16 event_id; 904 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL 905 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 906 __le32 event_data2; 907 u8 opaque_v; 908 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V 0x1UL 909 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL 910 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1 911 u8 timestamp_lo; 912 __le16 timestamp_hi; 913 __le32 event_data1; 914 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK 0x7fffffffUL 915 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT 0 916 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION 0x80000000UL 917 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX (0x0UL << 31) 918 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX (0x1UL << 31) 919 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX 920 }; 921 922 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */ 923 struct hwrm_async_event_cmpl_eem_cache_flush_req { 924 __le16 type; 925 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK 0x3fUL 926 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT 0 927 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 0x2eUL 928 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 929 __le16 event_id; 930 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 931 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 932 __le32 event_data2; 933 u8 opaque_v; 934 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V 0x1UL 935 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL 936 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1 937 u8 timestamp_lo; 938 __le16 timestamp_hi; 939 __le32 event_data1; 940 }; 941 942 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */ 943 struct hwrm_async_event_cmpl_eem_cache_flush_done { 944 __le16 type; 945 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK 0x3fUL 946 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT 0 947 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 948 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 949 __le16 event_id; 950 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 951 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 952 __le32 event_data2; 953 u8 opaque_v; 954 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V 0x1UL 955 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL 956 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1 957 u8 timestamp_lo; 958 __le16 timestamp_hi; 959 __le32 event_data1; 960 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL 961 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0 962 }; 963 964 /* hwrm_func_reset_input (size:192b/24B) */ 965 struct hwrm_func_reset_input { 966 __le16 req_type; 967 __le16 cmpl_ring; 968 __le16 seq_id; 969 __le16 target_id; 970 __le64 resp_addr; 971 __le32 enables; 972 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 973 __le16 vf_id; 974 u8 func_reset_level; 975 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL 976 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 977 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL 978 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL 979 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 980 u8 unused_0; 981 }; 982 983 /* hwrm_func_reset_output (size:128b/16B) */ 984 struct hwrm_func_reset_output { 985 __le16 error_code; 986 __le16 req_type; 987 __le16 seq_id; 988 __le16 resp_len; 989 u8 unused_0[7]; 990 u8 valid; 991 }; 992 993 /* hwrm_func_getfid_input (size:192b/24B) */ 994 struct hwrm_func_getfid_input { 995 __le16 req_type; 996 __le16 cmpl_ring; 997 __le16 seq_id; 998 __le16 target_id; 999 __le64 resp_addr; 1000 __le32 enables; 1001 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 1002 __le16 pci_id; 1003 u8 unused_0[2]; 1004 }; 1005 1006 /* hwrm_func_getfid_output (size:128b/16B) */ 1007 struct hwrm_func_getfid_output { 1008 __le16 error_code; 1009 __le16 req_type; 1010 __le16 seq_id; 1011 __le16 resp_len; 1012 __le16 fid; 1013 u8 unused_0[5]; 1014 u8 valid; 1015 }; 1016 1017 /* hwrm_func_vf_alloc_input (size:192b/24B) */ 1018 struct hwrm_func_vf_alloc_input { 1019 __le16 req_type; 1020 __le16 cmpl_ring; 1021 __le16 seq_id; 1022 __le16 target_id; 1023 __le64 resp_addr; 1024 __le32 enables; 1025 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 1026 __le16 first_vf_id; 1027 __le16 num_vfs; 1028 }; 1029 1030 /* hwrm_func_vf_alloc_output (size:128b/16B) */ 1031 struct hwrm_func_vf_alloc_output { 1032 __le16 error_code; 1033 __le16 req_type; 1034 __le16 seq_id; 1035 __le16 resp_len; 1036 __le16 first_vf_id; 1037 u8 unused_0[5]; 1038 u8 valid; 1039 }; 1040 1041 /* hwrm_func_vf_free_input (size:192b/24B) */ 1042 struct hwrm_func_vf_free_input { 1043 __le16 req_type; 1044 __le16 cmpl_ring; 1045 __le16 seq_id; 1046 __le16 target_id; 1047 __le64 resp_addr; 1048 __le32 enables; 1049 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 1050 __le16 first_vf_id; 1051 __le16 num_vfs; 1052 }; 1053 1054 /* hwrm_func_vf_free_output (size:128b/16B) */ 1055 struct hwrm_func_vf_free_output { 1056 __le16 error_code; 1057 __le16 req_type; 1058 __le16 seq_id; 1059 __le16 resp_len; 1060 u8 unused_0[7]; 1061 u8 valid; 1062 }; 1063 1064 /* hwrm_func_vf_cfg_input (size:448b/56B) */ 1065 struct hwrm_func_vf_cfg_input { 1066 __le16 req_type; 1067 __le16 cmpl_ring; 1068 __le16 seq_id; 1069 __le16 target_id; 1070 __le64 resp_addr; 1071 __le32 enables; 1072 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 1073 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 1074 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 1075 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 1076 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL 1077 #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL 1078 #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL 1079 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL 1080 #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL 1081 #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL 1082 #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL 1083 #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL 1084 __le16 mtu; 1085 __le16 guest_vlan; 1086 __le16 async_event_cr; 1087 u8 dflt_mac_addr[6]; 1088 __le32 flags; 1089 #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL 1090 #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL 1091 #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL 1092 #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL 1093 #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL 1094 #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL 1095 #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL 1096 #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL 1097 __le16 num_rsscos_ctxs; 1098 __le16 num_cmpl_rings; 1099 __le16 num_tx_rings; 1100 __le16 num_rx_rings; 1101 __le16 num_l2_ctxs; 1102 __le16 num_vnics; 1103 __le16 num_stat_ctxs; 1104 __le16 num_hw_ring_grps; 1105 u8 unused_0[4]; 1106 }; 1107 1108 /* hwrm_func_vf_cfg_output (size:128b/16B) */ 1109 struct hwrm_func_vf_cfg_output { 1110 __le16 error_code; 1111 __le16 req_type; 1112 __le16 seq_id; 1113 __le16 resp_len; 1114 u8 unused_0[7]; 1115 u8 valid; 1116 }; 1117 1118 /* hwrm_func_qcaps_input (size:192b/24B) */ 1119 struct hwrm_func_qcaps_input { 1120 __le16 req_type; 1121 __le16 cmpl_ring; 1122 __le16 seq_id; 1123 __le16 target_id; 1124 __le64 resp_addr; 1125 __le16 fid; 1126 u8 unused_0[6]; 1127 }; 1128 1129 /* hwrm_func_qcaps_output (size:704b/88B) */ 1130 struct hwrm_func_qcaps_output { 1131 __le16 error_code; 1132 __le16 req_type; 1133 __le16 seq_id; 1134 __le16 resp_len; 1135 __le16 fid; 1136 __le16 port_id; 1137 __le32 flags; 1138 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 1139 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 1140 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 1141 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 1142 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 1143 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 1144 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL 1145 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 1146 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 1147 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 1148 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 1149 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL 1150 #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL 1151 #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL 1152 #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL 1153 #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL 1154 #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL 1155 #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL 1156 #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL 1157 #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL 1158 #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL 1159 #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL 1160 #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL 1161 #define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE 0x800000UL 1162 #define FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED 0x1000000UL 1163 #define FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD 0x2000000UL 1164 #define FUNC_QCAPS_RESP_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED 0x4000000UL 1165 #define FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED 0x8000000UL 1166 #define FUNC_QCAPS_RESP_FLAGS_COREDUMP_CMD_SUPPORTED 0x10000000UL 1167 #define FUNC_QCAPS_RESP_FLAGS_CRASHDUMP_CMD_SUPPORTED 0x20000000UL 1168 #define FUNC_QCAPS_RESP_FLAGS_PFC_WD_STATS_SUPPORTED 0x40000000UL 1169 #define FUNC_QCAPS_RESP_FLAGS_DBG_QCAPS_CMD_SUPPORTED 0x80000000UL 1170 u8 mac_address[6]; 1171 __le16 max_rsscos_ctx; 1172 __le16 max_cmpl_rings; 1173 __le16 max_tx_rings; 1174 __le16 max_rx_rings; 1175 __le16 max_l2_ctxs; 1176 __le16 max_vnics; 1177 __le16 first_vf_id; 1178 __le16 max_vfs; 1179 __le16 max_stat_ctx; 1180 __le32 max_encap_records; 1181 __le32 max_decap_records; 1182 __le32 max_tx_em_flows; 1183 __le32 max_tx_wm_flows; 1184 __le32 max_rx_em_flows; 1185 __le32 max_rx_wm_flows; 1186 __le32 max_mcast_filters; 1187 __le32 max_flow_id; 1188 __le32 max_hw_ring_grps; 1189 __le16 max_sp_tx_rings; 1190 u8 unused_0[2]; 1191 __le32 flags_ext; 1192 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_MARK_SUPPORTED 0x1UL 1193 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_STATS_SUPPORTED 0x2UL 1194 #define FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED 0x4UL 1195 u8 unused_1[3]; 1196 u8 valid; 1197 }; 1198 1199 /* hwrm_func_qcfg_input (size:192b/24B) */ 1200 struct hwrm_func_qcfg_input { 1201 __le16 req_type; 1202 __le16 cmpl_ring; 1203 __le16 seq_id; 1204 __le16 target_id; 1205 __le64 resp_addr; 1206 __le16 fid; 1207 u8 unused_0[6]; 1208 }; 1209 1210 /* hwrm_func_qcfg_output (size:768b/96B) */ 1211 struct hwrm_func_qcfg_output { 1212 __le16 error_code; 1213 __le16 req_type; 1214 __le16 seq_id; 1215 __le16 resp_len; 1216 __le16 fid; 1217 __le16 port_id; 1218 __le16 vlan; 1219 __le16 flags; 1220 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL 1221 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL 1222 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL 1223 #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL 1224 #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL 1225 #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL 1226 #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL 1227 #define FUNC_QCFG_RESP_FLAGS_SECURE_MODE_ENABLED 0x80UL 1228 #define FUNC_QCFG_RESP_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x100UL 1229 u8 mac_address[6]; 1230 __le16 pci_id; 1231 __le16 alloc_rsscos_ctx; 1232 __le16 alloc_cmpl_rings; 1233 __le16 alloc_tx_rings; 1234 __le16 alloc_rx_rings; 1235 __le16 alloc_l2_ctx; 1236 __le16 alloc_vnics; 1237 __le16 mtu; 1238 __le16 mru; 1239 __le16 stat_ctx_id; 1240 u8 port_partition_type; 1241 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL 1242 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL 1243 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 1244 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL 1245 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL 1246 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL 1247 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 1248 u8 port_pf_cnt; 1249 #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL 1250 #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 1251 __le16 dflt_vnic_id; 1252 __le16 max_mtu_configured; 1253 __le32 min_bw; 1254 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1255 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0 1256 #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL 1257 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28) 1258 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28) 1259 #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES 1260 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1261 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29 1262 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1263 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1264 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1265 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1266 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1267 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1268 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID 1269 __le32 max_bw; 1270 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1271 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0 1272 #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL 1273 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28) 1274 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28) 1275 #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES 1276 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1277 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29 1278 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1279 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1280 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1281 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1282 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1283 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1284 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID 1285 u8 evb_mode; 1286 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL 1287 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL 1288 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 1289 #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA 1290 u8 options; 1291 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1292 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0 1293 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1294 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1295 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 1296 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 1297 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT 2 1298 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 1299 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 1300 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 1301 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO 1302 #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xf0UL 1303 #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 4 1304 __le16 alloc_vfs; 1305 __le32 alloc_mcast_filters; 1306 __le32 alloc_hw_ring_grps; 1307 __le16 alloc_sp_tx_rings; 1308 __le16 alloc_stat_ctx; 1309 __le16 alloc_msix; 1310 __le16 registered_vfs; 1311 __le16 l2_doorbell_bar_size_kb; 1312 u8 unused_1; 1313 u8 always_1; 1314 __le32 reset_addr_poll; 1315 __le16 legacy_l2_db_size_kb; 1316 __le16 svif_info; 1317 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_MASK 0x7fffUL 1318 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_SFT 0 1319 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_VALID 0x8000UL 1320 u8 unused_2[7]; 1321 u8 valid; 1322 }; 1323 1324 /* hwrm_func_cfg_input (size:704b/88B) */ 1325 struct hwrm_func_cfg_input { 1326 __le16 req_type; 1327 __le16 cmpl_ring; 1328 __le16 seq_id; 1329 __le16 target_id; 1330 __le64 resp_addr; 1331 __le16 fid; 1332 __le16 num_msix; 1333 __le32 flags; 1334 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL 1335 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL 1336 #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL 1337 #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2 1338 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL 1339 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL 1340 #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL 1341 #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL 1342 #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL 1343 #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL 1344 #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL 1345 #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL 1346 #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL 1347 #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL 1348 #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL 1349 #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL 1350 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL 1351 #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC 0x400000UL 1352 #define FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST 0x800000UL 1353 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_DISABLE 0x1000000UL 1354 #define FUNC_CFG_REQ_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x2000000UL 1355 __le32 enables; 1356 #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL 1357 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 1358 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 1359 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 1360 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 1361 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 1362 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 1363 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 1364 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 1365 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 1366 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 1367 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 1368 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 1369 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 1370 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 1371 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 1372 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 1373 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 1374 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 1375 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 1376 #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL 1377 #define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL 1378 #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL 1379 __le16 mtu; 1380 __le16 mru; 1381 __le16 num_rsscos_ctxs; 1382 __le16 num_cmpl_rings; 1383 __le16 num_tx_rings; 1384 __le16 num_rx_rings; 1385 __le16 num_l2_ctxs; 1386 __le16 num_vnics; 1387 __le16 num_stat_ctxs; 1388 __le16 num_hw_ring_grps; 1389 u8 dflt_mac_addr[6]; 1390 __le16 dflt_vlan; 1391 __be32 dflt_ip_addr[4]; 1392 __le32 min_bw; 1393 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1394 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0 1395 #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL 1396 #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28) 1397 #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28) 1398 #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES 1399 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1400 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29 1401 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1402 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1403 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1404 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1405 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1406 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1407 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID 1408 __le32 max_bw; 1409 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1410 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0 1411 #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL 1412 #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 1413 #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 1414 #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES 1415 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1416 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 1417 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1418 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1419 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1420 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1421 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1422 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1423 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 1424 __le16 async_event_cr; 1425 u8 vlan_antispoof_mode; 1426 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL 1427 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL 1428 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL 1429 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL 1430 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 1431 u8 allowed_vlan_pris; 1432 u8 evb_mode; 1433 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL 1434 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL 1435 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 1436 #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA 1437 u8 options; 1438 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1439 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0 1440 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1441 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1442 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 1443 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 1444 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT 2 1445 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 1446 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 1447 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 1448 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO 1449 #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xf0UL 1450 #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 4 1451 __le16 num_mcast_filters; 1452 }; 1453 1454 /* hwrm_func_cfg_output (size:128b/16B) */ 1455 struct hwrm_func_cfg_output { 1456 __le16 error_code; 1457 __le16 req_type; 1458 __le16 seq_id; 1459 __le16 resp_len; 1460 u8 unused_0[7]; 1461 u8 valid; 1462 }; 1463 1464 /* hwrm_func_qstats_input (size:192b/24B) */ 1465 struct hwrm_func_qstats_input { 1466 __le16 req_type; 1467 __le16 cmpl_ring; 1468 __le16 seq_id; 1469 __le16 target_id; 1470 __le64 resp_addr; 1471 __le16 fid; 1472 u8 flags; 1473 #define FUNC_QSTATS_REQ_FLAGS_UNUSED 0x0UL 1474 #define FUNC_QSTATS_REQ_FLAGS_ROCE_ONLY 0x1UL 1475 #define FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x2UL 1476 #define FUNC_QSTATS_REQ_FLAGS_LAST FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 1477 u8 unused_0[5]; 1478 }; 1479 1480 /* hwrm_func_qstats_output (size:1408b/176B) */ 1481 struct hwrm_func_qstats_output { 1482 __le16 error_code; 1483 __le16 req_type; 1484 __le16 seq_id; 1485 __le16 resp_len; 1486 __le64 tx_ucast_pkts; 1487 __le64 tx_mcast_pkts; 1488 __le64 tx_bcast_pkts; 1489 __le64 tx_discard_pkts; 1490 __le64 tx_drop_pkts; 1491 __le64 tx_ucast_bytes; 1492 __le64 tx_mcast_bytes; 1493 __le64 tx_bcast_bytes; 1494 __le64 rx_ucast_pkts; 1495 __le64 rx_mcast_pkts; 1496 __le64 rx_bcast_pkts; 1497 __le64 rx_discard_pkts; 1498 __le64 rx_drop_pkts; 1499 __le64 rx_ucast_bytes; 1500 __le64 rx_mcast_bytes; 1501 __le64 rx_bcast_bytes; 1502 __le64 rx_agg_pkts; 1503 __le64 rx_agg_bytes; 1504 __le64 rx_agg_events; 1505 __le64 rx_agg_aborts; 1506 u8 unused_0[7]; 1507 u8 valid; 1508 }; 1509 1510 /* hwrm_func_qstats_ext_input (size:192b/24B) */ 1511 struct hwrm_func_qstats_ext_input { 1512 __le16 req_type; 1513 __le16 cmpl_ring; 1514 __le16 seq_id; 1515 __le16 target_id; 1516 __le64 resp_addr; 1517 __le16 fid; 1518 u8 flags; 1519 #define FUNC_QSTATS_EXT_REQ_FLAGS_UNUSED 0x0UL 1520 #define FUNC_QSTATS_EXT_REQ_FLAGS_ROCE_ONLY 0x1UL 1521 #define FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x2UL 1522 #define FUNC_QSTATS_EXT_REQ_FLAGS_LAST FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 1523 u8 unused_0[5]; 1524 }; 1525 1526 /* hwrm_func_qstats_ext_output (size:1472b/184B) */ 1527 struct hwrm_func_qstats_ext_output { 1528 __le16 error_code; 1529 __le16 req_type; 1530 __le16 seq_id; 1531 __le16 resp_len; 1532 __le64 rx_ucast_pkts; 1533 __le64 rx_mcast_pkts; 1534 __le64 rx_bcast_pkts; 1535 __le64 rx_discard_pkts; 1536 __le64 rx_drop_pkts; 1537 __le64 rx_ucast_bytes; 1538 __le64 rx_mcast_bytes; 1539 __le64 rx_bcast_bytes; 1540 __le64 tx_ucast_pkts; 1541 __le64 tx_mcast_pkts; 1542 __le64 tx_bcast_pkts; 1543 __le64 tx_discard_pkts; 1544 __le64 tx_drop_pkts; 1545 __le64 tx_ucast_bytes; 1546 __le64 tx_mcast_bytes; 1547 __le64 tx_bcast_bytes; 1548 __le64 rx_tpa_eligible_pkt; 1549 __le64 rx_tpa_eligible_bytes; 1550 __le64 rx_tpa_pkt; 1551 __le64 rx_tpa_bytes; 1552 __le64 rx_tpa_errors; 1553 u8 unused_0[7]; 1554 u8 valid; 1555 }; 1556 1557 /* hwrm_func_clr_stats_input (size:192b/24B) */ 1558 struct hwrm_func_clr_stats_input { 1559 __le16 req_type; 1560 __le16 cmpl_ring; 1561 __le16 seq_id; 1562 __le16 target_id; 1563 __le64 resp_addr; 1564 __le16 fid; 1565 u8 unused_0[6]; 1566 }; 1567 1568 /* hwrm_func_clr_stats_output (size:128b/16B) */ 1569 struct hwrm_func_clr_stats_output { 1570 __le16 error_code; 1571 __le16 req_type; 1572 __le16 seq_id; 1573 __le16 resp_len; 1574 u8 unused_0[7]; 1575 u8 valid; 1576 }; 1577 1578 /* hwrm_func_vf_resc_free_input (size:192b/24B) */ 1579 struct hwrm_func_vf_resc_free_input { 1580 __le16 req_type; 1581 __le16 cmpl_ring; 1582 __le16 seq_id; 1583 __le16 target_id; 1584 __le64 resp_addr; 1585 __le16 vf_id; 1586 u8 unused_0[6]; 1587 }; 1588 1589 /* hwrm_func_vf_resc_free_output (size:128b/16B) */ 1590 struct hwrm_func_vf_resc_free_output { 1591 __le16 error_code; 1592 __le16 req_type; 1593 __le16 seq_id; 1594 __le16 resp_len; 1595 u8 unused_0[7]; 1596 u8 valid; 1597 }; 1598 1599 /* hwrm_func_drv_rgtr_input (size:896b/112B) */ 1600 struct hwrm_func_drv_rgtr_input { 1601 __le16 req_type; 1602 __le16 cmpl_ring; 1603 __le16 seq_id; 1604 __le16 target_id; 1605 __le64 resp_addr; 1606 __le32 flags; 1607 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 1608 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 1609 #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL 1610 #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL 1611 #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL 1612 #define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT 0x20UL 1613 #define FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT 0x40UL 1614 __le32 enables; 1615 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 1616 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 1617 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 1618 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 1619 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 1620 __le16 os_type; 1621 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL 1622 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 1623 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL 1624 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL 1625 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL 1626 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL 1627 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL 1628 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL 1629 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL 1630 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL 1631 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL 1632 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 1633 u8 ver_maj_8b; 1634 u8 ver_min_8b; 1635 u8 ver_upd_8b; 1636 u8 unused_0[3]; 1637 __le32 timestamp; 1638 u8 unused_1[4]; 1639 __le32 vf_req_fwd[8]; 1640 __le32 async_event_fwd[8]; 1641 __le16 ver_maj; 1642 __le16 ver_min; 1643 __le16 ver_upd; 1644 __le16 ver_patch; 1645 }; 1646 1647 /* hwrm_func_drv_rgtr_output (size:128b/16B) */ 1648 struct hwrm_func_drv_rgtr_output { 1649 __le16 error_code; 1650 __le16 req_type; 1651 __le16 seq_id; 1652 __le16 resp_len; 1653 __le32 flags; 1654 #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED 0x1UL 1655 u8 unused_0[3]; 1656 u8 valid; 1657 }; 1658 1659 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */ 1660 struct hwrm_func_drv_unrgtr_input { 1661 __le16 req_type; 1662 __le16 cmpl_ring; 1663 __le16 seq_id; 1664 __le16 target_id; 1665 __le64 resp_addr; 1666 __le32 flags; 1667 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 1668 u8 unused_0[4]; 1669 }; 1670 1671 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */ 1672 struct hwrm_func_drv_unrgtr_output { 1673 __le16 error_code; 1674 __le16 req_type; 1675 __le16 seq_id; 1676 __le16 resp_len; 1677 u8 unused_0[7]; 1678 u8 valid; 1679 }; 1680 1681 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */ 1682 struct hwrm_func_buf_rgtr_input { 1683 __le16 req_type; 1684 __le16 cmpl_ring; 1685 __le16 seq_id; 1686 __le16 target_id; 1687 __le64 resp_addr; 1688 __le32 enables; 1689 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 1690 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 1691 __le16 vf_id; 1692 __le16 req_buf_num_pages; 1693 __le16 req_buf_page_size; 1694 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL 1695 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL 1696 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL 1697 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL 1698 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL 1699 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL 1700 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL 1701 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 1702 __le16 req_buf_len; 1703 __le16 resp_buf_len; 1704 u8 unused_0[2]; 1705 __le64 req_buf_page_addr0; 1706 __le64 req_buf_page_addr1; 1707 __le64 req_buf_page_addr2; 1708 __le64 req_buf_page_addr3; 1709 __le64 req_buf_page_addr4; 1710 __le64 req_buf_page_addr5; 1711 __le64 req_buf_page_addr6; 1712 __le64 req_buf_page_addr7; 1713 __le64 req_buf_page_addr8; 1714 __le64 req_buf_page_addr9; 1715 __le64 error_buf_addr; 1716 __le64 resp_buf_addr; 1717 }; 1718 1719 /* hwrm_func_buf_rgtr_output (size:128b/16B) */ 1720 struct hwrm_func_buf_rgtr_output { 1721 __le16 error_code; 1722 __le16 req_type; 1723 __le16 seq_id; 1724 __le16 resp_len; 1725 u8 unused_0[7]; 1726 u8 valid; 1727 }; 1728 1729 /* hwrm_func_drv_qver_input (size:192b/24B) */ 1730 struct hwrm_func_drv_qver_input { 1731 __le16 req_type; 1732 __le16 cmpl_ring; 1733 __le16 seq_id; 1734 __le16 target_id; 1735 __le64 resp_addr; 1736 __le32 reserved; 1737 __le16 fid; 1738 u8 unused_0[2]; 1739 }; 1740 1741 /* hwrm_func_drv_qver_output (size:256b/32B) */ 1742 struct hwrm_func_drv_qver_output { 1743 __le16 error_code; 1744 __le16 req_type; 1745 __le16 seq_id; 1746 __le16 resp_len; 1747 __le16 os_type; 1748 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL 1749 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL 1750 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL 1751 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL 1752 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL 1753 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL 1754 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL 1755 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL 1756 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL 1757 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL 1758 #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL 1759 #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 1760 u8 ver_maj_8b; 1761 u8 ver_min_8b; 1762 u8 ver_upd_8b; 1763 u8 unused_0[3]; 1764 __le16 ver_maj; 1765 __le16 ver_min; 1766 __le16 ver_upd; 1767 __le16 ver_patch; 1768 u8 unused_1[7]; 1769 u8 valid; 1770 }; 1771 1772 /* hwrm_func_resource_qcaps_input (size:192b/24B) */ 1773 struct hwrm_func_resource_qcaps_input { 1774 __le16 req_type; 1775 __le16 cmpl_ring; 1776 __le16 seq_id; 1777 __le16 target_id; 1778 __le64 resp_addr; 1779 __le16 fid; 1780 u8 unused_0[6]; 1781 }; 1782 1783 /* hwrm_func_resource_qcaps_output (size:448b/56B) */ 1784 struct hwrm_func_resource_qcaps_output { 1785 __le16 error_code; 1786 __le16 req_type; 1787 __le16 seq_id; 1788 __le16 resp_len; 1789 __le16 max_vfs; 1790 __le16 max_msix; 1791 __le16 vf_reservation_strategy; 1792 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL 1793 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL 1794 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL 1795 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 1796 __le16 min_rsscos_ctx; 1797 __le16 max_rsscos_ctx; 1798 __le16 min_cmpl_rings; 1799 __le16 max_cmpl_rings; 1800 __le16 min_tx_rings; 1801 __le16 max_tx_rings; 1802 __le16 min_rx_rings; 1803 __le16 max_rx_rings; 1804 __le16 min_l2_ctxs; 1805 __le16 max_l2_ctxs; 1806 __le16 min_vnics; 1807 __le16 max_vnics; 1808 __le16 min_stat_ctx; 1809 __le16 max_stat_ctx; 1810 __le16 min_hw_ring_grps; 1811 __le16 max_hw_ring_grps; 1812 __le16 max_tx_scheduler_inputs; 1813 __le16 flags; 1814 #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED 0x1UL 1815 u8 unused_0[5]; 1816 u8 valid; 1817 }; 1818 1819 /* hwrm_func_vf_resource_cfg_input (size:448b/56B) */ 1820 struct hwrm_func_vf_resource_cfg_input { 1821 __le16 req_type; 1822 __le16 cmpl_ring; 1823 __le16 seq_id; 1824 __le16 target_id; 1825 __le64 resp_addr; 1826 __le16 vf_id; 1827 __le16 max_msix; 1828 __le16 min_rsscos_ctx; 1829 __le16 max_rsscos_ctx; 1830 __le16 min_cmpl_rings; 1831 __le16 max_cmpl_rings; 1832 __le16 min_tx_rings; 1833 __le16 max_tx_rings; 1834 __le16 min_rx_rings; 1835 __le16 max_rx_rings; 1836 __le16 min_l2_ctxs; 1837 __le16 max_l2_ctxs; 1838 __le16 min_vnics; 1839 __le16 max_vnics; 1840 __le16 min_stat_ctx; 1841 __le16 max_stat_ctx; 1842 __le16 min_hw_ring_grps; 1843 __le16 max_hw_ring_grps; 1844 __le16 flags; 1845 #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED 0x1UL 1846 u8 unused_0[2]; 1847 }; 1848 1849 /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */ 1850 struct hwrm_func_vf_resource_cfg_output { 1851 __le16 error_code; 1852 __le16 req_type; 1853 __le16 seq_id; 1854 __le16 resp_len; 1855 __le16 reserved_rsscos_ctx; 1856 __le16 reserved_cmpl_rings; 1857 __le16 reserved_tx_rings; 1858 __le16 reserved_rx_rings; 1859 __le16 reserved_l2_ctxs; 1860 __le16 reserved_vnics; 1861 __le16 reserved_stat_ctx; 1862 __le16 reserved_hw_ring_grps; 1863 u8 unused_0[7]; 1864 u8 valid; 1865 }; 1866 1867 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */ 1868 struct hwrm_func_backing_store_qcaps_input { 1869 __le16 req_type; 1870 __le16 cmpl_ring; 1871 __le16 seq_id; 1872 __le16 target_id; 1873 __le64 resp_addr; 1874 }; 1875 1876 /* hwrm_func_backing_store_qcaps_output (size:640b/80B) */ 1877 struct hwrm_func_backing_store_qcaps_output { 1878 __le16 error_code; 1879 __le16 req_type; 1880 __le16 seq_id; 1881 __le16 resp_len; 1882 __le32 qp_max_entries; 1883 __le16 qp_min_qp1_entries; 1884 __le16 qp_max_l2_entries; 1885 __le16 qp_entry_size; 1886 __le16 srq_max_l2_entries; 1887 __le32 srq_max_entries; 1888 __le16 srq_entry_size; 1889 __le16 cq_max_l2_entries; 1890 __le32 cq_max_entries; 1891 __le16 cq_entry_size; 1892 __le16 vnic_max_vnic_entries; 1893 __le16 vnic_max_ring_table_entries; 1894 __le16 vnic_entry_size; 1895 __le32 stat_max_entries; 1896 __le16 stat_entry_size; 1897 __le16 tqm_entry_size; 1898 __le32 tqm_min_entries_per_ring; 1899 __le32 tqm_max_entries_per_ring; 1900 __le32 mrav_max_entries; 1901 __le16 mrav_entry_size; 1902 __le16 tim_entry_size; 1903 __le32 tim_max_entries; 1904 __le16 mrav_num_entries_units; 1905 u8 tqm_entries_multiple; 1906 u8 ctx_kind_initializer; 1907 __le32 rsvd; 1908 __le16 rsvd1; 1909 u8 tqm_fp_rings_count; 1910 u8 valid; 1911 }; 1912 1913 /* hwrm_func_backing_store_cfg_input (size:2048b/256B) */ 1914 struct hwrm_func_backing_store_cfg_input { 1915 __le16 req_type; 1916 __le16 cmpl_ring; 1917 __le16 seq_id; 1918 __le16 target_id; 1919 __le64 resp_addr; 1920 __le32 flags; 1921 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL 1922 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT 0x2UL 1923 __le32 enables; 1924 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL 1925 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL 1926 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL 1927 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL 1928 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL 1929 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL 1930 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL 1931 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL 1932 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL 1933 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL 1934 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL 1935 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL 1936 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL 1937 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL 1938 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL 1939 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL 1940 u8 qpc_pg_size_qpc_lvl; 1941 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL 1942 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0 1943 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0 0x0UL 1944 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1 0x1UL 1945 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 0x2UL 1946 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 1947 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK 0xf0UL 1948 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT 4 1949 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K (0x0UL << 4) 1950 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K (0x1UL << 4) 1951 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K (0x2UL << 4) 1952 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M (0x3UL << 4) 1953 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M (0x4UL << 4) 1954 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G (0x5UL << 4) 1955 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G 1956 u8 srq_pg_size_srq_lvl; 1957 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK 0xfUL 1958 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT 0 1959 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0 0x0UL 1960 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1 0x1UL 1961 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 0x2UL 1962 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 1963 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK 0xf0UL 1964 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT 4 1965 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K (0x0UL << 4) 1966 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K (0x1UL << 4) 1967 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K (0x2UL << 4) 1968 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M (0x3UL << 4) 1969 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M (0x4UL << 4) 1970 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G (0x5UL << 4) 1971 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G 1972 u8 cq_pg_size_cq_lvl; 1973 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK 0xfUL 1974 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT 0 1975 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0 0x0UL 1976 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1 0x1UL 1977 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 0x2UL 1978 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 1979 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK 0xf0UL 1980 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT 4 1981 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K (0x0UL << 4) 1982 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K (0x1UL << 4) 1983 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K (0x2UL << 4) 1984 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M (0x3UL << 4) 1985 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M (0x4UL << 4) 1986 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G (0x5UL << 4) 1987 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G 1988 u8 vnic_pg_size_vnic_lvl; 1989 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK 0xfUL 1990 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT 0 1991 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0 0x0UL 1992 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1 0x1UL 1993 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 0x2UL 1994 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 1995 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK 0xf0UL 1996 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT 4 1997 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K (0x0UL << 4) 1998 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K (0x1UL << 4) 1999 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K (0x2UL << 4) 2000 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M (0x3UL << 4) 2001 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M (0x4UL << 4) 2002 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G (0x5UL << 4) 2003 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G 2004 u8 stat_pg_size_stat_lvl; 2005 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK 0xfUL 2006 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT 0 2007 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0 0x0UL 2008 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1 0x1UL 2009 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 0x2UL 2010 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 2011 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK 0xf0UL 2012 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT 4 2013 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K (0x0UL << 4) 2014 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K (0x1UL << 4) 2015 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K (0x2UL << 4) 2016 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M (0x3UL << 4) 2017 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M (0x4UL << 4) 2018 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G (0x5UL << 4) 2019 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G 2020 u8 tqm_sp_pg_size_tqm_sp_lvl; 2021 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK 0xfUL 2022 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT 0 2023 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0 0x0UL 2024 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1 0x1UL 2025 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 0x2UL 2026 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 2027 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK 0xf0UL 2028 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT 4 2029 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4) 2030 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4) 2031 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4) 2032 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4) 2033 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4) 2034 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4) 2035 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G 2036 u8 tqm_ring0_pg_size_tqm_ring0_lvl; 2037 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK 0xfUL 2038 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT 0 2039 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0 0x0UL 2040 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1 0x1UL 2041 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 0x2UL 2042 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 2043 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK 0xf0UL 2044 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT 4 2045 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4) 2046 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4) 2047 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4) 2048 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4) 2049 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4) 2050 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4) 2051 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G 2052 u8 tqm_ring1_pg_size_tqm_ring1_lvl; 2053 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK 0xfUL 2054 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT 0 2055 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0 0x0UL 2056 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1 0x1UL 2057 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 0x2UL 2058 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 2059 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK 0xf0UL 2060 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT 4 2061 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4) 2062 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4) 2063 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4) 2064 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4) 2065 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4) 2066 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4) 2067 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G 2068 u8 tqm_ring2_pg_size_tqm_ring2_lvl; 2069 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK 0xfUL 2070 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT 0 2071 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0 0x0UL 2072 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1 0x1UL 2073 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 0x2UL 2074 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 2075 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK 0xf0UL 2076 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT 4 2077 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4) 2078 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4) 2079 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4) 2080 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4) 2081 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4) 2082 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4) 2083 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G 2084 u8 tqm_ring3_pg_size_tqm_ring3_lvl; 2085 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK 0xfUL 2086 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT 0 2087 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0 0x0UL 2088 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1 0x1UL 2089 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 0x2UL 2090 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 2091 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK 0xf0UL 2092 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT 4 2093 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4) 2094 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4) 2095 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4) 2096 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4) 2097 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4) 2098 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4) 2099 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G 2100 u8 tqm_ring4_pg_size_tqm_ring4_lvl; 2101 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK 0xfUL 2102 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT 0 2103 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0 0x0UL 2104 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1 0x1UL 2105 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 0x2UL 2106 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 2107 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK 0xf0UL 2108 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT 4 2109 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4) 2110 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4) 2111 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4) 2112 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4) 2113 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4) 2114 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4) 2115 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G 2116 u8 tqm_ring5_pg_size_tqm_ring5_lvl; 2117 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK 0xfUL 2118 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT 0 2119 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0 0x0UL 2120 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1 0x1UL 2121 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 0x2UL 2122 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 2123 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK 0xf0UL 2124 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT 4 2125 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4) 2126 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4) 2127 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4) 2128 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4) 2129 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4) 2130 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4) 2131 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G 2132 u8 tqm_ring6_pg_size_tqm_ring6_lvl; 2133 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK 0xfUL 2134 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT 0 2135 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0 0x0UL 2136 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1 0x1UL 2137 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 0x2UL 2138 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 2139 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK 0xf0UL 2140 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT 4 2141 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4) 2142 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4) 2143 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4) 2144 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4) 2145 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4) 2146 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4) 2147 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G 2148 u8 tqm_ring7_pg_size_tqm_ring7_lvl; 2149 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK 0xfUL 2150 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT 0 2151 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0 0x0UL 2152 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1 0x1UL 2153 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 0x2UL 2154 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 2155 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK 0xf0UL 2156 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT 4 2157 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4) 2158 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4) 2159 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4) 2160 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4) 2161 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4) 2162 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4) 2163 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G 2164 u8 mrav_pg_size_mrav_lvl; 2165 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK 0xfUL 2166 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT 0 2167 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0 0x0UL 2168 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1 0x1UL 2169 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 0x2UL 2170 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 2171 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK 0xf0UL 2172 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT 4 2173 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K (0x0UL << 4) 2174 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K (0x1UL << 4) 2175 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K (0x2UL << 4) 2176 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M (0x3UL << 4) 2177 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M (0x4UL << 4) 2178 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G (0x5UL << 4) 2179 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G 2180 u8 tim_pg_size_tim_lvl; 2181 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK 0xfUL 2182 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT 0 2183 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0 0x0UL 2184 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1 0x1UL 2185 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 0x2UL 2186 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 2187 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK 0xf0UL 2188 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT 4 2189 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K (0x0UL << 4) 2190 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K (0x1UL << 4) 2191 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K (0x2UL << 4) 2192 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M (0x3UL << 4) 2193 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M (0x4UL << 4) 2194 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G (0x5UL << 4) 2195 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G 2196 __le64 qpc_page_dir; 2197 __le64 srq_page_dir; 2198 __le64 cq_page_dir; 2199 __le64 vnic_page_dir; 2200 __le64 stat_page_dir; 2201 __le64 tqm_sp_page_dir; 2202 __le64 tqm_ring0_page_dir; 2203 __le64 tqm_ring1_page_dir; 2204 __le64 tqm_ring2_page_dir; 2205 __le64 tqm_ring3_page_dir; 2206 __le64 tqm_ring4_page_dir; 2207 __le64 tqm_ring5_page_dir; 2208 __le64 tqm_ring6_page_dir; 2209 __le64 tqm_ring7_page_dir; 2210 __le64 mrav_page_dir; 2211 __le64 tim_page_dir; 2212 __le32 qp_num_entries; 2213 __le32 srq_num_entries; 2214 __le32 cq_num_entries; 2215 __le32 stat_num_entries; 2216 __le32 tqm_sp_num_entries; 2217 __le32 tqm_ring0_num_entries; 2218 __le32 tqm_ring1_num_entries; 2219 __le32 tqm_ring2_num_entries; 2220 __le32 tqm_ring3_num_entries; 2221 __le32 tqm_ring4_num_entries; 2222 __le32 tqm_ring5_num_entries; 2223 __le32 tqm_ring6_num_entries; 2224 __le32 tqm_ring7_num_entries; 2225 __le32 mrav_num_entries; 2226 __le32 tim_num_entries; 2227 __le16 qp_num_qp1_entries; 2228 __le16 qp_num_l2_entries; 2229 __le16 qp_entry_size; 2230 __le16 srq_num_l2_entries; 2231 __le16 srq_entry_size; 2232 __le16 cq_num_l2_entries; 2233 __le16 cq_entry_size; 2234 __le16 vnic_num_vnic_entries; 2235 __le16 vnic_num_ring_table_entries; 2236 __le16 vnic_entry_size; 2237 __le16 stat_entry_size; 2238 __le16 tqm_entry_size; 2239 __le16 mrav_entry_size; 2240 __le16 tim_entry_size; 2241 }; 2242 2243 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */ 2244 struct hwrm_func_backing_store_cfg_output { 2245 __le16 error_code; 2246 __le16 req_type; 2247 __le16 seq_id; 2248 __le16 resp_len; 2249 u8 unused_0[7]; 2250 u8 valid; 2251 }; 2252 2253 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */ 2254 struct hwrm_error_recovery_qcfg_input { 2255 __le16 req_type; 2256 __le16 cmpl_ring; 2257 __le16 seq_id; 2258 __le16 target_id; 2259 __le64 resp_addr; 2260 u8 unused_0[8]; 2261 }; 2262 2263 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */ 2264 struct hwrm_error_recovery_qcfg_output { 2265 __le16 error_code; 2266 __le16 req_type; 2267 __le16 seq_id; 2268 __le16 resp_len; 2269 __le32 flags; 2270 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST 0x1UL 2271 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU 0x2UL 2272 __le32 driver_polling_freq; 2273 __le32 master_func_wait_period; 2274 __le32 normal_func_wait_period; 2275 __le32 master_func_wait_period_after_reset; 2276 __le32 max_bailout_time_after_reset; 2277 __le32 fw_health_status_reg; 2278 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK 0x3UL 2279 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT 0 2280 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2281 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC 0x1UL 2282 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 0x2UL 2283 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 0x3UL 2284 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 2285 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_MASK 0xfffffffcUL 2286 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SFT 2 2287 __le32 fw_heartbeat_reg; 2288 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_MASK 0x3UL 2289 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_SFT 0 2290 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2291 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_GRC 0x1UL 2292 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 0x2UL 2293 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 0x3UL 2294 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 2295 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_MASK 0xfffffffcUL 2296 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SFT 2 2297 __le32 fw_reset_cnt_reg; 2298 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_MASK 0x3UL 2299 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_SFT 0 2300 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2301 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_GRC 0x1UL 2302 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 0x2UL 2303 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 0x3UL 2304 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 2305 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_MASK 0xfffffffcUL 2306 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SFT 2 2307 __le32 reset_inprogress_reg; 2308 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_MASK 0x3UL 2309 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_SFT 0 2310 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2311 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_GRC 0x1UL 2312 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 0x2UL 2313 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 0x3UL 2314 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 2315 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_MASK 0xfffffffcUL 2316 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SFT 2 2317 __le32 reset_inprogress_reg_mask; 2318 u8 unused_0[3]; 2319 u8 reg_array_cnt; 2320 __le32 reset_reg[16]; 2321 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_MASK 0x3UL 2322 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_SFT 0 2323 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2324 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_GRC 0x1UL 2325 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR0 0x2UL 2326 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 0x3UL 2327 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 2328 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_MASK 0xfffffffcUL 2329 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SFT 2 2330 __le32 reset_reg_val[16]; 2331 u8 delay_after_reset[16]; 2332 __le32 err_recovery_cnt_reg; 2333 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK 0x3UL 2334 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT 0 2335 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2336 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC 0x1UL 2337 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 0x2UL 2338 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 0x3UL 2339 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 2340 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_MASK 0xfffffffcUL 2341 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SFT 2 2342 u8 unused_1[3]; 2343 u8 valid; 2344 }; 2345 2346 /* hwrm_func_drv_if_change_input (size:192b/24B) */ 2347 struct hwrm_func_drv_if_change_input { 2348 __le16 req_type; 2349 __le16 cmpl_ring; 2350 __le16 seq_id; 2351 __le16 target_id; 2352 __le64 resp_addr; 2353 __le32 flags; 2354 #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP 0x1UL 2355 __le32 unused; 2356 }; 2357 2358 /* hwrm_func_drv_if_change_output (size:128b/16B) */ 2359 struct hwrm_func_drv_if_change_output { 2360 __le16 error_code; 2361 __le16 req_type; 2362 __le16 seq_id; 2363 __le16 resp_len; 2364 __le32 flags; 2365 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL 2366 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE 0x2UL 2367 u8 unused_0[3]; 2368 u8 valid; 2369 }; 2370 2371 /* hwrm_port_phy_cfg_input (size:448b/56B) */ 2372 struct hwrm_port_phy_cfg_input { 2373 __le16 req_type; 2374 __le16 cmpl_ring; 2375 __le16 seq_id; 2376 __le16 target_id; 2377 __le64 resp_addr; 2378 __le32 flags; 2379 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 2380 #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL 2381 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 2382 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 2383 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 2384 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 2385 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 2386 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 2387 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL 2388 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL 2389 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL 2390 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL 2391 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL 2392 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL 2393 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL 2394 __le32 enables; 2395 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 2396 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 2397 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 2398 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 2399 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 2400 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 2401 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 2402 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 2403 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 2404 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 2405 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 2406 __le16 port_id; 2407 __le16 force_link_speed; 2408 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL 2409 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 2410 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL 2411 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL 2412 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 2413 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL 2414 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 2415 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 2416 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 2417 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 2418 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_200GB 0x7d0UL 2419 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL 2420 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 2421 u8 auto_mode; 2422 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL 2423 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL 2424 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL 2425 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL 2426 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 2427 #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 2428 u8 auto_duplex; 2429 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL 2430 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL 2431 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 2432 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 2433 u8 auto_pause; 2434 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 2435 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 2436 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 2437 u8 unused_0; 2438 __le16 auto_link_speed; 2439 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL 2440 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL 2441 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL 2442 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL 2443 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL 2444 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL 2445 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL 2446 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL 2447 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL 2448 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL 2449 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_200GB 0x7d0UL 2450 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL 2451 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 2452 __le16 auto_link_speed_mask; 2453 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 2454 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 2455 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 2456 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 2457 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 2458 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 2459 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 2460 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 2461 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 2462 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 2463 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 2464 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 2465 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 2466 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 2467 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_200GB 0x4000UL 2468 u8 wirespeed; 2469 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL 2470 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 2471 #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON 2472 u8 lpbk; 2473 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 2474 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 2475 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 2476 #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL 2477 #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_EXTERNAL 2478 u8 force_pause; 2479 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 2480 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 2481 u8 unused_1; 2482 __le32 preemphasis; 2483 __le16 eee_link_speed_mask; 2484 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 2485 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 2486 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 2487 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 2488 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 2489 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 2490 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 2491 u8 unused_2[2]; 2492 __le32 tx_lpi_timer; 2493 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 2494 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 2495 __le32 unused_3; 2496 }; 2497 2498 /* hwrm_port_phy_cfg_output (size:128b/16B) */ 2499 struct hwrm_port_phy_cfg_output { 2500 __le16 error_code; 2501 __le16 req_type; 2502 __le16 seq_id; 2503 __le16 resp_len; 2504 u8 unused_0[7]; 2505 u8 valid; 2506 }; 2507 2508 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */ 2509 struct hwrm_port_phy_cfg_cmd_err { 2510 u8 code; 2511 #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 2512 #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL 2513 #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY 0x2UL 2514 #define PORT_PHY_CFG_CMD_ERR_CODE_LAST PORT_PHY_CFG_CMD_ERR_CODE_RETRY 2515 u8 unused_0[7]; 2516 }; 2517 2518 /* hwrm_port_phy_qcfg_input (size:192b/24B) */ 2519 struct hwrm_port_phy_qcfg_input { 2520 __le16 req_type; 2521 __le16 cmpl_ring; 2522 __le16 seq_id; 2523 __le16 target_id; 2524 __le64 resp_addr; 2525 __le16 port_id; 2526 u8 unused_0[6]; 2527 }; 2528 2529 /* hwrm_port_phy_qcfg_output (size:768b/96B) */ 2530 struct hwrm_port_phy_qcfg_output { 2531 __le16 error_code; 2532 __le16 req_type; 2533 __le16 seq_id; 2534 __le16 resp_len; 2535 u8 link; 2536 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 2537 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 2538 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 2539 #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK 2540 u8 unused_0; 2541 __le16 link_speed; 2542 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 2543 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 2544 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 2545 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 2546 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 2547 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 2548 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 2549 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 2550 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 2551 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 2552 #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL 2553 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 2554 #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 2555 u8 duplex_cfg; 2556 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL 2557 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL 2558 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 2559 u8 pause; 2560 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 2561 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 2562 __le16 support_speeds; 2563 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 2564 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 2565 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 2566 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 2567 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 2568 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 2569 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 2570 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 2571 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 2572 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 2573 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 2574 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 2575 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 2576 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 2577 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_200GB 0x4000UL 2578 __le16 force_link_speed; 2579 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL 2580 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL 2581 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL 2582 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL 2583 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL 2584 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL 2585 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL 2586 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL 2587 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL 2588 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL 2589 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_200GB 0x7d0UL 2590 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL 2591 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 2592 u8 auto_mode; 2593 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL 2594 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL 2595 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL 2596 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL 2597 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL 2598 #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 2599 u8 auto_pause; 2600 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 2601 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 2602 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 2603 __le16 auto_link_speed; 2604 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL 2605 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL 2606 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL 2607 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL 2608 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL 2609 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL 2610 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL 2611 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL 2612 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL 2613 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL 2614 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_200GB 0x7d0UL 2615 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL 2616 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 2617 __le16 auto_link_speed_mask; 2618 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 2619 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 2620 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 2621 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 2622 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 2623 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 2624 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 2625 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 2626 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 2627 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 2628 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 2629 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 2630 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 2631 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 2632 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_200GB 0x4000UL 2633 u8 wirespeed; 2634 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL 2635 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 2636 #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON 2637 u8 lpbk; 2638 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 2639 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 2640 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 2641 #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL 2642 #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 2643 u8 force_pause; 2644 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 2645 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 2646 u8 module_status; 2647 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL 2648 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL 2649 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL 2650 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 2651 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 2652 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT 0x5UL 2653 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 2654 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 2655 __le32 preemphasis; 2656 u8 phy_maj; 2657 u8 phy_min; 2658 u8 phy_bld; 2659 u8 phy_type; 2660 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL 2661 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL 2662 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL 2663 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL 2664 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL 2665 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL 2666 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL 2667 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL 2668 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL 2669 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL 2670 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL 2671 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL 2672 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL 2673 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL 2674 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL 2675 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL 2676 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL 2677 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL 2678 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL 2679 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL 2680 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL 2681 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL 2682 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL 2683 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL 2684 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL 2685 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL 2686 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL 2687 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL 2688 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4 0x1cUL 2689 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4 0x1dUL 2690 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4 0x1eUL 2691 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 0x1fUL 2692 #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 2693 u8 media_type; 2694 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 2695 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL 2696 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL 2697 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL 2698 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 2699 u8 xcvr_pkg_type; 2700 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL 2701 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL 2702 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 2703 u8 eee_config_phy_addr; 2704 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 2705 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 2706 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 2707 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 2708 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 2709 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 2710 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 2711 u8 parallel_detect; 2712 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 2713 __le16 link_partner_adv_speeds; 2714 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 2715 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 2716 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 2717 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 2718 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 2719 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 2720 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 2721 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 2722 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 2723 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 2724 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 2725 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 2726 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 2727 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 2728 u8 link_partner_adv_auto_mode; 2729 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL 2730 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL 2731 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL 2732 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL 2733 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL 2734 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 2735 u8 link_partner_adv_pause; 2736 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 2737 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 2738 __le16 adv_eee_link_speed_mask; 2739 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 2740 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 2741 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 2742 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 2743 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 2744 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 2745 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 2746 __le16 link_partner_adv_eee_link_speed_mask; 2747 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 2748 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 2749 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 2750 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 2751 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 2752 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 2753 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 2754 __le32 xcvr_identifier_type_tx_lpi_timer; 2755 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 2756 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 2757 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 2758 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 2759 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 2760 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 2761 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 2762 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 2763 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 2764 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 2765 __le16 fec_cfg; 2766 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 2767 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL 2768 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL 2769 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL 2770 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL 2771 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL 2772 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL 2773 u8 duplex_state; 2774 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL 2775 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL 2776 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 2777 u8 option_flags; 2778 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL 2779 char phy_vendor_name[16]; 2780 char phy_vendor_partnumber[16]; 2781 u8 unused_2[7]; 2782 u8 valid; 2783 }; 2784 2785 /* hwrm_port_mac_cfg_input (size:384b/48B) */ 2786 struct hwrm_port_mac_cfg_input { 2787 __le16 req_type; 2788 __le16 cmpl_ring; 2789 __le16 seq_id; 2790 __le16 target_id; 2791 __le64 resp_addr; 2792 __le32 flags; 2793 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 2794 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL 2795 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 2796 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 2797 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 2798 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 2799 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 2800 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 2801 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL 2802 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL 2803 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL 2804 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL 2805 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL 2806 #define PORT_MAC_CFG_REQ_FLAGS_PTP_ONE_STEP_TX_TS 0x2000UL 2807 __le32 enables; 2808 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 2809 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 2810 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL 2811 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 2812 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 2813 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 2814 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 2815 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL 2816 #define PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB 0x200UL 2817 __le16 port_id; 2818 u8 ipg; 2819 u8 lpbk; 2820 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 2821 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL 2822 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL 2823 #define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE 2824 u8 vlan_pri2cos_map_pri; 2825 u8 reserved1; 2826 u8 tunnel_pri2cos_map_pri; 2827 u8 dscp2pri_map_pri; 2828 __le16 rx_ts_capture_ptp_msg_type; 2829 __le16 tx_ts_capture_ptp_msg_type; 2830 u8 cos_field_cfg; 2831 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL 2832 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL 2833 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1 2834 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1) 2835 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1) 2836 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1) 2837 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1) 2838 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED 2839 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL 2840 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3 2841 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3) 2842 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3) 2843 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3) 2844 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3) 2845 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED 2846 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL 2847 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5 2848 u8 unused_0[3]; 2849 __s32 ptp_freq_adj_ppb; 2850 u8 unused_1[4]; 2851 }; 2852 2853 /* hwrm_port_mac_cfg_output (size:128b/16B) */ 2854 struct hwrm_port_mac_cfg_output { 2855 __le16 error_code; 2856 __le16 req_type; 2857 __le16 seq_id; 2858 __le16 resp_len; 2859 __le16 mru; 2860 __le16 mtu; 2861 u8 ipg; 2862 u8 lpbk; 2863 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL 2864 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL 2865 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL 2866 #define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE 2867 u8 unused_0; 2868 u8 valid; 2869 }; 2870 2871 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */ 2872 struct hwrm_port_mac_ptp_qcfg_input { 2873 __le16 req_type; 2874 __le16 cmpl_ring; 2875 __le16 seq_id; 2876 __le16 target_id; 2877 __le64 resp_addr; 2878 __le16 port_id; 2879 u8 unused_0[6]; 2880 }; 2881 2882 /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */ 2883 struct hwrm_port_mac_ptp_qcfg_output { 2884 __le16 error_code; 2885 __le16 req_type; 2886 __le16 seq_id; 2887 __le16 resp_len; 2888 u8 flags; 2889 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL 2890 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_ONE_STEP_TX_TS 0x4UL 2891 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x8UL 2892 u8 unused_0[3]; 2893 __le32 rx_ts_reg_off_lower; 2894 __le32 rx_ts_reg_off_upper; 2895 __le32 rx_ts_reg_off_seq_id; 2896 __le32 rx_ts_reg_off_src_id_0; 2897 __le32 rx_ts_reg_off_src_id_1; 2898 __le32 rx_ts_reg_off_src_id_2; 2899 __le32 rx_ts_reg_off_domain_id; 2900 __le32 rx_ts_reg_off_fifo; 2901 __le32 rx_ts_reg_off_fifo_adv; 2902 __le32 rx_ts_reg_off_granularity; 2903 __le32 tx_ts_reg_off_lower; 2904 __le32 tx_ts_reg_off_upper; 2905 __le32 tx_ts_reg_off_seq_id; 2906 __le32 tx_ts_reg_off_fifo; 2907 __le32 tx_ts_reg_off_granularity; 2908 u8 unused_1[7]; 2909 u8 valid; 2910 }; 2911 2912 /* tx_port_stats (size:3264b/408B) */ 2913 struct tx_port_stats { 2914 __le64 tx_64b_frames; 2915 __le64 tx_65b_127b_frames; 2916 __le64 tx_128b_255b_frames; 2917 __le64 tx_256b_511b_frames; 2918 __le64 tx_512b_1023b_frames; 2919 __le64 tx_1024b_1518b_frames; 2920 __le64 tx_good_vlan_frames; 2921 __le64 tx_1519b_2047b_frames; 2922 __le64 tx_2048b_4095b_frames; 2923 __le64 tx_4096b_9216b_frames; 2924 __le64 tx_9217b_16383b_frames; 2925 __le64 tx_good_frames; 2926 __le64 tx_total_frames; 2927 __le64 tx_ucast_frames; 2928 __le64 tx_mcast_frames; 2929 __le64 tx_bcast_frames; 2930 __le64 tx_pause_frames; 2931 __le64 tx_pfc_frames; 2932 __le64 tx_jabber_frames; 2933 __le64 tx_fcs_err_frames; 2934 __le64 tx_control_frames; 2935 __le64 tx_oversz_frames; 2936 __le64 tx_single_dfrl_frames; 2937 __le64 tx_multi_dfrl_frames; 2938 __le64 tx_single_coll_frames; 2939 __le64 tx_multi_coll_frames; 2940 __le64 tx_late_coll_frames; 2941 __le64 tx_excessive_coll_frames; 2942 __le64 tx_frag_frames; 2943 __le64 tx_err; 2944 __le64 tx_tagged_frames; 2945 __le64 tx_dbl_tagged_frames; 2946 __le64 tx_runt_frames; 2947 __le64 tx_fifo_underruns; 2948 __le64 tx_pfc_ena_frames_pri0; 2949 __le64 tx_pfc_ena_frames_pri1; 2950 __le64 tx_pfc_ena_frames_pri2; 2951 __le64 tx_pfc_ena_frames_pri3; 2952 __le64 tx_pfc_ena_frames_pri4; 2953 __le64 tx_pfc_ena_frames_pri5; 2954 __le64 tx_pfc_ena_frames_pri6; 2955 __le64 tx_pfc_ena_frames_pri7; 2956 __le64 tx_eee_lpi_events; 2957 __le64 tx_eee_lpi_duration; 2958 __le64 tx_llfc_logical_msgs; 2959 __le64 tx_hcfc_msgs; 2960 __le64 tx_total_collisions; 2961 __le64 tx_bytes; 2962 __le64 tx_xthol_frames; 2963 __le64 tx_stat_discard; 2964 __le64 tx_stat_error; 2965 }; 2966 2967 /* rx_port_stats (size:4224b/528B) */ 2968 struct rx_port_stats { 2969 __le64 rx_64b_frames; 2970 __le64 rx_65b_127b_frames; 2971 __le64 rx_128b_255b_frames; 2972 __le64 rx_256b_511b_frames; 2973 __le64 rx_512b_1023b_frames; 2974 __le64 rx_1024b_1518b_frames; 2975 __le64 rx_good_vlan_frames; 2976 __le64 rx_1519b_2047b_frames; 2977 __le64 rx_2048b_4095b_frames; 2978 __le64 rx_4096b_9216b_frames; 2979 __le64 rx_9217b_16383b_frames; 2980 __le64 rx_total_frames; 2981 __le64 rx_ucast_frames; 2982 __le64 rx_mcast_frames; 2983 __le64 rx_bcast_frames; 2984 __le64 rx_fcs_err_frames; 2985 __le64 rx_ctrl_frames; 2986 __le64 rx_pause_frames; 2987 __le64 rx_pfc_frames; 2988 __le64 rx_unsupported_opcode_frames; 2989 __le64 rx_unsupported_da_pausepfc_frames; 2990 __le64 rx_wrong_sa_frames; 2991 __le64 rx_align_err_frames; 2992 __le64 rx_oor_len_frames; 2993 __le64 rx_code_err_frames; 2994 __le64 rx_false_carrier_frames; 2995 __le64 rx_ovrsz_frames; 2996 __le64 rx_jbr_frames; 2997 __le64 rx_mtu_err_frames; 2998 __le64 rx_match_crc_frames; 2999 __le64 rx_promiscuous_frames; 3000 __le64 rx_tagged_frames; 3001 __le64 rx_double_tagged_frames; 3002 __le64 rx_trunc_frames; 3003 __le64 rx_good_frames; 3004 __le64 rx_pfc_xon2xoff_frames_pri0; 3005 __le64 rx_pfc_xon2xoff_frames_pri1; 3006 __le64 rx_pfc_xon2xoff_frames_pri2; 3007 __le64 rx_pfc_xon2xoff_frames_pri3; 3008 __le64 rx_pfc_xon2xoff_frames_pri4; 3009 __le64 rx_pfc_xon2xoff_frames_pri5; 3010 __le64 rx_pfc_xon2xoff_frames_pri6; 3011 __le64 rx_pfc_xon2xoff_frames_pri7; 3012 __le64 rx_pfc_ena_frames_pri0; 3013 __le64 rx_pfc_ena_frames_pri1; 3014 __le64 rx_pfc_ena_frames_pri2; 3015 __le64 rx_pfc_ena_frames_pri3; 3016 __le64 rx_pfc_ena_frames_pri4; 3017 __le64 rx_pfc_ena_frames_pri5; 3018 __le64 rx_pfc_ena_frames_pri6; 3019 __le64 rx_pfc_ena_frames_pri7; 3020 __le64 rx_sch_crc_err_frames; 3021 __le64 rx_undrsz_frames; 3022 __le64 rx_frag_frames; 3023 __le64 rx_eee_lpi_events; 3024 __le64 rx_eee_lpi_duration; 3025 __le64 rx_llfc_physical_msgs; 3026 __le64 rx_llfc_logical_msgs; 3027 __le64 rx_llfc_msgs_with_crc_err; 3028 __le64 rx_hcfc_msgs; 3029 __le64 rx_hcfc_msgs_with_crc_err; 3030 __le64 rx_bytes; 3031 __le64 rx_runt_bytes; 3032 __le64 rx_runt_frames; 3033 __le64 rx_stat_discard; 3034 __le64 rx_stat_err; 3035 }; 3036 3037 /* hwrm_port_qstats_input (size:320b/40B) */ 3038 struct hwrm_port_qstats_input { 3039 __le16 req_type; 3040 __le16 cmpl_ring; 3041 __le16 seq_id; 3042 __le16 target_id; 3043 __le64 resp_addr; 3044 __le16 port_id; 3045 u8 flags; 3046 #define PORT_QSTATS_REQ_FLAGS_UNUSED 0x0UL 3047 #define PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 3048 #define PORT_QSTATS_REQ_FLAGS_LAST PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 3049 u8 unused_0[5]; 3050 __le64 tx_stat_host_addr; 3051 __le64 rx_stat_host_addr; 3052 }; 3053 3054 /* hwrm_port_qstats_output (size:128b/16B) */ 3055 struct hwrm_port_qstats_output { 3056 __le16 error_code; 3057 __le16 req_type; 3058 __le16 seq_id; 3059 __le16 resp_len; 3060 __le16 tx_stat_size; 3061 __le16 rx_stat_size; 3062 u8 unused_0[3]; 3063 u8 valid; 3064 }; 3065 3066 /* tx_port_stats_ext (size:2048b/256B) */ 3067 struct tx_port_stats_ext { 3068 __le64 tx_bytes_cos0; 3069 __le64 tx_bytes_cos1; 3070 __le64 tx_bytes_cos2; 3071 __le64 tx_bytes_cos3; 3072 __le64 tx_bytes_cos4; 3073 __le64 tx_bytes_cos5; 3074 __le64 tx_bytes_cos6; 3075 __le64 tx_bytes_cos7; 3076 __le64 tx_packets_cos0; 3077 __le64 tx_packets_cos1; 3078 __le64 tx_packets_cos2; 3079 __le64 tx_packets_cos3; 3080 __le64 tx_packets_cos4; 3081 __le64 tx_packets_cos5; 3082 __le64 tx_packets_cos6; 3083 __le64 tx_packets_cos7; 3084 __le64 pfc_pri0_tx_duration_us; 3085 __le64 pfc_pri0_tx_transitions; 3086 __le64 pfc_pri1_tx_duration_us; 3087 __le64 pfc_pri1_tx_transitions; 3088 __le64 pfc_pri2_tx_duration_us; 3089 __le64 pfc_pri2_tx_transitions; 3090 __le64 pfc_pri3_tx_duration_us; 3091 __le64 pfc_pri3_tx_transitions; 3092 __le64 pfc_pri4_tx_duration_us; 3093 __le64 pfc_pri4_tx_transitions; 3094 __le64 pfc_pri5_tx_duration_us; 3095 __le64 pfc_pri5_tx_transitions; 3096 __le64 pfc_pri6_tx_duration_us; 3097 __le64 pfc_pri6_tx_transitions; 3098 __le64 pfc_pri7_tx_duration_us; 3099 __le64 pfc_pri7_tx_transitions; 3100 }; 3101 3102 /* rx_port_stats_ext (size:3648b/456B) */ 3103 struct rx_port_stats_ext { 3104 __le64 link_down_events; 3105 __le64 continuous_pause_events; 3106 __le64 resume_pause_events; 3107 __le64 continuous_roce_pause_events; 3108 __le64 resume_roce_pause_events; 3109 __le64 rx_bytes_cos0; 3110 __le64 rx_bytes_cos1; 3111 __le64 rx_bytes_cos2; 3112 __le64 rx_bytes_cos3; 3113 __le64 rx_bytes_cos4; 3114 __le64 rx_bytes_cos5; 3115 __le64 rx_bytes_cos6; 3116 __le64 rx_bytes_cos7; 3117 __le64 rx_packets_cos0; 3118 __le64 rx_packets_cos1; 3119 __le64 rx_packets_cos2; 3120 __le64 rx_packets_cos3; 3121 __le64 rx_packets_cos4; 3122 __le64 rx_packets_cos5; 3123 __le64 rx_packets_cos6; 3124 __le64 rx_packets_cos7; 3125 __le64 pfc_pri0_rx_duration_us; 3126 __le64 pfc_pri0_rx_transitions; 3127 __le64 pfc_pri1_rx_duration_us; 3128 __le64 pfc_pri1_rx_transitions; 3129 __le64 pfc_pri2_rx_duration_us; 3130 __le64 pfc_pri2_rx_transitions; 3131 __le64 pfc_pri3_rx_duration_us; 3132 __le64 pfc_pri3_rx_transitions; 3133 __le64 pfc_pri4_rx_duration_us; 3134 __le64 pfc_pri4_rx_transitions; 3135 __le64 pfc_pri5_rx_duration_us; 3136 __le64 pfc_pri5_rx_transitions; 3137 __le64 pfc_pri6_rx_duration_us; 3138 __le64 pfc_pri6_rx_transitions; 3139 __le64 pfc_pri7_rx_duration_us; 3140 __le64 pfc_pri7_rx_transitions; 3141 __le64 rx_bits; 3142 __le64 rx_buffer_passed_threshold; 3143 __le64 rx_pcs_symbol_err; 3144 __le64 rx_corrected_bits; 3145 __le64 rx_discard_bytes_cos0; 3146 __le64 rx_discard_bytes_cos1; 3147 __le64 rx_discard_bytes_cos2; 3148 __le64 rx_discard_bytes_cos3; 3149 __le64 rx_discard_bytes_cos4; 3150 __le64 rx_discard_bytes_cos5; 3151 __le64 rx_discard_bytes_cos6; 3152 __le64 rx_discard_bytes_cos7; 3153 __le64 rx_discard_packets_cos0; 3154 __le64 rx_discard_packets_cos1; 3155 __le64 rx_discard_packets_cos2; 3156 __le64 rx_discard_packets_cos3; 3157 __le64 rx_discard_packets_cos4; 3158 __le64 rx_discard_packets_cos5; 3159 __le64 rx_discard_packets_cos6; 3160 __le64 rx_discard_packets_cos7; 3161 }; 3162 3163 /* hwrm_port_qstats_ext_input (size:320b/40B) */ 3164 struct hwrm_port_qstats_ext_input { 3165 __le16 req_type; 3166 __le16 cmpl_ring; 3167 __le16 seq_id; 3168 __le16 target_id; 3169 __le64 resp_addr; 3170 __le16 port_id; 3171 __le16 tx_stat_size; 3172 __le16 rx_stat_size; 3173 u8 flags; 3174 #define PORT_QSTATS_EXT_REQ_FLAGS_UNUSED 0x0UL 3175 #define PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x1UL 3176 #define PORT_QSTATS_EXT_REQ_FLAGS_LAST PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 3177 u8 unused_0; 3178 __le64 tx_stat_host_addr; 3179 __le64 rx_stat_host_addr; 3180 }; 3181 3182 /* hwrm_port_qstats_ext_output (size:128b/16B) */ 3183 struct hwrm_port_qstats_ext_output { 3184 __le16 error_code; 3185 __le16 req_type; 3186 __le16 seq_id; 3187 __le16 resp_len; 3188 __le16 tx_stat_size; 3189 __le16 rx_stat_size; 3190 __le16 total_active_cos_queues; 3191 u8 flags; 3192 #define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED 0x1UL 3193 u8 valid; 3194 }; 3195 3196 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */ 3197 struct hwrm_port_lpbk_qstats_input { 3198 __le16 req_type; 3199 __le16 cmpl_ring; 3200 __le16 seq_id; 3201 __le16 target_id; 3202 __le64 resp_addr; 3203 }; 3204 3205 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */ 3206 struct hwrm_port_lpbk_qstats_output { 3207 __le16 error_code; 3208 __le16 req_type; 3209 __le16 seq_id; 3210 __le16 resp_len; 3211 __le64 lpbk_ucast_frames; 3212 __le64 lpbk_mcast_frames; 3213 __le64 lpbk_bcast_frames; 3214 __le64 lpbk_ucast_bytes; 3215 __le64 lpbk_mcast_bytes; 3216 __le64 lpbk_bcast_bytes; 3217 __le64 tx_stat_discard; 3218 __le64 tx_stat_error; 3219 __le64 rx_stat_discard; 3220 __le64 rx_stat_error; 3221 u8 unused_0[7]; 3222 u8 valid; 3223 }; 3224 3225 /* hwrm_port_clr_stats_input (size:192b/24B) */ 3226 struct hwrm_port_clr_stats_input { 3227 __le16 req_type; 3228 __le16 cmpl_ring; 3229 __le16 seq_id; 3230 __le16 target_id; 3231 __le64 resp_addr; 3232 __le16 port_id; 3233 u8 flags; 3234 #define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS 0x1UL 3235 u8 unused_0[5]; 3236 }; 3237 3238 /* hwrm_port_clr_stats_output (size:128b/16B) */ 3239 struct hwrm_port_clr_stats_output { 3240 __le16 error_code; 3241 __le16 req_type; 3242 __le16 seq_id; 3243 __le16 resp_len; 3244 u8 unused_0[7]; 3245 u8 valid; 3246 }; 3247 3248 /* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */ 3249 struct hwrm_port_lpbk_clr_stats_input { 3250 __le16 req_type; 3251 __le16 cmpl_ring; 3252 __le16 seq_id; 3253 __le16 target_id; 3254 __le64 resp_addr; 3255 }; 3256 3257 /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */ 3258 struct hwrm_port_lpbk_clr_stats_output { 3259 __le16 error_code; 3260 __le16 req_type; 3261 __le16 seq_id; 3262 __le16 resp_len; 3263 u8 unused_0[7]; 3264 u8 valid; 3265 }; 3266 3267 /* hwrm_port_ts_query_input (size:192b/24B) */ 3268 struct hwrm_port_ts_query_input { 3269 __le16 req_type; 3270 __le16 cmpl_ring; 3271 __le16 seq_id; 3272 __le16 target_id; 3273 __le64 resp_addr; 3274 __le32 flags; 3275 #define PORT_TS_QUERY_REQ_FLAGS_PATH 0x1UL 3276 #define PORT_TS_QUERY_REQ_FLAGS_PATH_TX 0x0UL 3277 #define PORT_TS_QUERY_REQ_FLAGS_PATH_RX 0x1UL 3278 #define PORT_TS_QUERY_REQ_FLAGS_PATH_LAST PORT_TS_QUERY_REQ_FLAGS_PATH_RX 3279 #define PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME 0x2UL 3280 __le16 port_id; 3281 u8 unused_0[2]; 3282 }; 3283 3284 /* hwrm_port_ts_query_output (size:192b/24B) */ 3285 struct hwrm_port_ts_query_output { 3286 __le16 error_code; 3287 __le16 req_type; 3288 __le16 seq_id; 3289 __le16 resp_len; 3290 __le64 ptp_msg_ts; 3291 __le16 ptp_msg_seqid; 3292 u8 unused_0[5]; 3293 u8 valid; 3294 }; 3295 3296 /* hwrm_port_phy_qcaps_input (size:192b/24B) */ 3297 struct hwrm_port_phy_qcaps_input { 3298 __le16 req_type; 3299 __le16 cmpl_ring; 3300 __le16 seq_id; 3301 __le16 target_id; 3302 __le64 resp_addr; 3303 __le16 port_id; 3304 u8 unused_0[6]; 3305 }; 3306 3307 /* hwrm_port_phy_qcaps_output (size:192b/24B) */ 3308 struct hwrm_port_phy_qcaps_output { 3309 __le16 error_code; 3310 __le16 req_type; 3311 __le16 seq_id; 3312 __le16 resp_len; 3313 u8 flags; 3314 #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL 3315 #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 0x2UL 3316 #define PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED 0x4UL 3317 #define PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED 0x8UL 3318 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_MASK 0xf0UL 3319 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_SFT 4 3320 u8 port_cnt; 3321 #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL 3322 #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL 3323 #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL 3324 #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL 3325 #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL 3326 #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_4 3327 __le16 supported_speeds_force_mode; 3328 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 3329 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 3330 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 3331 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 3332 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 3333 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 3334 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 3335 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 3336 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 3337 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 3338 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 3339 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 3340 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 3341 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 3342 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_200GB 0x4000UL 3343 __le16 supported_speeds_auto_mode; 3344 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 3345 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 3346 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 3347 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 3348 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 3349 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 3350 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 3351 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 3352 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 3353 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 3354 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 3355 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 3356 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 3357 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 3358 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_200GB 0x4000UL 3359 __le16 supported_speeds_eee_mode; 3360 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 3361 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 3362 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 3363 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 3364 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 3365 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 3366 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 3367 __le32 tx_lpi_timer_low; 3368 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 3369 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 3370 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 3371 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 3372 __le32 valid_tx_lpi_timer_high; 3373 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 3374 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 3375 #define PORT_PHY_QCAPS_RESP_VALID_MASK 0xff000000UL 3376 #define PORT_PHY_QCAPS_RESP_VALID_SFT 24 3377 }; 3378 3379 /* hwrm_port_phy_i2c_read_input (size:320b/40B) */ 3380 struct hwrm_port_phy_i2c_read_input { 3381 __le16 req_type; 3382 __le16 cmpl_ring; 3383 __le16 seq_id; 3384 __le16 target_id; 3385 __le64 resp_addr; 3386 __le32 flags; 3387 __le32 enables; 3388 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 3389 __le16 port_id; 3390 u8 i2c_slave_addr; 3391 u8 unused_0; 3392 __le16 page_number; 3393 __le16 page_offset; 3394 u8 data_length; 3395 u8 unused_1[7]; 3396 }; 3397 3398 /* hwrm_port_phy_i2c_read_output (size:640b/80B) */ 3399 struct hwrm_port_phy_i2c_read_output { 3400 __le16 error_code; 3401 __le16 req_type; 3402 __le16 seq_id; 3403 __le16 resp_len; 3404 __le32 data[16]; 3405 u8 unused_0[7]; 3406 u8 valid; 3407 }; 3408 3409 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */ 3410 struct hwrm_port_phy_mdio_write_input { 3411 __le16 req_type; 3412 __le16 cmpl_ring; 3413 __le16 seq_id; 3414 __le16 target_id; 3415 __le64 resp_addr; 3416 __le32 unused_0[2]; 3417 __le16 port_id; 3418 u8 phy_addr; 3419 u8 dev_addr; 3420 __le16 reg_addr; 3421 __le16 reg_data; 3422 u8 cl45_mdio; 3423 u8 unused_1[7]; 3424 }; 3425 3426 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */ 3427 struct hwrm_port_phy_mdio_write_output { 3428 __le16 error_code; 3429 __le16 req_type; 3430 __le16 seq_id; 3431 __le16 resp_len; 3432 u8 unused_0[7]; 3433 u8 valid; 3434 }; 3435 3436 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */ 3437 struct hwrm_port_phy_mdio_read_input { 3438 __le16 req_type; 3439 __le16 cmpl_ring; 3440 __le16 seq_id; 3441 __le16 target_id; 3442 __le64 resp_addr; 3443 __le32 unused_0[2]; 3444 __le16 port_id; 3445 u8 phy_addr; 3446 u8 dev_addr; 3447 __le16 reg_addr; 3448 u8 cl45_mdio; 3449 u8 unused_1; 3450 }; 3451 3452 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */ 3453 struct hwrm_port_phy_mdio_read_output { 3454 __le16 error_code; 3455 __le16 req_type; 3456 __le16 seq_id; 3457 __le16 resp_len; 3458 __le16 reg_data; 3459 u8 unused_0[5]; 3460 u8 valid; 3461 }; 3462 3463 /* hwrm_port_led_cfg_input (size:512b/64B) */ 3464 struct hwrm_port_led_cfg_input { 3465 __le16 req_type; 3466 __le16 cmpl_ring; 3467 __le16 seq_id; 3468 __le16 target_id; 3469 __le64 resp_addr; 3470 __le32 enables; 3471 #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL 3472 #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL 3473 #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL 3474 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL 3475 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL 3476 #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL 3477 #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL 3478 #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL 3479 #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL 3480 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL 3481 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL 3482 #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL 3483 #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL 3484 #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL 3485 #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL 3486 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL 3487 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL 3488 #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL 3489 #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL 3490 #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL 3491 #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL 3492 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL 3493 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL 3494 #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL 3495 __le16 port_id; 3496 u8 num_leds; 3497 u8 rsvd; 3498 u8 led0_id; 3499 u8 led0_state; 3500 #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL 3501 #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL 3502 #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL 3503 #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL 3504 #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL 3505 #define PORT_LED_CFG_REQ_LED0_STATE_LAST PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 3506 u8 led0_color; 3507 #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL 3508 #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL 3509 #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL 3510 #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL 3511 #define PORT_LED_CFG_REQ_LED0_COLOR_LAST PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 3512 u8 unused_0; 3513 __le16 led0_blink_on; 3514 __le16 led0_blink_off; 3515 u8 led0_group_id; 3516 u8 rsvd0; 3517 u8 led1_id; 3518 u8 led1_state; 3519 #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL 3520 #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL 3521 #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL 3522 #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL 3523 #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL 3524 #define PORT_LED_CFG_REQ_LED1_STATE_LAST PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 3525 u8 led1_color; 3526 #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL 3527 #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL 3528 #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL 3529 #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL 3530 #define PORT_LED_CFG_REQ_LED1_COLOR_LAST PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 3531 u8 unused_1; 3532 __le16 led1_blink_on; 3533 __le16 led1_blink_off; 3534 u8 led1_group_id; 3535 u8 rsvd1; 3536 u8 led2_id; 3537 u8 led2_state; 3538 #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL 3539 #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL 3540 #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL 3541 #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL 3542 #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL 3543 #define PORT_LED_CFG_REQ_LED2_STATE_LAST PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 3544 u8 led2_color; 3545 #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL 3546 #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL 3547 #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL 3548 #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL 3549 #define PORT_LED_CFG_REQ_LED2_COLOR_LAST PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 3550 u8 unused_2; 3551 __le16 led2_blink_on; 3552 __le16 led2_blink_off; 3553 u8 led2_group_id; 3554 u8 rsvd2; 3555 u8 led3_id; 3556 u8 led3_state; 3557 #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL 3558 #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL 3559 #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL 3560 #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL 3561 #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL 3562 #define PORT_LED_CFG_REQ_LED3_STATE_LAST PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 3563 u8 led3_color; 3564 #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL 3565 #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL 3566 #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL 3567 #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL 3568 #define PORT_LED_CFG_REQ_LED3_COLOR_LAST PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 3569 u8 unused_3; 3570 __le16 led3_blink_on; 3571 __le16 led3_blink_off; 3572 u8 led3_group_id; 3573 u8 rsvd3; 3574 }; 3575 3576 /* hwrm_port_led_cfg_output (size:128b/16B) */ 3577 struct hwrm_port_led_cfg_output { 3578 __le16 error_code; 3579 __le16 req_type; 3580 __le16 seq_id; 3581 __le16 resp_len; 3582 u8 unused_0[7]; 3583 u8 valid; 3584 }; 3585 3586 /* hwrm_port_led_qcfg_input (size:192b/24B) */ 3587 struct hwrm_port_led_qcfg_input { 3588 __le16 req_type; 3589 __le16 cmpl_ring; 3590 __le16 seq_id; 3591 __le16 target_id; 3592 __le64 resp_addr; 3593 __le16 port_id; 3594 u8 unused_0[6]; 3595 }; 3596 3597 /* hwrm_port_led_qcfg_output (size:448b/56B) */ 3598 struct hwrm_port_led_qcfg_output { 3599 __le16 error_code; 3600 __le16 req_type; 3601 __le16 seq_id; 3602 __le16 resp_len; 3603 u8 num_leds; 3604 u8 led0_id; 3605 u8 led0_type; 3606 #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED 0x0UL 3607 #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL 3608 #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 0xffUL 3609 #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 3610 u8 led0_state; 3611 #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT 0x0UL 3612 #define PORT_LED_QCFG_RESP_LED0_STATE_OFF 0x1UL 3613 #define PORT_LED_QCFG_RESP_LED0_STATE_ON 0x2UL 3614 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK 0x3UL 3615 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL 3616 #define PORT_LED_QCFG_RESP_LED0_STATE_LAST PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 3617 u8 led0_color; 3618 #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT 0x0UL 3619 #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER 0x1UL 3620 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN 0x2UL 3621 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL 3622 #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 3623 u8 unused_0; 3624 __le16 led0_blink_on; 3625 __le16 led0_blink_off; 3626 u8 led0_group_id; 3627 u8 led1_id; 3628 u8 led1_type; 3629 #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED 0x0UL 3630 #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL 3631 #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 0xffUL 3632 #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 3633 u8 led1_state; 3634 #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT 0x0UL 3635 #define PORT_LED_QCFG_RESP_LED1_STATE_OFF 0x1UL 3636 #define PORT_LED_QCFG_RESP_LED1_STATE_ON 0x2UL 3637 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK 0x3UL 3638 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL 3639 #define PORT_LED_QCFG_RESP_LED1_STATE_LAST PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 3640 u8 led1_color; 3641 #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT 0x0UL 3642 #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER 0x1UL 3643 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN 0x2UL 3644 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL 3645 #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 3646 u8 unused_1; 3647 __le16 led1_blink_on; 3648 __le16 led1_blink_off; 3649 u8 led1_group_id; 3650 u8 led2_id; 3651 u8 led2_type; 3652 #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED 0x0UL 3653 #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL 3654 #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 0xffUL 3655 #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 3656 u8 led2_state; 3657 #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT 0x0UL 3658 #define PORT_LED_QCFG_RESP_LED2_STATE_OFF 0x1UL 3659 #define PORT_LED_QCFG_RESP_LED2_STATE_ON 0x2UL 3660 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK 0x3UL 3661 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL 3662 #define PORT_LED_QCFG_RESP_LED2_STATE_LAST PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 3663 u8 led2_color; 3664 #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT 0x0UL 3665 #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER 0x1UL 3666 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN 0x2UL 3667 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL 3668 #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 3669 u8 unused_2; 3670 __le16 led2_blink_on; 3671 __le16 led2_blink_off; 3672 u8 led2_group_id; 3673 u8 led3_id; 3674 u8 led3_type; 3675 #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED 0x0UL 3676 #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL 3677 #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 0xffUL 3678 #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 3679 u8 led3_state; 3680 #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT 0x0UL 3681 #define PORT_LED_QCFG_RESP_LED3_STATE_OFF 0x1UL 3682 #define PORT_LED_QCFG_RESP_LED3_STATE_ON 0x2UL 3683 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK 0x3UL 3684 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL 3685 #define PORT_LED_QCFG_RESP_LED3_STATE_LAST PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 3686 u8 led3_color; 3687 #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT 0x0UL 3688 #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER 0x1UL 3689 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN 0x2UL 3690 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL 3691 #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 3692 u8 unused_3; 3693 __le16 led3_blink_on; 3694 __le16 led3_blink_off; 3695 u8 led3_group_id; 3696 u8 unused_4[6]; 3697 u8 valid; 3698 }; 3699 3700 /* hwrm_port_led_qcaps_input (size:192b/24B) */ 3701 struct hwrm_port_led_qcaps_input { 3702 __le16 req_type; 3703 __le16 cmpl_ring; 3704 __le16 seq_id; 3705 __le16 target_id; 3706 __le64 resp_addr; 3707 __le16 port_id; 3708 u8 unused_0[6]; 3709 }; 3710 3711 /* hwrm_port_led_qcaps_output (size:384b/48B) */ 3712 struct hwrm_port_led_qcaps_output { 3713 __le16 error_code; 3714 __le16 req_type; 3715 __le16 seq_id; 3716 __le16 resp_len; 3717 u8 num_leds; 3718 u8 unused[3]; 3719 u8 led0_id; 3720 u8 led0_type; 3721 #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL 3722 #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL 3723 #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL 3724 #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 3725 u8 led0_group_id; 3726 u8 unused_0; 3727 __le16 led0_state_caps; 3728 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL 3729 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL 3730 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL 3731 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL 3732 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 3733 __le16 led0_color_caps; 3734 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL 3735 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 3736 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 3737 u8 led1_id; 3738 u8 led1_type; 3739 #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL 3740 #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL 3741 #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL 3742 #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 3743 u8 led1_group_id; 3744 u8 unused_1; 3745 __le16 led1_state_caps; 3746 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL 3747 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL 3748 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL 3749 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL 3750 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 3751 __le16 led1_color_caps; 3752 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL 3753 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 3754 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 3755 u8 led2_id; 3756 u8 led2_type; 3757 #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL 3758 #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL 3759 #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL 3760 #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 3761 u8 led2_group_id; 3762 u8 unused_2; 3763 __le16 led2_state_caps; 3764 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL 3765 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL 3766 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL 3767 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL 3768 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 3769 __le16 led2_color_caps; 3770 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL 3771 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 3772 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 3773 u8 led3_id; 3774 u8 led3_type; 3775 #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL 3776 #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL 3777 #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL 3778 #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 3779 u8 led3_group_id; 3780 u8 unused_3; 3781 __le16 led3_state_caps; 3782 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL 3783 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL 3784 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL 3785 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL 3786 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 3787 __le16 led3_color_caps; 3788 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL 3789 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 3790 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 3791 u8 unused_4[3]; 3792 u8 valid; 3793 }; 3794 3795 /* hwrm_queue_qportcfg_input (size:192b/24B) */ 3796 struct hwrm_queue_qportcfg_input { 3797 __le16 req_type; 3798 __le16 cmpl_ring; 3799 __le16 seq_id; 3800 __le16 target_id; 3801 __le64 resp_addr; 3802 __le32 flags; 3803 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 3804 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL 3805 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL 3806 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 3807 __le16 port_id; 3808 u8 drv_qmap_cap; 3809 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL 3810 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 0x1UL 3811 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 3812 u8 unused_0; 3813 }; 3814 3815 /* hwrm_queue_qportcfg_output (size:256b/32B) */ 3816 struct hwrm_queue_qportcfg_output { 3817 __le16 error_code; 3818 __le16 req_type; 3819 __le16 seq_id; 3820 __le16 resp_len; 3821 u8 max_configurable_queues; 3822 u8 max_configurable_lossless_queues; 3823 u8 queue_cfg_allowed; 3824 u8 queue_cfg_info; 3825 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 3826 u8 queue_pfcenable_cfg_allowed; 3827 u8 queue_pri2cos_cfg_allowed; 3828 u8 queue_cos2bw_cfg_allowed; 3829 u8 queue_id0; 3830 u8 queue_id0_service_profile; 3831 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 3832 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL 3833 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3834 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3835 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3836 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL 3837 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 3838 u8 queue_id1; 3839 u8 queue_id1_service_profile; 3840 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 3841 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL 3842 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3843 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3844 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3845 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL 3846 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 3847 u8 queue_id2; 3848 u8 queue_id2_service_profile; 3849 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 3850 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL 3851 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3852 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3853 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3854 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL 3855 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 3856 u8 queue_id3; 3857 u8 queue_id3_service_profile; 3858 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 3859 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL 3860 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3861 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3862 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3863 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL 3864 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 3865 u8 queue_id4; 3866 u8 queue_id4_service_profile; 3867 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 3868 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL 3869 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3870 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3871 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3872 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL 3873 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 3874 u8 queue_id5; 3875 u8 queue_id5_service_profile; 3876 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 3877 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL 3878 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3879 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3880 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3881 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL 3882 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 3883 u8 queue_id6; 3884 u8 queue_id6_service_profile; 3885 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 3886 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL 3887 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3888 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3889 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3890 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL 3891 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 3892 u8 queue_id7; 3893 u8 queue_id7_service_profile; 3894 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 3895 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL 3896 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3897 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3898 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3899 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 3900 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 3901 u8 valid; 3902 }; 3903 3904 /* hwrm_queue_cfg_input (size:320b/40B) */ 3905 struct hwrm_queue_cfg_input { 3906 __le16 req_type; 3907 __le16 cmpl_ring; 3908 __le16 seq_id; 3909 __le16 target_id; 3910 __le64 resp_addr; 3911 __le32 flags; 3912 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL 3913 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0 3914 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL 3915 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL 3916 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 3917 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 3918 __le32 enables; 3919 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 3920 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 3921 __le32 queue_id; 3922 __le32 dflt_len; 3923 u8 service_profile; 3924 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL 3925 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL 3926 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL 3927 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 3928 u8 unused_0[7]; 3929 }; 3930 3931 /* hwrm_queue_cfg_output (size:128b/16B) */ 3932 struct hwrm_queue_cfg_output { 3933 __le16 error_code; 3934 __le16 req_type; 3935 __le16 seq_id; 3936 __le16 resp_len; 3937 u8 unused_0[7]; 3938 u8 valid; 3939 }; 3940 3941 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */ 3942 struct hwrm_queue_pfcenable_qcfg_input { 3943 __le16 req_type; 3944 __le16 cmpl_ring; 3945 __le16 seq_id; 3946 __le16 target_id; 3947 __le64 resp_addr; 3948 __le16 port_id; 3949 u8 unused_0[6]; 3950 }; 3951 3952 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */ 3953 struct hwrm_queue_pfcenable_qcfg_output { 3954 __le16 error_code; 3955 __le16 req_type; 3956 __le16 seq_id; 3957 __le16 resp_len; 3958 __le32 flags; 3959 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL 3960 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL 3961 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL 3962 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL 3963 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL 3964 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL 3965 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL 3966 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL 3967 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 3968 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 3969 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 3970 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 3971 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 3972 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 3973 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 3974 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 3975 u8 unused_0[3]; 3976 u8 valid; 3977 }; 3978 3979 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */ 3980 struct hwrm_queue_pfcenable_cfg_input { 3981 __le16 req_type; 3982 __le16 cmpl_ring; 3983 __le16 seq_id; 3984 __le16 target_id; 3985 __le64 resp_addr; 3986 __le32 flags; 3987 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 3988 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 3989 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 3990 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 3991 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 3992 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 3993 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 3994 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 3995 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 3996 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 3997 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 3998 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 3999 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 4000 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 4001 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 4002 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 4003 __le16 port_id; 4004 u8 unused_0[2]; 4005 }; 4006 4007 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */ 4008 struct hwrm_queue_pfcenable_cfg_output { 4009 __le16 error_code; 4010 __le16 req_type; 4011 __le16 seq_id; 4012 __le16 resp_len; 4013 u8 unused_0[7]; 4014 u8 valid; 4015 }; 4016 4017 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */ 4018 struct hwrm_queue_pri2cos_qcfg_input { 4019 __le16 req_type; 4020 __le16 cmpl_ring; 4021 __le16 seq_id; 4022 __le16 target_id; 4023 __le64 resp_addr; 4024 __le32 flags; 4025 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL 4026 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX 0x0UL 4027 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 0x1UL 4028 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 4029 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL 4030 u8 port_id; 4031 u8 unused_0[3]; 4032 }; 4033 4034 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */ 4035 struct hwrm_queue_pri2cos_qcfg_output { 4036 __le16 error_code; 4037 __le16 req_type; 4038 __le16 seq_id; 4039 __le16 resp_len; 4040 u8 pri0_cos_queue_id; 4041 u8 pri1_cos_queue_id; 4042 u8 pri2_cos_queue_id; 4043 u8 pri3_cos_queue_id; 4044 u8 pri4_cos_queue_id; 4045 u8 pri5_cos_queue_id; 4046 u8 pri6_cos_queue_id; 4047 u8 pri7_cos_queue_id; 4048 u8 queue_cfg_info; 4049 #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 4050 u8 unused_0[6]; 4051 u8 valid; 4052 }; 4053 4054 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */ 4055 struct hwrm_queue_pri2cos_cfg_input { 4056 __le16 req_type; 4057 __le16 cmpl_ring; 4058 __le16 seq_id; 4059 __le16 target_id; 4060 __le64 resp_addr; 4061 __le32 flags; 4062 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL 4063 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0 4064 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX 0x0UL 4065 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 0x1UL 4066 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 4067 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 4068 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL 4069 __le32 enables; 4070 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL 4071 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL 4072 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL 4073 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL 4074 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL 4075 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL 4076 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL 4077 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL 4078 u8 port_id; 4079 u8 pri0_cos_queue_id; 4080 u8 pri1_cos_queue_id; 4081 u8 pri2_cos_queue_id; 4082 u8 pri3_cos_queue_id; 4083 u8 pri4_cos_queue_id; 4084 u8 pri5_cos_queue_id; 4085 u8 pri6_cos_queue_id; 4086 u8 pri7_cos_queue_id; 4087 u8 unused_0[7]; 4088 }; 4089 4090 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */ 4091 struct hwrm_queue_pri2cos_cfg_output { 4092 __le16 error_code; 4093 __le16 req_type; 4094 __le16 seq_id; 4095 __le16 resp_len; 4096 u8 unused_0[7]; 4097 u8 valid; 4098 }; 4099 4100 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */ 4101 struct hwrm_queue_cos2bw_qcfg_input { 4102 __le16 req_type; 4103 __le16 cmpl_ring; 4104 __le16 seq_id; 4105 __le16 target_id; 4106 __le64 resp_addr; 4107 __le16 port_id; 4108 u8 unused_0[6]; 4109 }; 4110 4111 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */ 4112 struct hwrm_queue_cos2bw_qcfg_output { 4113 __le16 error_code; 4114 __le16 req_type; 4115 __le16 seq_id; 4116 __le16 resp_len; 4117 u8 queue_id0; 4118 u8 unused_0; 4119 __le16 unused_1; 4120 __le32 queue_id0_min_bw; 4121 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4122 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 4123 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 4124 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 4125 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 4126 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES 4127 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4128 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 4129 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4130 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4131 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4132 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4133 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4134 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4135 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 4136 __le32 queue_id0_max_bw; 4137 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4138 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 4139 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 4140 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 4141 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 4142 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES 4143 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4144 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 4145 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4146 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4147 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4148 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4149 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4150 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4151 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 4152 u8 queue_id0_tsa_assign; 4153 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 4154 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 4155 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4156 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 4157 u8 queue_id0_pri_lvl; 4158 u8 queue_id0_bw_weight; 4159 u8 queue_id1; 4160 __le32 queue_id1_min_bw; 4161 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4162 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 4163 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 4164 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 4165 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 4166 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES 4167 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4168 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 4169 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4170 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4171 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4172 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4173 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4174 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4175 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 4176 __le32 queue_id1_max_bw; 4177 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4178 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 4179 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 4180 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 4181 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 4182 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES 4183 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4184 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 4185 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4186 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4187 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4188 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4189 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4190 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4191 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 4192 u8 queue_id1_tsa_assign; 4193 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 4194 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 4195 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4196 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 4197 u8 queue_id1_pri_lvl; 4198 u8 queue_id1_bw_weight; 4199 u8 queue_id2; 4200 __le32 queue_id2_min_bw; 4201 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4202 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 4203 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 4204 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 4205 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 4206 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES 4207 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4208 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 4209 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4210 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4211 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4212 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4213 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4214 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4215 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 4216 __le32 queue_id2_max_bw; 4217 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4218 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 4219 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 4220 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 4221 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 4222 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES 4223 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4224 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 4225 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4226 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4227 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4228 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4229 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4230 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4231 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 4232 u8 queue_id2_tsa_assign; 4233 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 4234 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 4235 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4236 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 4237 u8 queue_id2_pri_lvl; 4238 u8 queue_id2_bw_weight; 4239 u8 queue_id3; 4240 __le32 queue_id3_min_bw; 4241 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4242 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 4243 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 4244 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 4245 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 4246 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES 4247 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4248 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 4249 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4250 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4251 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4252 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4253 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4254 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4255 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 4256 __le32 queue_id3_max_bw; 4257 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4258 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 4259 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 4260 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 4261 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 4262 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES 4263 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4264 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 4265 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4266 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4267 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4268 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4269 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4270 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4271 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 4272 u8 queue_id3_tsa_assign; 4273 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 4274 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 4275 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4276 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 4277 u8 queue_id3_pri_lvl; 4278 u8 queue_id3_bw_weight; 4279 u8 queue_id4; 4280 __le32 queue_id4_min_bw; 4281 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4282 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 4283 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 4284 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 4285 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 4286 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES 4287 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4288 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 4289 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4290 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4291 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4292 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4293 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4294 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4295 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 4296 __le32 queue_id4_max_bw; 4297 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4298 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 4299 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 4300 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 4301 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 4302 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES 4303 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4304 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 4305 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4306 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4307 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4308 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4309 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4310 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4311 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 4312 u8 queue_id4_tsa_assign; 4313 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 4314 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 4315 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4316 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 4317 u8 queue_id4_pri_lvl; 4318 u8 queue_id4_bw_weight; 4319 u8 queue_id5; 4320 __le32 queue_id5_min_bw; 4321 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4322 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 4323 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 4324 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 4325 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 4326 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES 4327 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4328 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 4329 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4330 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4331 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4332 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4333 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4334 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4335 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 4336 __le32 queue_id5_max_bw; 4337 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4338 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 4339 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 4340 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 4341 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 4342 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES 4343 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4344 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 4345 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4346 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4347 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4348 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4349 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4350 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4351 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 4352 u8 queue_id5_tsa_assign; 4353 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 4354 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 4355 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4356 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 4357 u8 queue_id5_pri_lvl; 4358 u8 queue_id5_bw_weight; 4359 u8 queue_id6; 4360 __le32 queue_id6_min_bw; 4361 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4362 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 4363 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 4364 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 4365 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 4366 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES 4367 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4368 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 4369 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4370 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4371 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4372 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4373 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4374 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4375 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 4376 __le32 queue_id6_max_bw; 4377 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4378 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 4379 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 4380 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 4381 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 4382 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES 4383 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4384 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 4385 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4386 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4387 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4388 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4389 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4390 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4391 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 4392 u8 queue_id6_tsa_assign; 4393 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 4394 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 4395 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4396 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 4397 u8 queue_id6_pri_lvl; 4398 u8 queue_id6_bw_weight; 4399 u8 queue_id7; 4400 __le32 queue_id7_min_bw; 4401 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4402 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 4403 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 4404 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 4405 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 4406 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES 4407 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4408 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 4409 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4410 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4411 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4412 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4413 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4414 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4415 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 4416 __le32 queue_id7_max_bw; 4417 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4418 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 4419 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 4420 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 4421 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 4422 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES 4423 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4424 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 4425 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4426 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4427 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4428 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4429 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4430 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4431 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 4432 u8 queue_id7_tsa_assign; 4433 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 4434 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 4435 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4436 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 4437 u8 queue_id7_pri_lvl; 4438 u8 queue_id7_bw_weight; 4439 u8 unused_2[4]; 4440 u8 valid; 4441 }; 4442 4443 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */ 4444 struct hwrm_queue_cos2bw_cfg_input { 4445 __le16 req_type; 4446 __le16 cmpl_ring; 4447 __le16 seq_id; 4448 __le16 target_id; 4449 __le64 resp_addr; 4450 __le32 flags; 4451 __le32 enables; 4452 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 4453 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 4454 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 4455 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 4456 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 4457 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 4458 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 4459 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 4460 __le16 port_id; 4461 u8 queue_id0; 4462 u8 unused_0; 4463 __le32 queue_id0_min_bw; 4464 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4465 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 4466 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 4467 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 4468 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 4469 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES 4470 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4471 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 4472 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4473 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4474 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4475 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4476 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4477 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4478 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 4479 __le32 queue_id0_max_bw; 4480 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4481 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 4482 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 4483 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 4484 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 4485 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES 4486 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4487 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 4488 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4489 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4490 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4491 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4492 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4493 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4494 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 4495 u8 queue_id0_tsa_assign; 4496 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 4497 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 4498 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4499 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 4500 u8 queue_id0_pri_lvl; 4501 u8 queue_id0_bw_weight; 4502 u8 queue_id1; 4503 __le32 queue_id1_min_bw; 4504 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4505 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 4506 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 4507 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 4508 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 4509 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES 4510 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4511 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 4512 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4513 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4514 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4515 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4516 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4517 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4518 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 4519 __le32 queue_id1_max_bw; 4520 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4521 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 4522 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 4523 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 4524 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 4525 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES 4526 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4527 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 4528 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4529 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4530 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4531 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4532 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4533 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4534 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 4535 u8 queue_id1_tsa_assign; 4536 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 4537 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 4538 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4539 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 4540 u8 queue_id1_pri_lvl; 4541 u8 queue_id1_bw_weight; 4542 u8 queue_id2; 4543 __le32 queue_id2_min_bw; 4544 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4545 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 4546 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 4547 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 4548 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 4549 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES 4550 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4551 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 4552 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4553 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4554 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4555 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4556 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4557 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4558 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 4559 __le32 queue_id2_max_bw; 4560 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4561 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 4562 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 4563 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 4564 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 4565 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES 4566 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4567 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 4568 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4569 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4570 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4571 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4572 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4573 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4574 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 4575 u8 queue_id2_tsa_assign; 4576 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 4577 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 4578 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4579 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 4580 u8 queue_id2_pri_lvl; 4581 u8 queue_id2_bw_weight; 4582 u8 queue_id3; 4583 __le32 queue_id3_min_bw; 4584 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4585 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 4586 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 4587 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 4588 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 4589 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES 4590 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4591 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 4592 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4593 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4594 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4595 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4596 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4597 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4598 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 4599 __le32 queue_id3_max_bw; 4600 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4601 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 4602 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 4603 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 4604 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 4605 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES 4606 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4607 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 4608 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4609 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4610 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4611 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4612 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4613 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4614 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 4615 u8 queue_id3_tsa_assign; 4616 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 4617 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 4618 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4619 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 4620 u8 queue_id3_pri_lvl; 4621 u8 queue_id3_bw_weight; 4622 u8 queue_id4; 4623 __le32 queue_id4_min_bw; 4624 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4625 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 4626 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 4627 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 4628 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 4629 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES 4630 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4631 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 4632 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4633 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4634 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4635 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4636 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4637 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4638 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 4639 __le32 queue_id4_max_bw; 4640 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4641 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 4642 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 4643 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 4644 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 4645 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES 4646 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4647 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 4648 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4649 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4650 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4651 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4652 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4653 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4654 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 4655 u8 queue_id4_tsa_assign; 4656 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 4657 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 4658 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4659 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 4660 u8 queue_id4_pri_lvl; 4661 u8 queue_id4_bw_weight; 4662 u8 queue_id5; 4663 __le32 queue_id5_min_bw; 4664 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4665 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 4666 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 4667 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 4668 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 4669 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES 4670 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4671 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 4672 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4673 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4674 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4675 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4676 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4677 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4678 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 4679 __le32 queue_id5_max_bw; 4680 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4681 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 4682 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 4683 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 4684 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 4685 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES 4686 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4687 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 4688 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4689 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4690 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4691 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4692 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4693 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4694 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 4695 u8 queue_id5_tsa_assign; 4696 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 4697 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 4698 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4699 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 4700 u8 queue_id5_pri_lvl; 4701 u8 queue_id5_bw_weight; 4702 u8 queue_id6; 4703 __le32 queue_id6_min_bw; 4704 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4705 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 4706 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 4707 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 4708 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 4709 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES 4710 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4711 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 4712 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4713 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4714 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4715 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4716 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4717 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4718 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 4719 __le32 queue_id6_max_bw; 4720 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4721 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 4722 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 4723 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 4724 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 4725 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES 4726 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4727 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 4728 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4729 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4730 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4731 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4732 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4733 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4734 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 4735 u8 queue_id6_tsa_assign; 4736 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 4737 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 4738 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4739 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 4740 u8 queue_id6_pri_lvl; 4741 u8 queue_id6_bw_weight; 4742 u8 queue_id7; 4743 __le32 queue_id7_min_bw; 4744 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4745 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 4746 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 4747 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 4748 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 4749 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES 4750 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4751 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 4752 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4753 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4754 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4755 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4756 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4757 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4758 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 4759 __le32 queue_id7_max_bw; 4760 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4761 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 4762 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 4763 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 4764 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 4765 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES 4766 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4767 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 4768 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4769 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4770 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4771 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4772 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4773 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4774 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 4775 u8 queue_id7_tsa_assign; 4776 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 4777 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 4778 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4779 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 4780 u8 queue_id7_pri_lvl; 4781 u8 queue_id7_bw_weight; 4782 u8 unused_1[5]; 4783 }; 4784 4785 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */ 4786 struct hwrm_queue_cos2bw_cfg_output { 4787 __le16 error_code; 4788 __le16 req_type; 4789 __le16 seq_id; 4790 __le16 resp_len; 4791 u8 unused_0[7]; 4792 u8 valid; 4793 }; 4794 4795 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ 4796 struct hwrm_queue_dscp_qcaps_input { 4797 __le16 req_type; 4798 __le16 cmpl_ring; 4799 __le16 seq_id; 4800 __le16 target_id; 4801 __le64 resp_addr; 4802 u8 port_id; 4803 u8 unused_0[7]; 4804 }; 4805 4806 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ 4807 struct hwrm_queue_dscp_qcaps_output { 4808 __le16 error_code; 4809 __le16 req_type; 4810 __le16 seq_id; 4811 __le16 resp_len; 4812 u8 num_dscp_bits; 4813 u8 unused_0; 4814 __le16 max_entries; 4815 u8 unused_1[3]; 4816 u8 valid; 4817 }; 4818 4819 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ 4820 struct hwrm_queue_dscp2pri_qcfg_input { 4821 __le16 req_type; 4822 __le16 cmpl_ring; 4823 __le16 seq_id; 4824 __le16 target_id; 4825 __le64 resp_addr; 4826 __le64 dest_data_addr; 4827 u8 port_id; 4828 u8 unused_0; 4829 __le16 dest_data_buffer_size; 4830 u8 unused_1[4]; 4831 }; 4832 4833 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ 4834 struct hwrm_queue_dscp2pri_qcfg_output { 4835 __le16 error_code; 4836 __le16 req_type; 4837 __le16 seq_id; 4838 __le16 resp_len; 4839 __le16 entry_cnt; 4840 u8 default_pri; 4841 u8 unused_0[4]; 4842 u8 valid; 4843 }; 4844 4845 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ 4846 struct hwrm_queue_dscp2pri_cfg_input { 4847 __le16 req_type; 4848 __le16 cmpl_ring; 4849 __le16 seq_id; 4850 __le16 target_id; 4851 __le64 resp_addr; 4852 __le64 src_data_addr; 4853 __le32 flags; 4854 #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL 4855 __le32 enables; 4856 #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL 4857 u8 port_id; 4858 u8 default_pri; 4859 __le16 entry_cnt; 4860 u8 unused_0[4]; 4861 }; 4862 4863 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ 4864 struct hwrm_queue_dscp2pri_cfg_output { 4865 __le16 error_code; 4866 __le16 req_type; 4867 __le16 seq_id; 4868 __le16 resp_len; 4869 u8 unused_0[7]; 4870 u8 valid; 4871 }; 4872 4873 /* hwrm_vnic_alloc_input (size:192b/24B) */ 4874 struct hwrm_vnic_alloc_input { 4875 __le16 req_type; 4876 __le16 cmpl_ring; 4877 __le16 seq_id; 4878 __le16 target_id; 4879 __le64 resp_addr; 4880 __le32 flags; 4881 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 4882 u8 unused_0[4]; 4883 }; 4884 4885 /* hwrm_vnic_alloc_output (size:128b/16B) */ 4886 struct hwrm_vnic_alloc_output { 4887 __le16 error_code; 4888 __le16 req_type; 4889 __le16 seq_id; 4890 __le16 resp_len; 4891 __le32 vnic_id; 4892 u8 unused_0[3]; 4893 u8 valid; 4894 }; 4895 4896 /* hwrm_vnic_free_input (size:192b/24B) */ 4897 struct hwrm_vnic_free_input { 4898 __le16 req_type; 4899 __le16 cmpl_ring; 4900 __le16 seq_id; 4901 __le16 target_id; 4902 __le64 resp_addr; 4903 __le32 vnic_id; 4904 u8 unused_0[4]; 4905 }; 4906 4907 /* hwrm_vnic_free_output (size:128b/16B) */ 4908 struct hwrm_vnic_free_output { 4909 __le16 error_code; 4910 __le16 req_type; 4911 __le16 seq_id; 4912 __le16 resp_len; 4913 u8 unused_0[7]; 4914 u8 valid; 4915 }; 4916 4917 /* hwrm_vnic_cfg_input (size:384b/48B) */ 4918 struct hwrm_vnic_cfg_input { 4919 __le16 req_type; 4920 __le16 cmpl_ring; 4921 __le16 seq_id; 4922 __le16 target_id; 4923 __le64 resp_addr; 4924 __le32 flags; 4925 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 4926 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 4927 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 4928 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 4929 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 4930 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 4931 #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL 4932 __le32 enables; 4933 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 4934 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 4935 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 4936 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 4937 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 4938 #define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID 0x20UL 4939 #define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID 0x40UL 4940 #define VNIC_CFG_REQ_ENABLES_QUEUE_ID 0x80UL 4941 __le16 vnic_id; 4942 __le16 dflt_ring_grp; 4943 __le16 rss_rule; 4944 __le16 cos_rule; 4945 __le16 lb_rule; 4946 __le16 mru; 4947 __le16 default_rx_ring_id; 4948 __le16 default_cmpl_ring_id; 4949 __le16 queue_id; 4950 u8 unused0[6]; 4951 }; 4952 4953 /* hwrm_vnic_cfg_output (size:128b/16B) */ 4954 struct hwrm_vnic_cfg_output { 4955 __le16 error_code; 4956 __le16 req_type; 4957 __le16 seq_id; 4958 __le16 resp_len; 4959 u8 unused_0[7]; 4960 u8 valid; 4961 }; 4962 4963 /* hwrm_vnic_qcaps_input (size:192b/24B) */ 4964 struct hwrm_vnic_qcaps_input { 4965 __le16 req_type; 4966 __le16 cmpl_ring; 4967 __le16 seq_id; 4968 __le16 target_id; 4969 __le64 resp_addr; 4970 __le32 enables; 4971 u8 unused_0[4]; 4972 }; 4973 4974 /* hwrm_vnic_qcaps_output (size:192b/24B) */ 4975 struct hwrm_vnic_qcaps_output { 4976 __le16 error_code; 4977 __le16 req_type; 4978 __le16 seq_id; 4979 __le16 resp_len; 4980 __le16 mru; 4981 u8 unused_0[2]; 4982 __le32 flags; 4983 #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL 4984 #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL 4985 #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL 4986 #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL 4987 #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL 4988 #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL 4989 #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL 4990 #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL 4991 #define VNIC_QCAPS_RESP_FLAGS_COS_ASSIGNMENT_CAP 0x100UL 4992 __le16 max_aggs_supported; 4993 u8 unused_1[5]; 4994 u8 valid; 4995 }; 4996 4997 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */ 4998 struct hwrm_vnic_tpa_cfg_input { 4999 __le16 req_type; 5000 __le16 cmpl_ring; 5001 __le16 seq_id; 5002 __le16 target_id; 5003 __le64 resp_addr; 5004 __le32 flags; 5005 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 5006 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 5007 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 5008 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 5009 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 5010 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 5011 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 5012 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 5013 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_PACK_AS_GRO 0x100UL 5014 __le32 enables; 5015 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 5016 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 5017 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 5018 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 5019 __le16 vnic_id; 5020 __le16 max_agg_segs; 5021 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL 5022 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL 5023 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL 5024 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL 5025 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL 5026 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 5027 __le16 max_aggs; 5028 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL 5029 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL 5030 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL 5031 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL 5032 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL 5033 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL 5034 #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 5035 u8 unused_0[2]; 5036 __le32 max_agg_timer; 5037 __le32 min_agg_len; 5038 }; 5039 5040 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ 5041 struct hwrm_vnic_tpa_cfg_output { 5042 __le16 error_code; 5043 __le16 req_type; 5044 __le16 seq_id; 5045 __le16 resp_len; 5046 u8 unused_0[7]; 5047 u8 valid; 5048 }; 5049 5050 /* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */ 5051 struct hwrm_vnic_tpa_qcfg_input { 5052 __le16 req_type; 5053 __le16 cmpl_ring; 5054 __le16 seq_id; 5055 __le16 target_id; 5056 __le64 resp_addr; 5057 __le16 vnic_id; 5058 u8 unused_0[6]; 5059 }; 5060 5061 /* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */ 5062 struct hwrm_vnic_tpa_qcfg_output { 5063 __le16 error_code; 5064 __le16 req_type; 5065 __le16 seq_id; 5066 __le16 resp_len; 5067 __le32 flags; 5068 #define VNIC_TPA_QCFG_RESP_FLAGS_TPA 0x1UL 5069 #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA 0x2UL 5070 #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE 0x4UL 5071 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO 0x8UL 5072 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN 0x10UL 5073 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 5074 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK 0x40UL 5075 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK 0x80UL 5076 __le16 max_agg_segs; 5077 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1 0x0UL 5078 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2 0x1UL 5079 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4 0x2UL 5080 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8 0x3UL 5081 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL 5082 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 5083 __le16 max_aggs; 5084 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1 0x0UL 5085 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2 0x1UL 5086 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4 0x2UL 5087 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8 0x3UL 5088 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16 0x4UL 5089 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL 5090 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 5091 __le32 max_agg_timer; 5092 __le32 min_agg_len; 5093 u8 unused_0[7]; 5094 u8 valid; 5095 }; 5096 5097 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */ 5098 struct hwrm_vnic_rss_cfg_input { 5099 __le16 req_type; 5100 __le16 cmpl_ring; 5101 __le16 seq_id; 5102 __le16 target_id; 5103 __le64 resp_addr; 5104 __le32 hash_type; 5105 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 5106 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 5107 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 5108 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 5109 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 5110 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 5111 __le16 vnic_id; 5112 u8 ring_table_pair_index; 5113 u8 hash_mode_flags; 5114 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT 0x1UL 5115 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4 0x2UL 5116 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2 0x4UL 5117 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL 5118 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL 5119 __le64 ring_grp_tbl_addr; 5120 __le64 hash_key_tbl_addr; 5121 __le16 rss_ctx_idx; 5122 u8 unused_1[6]; 5123 }; 5124 5125 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */ 5126 struct hwrm_vnic_rss_cfg_output { 5127 __le16 error_code; 5128 __le16 req_type; 5129 __le16 seq_id; 5130 __le16 resp_len; 5131 u8 unused_0[7]; 5132 u8 valid; 5133 }; 5134 5135 /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */ 5136 struct hwrm_vnic_rss_cfg_cmd_err { 5137 u8 code; 5138 #define VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 5139 #define VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 0x1UL 5140 #define VNIC_RSS_CFG_CMD_ERR_CODE_LAST VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 5141 u8 unused_0[7]; 5142 }; 5143 5144 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */ 5145 struct hwrm_vnic_plcmodes_cfg_input { 5146 __le16 req_type; 5147 __le16 cmpl_ring; 5148 __le16 seq_id; 5149 __le16 target_id; 5150 __le64 resp_addr; 5151 __le32 flags; 5152 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 5153 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 5154 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 5155 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 5156 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 5157 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 5158 __le32 enables; 5159 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 5160 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 5161 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 5162 __le32 vnic_id; 5163 __le16 jumbo_thresh; 5164 __le16 hds_offset; 5165 __le16 hds_threshold; 5166 u8 unused_0[6]; 5167 }; 5168 5169 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ 5170 struct hwrm_vnic_plcmodes_cfg_output { 5171 __le16 error_code; 5172 __le16 req_type; 5173 __le16 seq_id; 5174 __le16 resp_len; 5175 u8 unused_0[7]; 5176 u8 valid; 5177 }; 5178 5179 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */ 5180 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 5181 __le16 req_type; 5182 __le16 cmpl_ring; 5183 __le16 seq_id; 5184 __le16 target_id; 5185 __le64 resp_addr; 5186 }; 5187 5188 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ 5189 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 5190 __le16 error_code; 5191 __le16 req_type; 5192 __le16 seq_id; 5193 __le16 resp_len; 5194 __le16 rss_cos_lb_ctx_id; 5195 u8 unused_0[5]; 5196 u8 valid; 5197 }; 5198 5199 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */ 5200 struct hwrm_vnic_rss_cos_lb_ctx_free_input { 5201 __le16 req_type; 5202 __le16 cmpl_ring; 5203 __le16 seq_id; 5204 __le16 target_id; 5205 __le64 resp_addr; 5206 __le16 rss_cos_lb_ctx_id; 5207 u8 unused_0[6]; 5208 }; 5209 5210 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ 5211 struct hwrm_vnic_rss_cos_lb_ctx_free_output { 5212 __le16 error_code; 5213 __le16 req_type; 5214 __le16 seq_id; 5215 __le16 resp_len; 5216 u8 unused_0[7]; 5217 u8 valid; 5218 }; 5219 5220 /* hwrm_ring_alloc_input (size:704b/88B) */ 5221 struct hwrm_ring_alloc_input { 5222 __le16 req_type; 5223 __le16 cmpl_ring; 5224 __le16 seq_id; 5225 __le16 target_id; 5226 __le64 resp_addr; 5227 __le32 enables; 5228 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 5229 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 5230 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 5231 #define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL 5232 #define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL 5233 #define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL 5234 u8 ring_type; 5235 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL 5236 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 5237 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 5238 #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL 5239 #define RING_ALLOC_REQ_RING_TYPE_RX_AGG 0x4UL 5240 #define RING_ALLOC_REQ_RING_TYPE_NQ 0x5UL 5241 #define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_NQ 5242 u8 unused_0; 5243 __le16 flags; 5244 #define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD 0x1UL 5245 __le64 page_tbl_addr; 5246 __le32 fbo; 5247 u8 page_size; 5248 u8 page_tbl_depth; 5249 u8 unused_1[2]; 5250 __le32 length; 5251 __le16 logical_id; 5252 __le16 cmpl_ring_id; 5253 __le16 queue_id; 5254 __le16 rx_buf_size; 5255 __le16 rx_ring_id; 5256 __le16 nq_ring_id; 5257 __le16 ring_arb_cfg; 5258 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 5259 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 5260 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP 0x1UL 5261 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 0x2UL 5262 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 5263 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL 5264 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4 5265 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL 5266 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 5267 __le16 unused_3; 5268 __le32 reserved3; 5269 __le32 stat_ctx_id; 5270 __le32 reserved4; 5271 __le32 max_bw; 5272 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5273 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0 5274 #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL 5275 #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 5276 #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 5277 #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES 5278 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5279 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 5280 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5281 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5282 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5283 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5284 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5285 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5286 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 5287 u8 int_mode; 5288 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL 5289 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL 5290 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL 5291 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 5292 #define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL 5293 u8 unused_4[3]; 5294 __le64 cq_handle; 5295 }; 5296 5297 /* hwrm_ring_alloc_output (size:128b/16B) */ 5298 struct hwrm_ring_alloc_output { 5299 __le16 error_code; 5300 __le16 req_type; 5301 __le16 seq_id; 5302 __le16 resp_len; 5303 __le16 ring_id; 5304 __le16 logical_ring_id; 5305 u8 unused_0[3]; 5306 u8 valid; 5307 }; 5308 5309 /* hwrm_ring_free_input (size:192b/24B) */ 5310 struct hwrm_ring_free_input { 5311 __le16 req_type; 5312 __le16 cmpl_ring; 5313 __le16 seq_id; 5314 __le16 target_id; 5315 __le64 resp_addr; 5316 u8 ring_type; 5317 #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL 5318 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 5319 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 5320 #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL 5321 #define RING_FREE_REQ_RING_TYPE_RX_AGG 0x4UL 5322 #define RING_FREE_REQ_RING_TYPE_NQ 0x5UL 5323 #define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_NQ 5324 u8 unused_0; 5325 __le16 ring_id; 5326 u8 unused_1[4]; 5327 }; 5328 5329 /* hwrm_ring_free_output (size:128b/16B) */ 5330 struct hwrm_ring_free_output { 5331 __le16 error_code; 5332 __le16 req_type; 5333 __le16 seq_id; 5334 __le16 resp_len; 5335 u8 unused_0[7]; 5336 u8 valid; 5337 }; 5338 5339 /* hwrm_ring_reset_input (size:192b/24B) */ 5340 struct hwrm_ring_reset_input { 5341 __le16 req_type; 5342 __le16 cmpl_ring; 5343 __le16 seq_id; 5344 __le16 target_id; 5345 __le64 resp_addr; 5346 u8 ring_type; 5347 #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL 5348 #define RING_RESET_REQ_RING_TYPE_TX 0x1UL 5349 #define RING_RESET_REQ_RING_TYPE_RX 0x2UL 5350 #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL 5351 #define RING_RESET_REQ_RING_TYPE_LAST RING_RESET_REQ_RING_TYPE_ROCE_CMPL 5352 u8 unused_0; 5353 __le16 ring_id; 5354 u8 unused_1[4]; 5355 }; 5356 5357 /* hwrm_ring_reset_output (size:128b/16B) */ 5358 struct hwrm_ring_reset_output { 5359 __le16 error_code; 5360 __le16 req_type; 5361 __le16 seq_id; 5362 __le16 resp_len; 5363 u8 unused_0[4]; 5364 u8 consumer_idx[3]; 5365 u8 valid; 5366 }; 5367 5368 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */ 5369 struct hwrm_ring_aggint_qcaps_input { 5370 __le16 req_type; 5371 __le16 cmpl_ring; 5372 __le16 seq_id; 5373 __le16 target_id; 5374 __le64 resp_addr; 5375 }; 5376 5377 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */ 5378 struct hwrm_ring_aggint_qcaps_output { 5379 __le16 error_code; 5380 __le16 req_type; 5381 __le16 seq_id; 5382 __le16 resp_len; 5383 __le32 cmpl_params; 5384 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN 0x1UL 5385 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX 0x2UL 5386 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET 0x4UL 5387 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE 0x8UL 5388 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR 0x10UL 5389 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT 0x20UL 5390 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR 0x40UL 5391 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT 0x80UL 5392 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT 0x100UL 5393 __le32 nq_params; 5394 #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN 0x1UL 5395 __le16 num_cmpl_dma_aggr_min; 5396 __le16 num_cmpl_dma_aggr_max; 5397 __le16 num_cmpl_dma_aggr_during_int_min; 5398 __le16 num_cmpl_dma_aggr_during_int_max; 5399 __le16 cmpl_aggr_dma_tmr_min; 5400 __le16 cmpl_aggr_dma_tmr_max; 5401 __le16 cmpl_aggr_dma_tmr_during_int_min; 5402 __le16 cmpl_aggr_dma_tmr_during_int_max; 5403 __le16 int_lat_tmr_min_min; 5404 __le16 int_lat_tmr_min_max; 5405 __le16 int_lat_tmr_max_min; 5406 __le16 int_lat_tmr_max_max; 5407 __le16 num_cmpl_aggr_int_min; 5408 __le16 num_cmpl_aggr_int_max; 5409 __le16 timer_units; 5410 u8 unused_0[1]; 5411 u8 valid; 5412 }; 5413 5414 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ 5415 struct hwrm_ring_cmpl_ring_qaggint_params_input { 5416 __le16 req_type; 5417 __le16 cmpl_ring; 5418 __le16 seq_id; 5419 __le16 target_id; 5420 __le64 resp_addr; 5421 __le16 ring_id; 5422 __le16 flags; 5423 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_MASK 0x3UL 5424 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_SFT 0 5425 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 5426 u8 unused_0[4]; 5427 }; 5428 5429 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ 5430 struct hwrm_ring_cmpl_ring_qaggint_params_output { 5431 __le16 error_code; 5432 __le16 req_type; 5433 __le16 seq_id; 5434 __le16 resp_len; 5435 __le16 flags; 5436 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 5437 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 5438 __le16 num_cmpl_dma_aggr; 5439 __le16 num_cmpl_dma_aggr_during_int; 5440 __le16 cmpl_aggr_dma_tmr; 5441 __le16 cmpl_aggr_dma_tmr_during_int; 5442 __le16 int_lat_tmr_min; 5443 __le16 int_lat_tmr_max; 5444 __le16 num_cmpl_aggr_int; 5445 u8 unused_0[7]; 5446 u8 valid; 5447 }; 5448 5449 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ 5450 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 5451 __le16 req_type; 5452 __le16 cmpl_ring; 5453 __le16 seq_id; 5454 __le16 target_id; 5455 __le64 resp_addr; 5456 __le16 ring_id; 5457 __le16 flags; 5458 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 5459 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 5460 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 5461 __le16 num_cmpl_dma_aggr; 5462 __le16 num_cmpl_dma_aggr_during_int; 5463 __le16 cmpl_aggr_dma_tmr; 5464 __le16 cmpl_aggr_dma_tmr_during_int; 5465 __le16 int_lat_tmr_min; 5466 __le16 int_lat_tmr_max; 5467 __le16 num_cmpl_aggr_int; 5468 __le16 enables; 5469 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR 0x1UL 5470 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 0x2UL 5471 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR 0x4UL 5472 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 0x8UL 5473 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX 0x10UL 5474 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT 0x20UL 5475 u8 unused_0[4]; 5476 }; 5477 5478 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ 5479 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 5480 __le16 error_code; 5481 __le16 req_type; 5482 __le16 seq_id; 5483 __le16 resp_len; 5484 u8 unused_0[7]; 5485 u8 valid; 5486 }; 5487 5488 /* hwrm_ring_grp_alloc_input (size:192b/24B) */ 5489 struct hwrm_ring_grp_alloc_input { 5490 __le16 req_type; 5491 __le16 cmpl_ring; 5492 __le16 seq_id; 5493 __le16 target_id; 5494 __le64 resp_addr; 5495 __le16 cr; 5496 __le16 rr; 5497 __le16 ar; 5498 __le16 sc; 5499 }; 5500 5501 /* hwrm_ring_grp_alloc_output (size:128b/16B) */ 5502 struct hwrm_ring_grp_alloc_output { 5503 __le16 error_code; 5504 __le16 req_type; 5505 __le16 seq_id; 5506 __le16 resp_len; 5507 __le32 ring_group_id; 5508 u8 unused_0[3]; 5509 u8 valid; 5510 }; 5511 5512 /* hwrm_ring_grp_free_input (size:192b/24B) */ 5513 struct hwrm_ring_grp_free_input { 5514 __le16 req_type; 5515 __le16 cmpl_ring; 5516 __le16 seq_id; 5517 __le16 target_id; 5518 __le64 resp_addr; 5519 __le32 ring_group_id; 5520 u8 unused_0[4]; 5521 }; 5522 5523 /* hwrm_ring_grp_free_output (size:128b/16B) */ 5524 struct hwrm_ring_grp_free_output { 5525 __le16 error_code; 5526 __le16 req_type; 5527 __le16 seq_id; 5528 __le16 resp_len; 5529 u8 unused_0[7]; 5530 u8 valid; 5531 }; 5532 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL 5533 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL 5534 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL 5535 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL 5536 5537 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ 5538 struct hwrm_cfa_l2_filter_alloc_input { 5539 __le16 req_type; 5540 __le16 cmpl_ring; 5541 __le16 seq_id; 5542 __le16 target_id; 5543 __le64 resp_addr; 5544 __le32 flags; 5545 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 5546 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL 5547 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL 5548 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 5549 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 5550 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 5551 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 5552 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK 0x30UL 5553 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT 4 5554 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 4) 5555 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 4) 5556 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 4) 5557 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE 5558 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_XDP_DISABLE 0x40UL 5559 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_SOURCE_VALID 0x80UL 5560 __le32 enables; 5561 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 5562 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 5563 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 5564 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 5565 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 5566 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 5567 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 5568 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 5569 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 5570 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 5571 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 5572 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 5573 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 5574 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 5575 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 5576 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 5577 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 5578 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_NUM_VLANS 0x20000UL 5579 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_NUM_VLANS 0x40000UL 5580 u8 l2_addr[6]; 5581 u8 num_vlans; 5582 u8 t_num_vlans; 5583 u8 l2_addr_mask[6]; 5584 __le16 l2_ovlan; 5585 __le16 l2_ovlan_mask; 5586 __le16 l2_ivlan; 5587 __le16 l2_ivlan_mask; 5588 u8 unused_1[2]; 5589 u8 t_l2_addr[6]; 5590 u8 unused_2[2]; 5591 u8 t_l2_addr_mask[6]; 5592 __le16 t_l2_ovlan; 5593 __le16 t_l2_ovlan_mask; 5594 __le16 t_l2_ivlan; 5595 __le16 t_l2_ivlan_mask; 5596 u8 src_type; 5597 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 5598 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL 5599 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL 5600 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL 5601 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL 5602 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL 5603 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL 5604 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL 5605 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 5606 u8 unused_3; 5607 __le32 src_id; 5608 u8 tunnel_type; 5609 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 5610 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5611 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 5612 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 5613 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 5614 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5615 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 5616 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 5617 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 5618 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5619 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 5620 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 5621 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 5622 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 5623 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 5624 u8 unused_4; 5625 __le16 dst_id; 5626 __le16 mirror_vnic_id; 5627 u8 pri_hint; 5628 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 5629 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL 5630 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL 5631 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL 5632 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL 5633 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 5634 u8 unused_5; 5635 __le32 unused_6; 5636 __le64 l2_filter_id_hint; 5637 }; 5638 5639 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ 5640 struct hwrm_cfa_l2_filter_alloc_output { 5641 __le16 error_code; 5642 __le16 req_type; 5643 __le16 seq_id; 5644 __le16 resp_len; 5645 __le64 l2_filter_id; 5646 __le32 flow_id; 5647 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 5648 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 5649 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 5650 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 5651 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 5652 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 5653 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 5654 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 5655 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 5656 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 5657 u8 unused_0[3]; 5658 u8 valid; 5659 }; 5660 5661 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ 5662 struct hwrm_cfa_l2_filter_free_input { 5663 __le16 req_type; 5664 __le16 cmpl_ring; 5665 __le16 seq_id; 5666 __le16 target_id; 5667 __le64 resp_addr; 5668 __le64 l2_filter_id; 5669 }; 5670 5671 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ 5672 struct hwrm_cfa_l2_filter_free_output { 5673 __le16 error_code; 5674 __le16 req_type; 5675 __le16 seq_id; 5676 __le16 resp_len; 5677 u8 unused_0[7]; 5678 u8 valid; 5679 }; 5680 5681 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */ 5682 struct hwrm_cfa_l2_filter_cfg_input { 5683 __le16 req_type; 5684 __le16 cmpl_ring; 5685 __le16 seq_id; 5686 __le16 target_id; 5687 __le64 resp_addr; 5688 __le32 flags; 5689 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 5690 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL 5691 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL 5692 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 5693 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 5694 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK 0xcUL 5695 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT 2 5696 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 2) 5697 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2) 5698 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2) 5699 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE 5700 __le32 enables; 5701 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 5702 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 5703 __le64 l2_filter_id; 5704 __le32 dst_id; 5705 __le32 new_mirror_vnic_id; 5706 }; 5707 5708 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ 5709 struct hwrm_cfa_l2_filter_cfg_output { 5710 __le16 error_code; 5711 __le16 req_type; 5712 __le16 seq_id; 5713 __le16 resp_len; 5714 u8 unused_0[7]; 5715 u8 valid; 5716 }; 5717 5718 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ 5719 struct hwrm_cfa_l2_set_rx_mask_input { 5720 __le16 req_type; 5721 __le16 cmpl_ring; 5722 __le16 seq_id; 5723 __le16 target_id; 5724 __le64 resp_addr; 5725 __le32 vnic_id; 5726 __le32 mask; 5727 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 5728 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 5729 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 5730 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 5731 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 5732 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL 5733 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL 5734 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL 5735 __le64 mc_tbl_addr; 5736 __le32 num_mc_entries; 5737 u8 unused_0[4]; 5738 __le64 vlan_tag_tbl_addr; 5739 __le32 num_vlan_tags; 5740 u8 unused_1[4]; 5741 }; 5742 5743 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ 5744 struct hwrm_cfa_l2_set_rx_mask_output { 5745 __le16 error_code; 5746 __le16 req_type; 5747 __le16 seq_id; 5748 __le16 resp_len; 5749 u8 unused_0[7]; 5750 u8 valid; 5751 }; 5752 5753 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ 5754 struct hwrm_cfa_l2_set_rx_mask_cmd_err { 5755 u8 code; 5756 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL 5757 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL 5758 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 5759 u8 unused_0[7]; 5760 }; 5761 5762 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */ 5763 struct hwrm_cfa_tunnel_filter_alloc_input { 5764 __le16 req_type; 5765 __le16 cmpl_ring; 5766 __le16 seq_id; 5767 __le16 target_id; 5768 __le64 resp_addr; 5769 __le32 flags; 5770 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 5771 __le32 enables; 5772 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 5773 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 5774 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 5775 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 5776 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 5777 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 5778 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 5779 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 5780 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 5781 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 5782 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 5783 __le64 l2_filter_id; 5784 u8 l2_addr[6]; 5785 __le16 l2_ivlan; 5786 __le32 l3_addr[4]; 5787 __le32 t_l3_addr[4]; 5788 u8 l3_addr_type; 5789 u8 t_l3_addr_type; 5790 u8 tunnel_type; 5791 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 5792 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5793 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 5794 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 5795 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 5796 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5797 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 5798 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 5799 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 5800 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5801 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 5802 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 5803 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 5804 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 5805 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 5806 u8 tunnel_flags; 5807 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL 5808 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL 5809 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 0x4UL 5810 __le32 vni; 5811 __le32 dst_vnic_id; 5812 __le32 mirror_vnic_id; 5813 }; 5814 5815 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */ 5816 struct hwrm_cfa_tunnel_filter_alloc_output { 5817 __le16 error_code; 5818 __le16 req_type; 5819 __le16 seq_id; 5820 __le16 resp_len; 5821 __le64 tunnel_filter_id; 5822 __le32 flow_id; 5823 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 5824 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 5825 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 5826 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 5827 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 5828 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 5829 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 5830 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 5831 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 5832 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 5833 u8 unused_0[3]; 5834 u8 valid; 5835 }; 5836 5837 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */ 5838 struct hwrm_cfa_tunnel_filter_free_input { 5839 __le16 req_type; 5840 __le16 cmpl_ring; 5841 __le16 seq_id; 5842 __le16 target_id; 5843 __le64 resp_addr; 5844 __le64 tunnel_filter_id; 5845 }; 5846 5847 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */ 5848 struct hwrm_cfa_tunnel_filter_free_output { 5849 __le16 error_code; 5850 __le16 req_type; 5851 __le16 seq_id; 5852 __le16 resp_len; 5853 u8 unused_0[7]; 5854 u8 valid; 5855 }; 5856 5857 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */ 5858 struct hwrm_vxlan_ipv4_hdr { 5859 u8 ver_hlen; 5860 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL 5861 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0 5862 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL 5863 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4 5864 u8 tos; 5865 __be16 ip_id; 5866 __be16 flags_frag_offset; 5867 u8 ttl; 5868 u8 protocol; 5869 __be32 src_ip_addr; 5870 __be32 dest_ip_addr; 5871 }; 5872 5873 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */ 5874 struct hwrm_vxlan_ipv6_hdr { 5875 __be32 ver_tc_flow_label; 5876 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL 5877 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL 5878 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL 5879 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL 5880 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL 5881 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL 5882 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 5883 __be16 payload_len; 5884 u8 next_hdr; 5885 u8 ttl; 5886 __be32 src_ip_addr[4]; 5887 __be32 dest_ip_addr[4]; 5888 }; 5889 5890 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */ 5891 struct hwrm_cfa_encap_data_vxlan { 5892 u8 src_mac_addr[6]; 5893 __le16 unused_0; 5894 u8 dst_mac_addr[6]; 5895 u8 num_vlan_tags; 5896 u8 unused_1; 5897 __be16 ovlan_tpid; 5898 __be16 ovlan_tci; 5899 __be16 ivlan_tpid; 5900 __be16 ivlan_tci; 5901 __le32 l3[10]; 5902 #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL 5903 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL 5904 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL 5905 #define CFA_ENCAP_DATA_VXLAN_L3_LAST CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 5906 __be16 src_port; 5907 __be16 dst_port; 5908 __be32 vni; 5909 u8 hdr_rsvd0[3]; 5910 u8 hdr_rsvd1; 5911 u8 hdr_flags; 5912 u8 unused[3]; 5913 }; 5914 5915 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */ 5916 struct hwrm_cfa_encap_record_alloc_input { 5917 __le16 req_type; 5918 __le16 cmpl_ring; 5919 __le16 seq_id; 5920 __le16 target_id; 5921 __le64 resp_addr; 5922 __le32 flags; 5923 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 5924 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_EXTERNAL 0x2UL 5925 u8 encap_type; 5926 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL 5927 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL 5928 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL 5929 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL 5930 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL 5931 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL 5932 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL 5933 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL 5934 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL 5935 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL 5936 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL 5937 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 0xcUL 5938 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 5939 u8 unused_0[3]; 5940 __le32 encap_data[20]; 5941 }; 5942 5943 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */ 5944 struct hwrm_cfa_encap_record_alloc_output { 5945 __le16 error_code; 5946 __le16 req_type; 5947 __le16 seq_id; 5948 __le16 resp_len; 5949 __le32 encap_record_id; 5950 u8 unused_0[3]; 5951 u8 valid; 5952 }; 5953 5954 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */ 5955 struct hwrm_cfa_encap_record_free_input { 5956 __le16 req_type; 5957 __le16 cmpl_ring; 5958 __le16 seq_id; 5959 __le16 target_id; 5960 __le64 resp_addr; 5961 __le32 encap_record_id; 5962 u8 unused_0[4]; 5963 }; 5964 5965 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */ 5966 struct hwrm_cfa_encap_record_free_output { 5967 __le16 error_code; 5968 __le16 req_type; 5969 __le16 seq_id; 5970 __le16 resp_len; 5971 u8 unused_0[7]; 5972 u8 valid; 5973 }; 5974 5975 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */ 5976 struct hwrm_cfa_ntuple_filter_alloc_input { 5977 __le16 req_type; 5978 __le16 cmpl_ring; 5979 __le16 seq_id; 5980 __le16 target_id; 5981 __le64 resp_addr; 5982 __le32 flags; 5983 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 5984 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 5985 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL 5986 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_FID 0x8UL 5987 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_ARP_REPLY 0x10UL 5988 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX 0x20UL 5989 __le32 enables; 5990 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 5991 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 5992 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 5993 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 5994 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 5995 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 5996 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 5997 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 5998 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 5999 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 6000 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 6001 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 6002 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 6003 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 6004 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 6005 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 6006 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 6007 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 6008 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 6009 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX 0x80000UL 6010 __le64 l2_filter_id; 6011 u8 src_macaddr[6]; 6012 __be16 ethertype; 6013 u8 ip_addr_type; 6014 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 6015 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 6016 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 6017 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 6018 u8 ip_protocol; 6019 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 6020 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 6021 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 6022 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 6023 __le16 dst_id; 6024 __le16 mirror_vnic_id; 6025 u8 tunnel_type; 6026 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6027 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6028 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6029 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6030 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6031 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6032 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6033 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6034 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 6035 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6036 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6037 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6038 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6039 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6040 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6041 u8 pri_hint; 6042 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 6043 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 6044 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL 6045 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL 6046 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL 6047 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 6048 __be32 src_ipaddr[4]; 6049 __be32 src_ipaddr_mask[4]; 6050 __be32 dst_ipaddr[4]; 6051 __be32 dst_ipaddr_mask[4]; 6052 __be16 src_port; 6053 __be16 src_port_mask; 6054 __be16 dst_port; 6055 __be16 dst_port_mask; 6056 __le64 ntuple_filter_id_hint; 6057 }; 6058 6059 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ 6060 struct hwrm_cfa_ntuple_filter_alloc_output { 6061 __le16 error_code; 6062 __le16 req_type; 6063 __le16 seq_id; 6064 __le16 resp_len; 6065 __le64 ntuple_filter_id; 6066 __le32 flow_id; 6067 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 6068 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 6069 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 6070 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 6071 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 6072 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 6073 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 6074 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 6075 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 6076 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 6077 u8 unused_0[3]; 6078 u8 valid; 6079 }; 6080 6081 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ 6082 struct hwrm_cfa_ntuple_filter_alloc_cmd_err { 6083 u8 code; 6084 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 6085 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL 6086 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 6087 u8 unused_0[7]; 6088 }; 6089 6090 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */ 6091 struct hwrm_cfa_ntuple_filter_free_input { 6092 __le16 req_type; 6093 __le16 cmpl_ring; 6094 __le16 seq_id; 6095 __le16 target_id; 6096 __le64 resp_addr; 6097 __le64 ntuple_filter_id; 6098 }; 6099 6100 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ 6101 struct hwrm_cfa_ntuple_filter_free_output { 6102 __le16 error_code; 6103 __le16 req_type; 6104 __le16 seq_id; 6105 __le16 resp_len; 6106 u8 unused_0[7]; 6107 u8 valid; 6108 }; 6109 6110 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */ 6111 struct hwrm_cfa_ntuple_filter_cfg_input { 6112 __le16 req_type; 6113 __le16 cmpl_ring; 6114 __le16 seq_id; 6115 __le16 target_id; 6116 __le64 resp_addr; 6117 __le32 enables; 6118 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 6119 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 6120 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL 6121 __le32 flags; 6122 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_FID 0x1UL 6123 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_RFS_RING_IDX 0x2UL 6124 __le64 ntuple_filter_id; 6125 __le32 new_dst_id; 6126 __le32 new_mirror_vnic_id; 6127 __le16 new_meter_instance_id; 6128 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL 6129 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 6130 u8 unused_1[6]; 6131 }; 6132 6133 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ 6134 struct hwrm_cfa_ntuple_filter_cfg_output { 6135 __le16 error_code; 6136 __le16 req_type; 6137 __le16 seq_id; 6138 __le16 resp_len; 6139 u8 unused_0[7]; 6140 u8 valid; 6141 }; 6142 6143 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */ 6144 struct hwrm_cfa_decap_filter_alloc_input { 6145 __le16 req_type; 6146 __le16 cmpl_ring; 6147 __le16 seq_id; 6148 __le16 target_id; 6149 __le64 resp_addr; 6150 __le32 flags; 6151 #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL 6152 __le32 enables; 6153 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL 6154 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL 6155 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL 6156 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL 6157 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL 6158 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL 6159 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL 6160 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL 6161 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL 6162 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL 6163 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL 6164 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL 6165 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL 6166 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL 6167 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL 6168 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 6169 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 6170 __be32 tunnel_id; 6171 u8 tunnel_type; 6172 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6173 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6174 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6175 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6176 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6177 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6178 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6179 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6180 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 6181 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6182 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6183 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6184 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6185 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6186 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6187 u8 unused_0; 6188 __le16 unused_1; 6189 u8 src_macaddr[6]; 6190 u8 unused_2[2]; 6191 u8 dst_macaddr[6]; 6192 __be16 ovlan_vid; 6193 __be16 ivlan_vid; 6194 __be16 t_ovlan_vid; 6195 __be16 t_ivlan_vid; 6196 __be16 ethertype; 6197 u8 ip_addr_type; 6198 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 6199 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 6200 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 6201 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 6202 u8 ip_protocol; 6203 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 6204 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 6205 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 6206 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 6207 __le16 unused_3; 6208 __le32 unused_4; 6209 __be32 src_ipaddr[4]; 6210 __be32 dst_ipaddr[4]; 6211 __be16 src_port; 6212 __be16 dst_port; 6213 __le16 dst_id; 6214 __le16 l2_ctxt_ref_id; 6215 }; 6216 6217 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */ 6218 struct hwrm_cfa_decap_filter_alloc_output { 6219 __le16 error_code; 6220 __le16 req_type; 6221 __le16 seq_id; 6222 __le16 resp_len; 6223 __le32 decap_filter_id; 6224 u8 unused_0[3]; 6225 u8 valid; 6226 }; 6227 6228 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */ 6229 struct hwrm_cfa_decap_filter_free_input { 6230 __le16 req_type; 6231 __le16 cmpl_ring; 6232 __le16 seq_id; 6233 __le16 target_id; 6234 __le64 resp_addr; 6235 __le32 decap_filter_id; 6236 u8 unused_0[4]; 6237 }; 6238 6239 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */ 6240 struct hwrm_cfa_decap_filter_free_output { 6241 __le16 error_code; 6242 __le16 req_type; 6243 __le16 seq_id; 6244 __le16 resp_len; 6245 u8 unused_0[7]; 6246 u8 valid; 6247 }; 6248 6249 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */ 6250 struct hwrm_cfa_flow_alloc_input { 6251 __le16 req_type; 6252 __le16 cmpl_ring; 6253 __le16 seq_id; 6254 __le16 target_id; 6255 __le64 resp_addr; 6256 __le16 flags; 6257 #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL 6258 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL 6259 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1 6260 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1) 6261 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1) 6262 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1) 6263 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO 6264 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL 6265 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3 6266 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3) 6267 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3) 6268 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3) 6269 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 6270 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX 0x40UL 6271 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX 0x80UL 6272 #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI 0x100UL 6273 #define CFA_FLOW_ALLOC_REQ_FLAGS_VHOST_ID_USE_VLAN 0x200UL 6274 __le16 src_fid; 6275 __le32 tunnel_handle; 6276 __le16 action_flags; 6277 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL 6278 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL 6279 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL 6280 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL 6281 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL 6282 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL 6283 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL 6284 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL 6285 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL 6286 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL 6287 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP 0x400UL 6288 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED 0x800UL 6289 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_PRI_HINT 0x1000UL 6290 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC 0x2000UL 6291 __le16 dst_fid; 6292 __be16 l2_rewrite_vlan_tpid; 6293 __be16 l2_rewrite_vlan_tci; 6294 __le16 act_meter_id; 6295 __le16 ref_flow_handle; 6296 __be16 ethertype; 6297 __be16 outer_vlan_tci; 6298 __be16 dmac[3]; 6299 __be16 inner_vlan_tci; 6300 __be16 smac[3]; 6301 u8 ip_dst_mask_len; 6302 u8 ip_src_mask_len; 6303 __be32 ip_dst[4]; 6304 __be32 ip_src[4]; 6305 __be16 l4_src_port; 6306 __be16 l4_src_port_mask; 6307 __be16 l4_dst_port; 6308 __be16 l4_dst_port_mask; 6309 __be32 nat_ip_address[4]; 6310 __be16 l2_rewrite_dmac[3]; 6311 __be16 nat_port; 6312 __be16 l2_rewrite_smac[3]; 6313 u8 ip_proto; 6314 u8 tunnel_type; 6315 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6316 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6317 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6318 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6319 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6320 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6321 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6322 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6323 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 6324 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6325 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6326 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6327 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6328 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6329 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6330 }; 6331 6332 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */ 6333 struct hwrm_cfa_flow_alloc_output { 6334 __le16 error_code; 6335 __le16 req_type; 6336 __le16 seq_id; 6337 __le16 resp_len; 6338 __le16 flow_handle; 6339 u8 unused_0[2]; 6340 __le32 flow_id; 6341 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 6342 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 6343 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 6344 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 6345 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 6346 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT 6347 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 6348 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 6349 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 6350 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX 6351 __le64 ext_flow_handle; 6352 __le32 flow_counter_id; 6353 u8 unused_1[3]; 6354 u8 valid; 6355 }; 6356 6357 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */ 6358 struct hwrm_cfa_flow_alloc_cmd_err { 6359 u8 code; 6360 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 6361 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM 0x1UL 6362 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD 0x2UL 6363 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER 0x3UL 6364 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM 0x4UL 6365 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION 0x5UL 6366 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS 0x6UL 6367 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 0x7UL 6368 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 6369 u8 unused_0[7]; 6370 }; 6371 6372 /* hwrm_cfa_flow_free_input (size:256b/32B) */ 6373 struct hwrm_cfa_flow_free_input { 6374 __le16 req_type; 6375 __le16 cmpl_ring; 6376 __le16 seq_id; 6377 __le16 target_id; 6378 __le64 resp_addr; 6379 __le16 flow_handle; 6380 __le16 unused_0; 6381 __le32 flow_counter_id; 6382 __le64 ext_flow_handle; 6383 }; 6384 6385 /* hwrm_cfa_flow_free_output (size:256b/32B) */ 6386 struct hwrm_cfa_flow_free_output { 6387 __le16 error_code; 6388 __le16 req_type; 6389 __le16 seq_id; 6390 __le16 resp_len; 6391 __le64 packet; 6392 __le64 byte; 6393 u8 unused_0[7]; 6394 u8 valid; 6395 }; 6396 6397 /* hwrm_cfa_flow_info_input (size:256b/32B) */ 6398 struct hwrm_cfa_flow_info_input { 6399 __le16 req_type; 6400 __le16 cmpl_ring; 6401 __le16 seq_id; 6402 __le16 target_id; 6403 __le64 resp_addr; 6404 __le16 flow_handle; 6405 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK 0xfffUL 6406 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_SFT 0 6407 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT 0x1000UL 6408 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT 0x2000UL 6409 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT 0x4000UL 6410 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX 0x8000UL 6411 u8 unused_0[6]; 6412 __le64 ext_flow_handle; 6413 }; 6414 6415 /* hwrm_cfa_flow_info_output (size:5632b/704B) */ 6416 struct hwrm_cfa_flow_info_output { 6417 __le16 error_code; 6418 __le16 req_type; 6419 __le16 seq_id; 6420 __le16 resp_len; 6421 u8 flags; 6422 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_TX 0x1UL 6423 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_RX 0x2UL 6424 u8 profile; 6425 __le16 src_fid; 6426 __le16 dst_fid; 6427 __le16 l2_ctxt_id; 6428 __le64 em_info; 6429 __le64 tcam_info; 6430 __le64 vfp_tcam_info; 6431 __le16 ar_id; 6432 __le16 flow_handle; 6433 __le32 tunnel_handle; 6434 __le16 flow_timer; 6435 u8 unused_0[6]; 6436 __le32 flow_key_data[130]; 6437 __le32 flow_action_info[30]; 6438 u8 unused_1[7]; 6439 u8 valid; 6440 }; 6441 6442 /* hwrm_cfa_flow_stats_input (size:640b/80B) */ 6443 struct hwrm_cfa_flow_stats_input { 6444 __le16 req_type; 6445 __le16 cmpl_ring; 6446 __le16 seq_id; 6447 __le16 target_id; 6448 __le64 resp_addr; 6449 __le16 num_flows; 6450 __le16 flow_handle_0; 6451 __le16 flow_handle_1; 6452 __le16 flow_handle_2; 6453 __le16 flow_handle_3; 6454 __le16 flow_handle_4; 6455 __le16 flow_handle_5; 6456 __le16 flow_handle_6; 6457 __le16 flow_handle_7; 6458 __le16 flow_handle_8; 6459 __le16 flow_handle_9; 6460 u8 unused_0[2]; 6461 __le32 flow_id_0; 6462 __le32 flow_id_1; 6463 __le32 flow_id_2; 6464 __le32 flow_id_3; 6465 __le32 flow_id_4; 6466 __le32 flow_id_5; 6467 __le32 flow_id_6; 6468 __le32 flow_id_7; 6469 __le32 flow_id_8; 6470 __le32 flow_id_9; 6471 }; 6472 6473 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */ 6474 struct hwrm_cfa_flow_stats_output { 6475 __le16 error_code; 6476 __le16 req_type; 6477 __le16 seq_id; 6478 __le16 resp_len; 6479 __le64 packet_0; 6480 __le64 packet_1; 6481 __le64 packet_2; 6482 __le64 packet_3; 6483 __le64 packet_4; 6484 __le64 packet_5; 6485 __le64 packet_6; 6486 __le64 packet_7; 6487 __le64 packet_8; 6488 __le64 packet_9; 6489 __le64 byte_0; 6490 __le64 byte_1; 6491 __le64 byte_2; 6492 __le64 byte_3; 6493 __le64 byte_4; 6494 __le64 byte_5; 6495 __le64 byte_6; 6496 __le64 byte_7; 6497 __le64 byte_8; 6498 __le64 byte_9; 6499 u8 unused_0[7]; 6500 u8 valid; 6501 }; 6502 6503 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */ 6504 struct hwrm_cfa_vfr_alloc_input { 6505 __le16 req_type; 6506 __le16 cmpl_ring; 6507 __le16 seq_id; 6508 __le16 target_id; 6509 __le64 resp_addr; 6510 __le16 vf_id; 6511 __le16 reserved; 6512 u8 unused_0[4]; 6513 char vfr_name[32]; 6514 }; 6515 6516 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */ 6517 struct hwrm_cfa_vfr_alloc_output { 6518 __le16 error_code; 6519 __le16 req_type; 6520 __le16 seq_id; 6521 __le16 resp_len; 6522 __le16 rx_cfa_code; 6523 __le16 tx_cfa_action; 6524 u8 unused_0[3]; 6525 u8 valid; 6526 }; 6527 6528 /* hwrm_cfa_vfr_free_input (size:384b/48B) */ 6529 struct hwrm_cfa_vfr_free_input { 6530 __le16 req_type; 6531 __le16 cmpl_ring; 6532 __le16 seq_id; 6533 __le16 target_id; 6534 __le64 resp_addr; 6535 char vfr_name[32]; 6536 }; 6537 6538 /* hwrm_cfa_vfr_free_output (size:128b/16B) */ 6539 struct hwrm_cfa_vfr_free_output { 6540 __le16 error_code; 6541 __le16 req_type; 6542 __le16 seq_id; 6543 __le16 resp_len; 6544 u8 unused_0[7]; 6545 u8 valid; 6546 }; 6547 6548 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */ 6549 struct hwrm_cfa_eem_qcaps_input { 6550 __le16 req_type; 6551 __le16 cmpl_ring; 6552 __le16 seq_id; 6553 __le16 target_id; 6554 __le64 resp_addr; 6555 __le32 flags; 6556 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_TX 0x1UL 6557 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_RX 0x2UL 6558 #define CFA_EEM_QCAPS_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 6559 __le32 unused_0; 6560 }; 6561 6562 /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */ 6563 struct hwrm_cfa_eem_qcaps_output { 6564 __le16 error_code; 6565 __le16 req_type; 6566 __le16 seq_id; 6567 __le16 resp_len; 6568 __le32 flags; 6569 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_TX 0x1UL 6570 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_RX 0x2UL 6571 #define CFA_EEM_QCAPS_RESP_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x4UL 6572 #define CFA_EEM_QCAPS_RESP_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x8UL 6573 __le32 unused_0; 6574 __le32 supported; 6575 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY0_TABLE 0x1UL 6576 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY1_TABLE 0x2UL 6577 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_RECORD_TABLE 0x4UL 6578 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE 0x8UL 6579 #define CFA_EEM_QCAPS_RESP_SUPPORTED_FID_TABLE 0x10UL 6580 __le32 max_entries_supported; 6581 __le16 key_entry_size; 6582 __le16 record_entry_size; 6583 __le16 efc_entry_size; 6584 __le16 fid_entry_size; 6585 u8 unused_1[7]; 6586 u8 valid; 6587 }; 6588 6589 /* hwrm_cfa_eem_cfg_input (size:384b/48B) */ 6590 struct hwrm_cfa_eem_cfg_input { 6591 __le16 req_type; 6592 __le16 cmpl_ring; 6593 __le16 seq_id; 6594 __le16 target_id; 6595 __le64 resp_addr; 6596 __le32 flags; 6597 #define CFA_EEM_CFG_REQ_FLAGS_PATH_TX 0x1UL 6598 #define CFA_EEM_CFG_REQ_FLAGS_PATH_RX 0x2UL 6599 #define CFA_EEM_CFG_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 6600 #define CFA_EEM_CFG_REQ_FLAGS_SECONDARY_PF 0x8UL 6601 __le16 group_id; 6602 __le16 unused_0; 6603 __le32 num_entries; 6604 __le32 unused_1; 6605 __le16 key0_ctx_id; 6606 __le16 key1_ctx_id; 6607 __le16 record_ctx_id; 6608 __le16 efc_ctx_id; 6609 __le16 fid_ctx_id; 6610 __le16 unused_2; 6611 __le32 unused_3; 6612 }; 6613 6614 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */ 6615 struct hwrm_cfa_eem_cfg_output { 6616 __le16 error_code; 6617 __le16 req_type; 6618 __le16 seq_id; 6619 __le16 resp_len; 6620 u8 unused_0[7]; 6621 u8 valid; 6622 }; 6623 6624 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */ 6625 struct hwrm_cfa_eem_qcfg_input { 6626 __le16 req_type; 6627 __le16 cmpl_ring; 6628 __le16 seq_id; 6629 __le16 target_id; 6630 __le64 resp_addr; 6631 __le32 flags; 6632 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_TX 0x1UL 6633 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_RX 0x2UL 6634 __le32 unused_0; 6635 }; 6636 6637 /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */ 6638 struct hwrm_cfa_eem_qcfg_output { 6639 __le16 error_code; 6640 __le16 req_type; 6641 __le16 seq_id; 6642 __le16 resp_len; 6643 __le32 flags; 6644 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_TX 0x1UL 6645 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_RX 0x2UL 6646 #define CFA_EEM_QCFG_RESP_FLAGS_PREFERRED_OFFLOAD 0x4UL 6647 __le32 num_entries; 6648 __le16 key0_ctx_id; 6649 __le16 key1_ctx_id; 6650 __le16 record_ctx_id; 6651 __le16 efc_ctx_id; 6652 __le16 fid_ctx_id; 6653 u8 unused_2[5]; 6654 u8 valid; 6655 }; 6656 6657 /* hwrm_cfa_eem_op_input (size:192b/24B) */ 6658 struct hwrm_cfa_eem_op_input { 6659 __le16 req_type; 6660 __le16 cmpl_ring; 6661 __le16 seq_id; 6662 __le16 target_id; 6663 __le64 resp_addr; 6664 __le32 flags; 6665 #define CFA_EEM_OP_REQ_FLAGS_PATH_TX 0x1UL 6666 #define CFA_EEM_OP_REQ_FLAGS_PATH_RX 0x2UL 6667 __le16 unused_0; 6668 __le16 op; 6669 #define CFA_EEM_OP_REQ_OP_RESERVED 0x0UL 6670 #define CFA_EEM_OP_REQ_OP_EEM_DISABLE 0x1UL 6671 #define CFA_EEM_OP_REQ_OP_EEM_ENABLE 0x2UL 6672 #define CFA_EEM_OP_REQ_OP_EEM_CLEANUP 0x3UL 6673 #define CFA_EEM_OP_REQ_OP_LAST CFA_EEM_OP_REQ_OP_EEM_CLEANUP 6674 }; 6675 6676 /* hwrm_cfa_eem_op_output (size:128b/16B) */ 6677 struct hwrm_cfa_eem_op_output { 6678 __le16 error_code; 6679 __le16 req_type; 6680 __le16 seq_id; 6681 __le16 resp_len; 6682 u8 unused_0[7]; 6683 u8 valid; 6684 }; 6685 6686 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */ 6687 struct hwrm_cfa_adv_flow_mgnt_qcaps_input { 6688 __le16 req_type; 6689 __le16 cmpl_ring; 6690 __le16 seq_id; 6691 __le16 target_id; 6692 __le64 resp_addr; 6693 __le32 unused_0[4]; 6694 }; 6695 6696 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ 6697 struct hwrm_cfa_adv_flow_mgnt_qcaps_output { 6698 __le16 error_code; 6699 __le16 req_type; 6700 __le16 seq_id; 6701 __le16 resp_len; 6702 __le32 flags; 6703 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_16BIT_SUPPORTED 0x1UL 6704 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_64BIT_SUPPORTED 0x2UL 6705 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_BATCH_DELETE_SUPPORTED 0x4UL 6706 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_RESET_ALL_SUPPORTED 0x8UL 6707 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED 0x10UL 6708 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TX_EEM_FLOW_SUPPORTED 0x20UL 6709 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RX_EEM_FLOW_SUPPORTED 0x40UL 6710 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED 0x80UL 6711 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED 0x100UL 6712 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_UNTAGGED_VLAN_SUPPORTED 0x200UL 6713 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_XDP_SUPPORTED 0x400UL 6714 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED 0x800UL 6715 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED 0x1000UL 6716 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED 0x2000UL 6717 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED 0x4000UL 6718 u8 unused_0[3]; 6719 u8 valid; 6720 }; 6721 6722 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */ 6723 struct hwrm_tunnel_dst_port_query_input { 6724 __le16 req_type; 6725 __le16 cmpl_ring; 6726 __le16 seq_id; 6727 __le16 target_id; 6728 __le64 resp_addr; 6729 u8 tunnel_type; 6730 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6731 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6732 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6733 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6734 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6735 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6736 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 6737 u8 unused_0[7]; 6738 }; 6739 6740 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */ 6741 struct hwrm_tunnel_dst_port_query_output { 6742 __le16 error_code; 6743 __le16 req_type; 6744 __le16 seq_id; 6745 __le16 resp_len; 6746 __le16 tunnel_dst_port_id; 6747 __be16 tunnel_dst_port_val; 6748 u8 unused_0[3]; 6749 u8 valid; 6750 }; 6751 6752 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */ 6753 struct hwrm_tunnel_dst_port_alloc_input { 6754 __le16 req_type; 6755 __le16 cmpl_ring; 6756 __le16 seq_id; 6757 __le16 target_id; 6758 __le64 resp_addr; 6759 u8 tunnel_type; 6760 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6761 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6762 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6763 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6764 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6765 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6766 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 6767 u8 unused_0; 6768 __be16 tunnel_dst_port_val; 6769 u8 unused_1[4]; 6770 }; 6771 6772 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */ 6773 struct hwrm_tunnel_dst_port_alloc_output { 6774 __le16 error_code; 6775 __le16 req_type; 6776 __le16 seq_id; 6777 __le16 resp_len; 6778 __le16 tunnel_dst_port_id; 6779 u8 unused_0[5]; 6780 u8 valid; 6781 }; 6782 6783 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */ 6784 struct hwrm_tunnel_dst_port_free_input { 6785 __le16 req_type; 6786 __le16 cmpl_ring; 6787 __le16 seq_id; 6788 __le16 target_id; 6789 __le64 resp_addr; 6790 u8 tunnel_type; 6791 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6792 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6793 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6794 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6795 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6796 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6797 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 6798 u8 unused_0; 6799 __le16 tunnel_dst_port_id; 6800 u8 unused_1[4]; 6801 }; 6802 6803 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */ 6804 struct hwrm_tunnel_dst_port_free_output { 6805 __le16 error_code; 6806 __le16 req_type; 6807 __le16 seq_id; 6808 __le16 resp_len; 6809 u8 unused_1[7]; 6810 u8 valid; 6811 }; 6812 6813 /* ctx_hw_stats (size:1280b/160B) */ 6814 struct ctx_hw_stats { 6815 __le64 rx_ucast_pkts; 6816 __le64 rx_mcast_pkts; 6817 __le64 rx_bcast_pkts; 6818 __le64 rx_discard_pkts; 6819 __le64 rx_drop_pkts; 6820 __le64 rx_ucast_bytes; 6821 __le64 rx_mcast_bytes; 6822 __le64 rx_bcast_bytes; 6823 __le64 tx_ucast_pkts; 6824 __le64 tx_mcast_pkts; 6825 __le64 tx_bcast_pkts; 6826 __le64 tx_discard_pkts; 6827 __le64 tx_drop_pkts; 6828 __le64 tx_ucast_bytes; 6829 __le64 tx_mcast_bytes; 6830 __le64 tx_bcast_bytes; 6831 __le64 tpa_pkts; 6832 __le64 tpa_bytes; 6833 __le64 tpa_events; 6834 __le64 tpa_aborts; 6835 }; 6836 6837 /* ctx_hw_stats_ext (size:1344b/168B) */ 6838 struct ctx_hw_stats_ext { 6839 __le64 rx_ucast_pkts; 6840 __le64 rx_mcast_pkts; 6841 __le64 rx_bcast_pkts; 6842 __le64 rx_discard_pkts; 6843 __le64 rx_drop_pkts; 6844 __le64 rx_ucast_bytes; 6845 __le64 rx_mcast_bytes; 6846 __le64 rx_bcast_bytes; 6847 __le64 tx_ucast_pkts; 6848 __le64 tx_mcast_pkts; 6849 __le64 tx_bcast_pkts; 6850 __le64 tx_discard_pkts; 6851 __le64 tx_drop_pkts; 6852 __le64 tx_ucast_bytes; 6853 __le64 tx_mcast_bytes; 6854 __le64 tx_bcast_bytes; 6855 __le64 rx_tpa_eligible_pkt; 6856 __le64 rx_tpa_eligible_bytes; 6857 __le64 rx_tpa_pkt; 6858 __le64 rx_tpa_bytes; 6859 __le64 rx_tpa_errors; 6860 }; 6861 6862 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */ 6863 struct hwrm_stat_ctx_alloc_input { 6864 __le16 req_type; 6865 __le16 cmpl_ring; 6866 __le16 seq_id; 6867 __le16 target_id; 6868 __le64 resp_addr; 6869 __le64 stats_dma_addr; 6870 __le32 update_period_ms; 6871 u8 stat_ctx_flags; 6872 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL 6873 u8 unused_0; 6874 __le16 stats_dma_length; 6875 }; 6876 6877 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */ 6878 struct hwrm_stat_ctx_alloc_output { 6879 __le16 error_code; 6880 __le16 req_type; 6881 __le16 seq_id; 6882 __le16 resp_len; 6883 __le32 stat_ctx_id; 6884 u8 unused_0[3]; 6885 u8 valid; 6886 }; 6887 6888 /* hwrm_stat_ctx_free_input (size:192b/24B) */ 6889 struct hwrm_stat_ctx_free_input { 6890 __le16 req_type; 6891 __le16 cmpl_ring; 6892 __le16 seq_id; 6893 __le16 target_id; 6894 __le64 resp_addr; 6895 __le32 stat_ctx_id; 6896 u8 unused_0[4]; 6897 }; 6898 6899 /* hwrm_stat_ctx_free_output (size:128b/16B) */ 6900 struct hwrm_stat_ctx_free_output { 6901 __le16 error_code; 6902 __le16 req_type; 6903 __le16 seq_id; 6904 __le16 resp_len; 6905 __le32 stat_ctx_id; 6906 u8 unused_0[3]; 6907 u8 valid; 6908 }; 6909 6910 /* hwrm_stat_ctx_query_input (size:192b/24B) */ 6911 struct hwrm_stat_ctx_query_input { 6912 __le16 req_type; 6913 __le16 cmpl_ring; 6914 __le16 seq_id; 6915 __le16 target_id; 6916 __le64 resp_addr; 6917 __le32 stat_ctx_id; 6918 u8 unused_0[4]; 6919 }; 6920 6921 /* hwrm_stat_ctx_query_output (size:1408b/176B) */ 6922 struct hwrm_stat_ctx_query_output { 6923 __le16 error_code; 6924 __le16 req_type; 6925 __le16 seq_id; 6926 __le16 resp_len; 6927 __le64 tx_ucast_pkts; 6928 __le64 tx_mcast_pkts; 6929 __le64 tx_bcast_pkts; 6930 __le64 tx_err_pkts; 6931 __le64 tx_drop_pkts; 6932 __le64 tx_ucast_bytes; 6933 __le64 tx_mcast_bytes; 6934 __le64 tx_bcast_bytes; 6935 __le64 rx_ucast_pkts; 6936 __le64 rx_mcast_pkts; 6937 __le64 rx_bcast_pkts; 6938 __le64 rx_err_pkts; 6939 __le64 rx_drop_pkts; 6940 __le64 rx_ucast_bytes; 6941 __le64 rx_mcast_bytes; 6942 __le64 rx_bcast_bytes; 6943 __le64 rx_agg_pkts; 6944 __le64 rx_agg_bytes; 6945 __le64 rx_agg_events; 6946 __le64 rx_agg_aborts; 6947 u8 unused_0[7]; 6948 u8 valid; 6949 }; 6950 6951 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */ 6952 struct hwrm_stat_ctx_clr_stats_input { 6953 __le16 req_type; 6954 __le16 cmpl_ring; 6955 __le16 seq_id; 6956 __le16 target_id; 6957 __le64 resp_addr; 6958 __le32 stat_ctx_id; 6959 u8 unused_0[4]; 6960 }; 6961 6962 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */ 6963 struct hwrm_stat_ctx_clr_stats_output { 6964 __le16 error_code; 6965 __le16 req_type; 6966 __le16 seq_id; 6967 __le16 resp_len; 6968 u8 unused_0[7]; 6969 u8 valid; 6970 }; 6971 6972 /* hwrm_pcie_qstats_input (size:256b/32B) */ 6973 struct hwrm_pcie_qstats_input { 6974 __le16 req_type; 6975 __le16 cmpl_ring; 6976 __le16 seq_id; 6977 __le16 target_id; 6978 __le64 resp_addr; 6979 __le16 pcie_stat_size; 6980 u8 unused_0[6]; 6981 __le64 pcie_stat_host_addr; 6982 }; 6983 6984 /* hwrm_pcie_qstats_output (size:128b/16B) */ 6985 struct hwrm_pcie_qstats_output { 6986 __le16 error_code; 6987 __le16 req_type; 6988 __le16 seq_id; 6989 __le16 resp_len; 6990 __le16 pcie_stat_size; 6991 u8 unused_0[5]; 6992 u8 valid; 6993 }; 6994 6995 /* pcie_ctx_hw_stats (size:768b/96B) */ 6996 struct pcie_ctx_hw_stats { 6997 __le64 pcie_pl_signal_integrity; 6998 __le64 pcie_dl_signal_integrity; 6999 __le64 pcie_tl_signal_integrity; 7000 __le64 pcie_link_integrity; 7001 __le64 pcie_tx_traffic_rate; 7002 __le64 pcie_rx_traffic_rate; 7003 __le64 pcie_tx_dllp_statistics; 7004 __le64 pcie_rx_dllp_statistics; 7005 __le64 pcie_equalization_time; 7006 __le32 pcie_ltssm_histogram[4]; 7007 __le64 pcie_recovery_histogram; 7008 }; 7009 7010 /* hwrm_fw_reset_input (size:192b/24B) */ 7011 struct hwrm_fw_reset_input { 7012 __le16 req_type; 7013 __le16 cmpl_ring; 7014 __le16 seq_id; 7015 __le16 target_id; 7016 __le64 resp_addr; 7017 u8 embedded_proc_type; 7018 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 7019 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 7020 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 7021 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 7022 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 7023 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 7024 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 7025 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL 7026 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 0x8UL 7027 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 7028 u8 selfrst_status; 7029 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL 7030 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL 7031 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 7032 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 7033 #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 7034 u8 host_idx; 7035 u8 flags; 7036 #define FW_RESET_REQ_FLAGS_RESET_GRACEFUL 0x1UL 7037 u8 unused_0[4]; 7038 }; 7039 7040 /* hwrm_fw_reset_output (size:128b/16B) */ 7041 struct hwrm_fw_reset_output { 7042 __le16 error_code; 7043 __le16 req_type; 7044 __le16 seq_id; 7045 __le16 resp_len; 7046 u8 selfrst_status; 7047 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 7048 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 7049 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 7050 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 7051 #define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 7052 u8 unused_0[6]; 7053 u8 valid; 7054 }; 7055 7056 /* hwrm_fw_qstatus_input (size:192b/24B) */ 7057 struct hwrm_fw_qstatus_input { 7058 __le16 req_type; 7059 __le16 cmpl_ring; 7060 __le16 seq_id; 7061 __le16 target_id; 7062 __le64 resp_addr; 7063 u8 embedded_proc_type; 7064 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 7065 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 7066 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 7067 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 7068 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 7069 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 7070 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 7071 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 7072 u8 unused_0[7]; 7073 }; 7074 7075 /* hwrm_fw_qstatus_output (size:128b/16B) */ 7076 struct hwrm_fw_qstatus_output { 7077 __le16 error_code; 7078 __le16 req_type; 7079 __le16 seq_id; 7080 __le16 resp_len; 7081 u8 selfrst_status; 7082 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 7083 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 7084 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 7085 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 0x3UL 7086 #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 7087 u8 unused_0[6]; 7088 u8 valid; 7089 }; 7090 7091 /* hwrm_fw_set_time_input (size:256b/32B) */ 7092 struct hwrm_fw_set_time_input { 7093 __le16 req_type; 7094 __le16 cmpl_ring; 7095 __le16 seq_id; 7096 __le16 target_id; 7097 __le64 resp_addr; 7098 __le16 year; 7099 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL 7100 #define FW_SET_TIME_REQ_YEAR_LAST FW_SET_TIME_REQ_YEAR_UNKNOWN 7101 u8 month; 7102 u8 day; 7103 u8 hour; 7104 u8 minute; 7105 u8 second; 7106 u8 unused_0; 7107 __le16 millisecond; 7108 __le16 zone; 7109 #define FW_SET_TIME_REQ_ZONE_UTC 0 7110 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 65535 7111 #define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN 7112 u8 unused_1[4]; 7113 }; 7114 7115 /* hwrm_fw_set_time_output (size:128b/16B) */ 7116 struct hwrm_fw_set_time_output { 7117 __le16 error_code; 7118 __le16 req_type; 7119 __le16 seq_id; 7120 __le16 resp_len; 7121 u8 unused_0[7]; 7122 u8 valid; 7123 }; 7124 7125 /* hwrm_struct_hdr (size:128b/16B) */ 7126 struct hwrm_struct_hdr { 7127 __le16 struct_id; 7128 #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL 7129 #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL 7130 #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL 7131 #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL 7132 #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL 7133 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL 7134 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL 7135 #define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL 7136 #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL 7137 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL 7138 #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL 7139 #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_RSS_V2 7140 __le16 len; 7141 u8 version; 7142 u8 count; 7143 __le16 subtype; 7144 __le16 next_offset; 7145 #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL 7146 u8 unused_0[6]; 7147 }; 7148 7149 /* hwrm_struct_data_dcbx_app (size:64b/8B) */ 7150 struct hwrm_struct_data_dcbx_app { 7151 __be16 protocol_id; 7152 u8 protocol_selector; 7153 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL 7154 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL 7155 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL 7156 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL 7157 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 7158 u8 priority; 7159 u8 valid; 7160 u8 unused_0[3]; 7161 }; 7162 7163 /* hwrm_fw_set_structured_data_input (size:256b/32B) */ 7164 struct hwrm_fw_set_structured_data_input { 7165 __le16 req_type; 7166 __le16 cmpl_ring; 7167 __le16 seq_id; 7168 __le16 target_id; 7169 __le64 resp_addr; 7170 __le64 src_data_addr; 7171 __le16 data_len; 7172 u8 hdr_cnt; 7173 u8 unused_0[5]; 7174 }; 7175 7176 /* hwrm_fw_set_structured_data_output (size:128b/16B) */ 7177 struct hwrm_fw_set_structured_data_output { 7178 __le16 error_code; 7179 __le16 req_type; 7180 __le16 seq_id; 7181 __le16 resp_len; 7182 u8 unused_0[7]; 7183 u8 valid; 7184 }; 7185 7186 /* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */ 7187 struct hwrm_fw_set_structured_data_cmd_err { 7188 u8 code; 7189 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 7190 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL 7191 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL 7192 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 7193 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 7194 u8 unused_0[7]; 7195 }; 7196 7197 /* hwrm_fw_get_structured_data_input (size:256b/32B) */ 7198 struct hwrm_fw_get_structured_data_input { 7199 __le16 req_type; 7200 __le16 cmpl_ring; 7201 __le16 seq_id; 7202 __le16 target_id; 7203 __le64 resp_addr; 7204 __le64 dest_data_addr; 7205 __le16 data_len; 7206 __le16 structure_id; 7207 __le16 subtype; 7208 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED 0x0UL 7209 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL 7210 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL 7211 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL 7212 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL 7213 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL 7214 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL 7215 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 7216 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL 7217 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 7218 u8 count; 7219 u8 unused_0; 7220 }; 7221 7222 /* hwrm_fw_get_structured_data_output (size:128b/16B) */ 7223 struct hwrm_fw_get_structured_data_output { 7224 __le16 error_code; 7225 __le16 req_type; 7226 __le16 seq_id; 7227 __le16 resp_len; 7228 u8 hdr_cnt; 7229 u8 unused_0[6]; 7230 u8 valid; 7231 }; 7232 7233 /* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */ 7234 struct hwrm_fw_get_structured_data_cmd_err { 7235 u8 code; 7236 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 7237 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 7238 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 7239 u8 unused_0[7]; 7240 }; 7241 7242 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */ 7243 struct hwrm_exec_fwd_resp_input { 7244 __le16 req_type; 7245 __le16 cmpl_ring; 7246 __le16 seq_id; 7247 __le16 target_id; 7248 __le64 resp_addr; 7249 __le32 encap_request[26]; 7250 __le16 encap_resp_target_id; 7251 u8 unused_0[6]; 7252 }; 7253 7254 /* hwrm_exec_fwd_resp_output (size:128b/16B) */ 7255 struct hwrm_exec_fwd_resp_output { 7256 __le16 error_code; 7257 __le16 req_type; 7258 __le16 seq_id; 7259 __le16 resp_len; 7260 u8 unused_0[7]; 7261 u8 valid; 7262 }; 7263 7264 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */ 7265 struct hwrm_reject_fwd_resp_input { 7266 __le16 req_type; 7267 __le16 cmpl_ring; 7268 __le16 seq_id; 7269 __le16 target_id; 7270 __le64 resp_addr; 7271 __le32 encap_request[26]; 7272 __le16 encap_resp_target_id; 7273 u8 unused_0[6]; 7274 }; 7275 7276 /* hwrm_reject_fwd_resp_output (size:128b/16B) */ 7277 struct hwrm_reject_fwd_resp_output { 7278 __le16 error_code; 7279 __le16 req_type; 7280 __le16 seq_id; 7281 __le16 resp_len; 7282 u8 unused_0[7]; 7283 u8 valid; 7284 }; 7285 7286 /* hwrm_fwd_resp_input (size:1024b/128B) */ 7287 struct hwrm_fwd_resp_input { 7288 __le16 req_type; 7289 __le16 cmpl_ring; 7290 __le16 seq_id; 7291 __le16 target_id; 7292 __le64 resp_addr; 7293 __le16 encap_resp_target_id; 7294 __le16 encap_resp_cmpl_ring; 7295 __le16 encap_resp_len; 7296 u8 unused_0; 7297 u8 unused_1; 7298 __le64 encap_resp_addr; 7299 __le32 encap_resp[24]; 7300 }; 7301 7302 /* hwrm_fwd_resp_output (size:128b/16B) */ 7303 struct hwrm_fwd_resp_output { 7304 __le16 error_code; 7305 __le16 req_type; 7306 __le16 seq_id; 7307 __le16 resp_len; 7308 u8 unused_0[7]; 7309 u8 valid; 7310 }; 7311 7312 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */ 7313 struct hwrm_fwd_async_event_cmpl_input { 7314 __le16 req_type; 7315 __le16 cmpl_ring; 7316 __le16 seq_id; 7317 __le16 target_id; 7318 __le64 resp_addr; 7319 __le16 encap_async_event_target_id; 7320 u8 unused_0[6]; 7321 __le32 encap_async_event_cmpl[4]; 7322 }; 7323 7324 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */ 7325 struct hwrm_fwd_async_event_cmpl_output { 7326 __le16 error_code; 7327 __le16 req_type; 7328 __le16 seq_id; 7329 __le16 resp_len; 7330 u8 unused_0[7]; 7331 u8 valid; 7332 }; 7333 7334 /* hwrm_temp_monitor_query_input (size:128b/16B) */ 7335 struct hwrm_temp_monitor_query_input { 7336 __le16 req_type; 7337 __le16 cmpl_ring; 7338 __le16 seq_id; 7339 __le16 target_id; 7340 __le64 resp_addr; 7341 }; 7342 7343 /* hwrm_temp_monitor_query_output (size:128b/16B) */ 7344 struct hwrm_temp_monitor_query_output { 7345 __le16 error_code; 7346 __le16 req_type; 7347 __le16 seq_id; 7348 __le16 resp_len; 7349 u8 temp; 7350 u8 phy_temp; 7351 u8 om_temp; 7352 u8 flags; 7353 #define TEMP_MONITOR_QUERY_RESP_FLAGS_TEMP_NOT_AVAILABLE 0x1UL 7354 #define TEMP_MONITOR_QUERY_RESP_FLAGS_PHY_TEMP_NOT_AVAILABLE 0x2UL 7355 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_NOT_PRESENT 0x4UL 7356 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_TEMP_NOT_AVAILABLE 0x8UL 7357 u8 unused_0[3]; 7358 u8 valid; 7359 }; 7360 7361 /* hwrm_wol_filter_alloc_input (size:512b/64B) */ 7362 struct hwrm_wol_filter_alloc_input { 7363 __le16 req_type; 7364 __le16 cmpl_ring; 7365 __le16 seq_id; 7366 __le16 target_id; 7367 __le64 resp_addr; 7368 __le32 flags; 7369 __le32 enables; 7370 #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL 7371 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL 7372 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL 7373 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL 7374 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL 7375 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL 7376 __le16 port_id; 7377 u8 wol_type; 7378 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL 7379 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL 7380 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL 7381 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 7382 u8 unused_0[5]; 7383 u8 mac_address[6]; 7384 __le16 pattern_offset; 7385 __le16 pattern_buf_size; 7386 __le16 pattern_mask_size; 7387 u8 unused_1[4]; 7388 __le64 pattern_buf_addr; 7389 __le64 pattern_mask_addr; 7390 }; 7391 7392 /* hwrm_wol_filter_alloc_output (size:128b/16B) */ 7393 struct hwrm_wol_filter_alloc_output { 7394 __le16 error_code; 7395 __le16 req_type; 7396 __le16 seq_id; 7397 __le16 resp_len; 7398 u8 wol_filter_id; 7399 u8 unused_0[6]; 7400 u8 valid; 7401 }; 7402 7403 /* hwrm_wol_filter_free_input (size:256b/32B) */ 7404 struct hwrm_wol_filter_free_input { 7405 __le16 req_type; 7406 __le16 cmpl_ring; 7407 __le16 seq_id; 7408 __le16 target_id; 7409 __le64 resp_addr; 7410 __le32 flags; 7411 #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL 7412 __le32 enables; 7413 #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL 7414 __le16 port_id; 7415 u8 wol_filter_id; 7416 u8 unused_0[5]; 7417 }; 7418 7419 /* hwrm_wol_filter_free_output (size:128b/16B) */ 7420 struct hwrm_wol_filter_free_output { 7421 __le16 error_code; 7422 __le16 req_type; 7423 __le16 seq_id; 7424 __le16 resp_len; 7425 u8 unused_0[7]; 7426 u8 valid; 7427 }; 7428 7429 /* hwrm_wol_filter_qcfg_input (size:448b/56B) */ 7430 struct hwrm_wol_filter_qcfg_input { 7431 __le16 req_type; 7432 __le16 cmpl_ring; 7433 __le16 seq_id; 7434 __le16 target_id; 7435 __le64 resp_addr; 7436 __le16 port_id; 7437 __le16 handle; 7438 u8 unused_0[4]; 7439 __le64 pattern_buf_addr; 7440 __le16 pattern_buf_size; 7441 u8 unused_1[6]; 7442 __le64 pattern_mask_addr; 7443 __le16 pattern_mask_size; 7444 u8 unused_2[6]; 7445 }; 7446 7447 /* hwrm_wol_filter_qcfg_output (size:256b/32B) */ 7448 struct hwrm_wol_filter_qcfg_output { 7449 __le16 error_code; 7450 __le16 req_type; 7451 __le16 seq_id; 7452 __le16 resp_len; 7453 __le16 next_handle; 7454 u8 wol_filter_id; 7455 u8 wol_type; 7456 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL 7457 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL 7458 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL 7459 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 7460 __le32 unused_0; 7461 u8 mac_address[6]; 7462 __le16 pattern_offset; 7463 __le16 pattern_size; 7464 __le16 pattern_mask_size; 7465 u8 unused_1[3]; 7466 u8 valid; 7467 }; 7468 7469 /* hwrm_wol_reason_qcfg_input (size:320b/40B) */ 7470 struct hwrm_wol_reason_qcfg_input { 7471 __le16 req_type; 7472 __le16 cmpl_ring; 7473 __le16 seq_id; 7474 __le16 target_id; 7475 __le64 resp_addr; 7476 __le16 port_id; 7477 u8 unused_0[6]; 7478 __le64 wol_pkt_buf_addr; 7479 __le16 wol_pkt_buf_size; 7480 u8 unused_1[6]; 7481 }; 7482 7483 /* hwrm_wol_reason_qcfg_output (size:128b/16B) */ 7484 struct hwrm_wol_reason_qcfg_output { 7485 __le16 error_code; 7486 __le16 req_type; 7487 __le16 seq_id; 7488 __le16 resp_len; 7489 u8 wol_filter_id; 7490 u8 wol_reason; 7491 #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL 7492 #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL 7493 #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL 7494 #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 7495 u8 wol_pkt_len; 7496 u8 unused_0[4]; 7497 u8 valid; 7498 }; 7499 7500 /* coredump_segment_record (size:128b/16B) */ 7501 struct coredump_segment_record { 7502 __le16 component_id; 7503 __le16 segment_id; 7504 __le16 max_instances; 7505 u8 version_hi; 7506 u8 version_low; 7507 u8 seg_flags; 7508 u8 compress_flags; 7509 #define SFLAG_COMPRESSED_ZLIB 0x1UL 7510 u8 unused_0[6]; 7511 }; 7512 7513 /* hwrm_dbg_coredump_list_input (size:256b/32B) */ 7514 struct hwrm_dbg_coredump_list_input { 7515 __le16 req_type; 7516 __le16 cmpl_ring; 7517 __le16 seq_id; 7518 __le16 target_id; 7519 __le64 resp_addr; 7520 __le64 host_dest_addr; 7521 __le32 host_buf_len; 7522 __le16 seq_no; 7523 u8 flags; 7524 #define DBG_COREDUMP_LIST_REQ_FLAGS_CRASHDUMP 0x1UL 7525 u8 unused_0[1]; 7526 }; 7527 7528 /* hwrm_dbg_coredump_list_output (size:128b/16B) */ 7529 struct hwrm_dbg_coredump_list_output { 7530 __le16 error_code; 7531 __le16 req_type; 7532 __le16 seq_id; 7533 __le16 resp_len; 7534 u8 flags; 7535 #define DBG_COREDUMP_LIST_RESP_FLAGS_MORE 0x1UL 7536 u8 unused_0; 7537 __le16 total_segments; 7538 __le16 data_len; 7539 u8 unused_1; 7540 u8 valid; 7541 }; 7542 7543 /* hwrm_dbg_coredump_initiate_input (size:256b/32B) */ 7544 struct hwrm_dbg_coredump_initiate_input { 7545 __le16 req_type; 7546 __le16 cmpl_ring; 7547 __le16 seq_id; 7548 __le16 target_id; 7549 __le64 resp_addr; 7550 __le16 component_id; 7551 __le16 segment_id; 7552 __le16 instance; 7553 __le16 unused_0; 7554 u8 seg_flags; 7555 u8 unused_1[7]; 7556 }; 7557 7558 /* hwrm_dbg_coredump_initiate_output (size:128b/16B) */ 7559 struct hwrm_dbg_coredump_initiate_output { 7560 __le16 error_code; 7561 __le16 req_type; 7562 __le16 seq_id; 7563 __le16 resp_len; 7564 u8 unused_0[7]; 7565 u8 valid; 7566 }; 7567 7568 /* coredump_data_hdr (size:128b/16B) */ 7569 struct coredump_data_hdr { 7570 __le32 address; 7571 __le32 flags_length; 7572 __le32 instance; 7573 __le32 next_offset; 7574 }; 7575 7576 /* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */ 7577 struct hwrm_dbg_coredump_retrieve_input { 7578 __le16 req_type; 7579 __le16 cmpl_ring; 7580 __le16 seq_id; 7581 __le16 target_id; 7582 __le64 resp_addr; 7583 __le64 host_dest_addr; 7584 __le32 host_buf_len; 7585 __le32 unused_0; 7586 __le16 component_id; 7587 __le16 segment_id; 7588 __le16 instance; 7589 __le16 unused_1; 7590 u8 seg_flags; 7591 u8 unused_2; 7592 __le16 unused_3; 7593 __le32 unused_4; 7594 __le32 seq_no; 7595 __le32 unused_5; 7596 }; 7597 7598 /* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */ 7599 struct hwrm_dbg_coredump_retrieve_output { 7600 __le16 error_code; 7601 __le16 req_type; 7602 __le16 seq_id; 7603 __le16 resp_len; 7604 u8 flags; 7605 #define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE 0x1UL 7606 u8 unused_0; 7607 __le16 data_len; 7608 u8 unused_1[3]; 7609 u8 valid; 7610 }; 7611 7612 /* hwrm_dbg_ring_info_get_input (size:192b/24B) */ 7613 struct hwrm_dbg_ring_info_get_input { 7614 __le16 req_type; 7615 __le16 cmpl_ring; 7616 __le16 seq_id; 7617 __le16 target_id; 7618 __le64 resp_addr; 7619 u8 ring_type; 7620 #define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL 7621 #define DBG_RING_INFO_GET_REQ_RING_TYPE_TX 0x1UL 7622 #define DBG_RING_INFO_GET_REQ_RING_TYPE_RX 0x2UL 7623 #define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST DBG_RING_INFO_GET_REQ_RING_TYPE_RX 7624 u8 unused_0[3]; 7625 __le32 fw_ring_id; 7626 }; 7627 7628 /* hwrm_dbg_ring_info_get_output (size:192b/24B) */ 7629 struct hwrm_dbg_ring_info_get_output { 7630 __le16 error_code; 7631 __le16 req_type; 7632 __le16 seq_id; 7633 __le16 resp_len; 7634 __le32 producer_index; 7635 __le32 consumer_index; 7636 u8 unused_0[7]; 7637 u8 valid; 7638 }; 7639 7640 /* hwrm_nvm_read_input (size:320b/40B) */ 7641 struct hwrm_nvm_read_input { 7642 __le16 req_type; 7643 __le16 cmpl_ring; 7644 __le16 seq_id; 7645 __le16 target_id; 7646 __le64 resp_addr; 7647 __le64 host_dest_addr; 7648 __le16 dir_idx; 7649 u8 unused_0[2]; 7650 __le32 offset; 7651 __le32 len; 7652 u8 unused_1[4]; 7653 }; 7654 7655 /* hwrm_nvm_read_output (size:128b/16B) */ 7656 struct hwrm_nvm_read_output { 7657 __le16 error_code; 7658 __le16 req_type; 7659 __le16 seq_id; 7660 __le16 resp_len; 7661 u8 unused_0[7]; 7662 u8 valid; 7663 }; 7664 7665 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */ 7666 struct hwrm_nvm_get_dir_entries_input { 7667 __le16 req_type; 7668 __le16 cmpl_ring; 7669 __le16 seq_id; 7670 __le16 target_id; 7671 __le64 resp_addr; 7672 __le64 host_dest_addr; 7673 }; 7674 7675 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */ 7676 struct hwrm_nvm_get_dir_entries_output { 7677 __le16 error_code; 7678 __le16 req_type; 7679 __le16 seq_id; 7680 __le16 resp_len; 7681 u8 unused_0[7]; 7682 u8 valid; 7683 }; 7684 7685 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */ 7686 struct hwrm_nvm_get_dir_info_input { 7687 __le16 req_type; 7688 __le16 cmpl_ring; 7689 __le16 seq_id; 7690 __le16 target_id; 7691 __le64 resp_addr; 7692 }; 7693 7694 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */ 7695 struct hwrm_nvm_get_dir_info_output { 7696 __le16 error_code; 7697 __le16 req_type; 7698 __le16 seq_id; 7699 __le16 resp_len; 7700 __le32 entries; 7701 __le32 entry_length; 7702 u8 unused_0[7]; 7703 u8 valid; 7704 }; 7705 7706 /* hwrm_nvm_write_input (size:384b/48B) */ 7707 struct hwrm_nvm_write_input { 7708 __le16 req_type; 7709 __le16 cmpl_ring; 7710 __le16 seq_id; 7711 __le16 target_id; 7712 __le64 resp_addr; 7713 __le64 host_src_addr; 7714 __le16 dir_type; 7715 __le16 dir_ordinal; 7716 __le16 dir_ext; 7717 __le16 dir_attr; 7718 __le32 dir_data_length; 7719 __le16 option; 7720 __le16 flags; 7721 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 7722 __le32 dir_item_length; 7723 __le32 unused_0; 7724 }; 7725 7726 /* hwrm_nvm_write_output (size:128b/16B) */ 7727 struct hwrm_nvm_write_output { 7728 __le16 error_code; 7729 __le16 req_type; 7730 __le16 seq_id; 7731 __le16 resp_len; 7732 __le32 dir_item_length; 7733 __le16 dir_idx; 7734 u8 unused_0; 7735 u8 valid; 7736 }; 7737 7738 /* hwrm_nvm_write_cmd_err (size:64b/8B) */ 7739 struct hwrm_nvm_write_cmd_err { 7740 u8 code; 7741 #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL 7742 #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL 7743 #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL 7744 #define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_NO_SPACE 7745 u8 unused_0[7]; 7746 }; 7747 7748 /* hwrm_nvm_modify_input (size:320b/40B) */ 7749 struct hwrm_nvm_modify_input { 7750 __le16 req_type; 7751 __le16 cmpl_ring; 7752 __le16 seq_id; 7753 __le16 target_id; 7754 __le64 resp_addr; 7755 __le64 host_src_addr; 7756 __le16 dir_idx; 7757 __le16 flags; 7758 #define NVM_MODIFY_REQ_FLAGS_BATCH_MODE 0x1UL 7759 #define NVM_MODIFY_REQ_FLAGS_BATCH_LAST 0x2UL 7760 __le32 offset; 7761 __le32 len; 7762 u8 unused_1[4]; 7763 }; 7764 7765 /* hwrm_nvm_modify_output (size:128b/16B) */ 7766 struct hwrm_nvm_modify_output { 7767 __le16 error_code; 7768 __le16 req_type; 7769 __le16 seq_id; 7770 __le16 resp_len; 7771 u8 unused_0[7]; 7772 u8 valid; 7773 }; 7774 7775 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */ 7776 struct hwrm_nvm_find_dir_entry_input { 7777 __le16 req_type; 7778 __le16 cmpl_ring; 7779 __le16 seq_id; 7780 __le16 target_id; 7781 __le64 resp_addr; 7782 __le32 enables; 7783 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 7784 __le16 dir_idx; 7785 __le16 dir_type; 7786 __le16 dir_ordinal; 7787 __le16 dir_ext; 7788 u8 opt_ordinal; 7789 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 7790 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 7791 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL 7792 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL 7793 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL 7794 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 7795 u8 unused_0[3]; 7796 }; 7797 7798 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */ 7799 struct hwrm_nvm_find_dir_entry_output { 7800 __le16 error_code; 7801 __le16 req_type; 7802 __le16 seq_id; 7803 __le16 resp_len; 7804 __le32 dir_item_length; 7805 __le32 dir_data_length; 7806 __le32 fw_ver; 7807 __le16 dir_ordinal; 7808 __le16 dir_idx; 7809 u8 unused_0[7]; 7810 u8 valid; 7811 }; 7812 7813 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */ 7814 struct hwrm_nvm_erase_dir_entry_input { 7815 __le16 req_type; 7816 __le16 cmpl_ring; 7817 __le16 seq_id; 7818 __le16 target_id; 7819 __le64 resp_addr; 7820 __le16 dir_idx; 7821 u8 unused_0[6]; 7822 }; 7823 7824 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */ 7825 struct hwrm_nvm_erase_dir_entry_output { 7826 __le16 error_code; 7827 __le16 req_type; 7828 __le16 seq_id; 7829 __le16 resp_len; 7830 u8 unused_0[7]; 7831 u8 valid; 7832 }; 7833 7834 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */ 7835 struct hwrm_nvm_get_dev_info_input { 7836 __le16 req_type; 7837 __le16 cmpl_ring; 7838 __le16 seq_id; 7839 __le16 target_id; 7840 __le64 resp_addr; 7841 }; 7842 7843 /* hwrm_nvm_get_dev_info_output (size:256b/32B) */ 7844 struct hwrm_nvm_get_dev_info_output { 7845 __le16 error_code; 7846 __le16 req_type; 7847 __le16 seq_id; 7848 __le16 resp_len; 7849 __le16 manufacturer_id; 7850 __le16 device_id; 7851 __le32 sector_size; 7852 __le32 nvram_size; 7853 __le32 reserved_size; 7854 __le32 available_size; 7855 u8 nvm_cfg_ver_maj; 7856 u8 nvm_cfg_ver_min; 7857 u8 nvm_cfg_ver_upd; 7858 u8 valid; 7859 }; 7860 7861 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */ 7862 struct hwrm_nvm_mod_dir_entry_input { 7863 __le16 req_type; 7864 __le16 cmpl_ring; 7865 __le16 seq_id; 7866 __le16 target_id; 7867 __le64 resp_addr; 7868 __le32 enables; 7869 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 7870 __le16 dir_idx; 7871 __le16 dir_ordinal; 7872 __le16 dir_ext; 7873 __le16 dir_attr; 7874 __le32 checksum; 7875 }; 7876 7877 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */ 7878 struct hwrm_nvm_mod_dir_entry_output { 7879 __le16 error_code; 7880 __le16 req_type; 7881 __le16 seq_id; 7882 __le16 resp_len; 7883 u8 unused_0[7]; 7884 u8 valid; 7885 }; 7886 7887 /* hwrm_nvm_verify_update_input (size:192b/24B) */ 7888 struct hwrm_nvm_verify_update_input { 7889 __le16 req_type; 7890 __le16 cmpl_ring; 7891 __le16 seq_id; 7892 __le16 target_id; 7893 __le64 resp_addr; 7894 __le16 dir_type; 7895 __le16 dir_ordinal; 7896 __le16 dir_ext; 7897 u8 unused_0[2]; 7898 }; 7899 7900 /* hwrm_nvm_verify_update_output (size:128b/16B) */ 7901 struct hwrm_nvm_verify_update_output { 7902 __le16 error_code; 7903 __le16 req_type; 7904 __le16 seq_id; 7905 __le16 resp_len; 7906 u8 unused_0[7]; 7907 u8 valid; 7908 }; 7909 7910 /* hwrm_nvm_install_update_input (size:192b/24B) */ 7911 struct hwrm_nvm_install_update_input { 7912 __le16 req_type; 7913 __le16 cmpl_ring; 7914 __le16 seq_id; 7915 __le16 target_id; 7916 __le64 resp_addr; 7917 __le32 install_type; 7918 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 7919 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 7920 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 7921 __le16 flags; 7922 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL 7923 #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL 7924 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL 7925 u8 unused_0[2]; 7926 }; 7927 7928 /* hwrm_nvm_install_update_output (size:192b/24B) */ 7929 struct hwrm_nvm_install_update_output { 7930 __le16 error_code; 7931 __le16 req_type; 7932 __le16 seq_id; 7933 __le16 resp_len; 7934 __le64 installed_items; 7935 u8 result; 7936 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL 7937 #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 7938 u8 problem_item; 7939 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL 7940 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL 7941 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 7942 u8 reset_required; 7943 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL 7944 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL 7945 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL 7946 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 7947 u8 unused_0[4]; 7948 u8 valid; 7949 }; 7950 7951 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */ 7952 struct hwrm_nvm_install_update_cmd_err { 7953 u8 code; 7954 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL 7955 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL 7956 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL 7957 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 7958 u8 unused_0[7]; 7959 }; 7960 7961 /* hwrm_nvm_get_variable_input (size:320b/40B) */ 7962 struct hwrm_nvm_get_variable_input { 7963 __le16 req_type; 7964 __le16 cmpl_ring; 7965 __le16 seq_id; 7966 __le16 target_id; 7967 __le64 resp_addr; 7968 __le64 dest_data_addr; 7969 __le16 data_len; 7970 __le16 option_num; 7971 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 7972 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 7973 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 7974 __le16 dimensions; 7975 __le16 index_0; 7976 __le16 index_1; 7977 __le16 index_2; 7978 __le16 index_3; 7979 u8 flags; 7980 #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL 7981 u8 unused_0; 7982 }; 7983 7984 /* hwrm_nvm_get_variable_output (size:128b/16B) */ 7985 struct hwrm_nvm_get_variable_output { 7986 __le16 error_code; 7987 __le16 req_type; 7988 __le16 seq_id; 7989 __le16 resp_len; 7990 __le16 data_len; 7991 __le16 option_num; 7992 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL 7993 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL 7994 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 7995 u8 unused_0[3]; 7996 u8 valid; 7997 }; 7998 7999 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */ 8000 struct hwrm_nvm_get_variable_cmd_err { 8001 u8 code; 8002 #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 8003 #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 8004 #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 8005 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL 8006 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 8007 u8 unused_0[7]; 8008 }; 8009 8010 /* hwrm_nvm_set_variable_input (size:320b/40B) */ 8011 struct hwrm_nvm_set_variable_input { 8012 __le16 req_type; 8013 __le16 cmpl_ring; 8014 __le16 seq_id; 8015 __le16 target_id; 8016 __le64 resp_addr; 8017 __le64 src_data_addr; 8018 __le16 data_len; 8019 __le16 option_num; 8020 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 8021 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 8022 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 8023 __le16 dimensions; 8024 __le16 index_0; 8025 __le16 index_1; 8026 __le16 index_2; 8027 __le16 index_3; 8028 u8 flags; 8029 #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL 8030 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL 8031 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1 8032 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1) 8033 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1) 8034 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256 (0x2UL << 1) 8035 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (0x3UL << 1) 8036 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH 8037 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_MASK 0x70UL 8038 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_SFT 4 8039 #define NVM_SET_VARIABLE_REQ_FLAGS_FACTORY_DEFAULT 0x80UL 8040 u8 unused_0; 8041 }; 8042 8043 /* hwrm_nvm_set_variable_output (size:128b/16B) */ 8044 struct hwrm_nvm_set_variable_output { 8045 __le16 error_code; 8046 __le16 req_type; 8047 __le16 seq_id; 8048 __le16 resp_len; 8049 u8 unused_0[7]; 8050 u8 valid; 8051 }; 8052 8053 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */ 8054 struct hwrm_nvm_set_variable_cmd_err { 8055 u8 code; 8056 #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 8057 #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 8058 #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 8059 #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 8060 u8 unused_0[7]; 8061 }; 8062 8063 /* hwrm_selftest_qlist_input (size:128b/16B) */ 8064 struct hwrm_selftest_qlist_input { 8065 __le16 req_type; 8066 __le16 cmpl_ring; 8067 __le16 seq_id; 8068 __le16 target_id; 8069 __le64 resp_addr; 8070 }; 8071 8072 /* hwrm_selftest_qlist_output (size:2240b/280B) */ 8073 struct hwrm_selftest_qlist_output { 8074 __le16 error_code; 8075 __le16 req_type; 8076 __le16 seq_id; 8077 __le16 resp_len; 8078 u8 num_tests; 8079 u8 available_tests; 8080 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL 8081 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL 8082 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL 8083 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL 8084 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL 8085 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL 8086 u8 offline_tests; 8087 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL 8088 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL 8089 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL 8090 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL 8091 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL 8092 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL 8093 u8 unused_0; 8094 __le16 test_timeout; 8095 u8 unused_1[2]; 8096 char test0_name[32]; 8097 char test1_name[32]; 8098 char test2_name[32]; 8099 char test3_name[32]; 8100 char test4_name[32]; 8101 char test5_name[32]; 8102 char test6_name[32]; 8103 char test7_name[32]; 8104 u8 unused_2[7]; 8105 u8 valid; 8106 }; 8107 8108 /* hwrm_selftest_exec_input (size:192b/24B) */ 8109 struct hwrm_selftest_exec_input { 8110 __le16 req_type; 8111 __le16 cmpl_ring; 8112 __le16 seq_id; 8113 __le16 target_id; 8114 __le64 resp_addr; 8115 u8 flags; 8116 #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL 8117 #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL 8118 #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL 8119 #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL 8120 #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL 8121 #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL 8122 u8 unused_0[7]; 8123 }; 8124 8125 /* hwrm_selftest_exec_output (size:128b/16B) */ 8126 struct hwrm_selftest_exec_output { 8127 __le16 error_code; 8128 __le16 req_type; 8129 __le16 seq_id; 8130 __le16 resp_len; 8131 u8 requested_tests; 8132 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL 8133 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL 8134 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL 8135 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL 8136 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL 8137 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL 8138 u8 test_success; 8139 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL 8140 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL 8141 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL 8142 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL 8143 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL 8144 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL 8145 u8 unused_0[5]; 8146 u8 valid; 8147 }; 8148 8149 /* hwrm_selftest_irq_input (size:128b/16B) */ 8150 struct hwrm_selftest_irq_input { 8151 __le16 req_type; 8152 __le16 cmpl_ring; 8153 __le16 seq_id; 8154 __le16 target_id; 8155 __le64 resp_addr; 8156 }; 8157 8158 /* hwrm_selftest_irq_output (size:128b/16B) */ 8159 struct hwrm_selftest_irq_output { 8160 __le16 error_code; 8161 __le16 req_type; 8162 __le16 seq_id; 8163 __le16 resp_len; 8164 u8 unused_0[7]; 8165 u8 valid; 8166 }; 8167 8168 /* fw_status_reg (size:32b/4B) */ 8169 struct fw_status_reg { 8170 u32 fw_status; 8171 #define FW_STATUS_REG_CODE_MASK 0xffffUL 8172 #define FW_STATUS_REG_CODE_SFT 0 8173 #define FW_STATUS_REG_CODE_READY 0x8000UL 8174 #define FW_STATUS_REG_CODE_LAST FW_STATUS_REG_CODE_READY 8175 #define FW_STATUS_REG_IMAGE_DEGRADED 0x10000UL 8176 #define FW_STATUS_REG_RECOVERABLE 0x20000UL 8177 #define FW_STATUS_REG_CRASHDUMP_ONGOING 0x40000UL 8178 #define FW_STATUS_REG_CRASHDUMP_COMPLETE 0x80000UL 8179 #define FW_STATUS_REG_SHUTDOWN 0x100000UL 8180 }; 8181 8182 #endif /* _BNXT_HSI_H_ */ 8183