1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1028A family SoC. 4 * 5 * Copyright 2018 NXP 6 * 7 * Harninder Rai <harninder.rai@nxp.com> 8 * 9 */ 10 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "fsl,ls1028a"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 rtc1 = &ftm_alarm0; 22 }; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 cpu0: cpu@0 { 29 device_type = "cpu"; 30 compatible = "arm,cortex-a72"; 31 reg = <0x0>; 32 enable-method = "psci"; 33 clocks = <&clockgen 1 0>; 34 next-level-cache = <&l2>; 35 cpu-idle-states = <&CPU_PW20>; 36 #cooling-cells = <2>; 37 }; 38 39 cpu1: cpu@1 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a72"; 42 reg = <0x1>; 43 enable-method = "psci"; 44 clocks = <&clockgen 1 0>; 45 next-level-cache = <&l2>; 46 cpu-idle-states = <&CPU_PW20>; 47 #cooling-cells = <2>; 48 }; 49 50 l2: l2-cache { 51 compatible = "cache"; 52 }; 53 }; 54 55 idle-states { 56 /* 57 * PSCI node is not added default, U-boot will add missing 58 * parts if it determines to use PSCI. 59 */ 60 entry-method = "psci"; 61 62 CPU_PW20: cpu-pw20 { 63 compatible = "arm,idle-state"; 64 idle-state-name = "PW20"; 65 arm,psci-suspend-param = <0x0>; 66 entry-latency-us = <2000>; 67 exit-latency-us = <2000>; 68 min-residency-us = <6000>; 69 }; 70 }; 71 72 sysclk: clock-sysclk { 73 compatible = "fixed-clock"; 74 #clock-cells = <0>; 75 clock-frequency = <100000000>; 76 clock-output-names = "sysclk"; 77 }; 78 79 osc_27m: clock-osc-27m { 80 compatible = "fixed-clock"; 81 #clock-cells = <0>; 82 clock-frequency = <27000000>; 83 clock-output-names = "phy_27m"; 84 }; 85 86 dpclk: clock-controller@f1f0000 { 87 compatible = "fsl,ls1028a-plldig"; 88 reg = <0x0 0xf1f0000 0x0 0xffff>; 89 #clock-cells = <0>; 90 clocks = <&osc_27m>; 91 }; 92 93 reboot { 94 compatible ="syscon-reboot"; 95 regmap = <&rst>; 96 offset = <0xb0>; 97 mask = <0x02>; 98 }; 99 100 timer { 101 compatible = "arm,armv8-timer"; 102 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 103 IRQ_TYPE_LEVEL_LOW)>, 104 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 105 IRQ_TYPE_LEVEL_LOW)>, 106 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 107 IRQ_TYPE_LEVEL_LOW)>, 108 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 109 IRQ_TYPE_LEVEL_LOW)>; 110 }; 111 112 pmu { 113 compatible = "arm,cortex-a72-pmu"; 114 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 115 }; 116 117 gic: interrupt-controller@6000000 { 118 compatible= "arm,gic-v3"; 119 #address-cells = <2>; 120 #size-cells = <2>; 121 ranges; 122 reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 123 <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ 124 #interrupt-cells= <3>; 125 interrupt-controller; 126 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 127 IRQ_TYPE_LEVEL_LOW)>; 128 its: gic-its@6020000 { 129 compatible = "arm,gic-v3-its"; 130 msi-controller; 131 reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ 132 }; 133 }; 134 135 thermal-zones { 136 ddr-controller { 137 polling-delay-passive = <1000>; 138 polling-delay = <5000>; 139 thermal-sensors = <&tmu 0>; 140 141 trips { 142 ddr-ctrler-alert { 143 temperature = <85000>; 144 hysteresis = <2000>; 145 type = "passive"; 146 }; 147 148 ddr-ctrler-crit { 149 temperature = <95000>; 150 hysteresis = <2000>; 151 type = "critical"; 152 }; 153 }; 154 }; 155 156 core-cluster { 157 polling-delay-passive = <1000>; 158 polling-delay = <5000>; 159 thermal-sensors = <&tmu 1>; 160 161 trips { 162 core_cluster_alert: core-cluster-alert { 163 temperature = <85000>; 164 hysteresis = <2000>; 165 type = "passive"; 166 }; 167 168 core_cluster_crit: core-cluster-crit { 169 temperature = <95000>; 170 hysteresis = <2000>; 171 type = "critical"; 172 }; 173 }; 174 175 cooling-maps { 176 map0 { 177 trip = <&core_cluster_alert>; 178 cooling-device = 179 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 180 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 181 }; 182 }; 183 }; 184 }; 185 186 soc: soc { 187 compatible = "simple-bus"; 188 #address-cells = <2>; 189 #size-cells = <2>; 190 ranges; 191 192 ddr: memory-controller@1080000 { 193 compatible = "fsl,qoriq-memory-controller"; 194 reg = <0x0 0x1080000 0x0 0x1000>; 195 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 196 big-endian; 197 }; 198 199 dcfg: syscon@1e00000 { 200 compatible = "fsl,ls1028a-dcfg", "syscon"; 201 reg = <0x0 0x1e00000 0x0 0x10000>; 202 little-endian; 203 }; 204 205 rst: syscon@1e60000 { 206 compatible = "syscon"; 207 reg = <0x0 0x1e60000 0x0 0x10000>; 208 little-endian; 209 }; 210 211 scfg: syscon@1fc0000 { 212 compatible = "fsl,ls1028a-scfg", "syscon"; 213 reg = <0x0 0x1fc0000 0x0 0x10000>; 214 big-endian; 215 }; 216 217 clockgen: clock-controller@1300000 { 218 compatible = "fsl,ls1028a-clockgen"; 219 reg = <0x0 0x1300000 0x0 0xa0000>; 220 #clock-cells = <2>; 221 clocks = <&sysclk>; 222 }; 223 224 i2c0: i2c@2000000 { 225 compatible = "fsl,vf610-i2c"; 226 #address-cells = <1>; 227 #size-cells = <0>; 228 reg = <0x0 0x2000000 0x0 0x10000>; 229 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 230 clocks = <&clockgen 4 3>; 231 status = "disabled"; 232 }; 233 234 i2c1: i2c@2010000 { 235 compatible = "fsl,vf610-i2c"; 236 #address-cells = <1>; 237 #size-cells = <0>; 238 reg = <0x0 0x2010000 0x0 0x10000>; 239 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 240 clocks = <&clockgen 4 3>; 241 status = "disabled"; 242 }; 243 244 i2c2: i2c@2020000 { 245 compatible = "fsl,vf610-i2c"; 246 #address-cells = <1>; 247 #size-cells = <0>; 248 reg = <0x0 0x2020000 0x0 0x10000>; 249 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&clockgen 4 3>; 251 status = "disabled"; 252 }; 253 254 i2c3: i2c@2030000 { 255 compatible = "fsl,vf610-i2c"; 256 #address-cells = <1>; 257 #size-cells = <0>; 258 reg = <0x0 0x2030000 0x0 0x10000>; 259 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 260 clocks = <&clockgen 4 3>; 261 status = "disabled"; 262 }; 263 264 i2c4: i2c@2040000 { 265 compatible = "fsl,vf610-i2c"; 266 #address-cells = <1>; 267 #size-cells = <0>; 268 reg = <0x0 0x2040000 0x0 0x10000>; 269 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&clockgen 4 3>; 271 status = "disabled"; 272 }; 273 274 i2c5: i2c@2050000 { 275 compatible = "fsl,vf610-i2c"; 276 #address-cells = <1>; 277 #size-cells = <0>; 278 reg = <0x0 0x2050000 0x0 0x10000>; 279 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 280 clocks = <&clockgen 4 3>; 281 status = "disabled"; 282 }; 283 284 i2c6: i2c@2060000 { 285 compatible = "fsl,vf610-i2c"; 286 #address-cells = <1>; 287 #size-cells = <0>; 288 reg = <0x0 0x2060000 0x0 0x10000>; 289 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 290 clocks = <&clockgen 4 3>; 291 status = "disabled"; 292 }; 293 294 i2c7: i2c@2070000 { 295 compatible = "fsl,vf610-i2c"; 296 #address-cells = <1>; 297 #size-cells = <0>; 298 reg = <0x0 0x2070000 0x0 0x10000>; 299 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 300 clocks = <&clockgen 4 3>; 301 status = "disabled"; 302 }; 303 304 fspi: spi@20c0000 { 305 compatible = "nxp,lx2160a-fspi"; 306 #address-cells = <1>; 307 #size-cells = <0>; 308 reg = <0x0 0x20c0000 0x0 0x10000>, 309 <0x0 0x20000000 0x0 0x10000000>; 310 reg-names = "fspi_base", "fspi_mmap"; 311 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 313 clock-names = "fspi_en", "fspi"; 314 status = "disabled"; 315 }; 316 317 dspi0: spi@2100000 { 318 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 319 #address-cells = <1>; 320 #size-cells = <0>; 321 reg = <0x0 0x2100000 0x0 0x10000>; 322 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 323 clock-names = "dspi"; 324 clocks = <&clockgen 4 1>; 325 dmas = <&edma0 0 62>, <&edma0 0 60>; 326 dma-names = "tx", "rx"; 327 spi-num-chipselects = <4>; 328 little-endian; 329 status = "disabled"; 330 }; 331 332 dspi1: spi@2110000 { 333 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 334 #address-cells = <1>; 335 #size-cells = <0>; 336 reg = <0x0 0x2110000 0x0 0x10000>; 337 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 338 clock-names = "dspi"; 339 clocks = <&clockgen 4 1>; 340 dmas = <&edma0 0 58>, <&edma0 0 56>; 341 dma-names = "tx", "rx"; 342 spi-num-chipselects = <4>; 343 little-endian; 344 status = "disabled"; 345 }; 346 347 dspi2: spi@2120000 { 348 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 349 #address-cells = <1>; 350 #size-cells = <0>; 351 reg = <0x0 0x2120000 0x0 0x10000>; 352 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 353 clock-names = "dspi"; 354 clocks = <&clockgen 4 1>; 355 dmas = <&edma0 0 54>, <&edma0 0 2>; 356 dma-names = "tx", "rx"; 357 spi-num-chipselects = <3>; 358 little-endian; 359 status = "disabled"; 360 }; 361 362 esdhc: mmc@2140000 { 363 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 364 reg = <0x0 0x2140000 0x0 0x10000>; 365 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 366 clock-frequency = <0>; /* fixed up by bootloader */ 367 clocks = <&clockgen 2 1>; 368 voltage-ranges = <1800 1800 3300 3300>; 369 sdhci,auto-cmd12; 370 little-endian; 371 bus-width = <4>; 372 status = "disabled"; 373 }; 374 375 esdhc1: mmc@2150000 { 376 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 377 reg = <0x0 0x2150000 0x0 0x10000>; 378 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 379 clock-frequency = <0>; /* fixed up by bootloader */ 380 clocks = <&clockgen 2 1>; 381 voltage-ranges = <1800 1800 3300 3300>; 382 sdhci,auto-cmd12; 383 broken-cd; 384 little-endian; 385 bus-width = <4>; 386 status = "disabled"; 387 }; 388 389 duart0: serial@21c0500 { 390 compatible = "fsl,ns16550", "ns16550a"; 391 reg = <0x00 0x21c0500 0x0 0x100>; 392 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 393 clocks = <&clockgen 4 1>; 394 status = "disabled"; 395 }; 396 397 duart1: serial@21c0600 { 398 compatible = "fsl,ns16550", "ns16550a"; 399 reg = <0x00 0x21c0600 0x0 0x100>; 400 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 401 clocks = <&clockgen 4 1>; 402 status = "disabled"; 403 }; 404 405 406 lpuart0: serial@2260000 { 407 compatible = "fsl,ls1028a-lpuart"; 408 reg = <0x0 0x2260000 0x0 0x1000>; 409 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 410 clocks = <&clockgen 4 1>; 411 clock-names = "ipg"; 412 dma-names = "rx","tx"; 413 dmas = <&edma0 1 32>, 414 <&edma0 1 33>; 415 status = "disabled"; 416 }; 417 418 lpuart1: serial@2270000 { 419 compatible = "fsl,ls1028a-lpuart"; 420 reg = <0x0 0x2270000 0x0 0x1000>; 421 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 422 clocks = <&clockgen 4 1>; 423 clock-names = "ipg"; 424 dma-names = "rx","tx"; 425 dmas = <&edma0 1 30>, 426 <&edma0 1 31>; 427 status = "disabled"; 428 }; 429 430 lpuart2: serial@2280000 { 431 compatible = "fsl,ls1028a-lpuart"; 432 reg = <0x0 0x2280000 0x0 0x1000>; 433 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 434 clocks = <&clockgen 4 1>; 435 clock-names = "ipg"; 436 dma-names = "rx","tx"; 437 dmas = <&edma0 1 28>, 438 <&edma0 1 29>; 439 status = "disabled"; 440 }; 441 442 lpuart3: serial@2290000 { 443 compatible = "fsl,ls1028a-lpuart"; 444 reg = <0x0 0x2290000 0x0 0x1000>; 445 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 446 clocks = <&clockgen 4 1>; 447 clock-names = "ipg"; 448 dma-names = "rx","tx"; 449 dmas = <&edma0 1 26>, 450 <&edma0 1 27>; 451 status = "disabled"; 452 }; 453 454 lpuart4: serial@22a0000 { 455 compatible = "fsl,ls1028a-lpuart"; 456 reg = <0x0 0x22a0000 0x0 0x1000>; 457 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 458 clocks = <&clockgen 4 1>; 459 clock-names = "ipg"; 460 dma-names = "rx","tx"; 461 dmas = <&edma0 1 24>, 462 <&edma0 1 25>; 463 status = "disabled"; 464 }; 465 466 lpuart5: serial@22b0000 { 467 compatible = "fsl,ls1028a-lpuart"; 468 reg = <0x0 0x22b0000 0x0 0x1000>; 469 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 470 clocks = <&clockgen 4 1>; 471 clock-names = "ipg"; 472 dma-names = "rx","tx"; 473 dmas = <&edma0 1 22>, 474 <&edma0 1 23>; 475 status = "disabled"; 476 }; 477 478 edma0: dma-controller@22c0000 { 479 #dma-cells = <2>; 480 compatible = "fsl,ls1028a-edma", "fsl,vf610-edma"; 481 reg = <0x0 0x22c0000 0x0 0x10000>, 482 <0x0 0x22d0000 0x0 0x10000>, 483 <0x0 0x22e0000 0x0 0x10000>; 484 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 486 interrupt-names = "edma-tx", "edma-err"; 487 dma-channels = <32>; 488 clock-names = "dmamux0", "dmamux1"; 489 clocks = <&clockgen 4 1>, 490 <&clockgen 4 1>; 491 }; 492 493 gpio1: gpio@2300000 { 494 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 495 reg = <0x0 0x2300000 0x0 0x10000>; 496 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 497 gpio-controller; 498 #gpio-cells = <2>; 499 interrupt-controller; 500 #interrupt-cells = <2>; 501 little-endian; 502 }; 503 504 gpio2: gpio@2310000 { 505 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 506 reg = <0x0 0x2310000 0x0 0x10000>; 507 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 508 gpio-controller; 509 #gpio-cells = <2>; 510 interrupt-controller; 511 #interrupt-cells = <2>; 512 little-endian; 513 }; 514 515 gpio3: gpio@2320000 { 516 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 517 reg = <0x0 0x2320000 0x0 0x10000>; 518 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 519 gpio-controller; 520 #gpio-cells = <2>; 521 interrupt-controller; 522 #interrupt-cells = <2>; 523 little-endian; 524 }; 525 526 usb0: usb@3100000 { 527 compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 528 reg = <0x0 0x3100000 0x0 0x10000>; 529 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 530 dr_mode = "host"; 531 snps,dis_rxdet_inp3_quirk; 532 snps,quirk-frame-length-adjustment = <0x20>; 533 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 534 }; 535 536 usb1: usb@3110000 { 537 compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 538 reg = <0x0 0x3110000 0x0 0x10000>; 539 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 540 dr_mode = "host"; 541 snps,dis_rxdet_inp3_quirk; 542 snps,quirk-frame-length-adjustment = <0x20>; 543 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 544 }; 545 546 sata: sata@3200000 { 547 compatible = "fsl,ls1028a-ahci"; 548 reg = <0x0 0x3200000 0x0 0x10000>, 549 <0x7 0x100520 0x0 0x4>; 550 reg-names = "ahci", "sata-ecc"; 551 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&clockgen 4 1>; 553 status = "disabled"; 554 }; 555 556 pcie@3400000 { 557 compatible = "fsl,ls1028a-pcie"; 558 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 559 0x80 0x00000000 0x0 0x00002000>; /* configuration space */ 560 reg-names = "regs", "config"; 561 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 562 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 563 interrupt-names = "pme", "aer"; 564 #address-cells = <3>; 565 #size-cells = <2>; 566 device_type = "pci"; 567 dma-coherent; 568 num-viewport = <8>; 569 bus-range = <0x0 0xff>; 570 ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */ 571 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 572 msi-parent = <&its>; 573 #interrupt-cells = <1>; 574 interrupt-map-mask = <0 0 0 7>; 575 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 576 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 577 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 578 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 579 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 580 status = "disabled"; 581 }; 582 583 pcie@3500000 { 584 compatible = "fsl,ls1028a-pcie"; 585 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 586 0x88 0x00000000 0x0 0x00002000>; /* configuration space */ 587 reg-names = "regs", "config"; 588 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 590 interrupt-names = "pme", "aer"; 591 #address-cells = <3>; 592 #size-cells = <2>; 593 device_type = "pci"; 594 dma-coherent; 595 num-viewport = <8>; 596 bus-range = <0x0 0xff>; 597 ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */ 598 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 599 msi-parent = <&its>; 600 #interrupt-cells = <1>; 601 interrupt-map-mask = <0 0 0 7>; 602 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 603 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 604 <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 605 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 606 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 607 status = "disabled"; 608 }; 609 610 smmu: iommu@5000000 { 611 compatible = "arm,mmu-500"; 612 reg = <0 0x5000000 0 0x800000>; 613 #global-interrupts = <8>; 614 #iommu-cells = <1>; 615 stream-match-mask = <0x7c00>; 616 /* global secure fault */ 617 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 618 /* combined secure interrupt */ 619 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 620 /* global non-secure fault */ 621 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 622 /* combined non-secure interrupt */ 623 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 624 /* performance counter interrupts 0-7 */ 625 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 627 /* per context interrupt, 64 interrupts */ 628 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 631 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 632 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 651 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 652 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 657 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 660 }; 661 662 crypto: crypto@8000000 { 663 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 664 fsl,sec-era = <10>; 665 #address-cells = <1>; 666 #size-cells = <1>; 667 ranges = <0x0 0x00 0x8000000 0x100000>; 668 reg = <0x00 0x8000000 0x0 0x100000>; 669 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 670 dma-coherent; 671 672 sec_jr0: jr@10000 { 673 compatible = "fsl,sec-v5.0-job-ring", 674 "fsl,sec-v4.0-job-ring"; 675 reg = <0x10000 0x10000>; 676 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 677 }; 678 679 sec_jr1: jr@20000 { 680 compatible = "fsl,sec-v5.0-job-ring", 681 "fsl,sec-v4.0-job-ring"; 682 reg = <0x20000 0x10000>; 683 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 684 }; 685 686 sec_jr2: jr@30000 { 687 compatible = "fsl,sec-v5.0-job-ring", 688 "fsl,sec-v4.0-job-ring"; 689 reg = <0x30000 0x10000>; 690 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 691 }; 692 693 sec_jr3: jr@40000 { 694 compatible = "fsl,sec-v5.0-job-ring", 695 "fsl,sec-v4.0-job-ring"; 696 reg = <0x40000 0x10000>; 697 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 698 }; 699 }; 700 701 qdma: dma-controller@8380000 { 702 compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma"; 703 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 704 <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 705 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 706 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 711 interrupt-names = "qdma-error", "qdma-queue0", 712 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 713 dma-channels = <8>; 714 block-number = <1>; 715 block-offset = <0x10000>; 716 fsl,dma-queues = <2>; 717 status-sizes = <64>; 718 queue-sizes = <64 64>; 719 }; 720 721 cluster1_core0_watchdog: watchdog@c000000 { 722 compatible = "arm,sp805", "arm,primecell"; 723 reg = <0x0 0xc000000 0x0 0x1000>; 724 clocks = <&clockgen 4 15>, <&clockgen 4 15>; 725 clock-names = "apb_pclk", "wdog_clk"; 726 }; 727 728 cluster1_core1_watchdog: watchdog@c010000 { 729 compatible = "arm,sp805", "arm,primecell"; 730 reg = <0x0 0xc010000 0x0 0x1000>; 731 clocks = <&clockgen 4 15>, <&clockgen 4 15>; 732 clock-names = "apb_pclk", "wdog_clk"; 733 }; 734 735 sai1: audio-controller@f100000 { 736 #sound-dai-cells = <0>; 737 compatible = "fsl,vf610-sai"; 738 reg = <0x0 0xf100000 0x0 0x10000>; 739 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 740 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 741 <&clockgen 4 1>, <&clockgen 4 1>; 742 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 743 dma-names = "tx", "rx"; 744 dmas = <&edma0 1 4>, 745 <&edma0 1 3>; 746 fsl,sai-asynchronous; 747 status = "disabled"; 748 }; 749 750 sai2: audio-controller@f110000 { 751 #sound-dai-cells = <0>; 752 compatible = "fsl,vf610-sai"; 753 reg = <0x0 0xf110000 0x0 0x10000>; 754 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 755 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 756 <&clockgen 4 1>, <&clockgen 4 1>; 757 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 758 dma-names = "tx", "rx"; 759 dmas = <&edma0 1 6>, 760 <&edma0 1 5>; 761 fsl,sai-asynchronous; 762 status = "disabled"; 763 }; 764 765 sai3: audio-controller@f120000 { 766 #sound-dai-cells = <0>; 767 compatible = "fsl,vf610-sai"; 768 reg = <0x0 0xf120000 0x0 0x10000>; 769 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 770 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 771 <&clockgen 4 1>, <&clockgen 4 1>; 772 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 773 dma-names = "tx", "rx"; 774 dmas = <&edma0 1 8>, 775 <&edma0 1 7>; 776 fsl,sai-asynchronous; 777 status = "disabled"; 778 }; 779 780 sai4: audio-controller@f130000 { 781 #sound-dai-cells = <0>; 782 compatible = "fsl,vf610-sai"; 783 reg = <0x0 0xf130000 0x0 0x10000>; 784 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 785 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 786 <&clockgen 4 1>, <&clockgen 4 1>; 787 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 788 dma-names = "tx", "rx"; 789 dmas = <&edma0 1 10>, 790 <&edma0 1 9>; 791 fsl,sai-asynchronous; 792 status = "disabled"; 793 }; 794 795 sai5: audio-controller@f140000 { 796 #sound-dai-cells = <0>; 797 compatible = "fsl,vf610-sai"; 798 reg = <0x0 0xf140000 0x0 0x10000>; 799 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 800 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 801 <&clockgen 4 1>, <&clockgen 4 1>; 802 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 803 dma-names = "tx", "rx"; 804 dmas = <&edma0 1 12>, 805 <&edma0 1 11>; 806 fsl,sai-asynchronous; 807 status = "disabled"; 808 }; 809 810 sai6: audio-controller@f150000 { 811 #sound-dai-cells = <0>; 812 compatible = "fsl,vf610-sai"; 813 reg = <0x0 0xf150000 0x0 0x10000>; 814 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 815 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 816 <&clockgen 4 1>, <&clockgen 4 1>; 817 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 818 dma-names = "tx", "rx"; 819 dmas = <&edma0 1 14>, 820 <&edma0 1 13>; 821 fsl,sai-asynchronous; 822 status = "disabled"; 823 }; 824 825 tmu: tmu@1f80000 { 826 compatible = "fsl,qoriq-tmu"; 827 reg = <0x0 0x1f80000 0x0 0x10000>; 828 interrupts = <0 23 0x4>; 829 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 830 fsl,tmu-calibration = <0x00000000 0x00000024 831 0x00000001 0x0000002b 832 0x00000002 0x00000031 833 0x00000003 0x00000038 834 0x00000004 0x0000003f 835 0x00000005 0x00000045 836 0x00000006 0x0000004c 837 0x00000007 0x00000053 838 0x00000008 0x00000059 839 0x00000009 0x00000060 840 0x0000000a 0x00000066 841 0x0000000b 0x0000006d 842 843 0x00010000 0x0000001c 844 0x00010001 0x00000024 845 0x00010002 0x0000002c 846 0x00010003 0x00000035 847 0x00010004 0x0000003d 848 0x00010005 0x00000045 849 0x00010006 0x0000004d 850 0x00010007 0x00000055 851 0x00010008 0x0000005e 852 0x00010009 0x00000066 853 0x0001000a 0x0000006e 854 855 0x00020000 0x00000018 856 0x00020001 0x00000022 857 0x00020002 0x0000002d 858 0x00020003 0x00000038 859 0x00020004 0x00000043 860 0x00020005 0x0000004d 861 0x00020006 0x00000058 862 0x00020007 0x00000063 863 0x00020008 0x0000006e 864 865 0x00030000 0x00000010 866 0x00030001 0x0000001c 867 0x00030002 0x00000029 868 0x00030003 0x00000036 869 0x00030004 0x00000042 870 0x00030005 0x0000004f 871 0x00030006 0x0000005b 872 0x00030007 0x00000068>; 873 little-endian; 874 #thermal-sensor-cells = <1>; 875 }; 876 877 pcie@1f0000000 { /* Integrated Endpoint Root Complex */ 878 compatible = "pci-host-ecam-generic"; 879 reg = <0x01 0xf0000000 0x0 0x100000>; 880 #address-cells = <3>; 881 #size-cells = <2>; 882 msi-parent = <&its>; 883 device_type = "pci"; 884 bus-range = <0x0 0x0>; 885 dma-coherent; 886 msi-map = <0 &its 0x17 0xe>; 887 iommu-map = <0 &smmu 0x17 0xe>; 888 /* PF0-6 BAR0 - non-prefetchable memory */ 889 ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000 890 /* PF0-6 BAR2 - prefetchable memory */ 891 0xc2000000 0x0 0x00000000 0x1 0xf8160000 0x0 0x070000 892 /* PF0: VF0-1 BAR0 - non-prefetchable memory */ 893 0x82000000 0x0 0x00000000 0x1 0xf81d0000 0x0 0x020000 894 /* PF0: VF0-1 BAR2 - prefetchable memory */ 895 0xc2000000 0x0 0x00000000 0x1 0xf81f0000 0x0 0x020000 896 /* PF1: VF0-1 BAR0 - non-prefetchable memory */ 897 0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000 898 /* PF1: VF0-1 BAR2 - prefetchable memory */ 899 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000 900 /* BAR4 (PF5) - non-prefetchable memory */ 901 0x82000000 0x0 0x00000000 0x1 0xfc000000 0x0 0x400000>; 902 903 enetc_port0: ethernet@0,0 { 904 compatible = "fsl,enetc"; 905 reg = <0x000000 0 0 0 0>; 906 status = "disabled"; 907 }; 908 909 enetc_port1: ethernet@0,1 { 910 compatible = "fsl,enetc"; 911 reg = <0x000100 0 0 0 0>; 912 status = "disabled"; 913 }; 914 915 enetc_port2: ethernet@0,2 { 916 compatible = "fsl,enetc"; 917 reg = <0x000200 0 0 0 0>; 918 phy-mode = "internal"; 919 status = "disabled"; 920 921 fixed-link { 922 speed = <1000>; 923 full-duplex; 924 }; 925 }; 926 927 enetc_mdio_pf3: mdio@0,3 { 928 compatible = "fsl,enetc-mdio"; 929 reg = <0x000300 0 0 0 0>; 930 #address-cells = <1>; 931 #size-cells = <0>; 932 }; 933 934 ethernet@0,4 { 935 compatible = "fsl,enetc-ptp"; 936 reg = <0x000400 0 0 0 0>; 937 clocks = <&clockgen 4 0>; 938 little-endian; 939 fsl,extts-fifo; 940 }; 941 942 mscc_felix: ethernet-switch@0,5 { 943 reg = <0x000500 0 0 0 0>; 944 /* IEP INT_B */ 945 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 946 status = "disabled"; 947 948 ports { 949 #address-cells = <1>; 950 #size-cells = <0>; 951 952 /* External ports */ 953 mscc_felix_port0: port@0 { 954 reg = <0>; 955 status = "disabled"; 956 }; 957 958 mscc_felix_port1: port@1 { 959 reg = <1>; 960 status = "disabled"; 961 }; 962 963 mscc_felix_port2: port@2 { 964 reg = <2>; 965 status = "disabled"; 966 }; 967 968 mscc_felix_port3: port@3 { 969 reg = <3>; 970 status = "disabled"; 971 }; 972 973 /* Internal ports */ 974 mscc_felix_port4: port@4 { 975 reg = <4>; 976 phy-mode = "internal"; 977 status = "disabled"; 978 979 fixed-link { 980 speed = <2500>; 981 full-duplex; 982 }; 983 }; 984 985 mscc_felix_port5: port@5 { 986 reg = <5>; 987 phy-mode = "internal"; 988 status = "disabled"; 989 990 fixed-link { 991 speed = <1000>; 992 full-duplex; 993 }; 994 }; 995 }; 996 }; 997 998 enetc_port3: ethernet@0,6 { 999 compatible = "fsl,enetc"; 1000 reg = <0x000600 0 0 0 0>; 1001 phy-mode = "internal"; 1002 status = "disabled"; 1003 1004 fixed-link { 1005 speed = <1000>; 1006 full-duplex; 1007 }; 1008 }; 1009 }; 1010 1011 rcpm: power-controller@1e34040 { 1012 compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+"; 1013 reg = <0x0 0x1e34040 0x0 0x1c>; 1014 #fsl,rcpm-wakeup-cells = <7>; 1015 }; 1016 1017 ftm_alarm0: timer@2800000 { 1018 compatible = "fsl,ls1028a-ftm-alarm"; 1019 reg = <0x0 0x2800000 0x0 0x10000>; 1020 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 1021 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1022 }; 1023 }; 1024 1025 malidp0: display@f080000 { 1026 compatible = "arm,mali-dp500"; 1027 reg = <0x0 0xf080000 0x0 0x10000>; 1028 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, 1029 <0 223 IRQ_TYPE_LEVEL_HIGH>; 1030 interrupt-names = "DE", "SE"; 1031 clocks = <&dpclk>, <&clockgen 2 2>, <&clockgen 2 2>, 1032 <&clockgen 2 2>; 1033 clock-names = "pxlclk", "mclk", "aclk", "pclk"; 1034 arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; 1035 arm,malidp-arqos-value = <0xd000d000>; 1036 1037 port { 1038 dp0_out: endpoint { 1039 1040 }; 1041 }; 1042 }; 1043}; 1044