1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Ben Ho <ben.ho@mediatek.com>
5 *	   Erin Lo <erin.lo@mediatek.com>
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/input.h>
10#include "mt8183.dtsi"
11#include "mt6358.dtsi"
12
13/ {
14	aliases {
15		serial0 = &uart0;
16	};
17
18	chosen {
19		stdout-path = "serial0:115200n8";
20	};
21
22	memory@40000000 {
23		device_type = "memory";
24		reg = <0 0x40000000 0 0x80000000>;
25	};
26
27	clk32k: oscillator1 {
28		compatible = "fixed-clock";
29		#clock-cells = <0>;
30		clock-frequency = <32768>;
31		clock-output-names = "clk32k";
32	};
33
34	it6505_pp18_reg: regulator0 {
35		compatible = "regulator-fixed";
36		regulator-name = "it6505_pp18";
37		regulator-min-microvolt = <1800000>;
38		regulator-max-microvolt = <1800000>;
39		gpio = <&pio 178 0>;
40		enable-active-high;
41	};
42
43	lcd_pp3300: regulator1 {
44		compatible = "regulator-fixed";
45		regulator-name = "lcd_pp3300";
46		regulator-min-microvolt = <3300000>;
47		regulator-max-microvolt = <3300000>;
48		regulator-always-on;
49		regulator-boot-on;
50	};
51
52	bl_pp5000: regulator2 {
53		compatible = "regulator-fixed";
54		regulator-name = "bl_pp5000";
55		regulator-min-microvolt = <5000000>;
56		regulator-max-microvolt = <5000000>;
57		regulator-always-on;
58		regulator-boot-on;
59	};
60
61	mmc1_fixed_power: regulator3 {
62		compatible = "regulator-fixed";
63		regulator-name = "mmc1_power";
64		regulator-min-microvolt = <3300000>;
65		regulator-max-microvolt = <3300000>;
66	};
67
68	mmc1_fixed_io: regulator4 {
69		compatible = "regulator-fixed";
70		regulator-name = "mmc1_io";
71		regulator-min-microvolt = <1800000>;
72		regulator-max-microvolt = <1800000>;
73	};
74
75	pp1800_alw: regulator5 {
76		compatible = "regulator-fixed";
77		regulator-name = "pp1800_alw";
78		regulator-always-on;
79		regulator-boot-on;
80		regulator-min-microvolt = <1800000>;
81		regulator-max-microvolt = <1800000>;
82	};
83
84	pp3300_alw: regulator6 {
85		compatible = "regulator-fixed";
86		regulator-name = "pp3300_alw";
87		regulator-always-on;
88		regulator-boot-on;
89		regulator-min-microvolt = <3300000>;
90		regulator-max-microvolt = <3300000>;
91	};
92
93	max98357a: codec0 {
94		compatible = "maxim,max98357a";
95		sdmode-gpios = <&pio 175 0>;
96	};
97
98	btsco: codec1 {
99		compatible = "linux,bt-sco";
100	};
101
102	wifi_pwrseq: wifi-pwrseq {
103		compatible = "mmc-pwrseq-simple";
104		pinctrl-names = "default";
105		pinctrl-0 = <&wifi_pins_pwrseq>;
106
107		/* Toggle WIFI_ENABLE to reset the chip. */
108		reset-gpios = <&pio 119 1>;
109	};
110
111	wifi_wakeup: wifi-wakeup {
112		compatible = "gpio-keys";
113		pinctrl-names = "default";
114		pinctrl-0 = <&wifi_pins_wakeup>;
115
116		wowlan {
117			label = "Wake on WiFi";
118			gpios = <&pio 113 GPIO_ACTIVE_HIGH>;
119			linux,code = <KEY_WAKEUP>;
120			wakeup-source;
121		};
122	};
123
124	tboard_thermistor1: thermal-sensor1 {
125		compatible = "generic-adc-thermal";
126		#thermal-sensor-cells = <0>;
127		io-channels = <&auxadc 0>;
128		io-channel-names = "sensor-channel";
129		temperature-lookup-table = <    (-5000) 4241
130						0 4063
131						5000 3856
132						10000 3621
133						15000 3364
134						20000 3091
135						25000 2810
136						30000 2526
137						35000 2247
138						40000 1982
139						45000 1734
140						50000 1507
141						55000 1305
142						60000 1122
143						65000 964
144						70000 827
145						75000 710
146						80000 606
147						85000 519
148						90000 445
149						95000 382
150						100000 330
151						105000 284
152						110000 245
153						115000 213
154						120000 183
155						125000 161>;
156	};
157
158	tboard_thermistor2: thermal-sensor2 {
159		compatible = "generic-adc-thermal";
160		#thermal-sensor-cells = <0>;
161		io-channels = <&auxadc 1>;
162		io-channel-names = "sensor-channel";
163		temperature-lookup-table = <    (-5000) 4241
164						0 4063
165						5000 3856
166						10000 3621
167						15000 3364
168						20000 3091
169						25000 2810
170						30000 2526
171						35000 2247
172						40000 1982
173						45000 1734
174						50000 1507
175						55000 1305
176						60000 1122
177						65000 964
178						70000 827
179						75000 710
180						80000 606
181						85000 519
182						90000 445
183						95000 382
184						100000 330
185						105000 284
186						110000 245
187						115000 213
188						120000 183
189						125000 161>;
190	};
191};
192
193&auxadc {
194	status = "okay";
195};
196
197&cpu0 {
198	proc-supply = <&mt6358_vproc12_reg>;
199};
200
201&cpu1 {
202	proc-supply = <&mt6358_vproc12_reg>;
203};
204
205&cpu2 {
206	proc-supply = <&mt6358_vproc12_reg>;
207};
208
209&cpu3 {
210	proc-supply = <&mt6358_vproc12_reg>;
211};
212
213&cpu4 {
214	proc-supply = <&mt6358_vproc11_reg>;
215};
216
217&cpu5 {
218	proc-supply = <&mt6358_vproc11_reg>;
219};
220
221&cpu6 {
222	proc-supply = <&mt6358_vproc11_reg>;
223};
224
225&cpu7 {
226	proc-supply = <&mt6358_vproc11_reg>;
227};
228
229&i2c0 {
230	pinctrl-names = "default";
231	pinctrl-0 = <&i2c0_pins>;
232	status = "okay";
233	clock-frequency = <400000>;
234	#address-cells = <1>;
235	#size-cells = <0>;
236};
237
238&i2c1 {
239	pinctrl-names = "default";
240	pinctrl-0 = <&i2c1_pins>;
241	status = "okay";
242	clock-frequency = <100000>;
243};
244
245&i2c3 {
246	pinctrl-names = "default";
247	pinctrl-0 = <&i2c3_pins>;
248	status = "okay";
249	clock-frequency = <100000>;
250	#address-cells = <1>;
251	#size-cells = <0>;
252};
253
254&i2c5 {
255	pinctrl-names = "default";
256	pinctrl-0 = <&i2c5_pins>;
257	status = "okay";
258	clock-frequency = <100000>;
259	#address-cells = <1>;
260	#size-cells = <0>;
261};
262
263&i2c6 {
264	pinctrl-names = "default";
265	pinctrl-0 = <&i2c6_pins>;
266	status = "okay";
267	clock-frequency = <100000>;
268};
269
270&mmc0 {
271	status = "okay";
272	pinctrl-names = "default", "state_uhs";
273	pinctrl-0 = <&mmc0_pins_default>;
274	pinctrl-1 = <&mmc0_pins_uhs>;
275	bus-width = <8>;
276	max-frequency = <200000000>;
277	cap-mmc-highspeed;
278	mmc-hs200-1_8v;
279	mmc-hs400-1_8v;
280	cap-mmc-hw-reset;
281	no-sdio;
282	no-sd;
283	hs400-ds-delay = <0x12814>;
284	vmmc-supply = <&mt6358_vemc_reg>;
285	vqmmc-supply = <&mt6358_vio18_reg>;
286	assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
287	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>;
288	non-removable;
289};
290
291&mmc1 {
292	status = "okay";
293	pinctrl-names = "default", "state_uhs";
294	pinctrl-0 = <&mmc1_pins_default>;
295	pinctrl-1 = <&mmc1_pins_uhs>;
296	vmmc-supply = <&mmc1_fixed_power>;
297	vqmmc-supply = <&mmc1_fixed_io>;
298	mmc-pwrseq = <&wifi_pwrseq>;
299	bus-width = <4>;
300	max-frequency = <200000000>;
301	drv-type = <2>;
302	cap-sd-highspeed;
303	sd-uhs-sdr50;
304	sd-uhs-sdr104;
305	keep-power-in-suspend;
306	enable-sdio-wakeup;
307	cap-sdio-irq;
308	non-removable;
309	no-mmc;
310	no-sd;
311	assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>;
312	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
313	#address-cells = <1>;
314	#size-cells = <0>;
315
316	qca_wifi: qca-wifi@1 {
317		compatible = "qcom,ath10k";
318		reg = <1>;
319	};
320};
321
322&mt6358_vdram2_reg {
323	regulator-always-on;
324};
325
326&mt6358codec {
327	Avdd-supply = <&mt6358_vaud28_reg>;
328};
329
330&mt6358_vsim1_reg {
331	regulator-min-microvolt = <2700000>;
332	regulator-max-microvolt = <2700000>;
333};
334
335&mt6358_vsim2_reg {
336	regulator-min-microvolt = <2700000>;
337	regulator-max-microvolt = <2700000>;
338};
339
340&pio {
341	bt_pins: bt-pins {
342		pins_bt_en {
343			pinmux = <PINMUX_GPIO120__FUNC_GPIO120>;
344			output-low;
345		};
346	};
347
348	ec_ap_int_odl: ec_ap_int_odl {
349		pins1 {
350			pinmux = <PINMUX_GPIO151__FUNC_GPIO151>;
351			input-enable;
352			bias-pull-up;
353		};
354	};
355
356	h1_int_od_l: h1_int_od_l {
357		pins1 {
358			pinmux = <PINMUX_GPIO153__FUNC_GPIO153>;
359			input-enable;
360		};
361	};
362
363	i2c0_pins: i2c0 {
364		pins_bus {
365			pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
366				 <PINMUX_GPIO83__FUNC_SCL0>;
367			mediatek,pull-up-adv = <3>;
368			mediatek,drive-strength-adv = <00>;
369		};
370	};
371
372	i2c1_pins: i2c1 {
373		pins_bus {
374			pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
375				 <PINMUX_GPIO84__FUNC_SCL1>;
376			mediatek,pull-up-adv = <3>;
377			mediatek,drive-strength-adv = <00>;
378		};
379	};
380
381	i2c2_pins: i2c2 {
382		pins_bus {
383			pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
384				 <PINMUX_GPIO104__FUNC_SDA2>;
385			bias-disable;
386			mediatek,drive-strength-adv = <00>;
387		};
388	};
389
390	i2c3_pins: i2c3 {
391		pins_bus {
392			pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
393				 <PINMUX_GPIO51__FUNC_SDA3>;
394			mediatek,pull-up-adv = <3>;
395			mediatek,drive-strength-adv = <00>;
396		};
397	};
398
399	i2c4_pins: i2c4 {
400		pins_bus {
401			pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
402				 <PINMUX_GPIO106__FUNC_SDA4>;
403			bias-disable;
404			mediatek,drive-strength-adv = <00>;
405		};
406	};
407
408	i2c5_pins: i2c5 {
409		pins_bus {
410			pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
411				 <PINMUX_GPIO49__FUNC_SDA5>;
412			mediatek,pull-up-adv = <3>;
413			mediatek,drive-strength-adv = <00>;
414		};
415	};
416
417	i2c6_pins: i2c6 {
418		pins_bus {
419			pinmux = <PINMUX_GPIO11__FUNC_SCL6>,
420				 <PINMUX_GPIO12__FUNC_SDA6>;
421			bias-disable;
422		};
423	};
424
425	mmc0_pins_default: mmc0-pins-default {
426		pins_cmd_dat {
427			pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
428				 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
429				 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
430				 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
431				 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
432				 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
433				 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
434				 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
435				 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
436			input-enable;
437			drive-strength = <MTK_DRIVE_14mA>;
438			mediatek,pull-up-adv = <01>;
439		};
440
441		pins_clk {
442			pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
443			drive-strength = <MTK_DRIVE_14mA>;
444			mediatek,pull-down-adv = <10>;
445		};
446
447		pins_rst {
448			pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
449			drive-strength = <MTK_DRIVE_14mA>;
450			mediatek,pull-down-adv = <01>;
451		};
452	};
453
454	mmc0_pins_uhs: mmc0-pins-uhs {
455		pins_cmd_dat {
456			pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
457				 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
458				 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
459				 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
460				 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
461				 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
462				 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
463				 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
464				 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
465			input-enable;
466			drive-strength = <MTK_DRIVE_14mA>;
467			mediatek,pull-up-adv = <01>;
468		};
469
470		pins_clk {
471			pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
472			drive-strength = <MTK_DRIVE_14mA>;
473			mediatek,pull-down-adv = <10>;
474		};
475
476		pins_ds {
477			pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>;
478			drive-strength = <MTK_DRIVE_14mA>;
479			mediatek,pull-down-adv = <10>;
480		};
481
482		pins_rst {
483			pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
484			drive-strength = <MTK_DRIVE_14mA>;
485			mediatek,pull-up-adv = <01>;
486		};
487	};
488
489	mmc1_pins_default: mmc1-pins-default {
490		pins_cmd_dat {
491			pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
492				 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
493				 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
494				 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
495				 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
496			input-enable;
497			mediatek,pull-up-adv = <10>;
498		};
499
500		pins_clk {
501			pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
502			input-enable;
503			mediatek,pull-down-adv = <10>;
504		};
505	};
506
507	mmc1_pins_uhs: mmc1-pins-uhs {
508		pins_cmd_dat {
509			pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
510				 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
511				 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
512				 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
513				 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
514			drive-strength = <MTK_DRIVE_6mA>;
515			input-enable;
516			mediatek,pull-up-adv = <10>;
517		};
518
519		pins_clk {
520			pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
521			drive-strength = <MTK_DRIVE_8mA>;
522			mediatek,pull-down-adv = <10>;
523			input-enable;
524		};
525	};
526
527	spi0_pins: spi0 {
528		pins_spi{
529			pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
530				 <PINMUX_GPIO86__FUNC_GPIO86>,
531				 <PINMUX_GPIO87__FUNC_SPI0_MO>,
532				 <PINMUX_GPIO88__FUNC_SPI0_CLK>;
533			bias-disable;
534		};
535	};
536
537	spi1_pins: spi1 {
538		pins_spi{
539			pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
540				 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
541				 <PINMUX_GPIO163__FUNC_SPI1_A_MO>,
542				 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>;
543			bias-disable;
544		};
545	};
546
547	spi2_pins: spi2 {
548		pins_spi{
549			pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
550				 <PINMUX_GPIO1__FUNC_SPI2_MO>,
551				 <PINMUX_GPIO2__FUNC_SPI2_CLK>;
552			bias-disable;
553		};
554		pins_spi_mi {
555			pinmux = <PINMUX_GPIO94__FUNC_SPI2_MI>;
556			mediatek,pull-down-adv = <00>;
557		};
558	};
559
560	spi3_pins: spi3 {
561		pins_spi{
562			pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
563				 <PINMUX_GPIO22__FUNC_SPI3_CSB>,
564				 <PINMUX_GPIO23__FUNC_SPI3_MO>,
565				 <PINMUX_GPIO24__FUNC_SPI3_CLK>;
566			bias-disable;
567		};
568	};
569
570	spi4_pins: spi4 {
571		pins_spi{
572			pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
573				 <PINMUX_GPIO18__FUNC_SPI4_CSB>,
574				 <PINMUX_GPIO19__FUNC_SPI4_MO>,
575				 <PINMUX_GPIO20__FUNC_SPI4_CLK>;
576			bias-disable;
577		};
578	};
579
580	spi5_pins: spi5 {
581		pins_spi{
582			pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
583				 <PINMUX_GPIO14__FUNC_SPI5_CSB>,
584				 <PINMUX_GPIO15__FUNC_SPI5_MO>,
585				 <PINMUX_GPIO16__FUNC_SPI5_CLK>;
586			bias-disable;
587		};
588	};
589
590	uart0_pins_default: uart0-pins-default {
591		pins_rx {
592			pinmux = <PINMUX_GPIO95__FUNC_URXD0>;
593			input-enable;
594			bias-pull-up;
595		};
596		pins_tx {
597			pinmux = <PINMUX_GPIO96__FUNC_UTXD0>;
598		};
599	};
600
601	uart1_pins_default: uart1-pins-default {
602		pins_rx {
603			pinmux = <PINMUX_GPIO121__FUNC_URXD1>;
604			input-enable;
605			bias-pull-up;
606		};
607		pins_tx {
608			pinmux = <PINMUX_GPIO115__FUNC_UTXD1>;
609		};
610		pins_rts {
611			pinmux = <PINMUX_GPIO47__FUNC_URTS1>;
612			output-enable;
613		};
614		pins_cts {
615			pinmux = <PINMUX_GPIO46__FUNC_UCTS1>;
616			input-enable;
617		};
618	};
619
620	uart1_pins_sleep: uart1-pins-sleep {
621		pins_rx {
622			pinmux = <PINMUX_GPIO121__FUNC_GPIO121>;
623			input-enable;
624			bias-pull-up;
625		};
626		pins_tx {
627			pinmux = <PINMUX_GPIO115__FUNC_UTXD1>;
628		};
629		pins_rts {
630			pinmux = <PINMUX_GPIO47__FUNC_URTS1>;
631			output-enable;
632		};
633		pins_cts {
634			pinmux = <PINMUX_GPIO46__FUNC_UCTS1>;
635			input-enable;
636		};
637	};
638
639	wifi_pins_pwrseq: wifi-pins-pwrseq {
640		pins_wifi_enable {
641			pinmux = <PINMUX_GPIO119__FUNC_GPIO119>;
642			output-low;
643		};
644	};
645
646	wifi_pins_wakeup: wifi-pins-wakeup {
647		pins_wifi_wakeup {
648			pinmux = <PINMUX_GPIO113__FUNC_GPIO113>;
649			input-enable;
650		};
651	};
652};
653
654&soc_data {
655	status = "okay";
656};
657
658&spi0 {
659	pinctrl-names = "default";
660	pinctrl-0 = <&spi0_pins>;
661	mediatek,pad-select = <0>;
662	status = "okay";
663	cs-gpios = <&pio 86 GPIO_ACTIVE_LOW>;
664
665	cr50@0 {
666		compatible = "google,cr50";
667		reg = <0>;
668		spi-max-frequency = <1000000>;
669		pinctrl-names = "default";
670		pinctrl-0 = <&h1_int_od_l>;
671		interrupt-parent = <&pio>;
672		interrupts = <153 IRQ_TYPE_EDGE_RISING>;
673	};
674};
675
676&spi1 {
677	pinctrl-names = "default";
678	pinctrl-0 = <&spi1_pins>;
679	mediatek,pad-select = <0>;
680	status = "okay";
681
682	w25q64dw: spi-flash@0 {
683		compatible = "winbond,w25q64dw", "jedec,spi-nor";
684		reg = <0>;
685		spi-max-frequency = <25000000>;
686	};
687};
688
689&spi2 {
690	pinctrl-names = "default";
691	pinctrl-0 = <&spi2_pins>;
692	mediatek,pad-select = <0>;
693	status = "okay";
694
695	cros_ec: cros-ec@0 {
696		compatible = "google,cros-ec-spi";
697		reg = <0>;
698		spi-max-frequency = <3000000>;
699		interrupt-parent = <&pio>;
700		interrupts = <151 IRQ_TYPE_LEVEL_LOW>;
701		pinctrl-names = "default";
702		pinctrl-0 = <&ec_ap_int_odl>;
703
704		i2c_tunnel: i2c-tunnel {
705			compatible = "google,cros-ec-i2c-tunnel";
706			google,remote-bus = <1>;
707			#address-cells = <1>;
708			#size-cells = <0>;
709		};
710
711		usbc_extcon: extcon0 {
712			compatible = "google,extcon-usbc-cros-ec";
713			google,usb-port-id = <0>;
714		};
715	};
716};
717
718&spi3 {
719	pinctrl-names = "default";
720	pinctrl-0 = <&spi3_pins>;
721	mediatek,pad-select = <0>;
722	status = "disabled";
723};
724
725&spi4 {
726	pinctrl-names = "default";
727	pinctrl-0 = <&spi4_pins>;
728	mediatek,pad-select = <0>;
729	status = "disabled";
730};
731
732&spi5 {
733	pinctrl-names = "default";
734	pinctrl-0 = <&spi5_pins>;
735	mediatek,pad-select = <0>;
736	status = "disabled";
737};
738
739&ssusb {
740	dr_mode = "host";
741	wakeup-source;
742	vusb33-supply = <&mt6358_vusb_reg>;
743	status = "okay";
744};
745
746&u3phy {
747	status = "okay";
748};
749
750&uart0 {
751	pinctrl-names = "default";
752	pinctrl-0 = <&uart0_pins_default>;
753	status = "okay";
754};
755
756&uart1 {
757	pinctrl-names = "default", "sleep";
758	pinctrl-0 = <&uart1_pins_default>;
759	pinctrl-1 = <&uart1_pins_sleep>;
760	status = "okay";
761	interrupts-extended = <&sysirq GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>,
762			      <&pio 121 IRQ_TYPE_EDGE_FALLING>;
763
764	bluetooth: bluetooth {
765		pinctrl-names = "default";
766		pinctrl-0 = <&bt_pins>;
767		status = "okay";
768		compatible = "qcom,qca6174-bt";
769		enable-gpios = <&pio 120 0>;
770		clocks = <&clk32k>;
771		firmware-name = "nvm_00440302_i2s.bin";
772	};
773};
774
775&usb_host {
776	#address-cells = <1>;
777	#size-cells = <0>;
778	vusb33-supply = <&mt6358_vusb_reg>;
779	status = "okay";
780
781	hub@1 {
782		compatible = "usb5e3,610";
783		reg = <1>;
784	};
785};
786
787#include <arm/cros-ec-keyboard.dtsi>
788#include <arm/cros-ec-sbs.dtsi>
789