1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Defining registers address and its bit definitions of MAX77620 and MAX20024 4 * 5 * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved. 6 */ 7 8 #ifndef _MFD_MAX77620_H_ 9 #define _MFD_MAX77620_H_ 10 11 #include <linux/types.h> 12 13 /* GLOBAL, PMIC, GPIO, FPS, ONOFFC, CID Registers */ 14 #define MAX77620_REG_CNFGGLBL1 0x00 15 #define MAX77620_REG_CNFGGLBL2 0x01 16 #define MAX77620_REG_CNFGGLBL3 0x02 17 #define MAX77620_REG_CNFG1_32K 0x03 18 #define MAX77620_REG_CNFGBBC 0x04 19 #define MAX77620_REG_IRQTOP 0x05 20 #define MAX77620_REG_INTLBT 0x06 21 #define MAX77620_REG_IRQSD 0x07 22 #define MAX77620_REG_IRQ_LVL2_L0_7 0x08 23 #define MAX77620_REG_IRQ_LVL2_L8 0x09 24 #define MAX77620_REG_IRQ_LVL2_GPIO 0x0A 25 #define MAX77620_REG_ONOFFIRQ 0x0B 26 #define MAX77620_REG_NVERC 0x0C 27 #define MAX77620_REG_IRQTOPM 0x0D 28 #define MAX77620_REG_INTENLBT 0x0E 29 #define MAX77620_REG_IRQMASKSD 0x0F 30 #define MAX77620_REG_IRQ_MSK_L0_7 0x10 31 #define MAX77620_REG_IRQ_MSK_L8 0x11 32 #define MAX77620_REG_ONOFFIRQM 0x12 33 #define MAX77620_REG_STATLBT 0x13 34 #define MAX77620_REG_STATSD 0x14 35 #define MAX77620_REG_ONOFFSTAT 0x15 36 37 /* SD and LDO Registers */ 38 #define MAX77620_REG_SD0 0x16 39 #define MAX77620_REG_SD1 0x17 40 #define MAX77620_REG_SD2 0x18 41 #define MAX77620_REG_SD3 0x19 42 #define MAX77620_REG_SD4 0x1A 43 #define MAX77620_REG_DVSSD0 0x1B 44 #define MAX77620_REG_DVSSD1 0x1C 45 #define MAX77620_REG_SD0_CFG 0x1D 46 #define MAX77620_REG_SD1_CFG 0x1E 47 #define MAX77620_REG_SD2_CFG 0x1F 48 #define MAX77620_REG_SD3_CFG 0x20 49 #define MAX77620_REG_SD4_CFG 0x21 50 #define MAX77620_REG_SD_CFG2 0x22 51 #define MAX77620_REG_LDO0_CFG 0x23 52 #define MAX77620_REG_LDO0_CFG2 0x24 53 #define MAX77620_REG_LDO1_CFG 0x25 54 #define MAX77620_REG_LDO1_CFG2 0x26 55 #define MAX77620_REG_LDO2_CFG 0x27 56 #define MAX77620_REG_LDO2_CFG2 0x28 57 #define MAX77620_REG_LDO3_CFG 0x29 58 #define MAX77620_REG_LDO3_CFG2 0x2A 59 #define MAX77620_REG_LDO4_CFG 0x2B 60 #define MAX77620_REG_LDO4_CFG2 0x2C 61 #define MAX77620_REG_LDO5_CFG 0x2D 62 #define MAX77620_REG_LDO5_CFG2 0x2E 63 #define MAX77620_REG_LDO6_CFG 0x2F 64 #define MAX77620_REG_LDO6_CFG2 0x30 65 #define MAX77620_REG_LDO7_CFG 0x31 66 #define MAX77620_REG_LDO7_CFG2 0x32 67 #define MAX77620_REG_LDO8_CFG 0x33 68 #define MAX77620_REG_LDO8_CFG2 0x34 69 #define MAX77620_REG_LDO_CFG3 0x35 70 71 #define MAX77620_LDO_SLEW_RATE_MASK 0x1 72 73 /* LDO Configuration 3 */ 74 #define MAX77620_TRACK4_MASK BIT(5) 75 #define MAX77620_TRACK4_SHIFT 5 76 77 /* Voltage */ 78 #define MAX77620_SDX_VOLT_MASK 0xFF 79 #define MAX77620_SD0_VOLT_MASK 0x3F 80 #define MAX77620_SD1_VOLT_MASK 0x7F 81 #define MAX77620_LDO_VOLT_MASK 0x3F 82 83 #define MAX77620_REG_GPIO0 0x36 84 #define MAX77620_REG_GPIO1 0x37 85 #define MAX77620_REG_GPIO2 0x38 86 #define MAX77620_REG_GPIO3 0x39 87 #define MAX77620_REG_GPIO4 0x3A 88 #define MAX77620_REG_GPIO5 0x3B 89 #define MAX77620_REG_GPIO6 0x3C 90 #define MAX77620_REG_GPIO7 0x3D 91 #define MAX77620_REG_PUE_GPIO 0x3E 92 #define MAX77620_REG_PDE_GPIO 0x3F 93 #define MAX77620_REG_AME_GPIO 0x40 94 #define MAX77620_REG_ONOFFCNFG1 0x41 95 #define MAX77620_REG_ONOFFCNFG2 0x42 96 97 /* FPS Registers */ 98 #define MAX77620_REG_FPS_CFG0 0x43 99 #define MAX77620_REG_FPS_CFG1 0x44 100 #define MAX77620_REG_FPS_CFG2 0x45 101 #define MAX77620_REG_FPS_LDO0 0x46 102 #define MAX77620_REG_FPS_LDO1 0x47 103 #define MAX77620_REG_FPS_LDO2 0x48 104 #define MAX77620_REG_FPS_LDO3 0x49 105 #define MAX77620_REG_FPS_LDO4 0x4A 106 #define MAX77620_REG_FPS_LDO5 0x4B 107 #define MAX77620_REG_FPS_LDO6 0x4C 108 #define MAX77620_REG_FPS_LDO7 0x4D 109 #define MAX77620_REG_FPS_LDO8 0x4E 110 #define MAX77620_REG_FPS_SD0 0x4F 111 #define MAX77620_REG_FPS_SD1 0x50 112 #define MAX77620_REG_FPS_SD2 0x51 113 #define MAX77620_REG_FPS_SD3 0x52 114 #define MAX77620_REG_FPS_SD4 0x53 115 #define MAX77620_REG_FPS_NONE 0 116 117 #define MAX77620_FPS_SRC_MASK 0xC0 118 #define MAX77620_FPS_SRC_SHIFT 6 119 #define MAX77620_FPS_PU_PERIOD_MASK 0x38 120 #define MAX77620_FPS_PU_PERIOD_SHIFT 3 121 #define MAX77620_FPS_PD_PERIOD_MASK 0x07 122 #define MAX77620_FPS_PD_PERIOD_SHIFT 0 123 #define MAX77620_FPS_TIME_PERIOD_MASK 0x38 124 #define MAX77620_FPS_TIME_PERIOD_SHIFT 3 125 #define MAX77620_FPS_EN_SRC_MASK 0x06 126 #define MAX77620_FPS_EN_SRC_SHIFT 1 127 #define MAX77620_FPS_ENFPS_SW_MASK 0x01 128 #define MAX77620_FPS_ENFPS_SW 0x01 129 130 /* Minimum and maximum FPS period time (in microseconds) are 131 * different for MAX77620 and Max20024. 132 */ 133 #define MAX77620_FPS_PERIOD_MIN_US 40 134 #define MAX20024_FPS_PERIOD_MIN_US 20 135 136 #define MAX20024_FPS_PERIOD_MAX_US 2560 137 #define MAX77620_FPS_PERIOD_MAX_US 5120 138 139 #define MAX77620_REG_FPS_GPIO1 0x54 140 #define MAX77620_REG_FPS_GPIO2 0x55 141 #define MAX77620_REG_FPS_GPIO3 0x56 142 #define MAX77620_REG_FPS_RSO 0x57 143 #define MAX77620_REG_CID0 0x58 144 #define MAX77620_REG_CID1 0x59 145 #define MAX77620_REG_CID2 0x5A 146 #define MAX77620_REG_CID3 0x5B 147 #define MAX77620_REG_CID4 0x5C 148 #define MAX77620_REG_CID5 0x5D 149 150 #define MAX77620_REG_DVSSD4 0x5E 151 #define MAX20024_REG_MAX_ADD 0x70 152 153 #define MAX77620_CID_DIDM_MASK 0xF0 154 #define MAX77620_CID_DIDM_SHIFT 4 155 156 /* CNCG2SD */ 157 #define MAX77620_SD_CNF2_ROVS_EN_SD1 BIT(1) 158 #define MAX77620_SD_CNF2_ROVS_EN_SD0 BIT(2) 159 160 /* Device Identification Metal */ 161 #define MAX77620_CID5_DIDM(n) (((n) >> 4) & 0xF) 162 /* Device Indentification OTP */ 163 #define MAX77620_CID5_DIDO(n) ((n) & 0xF) 164 165 /* SD CNFG1 */ 166 #define MAX77620_SD_SR_MASK 0xC0 167 #define MAX77620_SD_SR_SHIFT 6 168 #define MAX77620_SD_POWER_MODE_MASK 0x30 169 #define MAX77620_SD_POWER_MODE_SHIFT 4 170 #define MAX77620_SD_CFG1_ADE_MASK BIT(3) 171 #define MAX77620_SD_CFG1_ADE_DISABLE 0 172 #define MAX77620_SD_CFG1_ADE_ENABLE BIT(3) 173 #define MAX77620_SD_FPWM_MASK 0x04 174 #define MAX77620_SD_FPWM_SHIFT 2 175 #define MAX77620_SD_FSRADE_MASK 0x01 176 #define MAX77620_SD_FSRADE_SHIFT 0 177 #define MAX77620_SD_CFG1_FPWM_SD_MASK BIT(2) 178 #define MAX77620_SD_CFG1_FPWM_SD_SKIP 0 179 #define MAX77620_SD_CFG1_FPWM_SD_FPWM BIT(2) 180 #define MAX20024_SD_CFG1_MPOK_MASK BIT(1) 181 #define MAX77620_SD_CFG1_FSRADE_SD_MASK BIT(0) 182 #define MAX77620_SD_CFG1_FSRADE_SD_DISABLE 0 183 #define MAX77620_SD_CFG1_FSRADE_SD_ENABLE BIT(0) 184 185 /* LDO_CNFG2 */ 186 #define MAX77620_LDO_POWER_MODE_MASK 0xC0 187 #define MAX77620_LDO_POWER_MODE_SHIFT 6 188 #define MAX20024_LDO_CFG2_MPOK_MASK BIT(2) 189 #define MAX77620_LDO_CFG2_ADE_MASK BIT(1) 190 #define MAX77620_LDO_CFG2_ADE_DISABLE 0 191 #define MAX77620_LDO_CFG2_ADE_ENABLE BIT(1) 192 #define MAX77620_LDO_CFG2_SS_MASK BIT(0) 193 #define MAX77620_LDO_CFG2_SS_FAST BIT(0) 194 #define MAX77620_LDO_CFG2_SS_SLOW 0 195 196 #define MAX77620_IRQ_TOP_GLBL_MASK BIT(7) 197 #define MAX77620_IRQ_TOP_SD_MASK BIT(6) 198 #define MAX77620_IRQ_TOP_LDO_MASK BIT(5) 199 #define MAX77620_IRQ_TOP_GPIO_MASK BIT(4) 200 #define MAX77620_IRQ_TOP_RTC_MASK BIT(3) 201 #define MAX77620_IRQ_TOP_32K_MASK BIT(2) 202 #define MAX77620_IRQ_TOP_ONOFF_MASK BIT(1) 203 204 #define MAX77620_IRQ_LBM_MASK BIT(3) 205 #define MAX77620_IRQ_TJALRM1_MASK BIT(2) 206 #define MAX77620_IRQ_TJALRM2_MASK BIT(1) 207 208 #define MAX77620_PWR_I2C_ADDR 0x3c 209 #define MAX77620_RTC_I2C_ADDR 0x68 210 211 #define MAX77620_CNFG_GPIO_DRV_MASK BIT(0) 212 #define MAX77620_CNFG_GPIO_DRV_PUSHPULL BIT(0) 213 #define MAX77620_CNFG_GPIO_DRV_OPENDRAIN 0 214 #define MAX77620_CNFG_GPIO_DIR_MASK BIT(1) 215 #define MAX77620_CNFG_GPIO_DIR_INPUT BIT(1) 216 #define MAX77620_CNFG_GPIO_DIR_OUTPUT 0 217 #define MAX77620_CNFG_GPIO_INPUT_VAL_MASK BIT(2) 218 #define MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK BIT(3) 219 #define MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH BIT(3) 220 #define MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW 0 221 #define MAX77620_CNFG_GPIO_INT_MASK (0x3 << 4) 222 #define MAX77620_CNFG_GPIO_INT_FALLING BIT(4) 223 #define MAX77620_CNFG_GPIO_INT_RISING BIT(5) 224 #define MAX77620_CNFG_GPIO_DBNC_MASK (0x3 << 6) 225 #define MAX77620_CNFG_GPIO_DBNC_None (0x0 << 6) 226 #define MAX77620_CNFG_GPIO_DBNC_8ms (0x1 << 6) 227 #define MAX77620_CNFG_GPIO_DBNC_16ms (0x2 << 6) 228 #define MAX77620_CNFG_GPIO_DBNC_32ms (0x3 << 6) 229 230 #define MAX77620_IRQ_LVL2_GPIO_EDGE0 BIT(0) 231 #define MAX77620_IRQ_LVL2_GPIO_EDGE1 BIT(1) 232 #define MAX77620_IRQ_LVL2_GPIO_EDGE2 BIT(2) 233 #define MAX77620_IRQ_LVL2_GPIO_EDGE3 BIT(3) 234 #define MAX77620_IRQ_LVL2_GPIO_EDGE4 BIT(4) 235 #define MAX77620_IRQ_LVL2_GPIO_EDGE5 BIT(5) 236 #define MAX77620_IRQ_LVL2_GPIO_EDGE6 BIT(6) 237 #define MAX77620_IRQ_LVL2_GPIO_EDGE7 BIT(7) 238 239 #define MAX77620_CNFG1_32K_OUT0_EN BIT(2) 240 241 #define MAX77620_ONOFFCNFG1_SFT_RST BIT(7) 242 #define MAX77620_ONOFFCNFG1_MRT_MASK 0x38 243 #define MAX77620_ONOFFCNFG1_MRT_SHIFT 0x3 244 #define MAX77620_ONOFFCNFG1_SLPEN BIT(2) 245 #define MAX77620_ONOFFCNFG1_PWR_OFF BIT(1) 246 #define MAX20024_ONOFFCNFG1_CLRSE 0x18 247 248 #define MAX77620_ONOFFCNFG2_SFT_RST_WK BIT(7) 249 #define MAX77620_ONOFFCNFG2_WD_RST_WK BIT(6) 250 #define MAX77620_ONOFFCNFG2_SLP_LPM_MSK BIT(5) 251 #define MAX77620_ONOFFCNFG2_WK_ALARM1 BIT(2) 252 #define MAX77620_ONOFFCNFG2_WK_EN0 BIT(0) 253 254 #define MAX77620_GLBLM_MASK BIT(0) 255 256 #define MAX77620_WDTC_MASK 0x3 257 #define MAX77620_WDTOFFC BIT(4) 258 #define MAX77620_WDTSLPC BIT(3) 259 #define MAX77620_WDTEN BIT(2) 260 261 #define MAX77620_TWD_MASK 0x3 262 #define MAX77620_TWD_2s 0x0 263 #define MAX77620_TWD_16s 0x1 264 #define MAX77620_TWD_64s 0x2 265 #define MAX77620_TWD_128s 0x3 266 267 #define MAX77620_CNFGGLBL1_LBDAC_EN BIT(7) 268 #define MAX77620_CNFGGLBL1_MPPLD BIT(6) 269 #define MAX77620_CNFGGLBL1_LBHYST (BIT(5) | BIT(4)) 270 #define MAX77620_CNFGGLBL1_LBDAC 0x0E 271 #define MAX77620_CNFGGLBL1_LBRSTEN BIT(0) 272 273 /* CNFG BBC registers */ 274 #define MAX77620_CNFGBBC_ENABLE BIT(0) 275 #define MAX77620_CNFGBBC_CURRENT_MASK 0x06 276 #define MAX77620_CNFGBBC_CURRENT_SHIFT 1 277 #define MAX77620_CNFGBBC_VOLTAGE_MASK 0x18 278 #define MAX77620_CNFGBBC_VOLTAGE_SHIFT 3 279 #define MAX77620_CNFGBBC_LOW_CURRENT_DISABLE BIT(5) 280 #define MAX77620_CNFGBBC_RESISTOR_MASK 0xC0 281 #define MAX77620_CNFGBBC_RESISTOR_SHIFT 6 282 283 #define MAX77620_FPS_COUNT 3 284 285 /* Interrupts */ 286 enum { 287 MAX77620_IRQ_TOP_GLBL, /* Low-Battery */ 288 MAX77620_IRQ_TOP_SD, /* SD power fail */ 289 MAX77620_IRQ_TOP_LDO, /* LDO power fail */ 290 MAX77620_IRQ_TOP_GPIO, /* TOP GPIO internal int to MAX77620 */ 291 MAX77620_IRQ_TOP_RTC, /* RTC */ 292 MAX77620_IRQ_TOP_32K, /* 32kHz oscillator */ 293 MAX77620_IRQ_TOP_ONOFF, /* ON/OFF oscillator */ 294 MAX77620_IRQ_LBT_MBATLOW, /* Thermal alarm status, > 120C */ 295 MAX77620_IRQ_LBT_TJALRM1, /* Thermal alarm status, > 120C */ 296 MAX77620_IRQ_LBT_TJALRM2, /* Thermal alarm status, > 140C */ 297 }; 298 299 /* GPIOs */ 300 enum { 301 MAX77620_GPIO0, 302 MAX77620_GPIO1, 303 MAX77620_GPIO2, 304 MAX77620_GPIO3, 305 MAX77620_GPIO4, 306 MAX77620_GPIO5, 307 MAX77620_GPIO6, 308 MAX77620_GPIO7, 309 MAX77620_GPIO_NR, 310 }; 311 312 /* FPS Source */ 313 enum max77620_fps_src { 314 MAX77620_FPS_SRC_0, 315 MAX77620_FPS_SRC_1, 316 MAX77620_FPS_SRC_2, 317 MAX77620_FPS_SRC_NONE, 318 MAX77620_FPS_SRC_DEF, 319 }; 320 321 enum max77620_chip_id { 322 MAX77620, 323 MAX20024, 324 MAX77663, 325 }; 326 327 struct max77620_chip { 328 struct device *dev; 329 struct regmap *rmap; 330 331 int chip_irq; 332 333 /* chip id */ 334 enum max77620_chip_id chip_id; 335 336 bool sleep_enable; 337 bool enable_global_lpm; 338 int shutdown_fps_period[MAX77620_FPS_COUNT]; 339 int suspend_fps_period[MAX77620_FPS_COUNT]; 340 341 struct regmap_irq_chip_data *top_irq_data; 342 struct regmap_irq_chip_data *gpio_irq_data; 343 }; 344 345 #endif /* _MFD_MAX77620_H_ */ 346