1 // SPDX-License-Identifier: GPL-2.0-only 2 /**************************************************************************** 3 * Driver for Solarflare network controllers and boards 4 * Copyright 2018 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 #include "net_driver.h" 12 #include <linux/module.h> 13 #include "efx_channels.h" 14 #include "efx.h" 15 #include "efx_common.h" 16 #include "tx_common.h" 17 #include "rx_common.h" 18 #include "nic.h" 19 #include "sriov.h" 20 21 /* This is the first interrupt mode to try out of: 22 * 0 => MSI-X 23 * 1 => MSI 24 * 2 => legacy 25 */ 26 static unsigned int interrupt_mode; 27 module_param(interrupt_mode, uint, 0444); 28 MODULE_PARM_DESC(interrupt_mode, 29 "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); 30 31 /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), 32 * i.e. the number of CPUs among which we may distribute simultaneous 33 * interrupt handling. 34 * 35 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. 36 * The default (0) means to assign an interrupt to each core. 37 */ 38 static unsigned int rss_cpus; 39 module_param(rss_cpus, uint, 0444); 40 MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); 41 42 static unsigned int irq_adapt_low_thresh = 8000; 43 module_param(irq_adapt_low_thresh, uint, 0644); 44 MODULE_PARM_DESC(irq_adapt_low_thresh, 45 "Threshold score for reducing IRQ moderation"); 46 47 static unsigned int irq_adapt_high_thresh = 16000; 48 module_param(irq_adapt_high_thresh, uint, 0644); 49 MODULE_PARM_DESC(irq_adapt_high_thresh, 50 "Threshold score for increasing IRQ moderation"); 51 52 /* This is the weight assigned to each of the (per-channel) virtual 53 * NAPI devices. 54 */ 55 static int napi_weight = 64; 56 57 /*************** 58 * Housekeeping 59 ***************/ 60 61 int efx_channel_dummy_op_int(struct efx_channel *channel) 62 { 63 return 0; 64 } 65 66 void efx_channel_dummy_op_void(struct efx_channel *channel) 67 { 68 } 69 70 static const struct efx_channel_type efx_default_channel_type = { 71 .pre_probe = efx_channel_dummy_op_int, 72 .post_remove = efx_channel_dummy_op_void, 73 .get_name = efx_get_channel_name, 74 .copy = efx_copy_channel, 75 .want_txqs = efx_default_channel_want_txqs, 76 .keep_eventq = false, 77 .want_pio = true, 78 }; 79 80 /************* 81 * INTERRUPTS 82 *************/ 83 84 static unsigned int efx_wanted_parallelism(struct efx_nic *efx) 85 { 86 cpumask_var_t thread_mask; 87 unsigned int count; 88 int cpu; 89 90 if (rss_cpus) { 91 count = rss_cpus; 92 } else { 93 if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) { 94 netif_warn(efx, probe, efx->net_dev, 95 "RSS disabled due to allocation failure\n"); 96 return 1; 97 } 98 99 count = 0; 100 for_each_online_cpu(cpu) { 101 if (!cpumask_test_cpu(cpu, thread_mask)) { 102 ++count; 103 cpumask_or(thread_mask, thread_mask, 104 topology_sibling_cpumask(cpu)); 105 } 106 } 107 108 free_cpumask_var(thread_mask); 109 } 110 111 if (count > EFX_MAX_RX_QUEUES) { 112 netif_cond_dbg(efx, probe, efx->net_dev, !rss_cpus, warn, 113 "Reducing number of rx queues from %u to %u.\n", 114 count, EFX_MAX_RX_QUEUES); 115 count = EFX_MAX_RX_QUEUES; 116 } 117 118 /* If RSS is requested for the PF *and* VFs then we can't write RSS 119 * table entries that are inaccessible to VFs 120 */ 121 #ifdef CONFIG_SFC_SRIOV 122 if (efx->type->sriov_wanted) { 123 if (efx->type->sriov_wanted(efx) && efx_vf_size(efx) > 1 && 124 count > efx_vf_size(efx)) { 125 netif_warn(efx, probe, efx->net_dev, 126 "Reducing number of RSS channels from %u to %u for " 127 "VF support. Increase vf-msix-limit to use more " 128 "channels on the PF.\n", 129 count, efx_vf_size(efx)); 130 count = efx_vf_size(efx); 131 } 132 } 133 #endif 134 135 return count; 136 } 137 138 static int efx_allocate_msix_channels(struct efx_nic *efx, 139 unsigned int max_channels, 140 unsigned int extra_channels, 141 unsigned int parallelism) 142 { 143 unsigned int n_channels = parallelism; 144 int vec_count; 145 int n_xdp_tx; 146 int n_xdp_ev; 147 148 if (efx_separate_tx_channels) 149 n_channels *= 2; 150 n_channels += extra_channels; 151 152 /* To allow XDP transmit to happen from arbitrary NAPI contexts 153 * we allocate a TX queue per CPU. We share event queues across 154 * multiple tx queues, assuming tx and ev queues are both 155 * maximum size. 156 */ 157 158 n_xdp_tx = num_possible_cpus(); 159 n_xdp_ev = DIV_ROUND_UP(n_xdp_tx, EFX_TXQ_TYPES); 160 161 vec_count = pci_msix_vec_count(efx->pci_dev); 162 if (vec_count < 0) 163 return vec_count; 164 165 max_channels = min_t(unsigned int, vec_count, max_channels); 166 167 /* Check resources. 168 * We need a channel per event queue, plus a VI per tx queue. 169 * This may be more pessimistic than it needs to be. 170 */ 171 if (n_channels + n_xdp_ev > max_channels) { 172 netif_err(efx, drv, efx->net_dev, 173 "Insufficient resources for %d XDP event queues (%d other channels, max %d)\n", 174 n_xdp_ev, n_channels, max_channels); 175 efx->n_xdp_channels = 0; 176 efx->xdp_tx_per_channel = 0; 177 efx->xdp_tx_queue_count = 0; 178 } else { 179 efx->n_xdp_channels = n_xdp_ev; 180 efx->xdp_tx_per_channel = EFX_TXQ_TYPES; 181 efx->xdp_tx_queue_count = n_xdp_tx; 182 n_channels += n_xdp_ev; 183 netif_dbg(efx, drv, efx->net_dev, 184 "Allocating %d TX and %d event queues for XDP\n", 185 n_xdp_tx, n_xdp_ev); 186 } 187 188 if (vec_count < n_channels) { 189 netif_err(efx, drv, efx->net_dev, 190 "WARNING: Insufficient MSI-X vectors available (%d < %u).\n", 191 vec_count, n_channels); 192 netif_err(efx, drv, efx->net_dev, 193 "WARNING: Performance may be reduced.\n"); 194 n_channels = vec_count; 195 } 196 197 n_channels = min(n_channels, max_channels); 198 199 efx->n_channels = n_channels; 200 201 /* Ignore XDP tx channels when creating rx channels. */ 202 n_channels -= efx->n_xdp_channels; 203 204 if (efx_separate_tx_channels) { 205 efx->n_tx_channels = 206 min(max(n_channels / 2, 1U), 207 efx->max_tx_channels); 208 efx->tx_channel_offset = 209 n_channels - efx->n_tx_channels; 210 efx->n_rx_channels = 211 max(n_channels - 212 efx->n_tx_channels, 1U); 213 } else { 214 efx->n_tx_channels = min(n_channels, efx->max_tx_channels); 215 efx->tx_channel_offset = 0; 216 efx->n_rx_channels = n_channels; 217 } 218 219 efx->n_rx_channels = min(efx->n_rx_channels, parallelism); 220 efx->n_tx_channels = min(efx->n_tx_channels, parallelism); 221 222 efx->xdp_channel_offset = n_channels; 223 224 netif_dbg(efx, drv, efx->net_dev, 225 "Allocating %u RX channels\n", 226 efx->n_rx_channels); 227 228 return efx->n_channels; 229 } 230 231 /* Probe the number and type of interrupts we are able to obtain, and 232 * the resulting numbers of channels and RX queues. 233 */ 234 int efx_probe_interrupts(struct efx_nic *efx) 235 { 236 unsigned int extra_channels = 0; 237 unsigned int rss_spread; 238 unsigned int i, j; 239 int rc; 240 241 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) 242 if (efx->extra_channel_type[i]) 243 ++extra_channels; 244 245 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { 246 unsigned int parallelism = efx_wanted_parallelism(efx); 247 struct msix_entry xentries[EFX_MAX_CHANNELS]; 248 unsigned int n_channels; 249 250 rc = efx_allocate_msix_channels(efx, efx->max_channels, 251 extra_channels, parallelism); 252 if (rc >= 0) { 253 n_channels = rc; 254 for (i = 0; i < n_channels; i++) 255 xentries[i].entry = i; 256 rc = pci_enable_msix_range(efx->pci_dev, xentries, 1, 257 n_channels); 258 } 259 if (rc < 0) { 260 /* Fall back to single channel MSI */ 261 netif_err(efx, drv, efx->net_dev, 262 "could not enable MSI-X\n"); 263 if (efx->type->min_interrupt_mode >= EFX_INT_MODE_MSI) 264 efx->interrupt_mode = EFX_INT_MODE_MSI; 265 else 266 return rc; 267 } else if (rc < n_channels) { 268 netif_err(efx, drv, efx->net_dev, 269 "WARNING: Insufficient MSI-X vectors" 270 " available (%d < %u).\n", rc, n_channels); 271 netif_err(efx, drv, efx->net_dev, 272 "WARNING: Performance may be reduced.\n"); 273 n_channels = rc; 274 } 275 276 if (rc > 0) { 277 for (i = 0; i < efx->n_channels; i++) 278 efx_get_channel(efx, i)->irq = 279 xentries[i].vector; 280 } 281 } 282 283 /* Try single interrupt MSI */ 284 if (efx->interrupt_mode == EFX_INT_MODE_MSI) { 285 efx->n_channels = 1; 286 efx->n_rx_channels = 1; 287 efx->n_tx_channels = 1; 288 efx->n_xdp_channels = 0; 289 efx->xdp_channel_offset = efx->n_channels; 290 rc = pci_enable_msi(efx->pci_dev); 291 if (rc == 0) { 292 efx_get_channel(efx, 0)->irq = efx->pci_dev->irq; 293 } else { 294 netif_err(efx, drv, efx->net_dev, 295 "could not enable MSI\n"); 296 if (efx->type->min_interrupt_mode >= EFX_INT_MODE_LEGACY) 297 efx->interrupt_mode = EFX_INT_MODE_LEGACY; 298 else 299 return rc; 300 } 301 } 302 303 /* Assume legacy interrupts */ 304 if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { 305 efx->n_channels = 1 + (efx_separate_tx_channels ? 1 : 0); 306 efx->n_rx_channels = 1; 307 efx->n_tx_channels = 1; 308 efx->n_xdp_channels = 0; 309 efx->xdp_channel_offset = efx->n_channels; 310 efx->legacy_irq = efx->pci_dev->irq; 311 } 312 313 /* Assign extra channels if possible, before XDP channels */ 314 efx->n_extra_tx_channels = 0; 315 j = efx->xdp_channel_offset; 316 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) { 317 if (!efx->extra_channel_type[i]) 318 continue; 319 if (j <= efx->tx_channel_offset + efx->n_tx_channels) { 320 efx->extra_channel_type[i]->handle_no_channel(efx); 321 } else { 322 --j; 323 efx_get_channel(efx, j)->type = 324 efx->extra_channel_type[i]; 325 if (efx_channel_has_tx_queues(efx_get_channel(efx, j))) 326 efx->n_extra_tx_channels++; 327 } 328 } 329 330 rss_spread = efx->n_rx_channels; 331 /* RSS might be usable on VFs even if it is disabled on the PF */ 332 #ifdef CONFIG_SFC_SRIOV 333 if (efx->type->sriov_wanted) { 334 efx->rss_spread = ((rss_spread > 1 || 335 !efx->type->sriov_wanted(efx)) ? 336 rss_spread : efx_vf_size(efx)); 337 return 0; 338 } 339 #endif 340 efx->rss_spread = rss_spread; 341 342 return 0; 343 } 344 345 #if defined(CONFIG_SMP) 346 void efx_set_interrupt_affinity(struct efx_nic *efx) 347 { 348 struct efx_channel *channel; 349 unsigned int cpu; 350 351 efx_for_each_channel(channel, efx) { 352 cpu = cpumask_local_spread(channel->channel, 353 pcibus_to_node(efx->pci_dev->bus)); 354 irq_set_affinity_hint(channel->irq, cpumask_of(cpu)); 355 } 356 } 357 358 void efx_clear_interrupt_affinity(struct efx_nic *efx) 359 { 360 struct efx_channel *channel; 361 362 efx_for_each_channel(channel, efx) 363 irq_set_affinity_hint(channel->irq, NULL); 364 } 365 #else 366 void 367 efx_set_interrupt_affinity(struct efx_nic *efx __attribute__ ((unused))) 368 { 369 } 370 371 void 372 efx_clear_interrupt_affinity(struct efx_nic *efx __attribute__ ((unused))) 373 { 374 } 375 #endif /* CONFIG_SMP */ 376 377 void efx_remove_interrupts(struct efx_nic *efx) 378 { 379 struct efx_channel *channel; 380 381 /* Remove MSI/MSI-X interrupts */ 382 efx_for_each_channel(channel, efx) 383 channel->irq = 0; 384 pci_disable_msi(efx->pci_dev); 385 pci_disable_msix(efx->pci_dev); 386 387 /* Remove legacy interrupt */ 388 efx->legacy_irq = 0; 389 } 390 391 /*************** 392 * EVENT QUEUES 393 ***************/ 394 395 /* Create event queue 396 * Event queue memory allocations are done only once. If the channel 397 * is reset, the memory buffer will be reused; this guards against 398 * errors during channel reset and also simplifies interrupt handling. 399 */ 400 int efx_probe_eventq(struct efx_channel *channel) 401 { 402 struct efx_nic *efx = channel->efx; 403 unsigned long entries; 404 405 netif_dbg(efx, probe, efx->net_dev, 406 "chan %d create event queue\n", channel->channel); 407 408 /* Build an event queue with room for one event per tx and rx buffer, 409 * plus some extra for link state events and MCDI completions. 410 */ 411 entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128); 412 EFX_WARN_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE); 413 channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1; 414 415 return efx_nic_probe_eventq(channel); 416 } 417 418 /* Prepare channel's event queue */ 419 int efx_init_eventq(struct efx_channel *channel) 420 { 421 struct efx_nic *efx = channel->efx; 422 int rc; 423 424 EFX_WARN_ON_PARANOID(channel->eventq_init); 425 426 netif_dbg(efx, drv, efx->net_dev, 427 "chan %d init event queue\n", channel->channel); 428 429 rc = efx_nic_init_eventq(channel); 430 if (rc == 0) { 431 efx->type->push_irq_moderation(channel); 432 channel->eventq_read_ptr = 0; 433 channel->eventq_init = true; 434 } 435 return rc; 436 } 437 438 /* Enable event queue processing and NAPI */ 439 void efx_start_eventq(struct efx_channel *channel) 440 { 441 netif_dbg(channel->efx, ifup, channel->efx->net_dev, 442 "chan %d start event queue\n", channel->channel); 443 444 /* Make sure the NAPI handler sees the enabled flag set */ 445 channel->enabled = true; 446 smp_wmb(); 447 448 napi_enable(&channel->napi_str); 449 efx_nic_eventq_read_ack(channel); 450 } 451 452 /* Disable event queue processing and NAPI */ 453 void efx_stop_eventq(struct efx_channel *channel) 454 { 455 if (!channel->enabled) 456 return; 457 458 napi_disable(&channel->napi_str); 459 channel->enabled = false; 460 } 461 462 void efx_fini_eventq(struct efx_channel *channel) 463 { 464 if (!channel->eventq_init) 465 return; 466 467 netif_dbg(channel->efx, drv, channel->efx->net_dev, 468 "chan %d fini event queue\n", channel->channel); 469 470 efx_nic_fini_eventq(channel); 471 channel->eventq_init = false; 472 } 473 474 void efx_remove_eventq(struct efx_channel *channel) 475 { 476 netif_dbg(channel->efx, drv, channel->efx->net_dev, 477 "chan %d remove event queue\n", channel->channel); 478 479 efx_nic_remove_eventq(channel); 480 } 481 482 /************************************************************************** 483 * 484 * Channel handling 485 * 486 *************************************************************************/ 487 488 #ifdef CONFIG_RFS_ACCEL 489 static void efx_filter_rfs_expire(struct work_struct *data) 490 { 491 struct delayed_work *dwork = to_delayed_work(data); 492 struct efx_channel *channel; 493 unsigned int time, quota; 494 495 channel = container_of(dwork, struct efx_channel, filter_work); 496 time = jiffies - channel->rfs_last_expiry; 497 quota = channel->rfs_filter_count * time / (30 * HZ); 498 if (quota >= 20 && __efx_filter_rfs_expire(channel, min(channel->rfs_filter_count, quota))) 499 channel->rfs_last_expiry += time; 500 /* Ensure we do more work eventually even if NAPI poll is not happening */ 501 schedule_delayed_work(dwork, 30 * HZ); 502 } 503 #endif 504 505 /* Allocate and initialise a channel structure. */ 506 struct efx_channel * 507 efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel) 508 { 509 struct efx_rx_queue *rx_queue; 510 struct efx_tx_queue *tx_queue; 511 struct efx_channel *channel; 512 int j; 513 514 channel = kzalloc(sizeof(*channel), GFP_KERNEL); 515 if (!channel) 516 return NULL; 517 518 channel->efx = efx; 519 channel->channel = i; 520 channel->type = &efx_default_channel_type; 521 522 for (j = 0; j < EFX_TXQ_TYPES; j++) { 523 tx_queue = &channel->tx_queue[j]; 524 tx_queue->efx = efx; 525 tx_queue->queue = i * EFX_TXQ_TYPES + j; 526 tx_queue->channel = channel; 527 } 528 529 #ifdef CONFIG_RFS_ACCEL 530 INIT_DELAYED_WORK(&channel->filter_work, efx_filter_rfs_expire); 531 #endif 532 533 rx_queue = &channel->rx_queue; 534 rx_queue->efx = efx; 535 timer_setup(&rx_queue->slow_fill, efx_rx_slow_fill, 0); 536 537 return channel; 538 } 539 540 int efx_init_channels(struct efx_nic *efx) 541 { 542 unsigned int i; 543 544 for (i = 0; i < EFX_MAX_CHANNELS; i++) { 545 efx->channel[i] = efx_alloc_channel(efx, i, NULL); 546 if (!efx->channel[i]) 547 return -ENOMEM; 548 efx->msi_context[i].efx = efx; 549 efx->msi_context[i].index = i; 550 } 551 552 /* Higher numbered interrupt modes are less capable! */ 553 if (WARN_ON_ONCE(efx->type->max_interrupt_mode > 554 efx->type->min_interrupt_mode)) { 555 return -EIO; 556 } 557 efx->interrupt_mode = max(efx->type->max_interrupt_mode, 558 interrupt_mode); 559 efx->interrupt_mode = min(efx->type->min_interrupt_mode, 560 interrupt_mode); 561 562 return 0; 563 } 564 565 void efx_fini_channels(struct efx_nic *efx) 566 { 567 unsigned int i; 568 569 for (i = 0; i < EFX_MAX_CHANNELS; i++) 570 if (efx->channel[i]) { 571 kfree(efx->channel[i]); 572 efx->channel[i] = NULL; 573 } 574 } 575 576 /* Allocate and initialise a channel structure, copying parameters 577 * (but not resources) from an old channel structure. 578 */ 579 struct efx_channel *efx_copy_channel(const struct efx_channel *old_channel) 580 { 581 struct efx_rx_queue *rx_queue; 582 struct efx_tx_queue *tx_queue; 583 struct efx_channel *channel; 584 int j; 585 586 channel = kmalloc(sizeof(*channel), GFP_KERNEL); 587 if (!channel) 588 return NULL; 589 590 *channel = *old_channel; 591 592 channel->napi_dev = NULL; 593 INIT_HLIST_NODE(&channel->napi_str.napi_hash_node); 594 channel->napi_str.napi_id = 0; 595 channel->napi_str.state = 0; 596 memset(&channel->eventq, 0, sizeof(channel->eventq)); 597 598 for (j = 0; j < EFX_TXQ_TYPES; j++) { 599 tx_queue = &channel->tx_queue[j]; 600 if (tx_queue->channel) 601 tx_queue->channel = channel; 602 tx_queue->buffer = NULL; 603 tx_queue->cb_page = NULL; 604 memset(&tx_queue->txd, 0, sizeof(tx_queue->txd)); 605 } 606 607 rx_queue = &channel->rx_queue; 608 rx_queue->buffer = NULL; 609 memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd)); 610 timer_setup(&rx_queue->slow_fill, efx_rx_slow_fill, 0); 611 #ifdef CONFIG_RFS_ACCEL 612 INIT_DELAYED_WORK(&channel->filter_work, efx_filter_rfs_expire); 613 #endif 614 615 return channel; 616 } 617 618 static int efx_probe_channel(struct efx_channel *channel) 619 { 620 struct efx_tx_queue *tx_queue; 621 struct efx_rx_queue *rx_queue; 622 int rc; 623 624 netif_dbg(channel->efx, probe, channel->efx->net_dev, 625 "creating channel %d\n", channel->channel); 626 627 rc = channel->type->pre_probe(channel); 628 if (rc) 629 goto fail; 630 631 rc = efx_probe_eventq(channel); 632 if (rc) 633 goto fail; 634 635 efx_for_each_channel_tx_queue(tx_queue, channel) { 636 rc = efx_probe_tx_queue(tx_queue); 637 if (rc) 638 goto fail; 639 } 640 641 efx_for_each_channel_rx_queue(rx_queue, channel) { 642 rc = efx_probe_rx_queue(rx_queue); 643 if (rc) 644 goto fail; 645 } 646 647 channel->rx_list = NULL; 648 649 return 0; 650 651 fail: 652 efx_remove_channel(channel); 653 return rc; 654 } 655 656 void efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len) 657 { 658 struct efx_nic *efx = channel->efx; 659 const char *type; 660 int number; 661 662 number = channel->channel; 663 664 if (number >= efx->xdp_channel_offset && 665 !WARN_ON_ONCE(!efx->n_xdp_channels)) { 666 type = "-xdp"; 667 number -= efx->xdp_channel_offset; 668 } else if (efx->tx_channel_offset == 0) { 669 type = ""; 670 } else if (number < efx->tx_channel_offset) { 671 type = "-rx"; 672 } else { 673 type = "-tx"; 674 number -= efx->tx_channel_offset; 675 } 676 snprintf(buf, len, "%s%s-%d", efx->name, type, number); 677 } 678 679 void efx_set_channel_names(struct efx_nic *efx) 680 { 681 struct efx_channel *channel; 682 683 efx_for_each_channel(channel, efx) 684 channel->type->get_name(channel, 685 efx->msi_context[channel->channel].name, 686 sizeof(efx->msi_context[0].name)); 687 } 688 689 int efx_probe_channels(struct efx_nic *efx) 690 { 691 struct efx_channel *channel; 692 int rc; 693 694 /* Restart special buffer allocation */ 695 efx->next_buffer_table = 0; 696 697 /* Probe channels in reverse, so that any 'extra' channels 698 * use the start of the buffer table. This allows the traffic 699 * channels to be resized without moving them or wasting the 700 * entries before them. 701 */ 702 efx_for_each_channel_rev(channel, efx) { 703 rc = efx_probe_channel(channel); 704 if (rc) { 705 netif_err(efx, probe, efx->net_dev, 706 "failed to create channel %d\n", 707 channel->channel); 708 goto fail; 709 } 710 } 711 efx_set_channel_names(efx); 712 713 return 0; 714 715 fail: 716 efx_remove_channels(efx); 717 return rc; 718 } 719 720 void efx_remove_channel(struct efx_channel *channel) 721 { 722 struct efx_tx_queue *tx_queue; 723 struct efx_rx_queue *rx_queue; 724 725 netif_dbg(channel->efx, drv, channel->efx->net_dev, 726 "destroy chan %d\n", channel->channel); 727 728 efx_for_each_channel_rx_queue(rx_queue, channel) 729 efx_remove_rx_queue(rx_queue); 730 efx_for_each_possible_channel_tx_queue(tx_queue, channel) 731 efx_remove_tx_queue(tx_queue); 732 efx_remove_eventq(channel); 733 channel->type->post_remove(channel); 734 } 735 736 void efx_remove_channels(struct efx_nic *efx) 737 { 738 struct efx_channel *channel; 739 740 efx_for_each_channel(channel, efx) 741 efx_remove_channel(channel); 742 743 kfree(efx->xdp_tx_queues); 744 } 745 746 int efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries) 747 { 748 struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel; 749 unsigned int i, next_buffer_table = 0; 750 u32 old_rxq_entries, old_txq_entries; 751 int rc, rc2; 752 753 rc = efx_check_disabled(efx); 754 if (rc) 755 return rc; 756 757 /* Not all channels should be reallocated. We must avoid 758 * reallocating their buffer table entries. 759 */ 760 efx_for_each_channel(channel, efx) { 761 struct efx_rx_queue *rx_queue; 762 struct efx_tx_queue *tx_queue; 763 764 if (channel->type->copy) 765 continue; 766 next_buffer_table = max(next_buffer_table, 767 channel->eventq.index + 768 channel->eventq.entries); 769 efx_for_each_channel_rx_queue(rx_queue, channel) 770 next_buffer_table = max(next_buffer_table, 771 rx_queue->rxd.index + 772 rx_queue->rxd.entries); 773 efx_for_each_channel_tx_queue(tx_queue, channel) 774 next_buffer_table = max(next_buffer_table, 775 tx_queue->txd.index + 776 tx_queue->txd.entries); 777 } 778 779 efx_device_detach_sync(efx); 780 efx_stop_all(efx); 781 efx_soft_disable_interrupts(efx); 782 783 /* Clone channels (where possible) */ 784 memset(other_channel, 0, sizeof(other_channel)); 785 for (i = 0; i < efx->n_channels; i++) { 786 channel = efx->channel[i]; 787 if (channel->type->copy) 788 channel = channel->type->copy(channel); 789 if (!channel) { 790 rc = -ENOMEM; 791 goto out; 792 } 793 other_channel[i] = channel; 794 } 795 796 /* Swap entry counts and channel pointers */ 797 old_rxq_entries = efx->rxq_entries; 798 old_txq_entries = efx->txq_entries; 799 efx->rxq_entries = rxq_entries; 800 efx->txq_entries = txq_entries; 801 for (i = 0; i < efx->n_channels; i++) { 802 channel = efx->channel[i]; 803 efx->channel[i] = other_channel[i]; 804 other_channel[i] = channel; 805 } 806 807 /* Restart buffer table allocation */ 808 efx->next_buffer_table = next_buffer_table; 809 810 for (i = 0; i < efx->n_channels; i++) { 811 channel = efx->channel[i]; 812 if (!channel->type->copy) 813 continue; 814 rc = efx_probe_channel(channel); 815 if (rc) 816 goto rollback; 817 efx_init_napi_channel(efx->channel[i]); 818 } 819 820 out: 821 /* Destroy unused channel structures */ 822 for (i = 0; i < efx->n_channels; i++) { 823 channel = other_channel[i]; 824 if (channel && channel->type->copy) { 825 efx_fini_napi_channel(channel); 826 efx_remove_channel(channel); 827 kfree(channel); 828 } 829 } 830 831 rc2 = efx_soft_enable_interrupts(efx); 832 if (rc2) { 833 rc = rc ? rc : rc2; 834 netif_err(efx, drv, efx->net_dev, 835 "unable to restart interrupts on channel reallocation\n"); 836 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 837 } else { 838 efx_start_all(efx); 839 efx_device_attach_if_not_resetting(efx); 840 } 841 return rc; 842 843 rollback: 844 /* Swap back */ 845 efx->rxq_entries = old_rxq_entries; 846 efx->txq_entries = old_txq_entries; 847 for (i = 0; i < efx->n_channels; i++) { 848 channel = efx->channel[i]; 849 efx->channel[i] = other_channel[i]; 850 other_channel[i] = channel; 851 } 852 goto out; 853 } 854 855 int efx_set_channels(struct efx_nic *efx) 856 { 857 struct efx_channel *channel; 858 struct efx_tx_queue *tx_queue; 859 int xdp_queue_number; 860 861 efx->tx_channel_offset = 862 efx_separate_tx_channels ? 863 efx->n_channels - efx->n_tx_channels : 0; 864 865 if (efx->xdp_tx_queue_count) { 866 EFX_WARN_ON_PARANOID(efx->xdp_tx_queues); 867 868 /* Allocate array for XDP TX queue lookup. */ 869 efx->xdp_tx_queues = kcalloc(efx->xdp_tx_queue_count, 870 sizeof(*efx->xdp_tx_queues), 871 GFP_KERNEL); 872 if (!efx->xdp_tx_queues) 873 return -ENOMEM; 874 } 875 876 /* We need to mark which channels really have RX and TX 877 * queues, and adjust the TX queue numbers if we have separate 878 * RX-only and TX-only channels. 879 */ 880 xdp_queue_number = 0; 881 efx_for_each_channel(channel, efx) { 882 if (channel->channel < efx->n_rx_channels) 883 channel->rx_queue.core_index = channel->channel; 884 else 885 channel->rx_queue.core_index = -1; 886 887 efx_for_each_channel_tx_queue(tx_queue, channel) { 888 tx_queue->queue -= (efx->tx_channel_offset * 889 EFX_TXQ_TYPES); 890 891 if (efx_channel_is_xdp_tx(channel) && 892 xdp_queue_number < efx->xdp_tx_queue_count) { 893 efx->xdp_tx_queues[xdp_queue_number] = tx_queue; 894 xdp_queue_number++; 895 } 896 } 897 } 898 return 0; 899 } 900 901 bool efx_default_channel_want_txqs(struct efx_channel *channel) 902 { 903 return channel->channel - channel->efx->tx_channel_offset < 904 channel->efx->n_tx_channels; 905 } 906 907 /************* 908 * START/STOP 909 *************/ 910 911 int efx_soft_enable_interrupts(struct efx_nic *efx) 912 { 913 struct efx_channel *channel, *end_channel; 914 int rc; 915 916 BUG_ON(efx->state == STATE_DISABLED); 917 918 efx->irq_soft_enabled = true; 919 smp_wmb(); 920 921 efx_for_each_channel(channel, efx) { 922 if (!channel->type->keep_eventq) { 923 rc = efx_init_eventq(channel); 924 if (rc) 925 goto fail; 926 } 927 efx_start_eventq(channel); 928 } 929 930 efx_mcdi_mode_event(efx); 931 932 return 0; 933 fail: 934 end_channel = channel; 935 efx_for_each_channel(channel, efx) { 936 if (channel == end_channel) 937 break; 938 efx_stop_eventq(channel); 939 if (!channel->type->keep_eventq) 940 efx_fini_eventq(channel); 941 } 942 943 return rc; 944 } 945 946 void efx_soft_disable_interrupts(struct efx_nic *efx) 947 { 948 struct efx_channel *channel; 949 950 if (efx->state == STATE_DISABLED) 951 return; 952 953 efx_mcdi_mode_poll(efx); 954 955 efx->irq_soft_enabled = false; 956 smp_wmb(); 957 958 if (efx->legacy_irq) 959 synchronize_irq(efx->legacy_irq); 960 961 efx_for_each_channel(channel, efx) { 962 if (channel->irq) 963 synchronize_irq(channel->irq); 964 965 efx_stop_eventq(channel); 966 if (!channel->type->keep_eventq) 967 efx_fini_eventq(channel); 968 } 969 970 /* Flush the asynchronous MCDI request queue */ 971 efx_mcdi_flush_async(efx); 972 } 973 974 int efx_enable_interrupts(struct efx_nic *efx) 975 { 976 struct efx_channel *channel, *end_channel; 977 int rc; 978 979 /* TODO: Is this really a bug? */ 980 BUG_ON(efx->state == STATE_DISABLED); 981 982 if (efx->eeh_disabled_legacy_irq) { 983 enable_irq(efx->legacy_irq); 984 efx->eeh_disabled_legacy_irq = false; 985 } 986 987 efx->type->irq_enable_master(efx); 988 989 efx_for_each_channel(channel, efx) { 990 if (channel->type->keep_eventq) { 991 rc = efx_init_eventq(channel); 992 if (rc) 993 goto fail; 994 } 995 } 996 997 rc = efx_soft_enable_interrupts(efx); 998 if (rc) 999 goto fail; 1000 1001 return 0; 1002 1003 fail: 1004 end_channel = channel; 1005 efx_for_each_channel(channel, efx) { 1006 if (channel == end_channel) 1007 break; 1008 if (channel->type->keep_eventq) 1009 efx_fini_eventq(channel); 1010 } 1011 1012 efx->type->irq_disable_non_ev(efx); 1013 1014 return rc; 1015 } 1016 1017 void efx_disable_interrupts(struct efx_nic *efx) 1018 { 1019 struct efx_channel *channel; 1020 1021 efx_soft_disable_interrupts(efx); 1022 1023 efx_for_each_channel(channel, efx) { 1024 if (channel->type->keep_eventq) 1025 efx_fini_eventq(channel); 1026 } 1027 1028 efx->type->irq_disable_non_ev(efx); 1029 } 1030 1031 void efx_start_channels(struct efx_nic *efx) 1032 { 1033 struct efx_tx_queue *tx_queue; 1034 struct efx_rx_queue *rx_queue; 1035 struct efx_channel *channel; 1036 1037 efx_for_each_channel(channel, efx) { 1038 efx_for_each_channel_tx_queue(tx_queue, channel) { 1039 efx_init_tx_queue(tx_queue); 1040 atomic_inc(&efx->active_queues); 1041 } 1042 1043 efx_for_each_channel_rx_queue(rx_queue, channel) { 1044 efx_init_rx_queue(rx_queue); 1045 atomic_inc(&efx->active_queues); 1046 efx_stop_eventq(channel); 1047 efx_fast_push_rx_descriptors(rx_queue, false); 1048 efx_start_eventq(channel); 1049 } 1050 1051 WARN_ON(channel->rx_pkt_n_frags); 1052 } 1053 } 1054 1055 void efx_stop_channels(struct efx_nic *efx) 1056 { 1057 struct efx_tx_queue *tx_queue; 1058 struct efx_rx_queue *rx_queue; 1059 struct efx_channel *channel; 1060 int rc = 0; 1061 1062 /* Stop RX refill */ 1063 efx_for_each_channel(channel, efx) { 1064 efx_for_each_channel_rx_queue(rx_queue, channel) 1065 rx_queue->refill_enabled = false; 1066 } 1067 1068 efx_for_each_channel(channel, efx) { 1069 /* RX packet processing is pipelined, so wait for the 1070 * NAPI handler to complete. At least event queue 0 1071 * might be kept active by non-data events, so don't 1072 * use napi_synchronize() but actually disable NAPI 1073 * temporarily. 1074 */ 1075 if (efx_channel_has_rx_queue(channel)) { 1076 efx_stop_eventq(channel); 1077 efx_start_eventq(channel); 1078 } 1079 } 1080 1081 if (efx->type->fini_dmaq) 1082 rc = efx->type->fini_dmaq(efx); 1083 1084 if (rc) { 1085 netif_err(efx, drv, efx->net_dev, "failed to flush queues\n"); 1086 } else { 1087 netif_dbg(efx, drv, efx->net_dev, 1088 "successfully flushed all queues\n"); 1089 } 1090 1091 efx_for_each_channel(channel, efx) { 1092 efx_for_each_channel_rx_queue(rx_queue, channel) 1093 efx_fini_rx_queue(rx_queue); 1094 efx_for_each_possible_channel_tx_queue(tx_queue, channel) 1095 efx_fini_tx_queue(tx_queue); 1096 } 1097 } 1098 1099 /************************************************************************** 1100 * 1101 * NAPI interface 1102 * 1103 *************************************************************************/ 1104 1105 /* Process channel's event queue 1106 * 1107 * This function is responsible for processing the event queue of a 1108 * single channel. The caller must guarantee that this function will 1109 * never be concurrently called more than once on the same channel, 1110 * though different channels may be being processed concurrently. 1111 */ 1112 static int efx_process_channel(struct efx_channel *channel, int budget) 1113 { 1114 struct efx_tx_queue *tx_queue; 1115 struct list_head rx_list; 1116 int spent; 1117 1118 if (unlikely(!channel->enabled)) 1119 return 0; 1120 1121 /* Prepare the batch receive list */ 1122 EFX_WARN_ON_PARANOID(channel->rx_list != NULL); 1123 INIT_LIST_HEAD(&rx_list); 1124 channel->rx_list = &rx_list; 1125 1126 efx_for_each_channel_tx_queue(tx_queue, channel) { 1127 tx_queue->pkts_compl = 0; 1128 tx_queue->bytes_compl = 0; 1129 } 1130 1131 spent = efx_nic_process_eventq(channel, budget); 1132 if (spent && efx_channel_has_rx_queue(channel)) { 1133 struct efx_rx_queue *rx_queue = 1134 efx_channel_get_rx_queue(channel); 1135 1136 efx_rx_flush_packet(channel); 1137 efx_fast_push_rx_descriptors(rx_queue, true); 1138 } 1139 1140 /* Update BQL */ 1141 efx_for_each_channel_tx_queue(tx_queue, channel) { 1142 if (tx_queue->bytes_compl) { 1143 netdev_tx_completed_queue(tx_queue->core_txq, 1144 tx_queue->pkts_compl, 1145 tx_queue->bytes_compl); 1146 } 1147 } 1148 1149 /* Receive any packets we queued up */ 1150 netif_receive_skb_list(channel->rx_list); 1151 channel->rx_list = NULL; 1152 1153 return spent; 1154 } 1155 1156 static void efx_update_irq_mod(struct efx_nic *efx, struct efx_channel *channel) 1157 { 1158 int step = efx->irq_mod_step_us; 1159 1160 if (channel->irq_mod_score < irq_adapt_low_thresh) { 1161 if (channel->irq_moderation_us > step) { 1162 channel->irq_moderation_us -= step; 1163 efx->type->push_irq_moderation(channel); 1164 } 1165 } else if (channel->irq_mod_score > irq_adapt_high_thresh) { 1166 if (channel->irq_moderation_us < 1167 efx->irq_rx_moderation_us) { 1168 channel->irq_moderation_us += step; 1169 efx->type->push_irq_moderation(channel); 1170 } 1171 } 1172 1173 channel->irq_count = 0; 1174 channel->irq_mod_score = 0; 1175 } 1176 1177 /* NAPI poll handler 1178 * 1179 * NAPI guarantees serialisation of polls of the same device, which 1180 * provides the guarantee required by efx_process_channel(). 1181 */ 1182 static int efx_poll(struct napi_struct *napi, int budget) 1183 { 1184 struct efx_channel *channel = 1185 container_of(napi, struct efx_channel, napi_str); 1186 struct efx_nic *efx = channel->efx; 1187 #ifdef CONFIG_RFS_ACCEL 1188 unsigned int time; 1189 #endif 1190 int spent; 1191 1192 netif_vdbg(efx, intr, efx->net_dev, 1193 "channel %d NAPI poll executing on CPU %d\n", 1194 channel->channel, raw_smp_processor_id()); 1195 1196 spent = efx_process_channel(channel, budget); 1197 1198 xdp_do_flush_map(); 1199 1200 if (spent < budget) { 1201 if (efx_channel_has_rx_queue(channel) && 1202 efx->irq_rx_adaptive && 1203 unlikely(++channel->irq_count == 1000)) { 1204 efx_update_irq_mod(efx, channel); 1205 } 1206 1207 #ifdef CONFIG_RFS_ACCEL 1208 /* Perhaps expire some ARFS filters */ 1209 time = jiffies - channel->rfs_last_expiry; 1210 /* Would our quota be >= 20? */ 1211 if (channel->rfs_filter_count * time >= 600 * HZ) 1212 mod_delayed_work(system_wq, &channel->filter_work, 0); 1213 #endif 1214 1215 /* There is no race here; although napi_disable() will 1216 * only wait for napi_complete(), this isn't a problem 1217 * since efx_nic_eventq_read_ack() will have no effect if 1218 * interrupts have already been disabled. 1219 */ 1220 if (napi_complete_done(napi, spent)) 1221 efx_nic_eventq_read_ack(channel); 1222 } 1223 1224 return spent; 1225 } 1226 1227 void efx_init_napi_channel(struct efx_channel *channel) 1228 { 1229 struct efx_nic *efx = channel->efx; 1230 1231 channel->napi_dev = efx->net_dev; 1232 netif_napi_add(channel->napi_dev, &channel->napi_str, 1233 efx_poll, napi_weight); 1234 } 1235 1236 void efx_init_napi(struct efx_nic *efx) 1237 { 1238 struct efx_channel *channel; 1239 1240 efx_for_each_channel(channel, efx) 1241 efx_init_napi_channel(channel); 1242 } 1243 1244 void efx_fini_napi_channel(struct efx_channel *channel) 1245 { 1246 if (channel->napi_dev) 1247 netif_napi_del(&channel->napi_str); 1248 1249 channel->napi_dev = NULL; 1250 } 1251 1252 void efx_fini_napi(struct efx_nic *efx) 1253 { 1254 struct efx_channel *channel; 1255 1256 efx_for_each_channel(channel, efx) 1257 efx_fini_napi_channel(channel); 1258 } 1259