1 /* 2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/module.h> 35 #include <linux/init.h> 36 #include <linux/slab.h> 37 #include <linux/errno.h> 38 #include <linux/netdevice.h> 39 #include <linux/inetdevice.h> 40 #include <linux/rtnetlink.h> 41 #include <linux/if_vlan.h> 42 #include <linux/sched/mm.h> 43 #include <linux/sched/task.h> 44 45 #include <net/ipv6.h> 46 #include <net/addrconf.h> 47 #include <net/devlink.h> 48 49 #include <rdma/ib_smi.h> 50 #include <rdma/ib_user_verbs.h> 51 #include <rdma/ib_addr.h> 52 #include <rdma/ib_cache.h> 53 54 #include <net/bonding.h> 55 56 #include <linux/mlx4/driver.h> 57 #include <linux/mlx4/cmd.h> 58 #include <linux/mlx4/qp.h> 59 60 #include "mlx4_ib.h" 61 #include <rdma/mlx4-abi.h> 62 63 #define DRV_NAME MLX4_IB_DRV_NAME 64 #define DRV_VERSION "4.0-0" 65 66 #define MLX4_IB_FLOW_MAX_PRIO 0xFFF 67 #define MLX4_IB_FLOW_QPN_MASK 0xFFFFFF 68 #define MLX4_IB_CARD_REV_A0 0xA0 69 70 MODULE_AUTHOR("Roland Dreier"); 71 MODULE_DESCRIPTION("Mellanox ConnectX HCA InfiniBand driver"); 72 MODULE_LICENSE("Dual BSD/GPL"); 73 74 int mlx4_ib_sm_guid_assign = 0; 75 module_param_named(sm_guid_assign, mlx4_ib_sm_guid_assign, int, 0444); 76 MODULE_PARM_DESC(sm_guid_assign, "Enable SM alias_GUID assignment if sm_guid_assign > 0 (Default: 0)"); 77 78 static const char mlx4_ib_version[] = 79 DRV_NAME ": Mellanox ConnectX InfiniBand driver v" 80 DRV_VERSION "\n"; 81 82 static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init); 83 static enum rdma_link_layer mlx4_ib_port_link_layer(struct ib_device *device, 84 u8 port_num); 85 86 static struct workqueue_struct *wq; 87 88 static void init_query_mad(struct ib_smp *mad) 89 { 90 mad->base_version = 1; 91 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 92 mad->class_version = 1; 93 mad->method = IB_MGMT_METHOD_GET; 94 } 95 96 static int check_flow_steering_support(struct mlx4_dev *dev) 97 { 98 int eth_num_ports = 0; 99 int ib_num_ports = 0; 100 101 int dmfs = dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED; 102 103 if (dmfs) { 104 int i; 105 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) 106 eth_num_ports++; 107 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 108 ib_num_ports++; 109 dmfs &= (!ib_num_ports || 110 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB)) && 111 (!eth_num_ports || 112 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)); 113 if (ib_num_ports && mlx4_is_mfunc(dev)) { 114 pr_warn("Device managed flow steering is unavailable for IB port in multifunction env.\n"); 115 dmfs = 0; 116 } 117 } 118 return dmfs; 119 } 120 121 static int num_ib_ports(struct mlx4_dev *dev) 122 { 123 int ib_ports = 0; 124 int i; 125 126 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 127 ib_ports++; 128 129 return ib_ports; 130 } 131 132 static struct net_device *mlx4_ib_get_netdev(struct ib_device *device, u8 port_num) 133 { 134 struct mlx4_ib_dev *ibdev = to_mdev(device); 135 struct net_device *dev; 136 137 rcu_read_lock(); 138 dev = mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port_num); 139 140 if (dev) { 141 if (mlx4_is_bonded(ibdev->dev)) { 142 struct net_device *upper = NULL; 143 144 upper = netdev_master_upper_dev_get_rcu(dev); 145 if (upper) { 146 struct net_device *active; 147 148 active = bond_option_active_slave_get_rcu(netdev_priv(upper)); 149 if (active) 150 dev = active; 151 } 152 } 153 } 154 if (dev) 155 dev_hold(dev); 156 157 rcu_read_unlock(); 158 return dev; 159 } 160 161 static int mlx4_ib_update_gids_v1(struct gid_entry *gids, 162 struct mlx4_ib_dev *ibdev, 163 u8 port_num) 164 { 165 struct mlx4_cmd_mailbox *mailbox; 166 int err; 167 struct mlx4_dev *dev = ibdev->dev; 168 int i; 169 union ib_gid *gid_tbl; 170 171 mailbox = mlx4_alloc_cmd_mailbox(dev); 172 if (IS_ERR(mailbox)) 173 return -ENOMEM; 174 175 gid_tbl = mailbox->buf; 176 177 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) 178 memcpy(&gid_tbl[i], &gids[i].gid, sizeof(union ib_gid)); 179 180 err = mlx4_cmd(dev, mailbox->dma, 181 MLX4_SET_PORT_GID_TABLE << 8 | port_num, 182 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 183 MLX4_CMD_WRAPPED); 184 if (mlx4_is_bonded(dev)) 185 err += mlx4_cmd(dev, mailbox->dma, 186 MLX4_SET_PORT_GID_TABLE << 8 | 2, 187 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 188 MLX4_CMD_WRAPPED); 189 190 mlx4_free_cmd_mailbox(dev, mailbox); 191 return err; 192 } 193 194 static int mlx4_ib_update_gids_v1_v2(struct gid_entry *gids, 195 struct mlx4_ib_dev *ibdev, 196 u8 port_num) 197 { 198 struct mlx4_cmd_mailbox *mailbox; 199 int err; 200 struct mlx4_dev *dev = ibdev->dev; 201 int i; 202 struct { 203 union ib_gid gid; 204 __be32 rsrvd1[2]; 205 __be16 rsrvd2; 206 u8 type; 207 u8 version; 208 __be32 rsrvd3; 209 } *gid_tbl; 210 211 mailbox = mlx4_alloc_cmd_mailbox(dev); 212 if (IS_ERR(mailbox)) 213 return -ENOMEM; 214 215 gid_tbl = mailbox->buf; 216 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) { 217 memcpy(&gid_tbl[i].gid, &gids[i].gid, sizeof(union ib_gid)); 218 if (gids[i].gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { 219 gid_tbl[i].version = 2; 220 if (!ipv6_addr_v4mapped((struct in6_addr *)&gids[i].gid)) 221 gid_tbl[i].type = 1; 222 } 223 } 224 225 err = mlx4_cmd(dev, mailbox->dma, 226 MLX4_SET_PORT_ROCE_ADDR << 8 | port_num, 227 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 228 MLX4_CMD_WRAPPED); 229 if (mlx4_is_bonded(dev)) 230 err += mlx4_cmd(dev, mailbox->dma, 231 MLX4_SET_PORT_ROCE_ADDR << 8 | 2, 232 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 233 MLX4_CMD_WRAPPED); 234 235 mlx4_free_cmd_mailbox(dev, mailbox); 236 return err; 237 } 238 239 static int mlx4_ib_update_gids(struct gid_entry *gids, 240 struct mlx4_ib_dev *ibdev, 241 u8 port_num) 242 { 243 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) 244 return mlx4_ib_update_gids_v1_v2(gids, ibdev, port_num); 245 246 return mlx4_ib_update_gids_v1(gids, ibdev, port_num); 247 } 248 249 static void free_gid_entry(struct gid_entry *entry) 250 { 251 memset(&entry->gid, 0, sizeof(entry->gid)); 252 kfree(entry->ctx); 253 entry->ctx = NULL; 254 } 255 256 static int mlx4_ib_add_gid(const struct ib_gid_attr *attr, void **context) 257 { 258 struct mlx4_ib_dev *ibdev = to_mdev(attr->device); 259 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 260 struct mlx4_port_gid_table *port_gid_table; 261 int free = -1, found = -1; 262 int ret = 0; 263 int hw_update = 0; 264 int i; 265 struct gid_entry *gids = NULL; 266 u16 vlan_id = 0xffff; 267 u8 mac[ETH_ALEN]; 268 269 if (!rdma_cap_roce_gid_table(attr->device, attr->port_num)) 270 return -EINVAL; 271 272 if (attr->port_num > MLX4_MAX_PORTS) 273 return -EINVAL; 274 275 if (!context) 276 return -EINVAL; 277 278 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]); 279 if (ret) 280 return ret; 281 port_gid_table = &iboe->gids[attr->port_num - 1]; 282 spin_lock_bh(&iboe->lock); 283 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) { 284 if (!memcmp(&port_gid_table->gids[i].gid, 285 &attr->gid, sizeof(attr->gid)) && 286 port_gid_table->gids[i].gid_type == attr->gid_type && 287 port_gid_table->gids[i].vlan_id == vlan_id) { 288 found = i; 289 break; 290 } 291 if (free < 0 && rdma_is_zero_gid(&port_gid_table->gids[i].gid)) 292 free = i; /* HW has space */ 293 } 294 295 if (found < 0) { 296 if (free < 0) { 297 ret = -ENOSPC; 298 } else { 299 port_gid_table->gids[free].ctx = kmalloc(sizeof(*port_gid_table->gids[free].ctx), GFP_ATOMIC); 300 if (!port_gid_table->gids[free].ctx) { 301 ret = -ENOMEM; 302 } else { 303 *context = port_gid_table->gids[free].ctx; 304 memcpy(&port_gid_table->gids[free].gid, 305 &attr->gid, sizeof(attr->gid)); 306 port_gid_table->gids[free].gid_type = attr->gid_type; 307 port_gid_table->gids[free].vlan_id = vlan_id; 308 port_gid_table->gids[free].ctx->real_index = free; 309 port_gid_table->gids[free].ctx->refcount = 1; 310 hw_update = 1; 311 } 312 } 313 } else { 314 struct gid_cache_context *ctx = port_gid_table->gids[found].ctx; 315 *context = ctx; 316 ctx->refcount++; 317 } 318 if (!ret && hw_update) { 319 gids = kmalloc_array(MLX4_MAX_PORT_GIDS, sizeof(*gids), 320 GFP_ATOMIC); 321 if (!gids) { 322 ret = -ENOMEM; 323 *context = NULL; 324 free_gid_entry(&port_gid_table->gids[free]); 325 } else { 326 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) { 327 memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid)); 328 gids[i].gid_type = port_gid_table->gids[i].gid_type; 329 } 330 } 331 } 332 spin_unlock_bh(&iboe->lock); 333 334 if (!ret && hw_update) { 335 ret = mlx4_ib_update_gids(gids, ibdev, attr->port_num); 336 if (ret) { 337 spin_lock_bh(&iboe->lock); 338 *context = NULL; 339 free_gid_entry(&port_gid_table->gids[free]); 340 spin_unlock_bh(&iboe->lock); 341 } 342 kfree(gids); 343 } 344 345 return ret; 346 } 347 348 static int mlx4_ib_del_gid(const struct ib_gid_attr *attr, void **context) 349 { 350 struct gid_cache_context *ctx = *context; 351 struct mlx4_ib_dev *ibdev = to_mdev(attr->device); 352 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 353 struct mlx4_port_gid_table *port_gid_table; 354 int ret = 0; 355 int hw_update = 0; 356 struct gid_entry *gids = NULL; 357 358 if (!rdma_cap_roce_gid_table(attr->device, attr->port_num)) 359 return -EINVAL; 360 361 if (attr->port_num > MLX4_MAX_PORTS) 362 return -EINVAL; 363 364 port_gid_table = &iboe->gids[attr->port_num - 1]; 365 spin_lock_bh(&iboe->lock); 366 if (ctx) { 367 ctx->refcount--; 368 if (!ctx->refcount) { 369 unsigned int real_index = ctx->real_index; 370 371 free_gid_entry(&port_gid_table->gids[real_index]); 372 hw_update = 1; 373 } 374 } 375 if (!ret && hw_update) { 376 int i; 377 378 gids = kmalloc_array(MLX4_MAX_PORT_GIDS, sizeof(*gids), 379 GFP_ATOMIC); 380 if (!gids) { 381 ret = -ENOMEM; 382 } else { 383 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) { 384 memcpy(&gids[i].gid, 385 &port_gid_table->gids[i].gid, 386 sizeof(union ib_gid)); 387 gids[i].gid_type = 388 port_gid_table->gids[i].gid_type; 389 } 390 } 391 } 392 spin_unlock_bh(&iboe->lock); 393 394 if (!ret && hw_update) { 395 ret = mlx4_ib_update_gids(gids, ibdev, attr->port_num); 396 kfree(gids); 397 } 398 return ret; 399 } 400 401 int mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev *ibdev, 402 const struct ib_gid_attr *attr) 403 { 404 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 405 struct gid_cache_context *ctx = NULL; 406 struct mlx4_port_gid_table *port_gid_table; 407 int real_index = -EINVAL; 408 int i; 409 unsigned long flags; 410 u8 port_num = attr->port_num; 411 412 if (port_num > MLX4_MAX_PORTS) 413 return -EINVAL; 414 415 if (mlx4_is_bonded(ibdev->dev)) 416 port_num = 1; 417 418 if (!rdma_cap_roce_gid_table(&ibdev->ib_dev, port_num)) 419 return attr->index; 420 421 spin_lock_irqsave(&iboe->lock, flags); 422 port_gid_table = &iboe->gids[port_num - 1]; 423 424 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) 425 if (!memcmp(&port_gid_table->gids[i].gid, 426 &attr->gid, sizeof(attr->gid)) && 427 attr->gid_type == port_gid_table->gids[i].gid_type) { 428 ctx = port_gid_table->gids[i].ctx; 429 break; 430 } 431 if (ctx) 432 real_index = ctx->real_index; 433 spin_unlock_irqrestore(&iboe->lock, flags); 434 return real_index; 435 } 436 437 static int mlx4_ib_query_device(struct ib_device *ibdev, 438 struct ib_device_attr *props, 439 struct ib_udata *uhw) 440 { 441 struct mlx4_ib_dev *dev = to_mdev(ibdev); 442 struct ib_smp *in_mad = NULL; 443 struct ib_smp *out_mad = NULL; 444 int err; 445 int have_ib_ports; 446 struct mlx4_uverbs_ex_query_device cmd; 447 struct mlx4_uverbs_ex_query_device_resp resp = {}; 448 struct mlx4_clock_params clock_params; 449 450 if (uhw->inlen) { 451 if (uhw->inlen < sizeof(cmd)) 452 return -EINVAL; 453 454 err = ib_copy_from_udata(&cmd, uhw, sizeof(cmd)); 455 if (err) 456 return err; 457 458 if (cmd.comp_mask) 459 return -EINVAL; 460 461 if (cmd.reserved) 462 return -EINVAL; 463 } 464 465 resp.response_length = offsetof(typeof(resp), response_length) + 466 sizeof(resp.response_length); 467 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 468 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 469 err = -ENOMEM; 470 if (!in_mad || !out_mad) 471 goto out; 472 473 init_query_mad(in_mad); 474 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO; 475 476 err = mlx4_MAD_IFC(to_mdev(ibdev), MLX4_MAD_IFC_IGNORE_KEYS, 477 1, NULL, NULL, in_mad, out_mad); 478 if (err) 479 goto out; 480 481 memset(props, 0, sizeof *props); 482 483 have_ib_ports = num_ib_ports(dev->dev); 484 485 props->fw_ver = dev->dev->caps.fw_ver; 486 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 487 IB_DEVICE_PORT_ACTIVE_EVENT | 488 IB_DEVICE_SYS_IMAGE_GUID | 489 IB_DEVICE_RC_RNR_NAK_GEN | 490 IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 491 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR) 492 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 493 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR) 494 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 495 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_APM && have_ib_ports) 496 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 497 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT) 498 props->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE; 499 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) 500 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 501 if (dev->dev->caps.max_gso_sz && 502 (dev->dev->rev_id != MLX4_IB_CARD_REV_A0) && 503 (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BLH)) 504 props->device_cap_flags |= IB_DEVICE_UD_TSO; 505 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_RESERVED_LKEY) 506 props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY; 507 if ((dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_LOCAL_INV) && 508 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_REMOTE_INV) && 509 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_FAST_REG_WR)) 510 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 511 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) 512 props->device_cap_flags |= IB_DEVICE_XRC; 513 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW) 514 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW; 515 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) { 516 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_WIN_TYPE_2B) 517 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2B; 518 else 519 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2A; 520 } 521 if (dev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED) 522 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 523 524 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 525 526 props->vendor_id = be32_to_cpup((__be32 *) (out_mad->data + 36)) & 527 0xffffff; 528 props->vendor_part_id = dev->dev->persist->pdev->device; 529 props->hw_ver = be32_to_cpup((__be32 *) (out_mad->data + 32)); 530 memcpy(&props->sys_image_guid, out_mad->data + 4, 8); 531 532 props->max_mr_size = ~0ull; 533 props->page_size_cap = dev->dev->caps.page_size_cap; 534 props->max_qp = dev->dev->quotas.qp; 535 props->max_qp_wr = dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE; 536 props->max_send_sge = 537 min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg); 538 props->max_recv_sge = 539 min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg); 540 props->max_sge_rd = MLX4_MAX_SGE_RD; 541 props->max_cq = dev->dev->quotas.cq; 542 props->max_cqe = dev->dev->caps.max_cqes; 543 props->max_mr = dev->dev->quotas.mpt; 544 props->max_pd = dev->dev->caps.num_pds - dev->dev->caps.reserved_pds; 545 props->max_qp_rd_atom = dev->dev->caps.max_qp_dest_rdma; 546 props->max_qp_init_rd_atom = dev->dev->caps.max_qp_init_rdma; 547 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 548 props->max_srq = dev->dev->quotas.srq; 549 props->max_srq_wr = dev->dev->caps.max_srq_wqes - 1; 550 props->max_srq_sge = dev->dev->caps.max_srq_sge; 551 props->max_fast_reg_page_list_len = MLX4_MAX_FAST_REG_PAGES; 552 props->local_ca_ack_delay = dev->dev->caps.local_ca_ack_delay; 553 props->atomic_cap = dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_ATOMIC ? 554 IB_ATOMIC_HCA : IB_ATOMIC_NONE; 555 props->masked_atomic_cap = props->atomic_cap; 556 props->max_pkeys = dev->dev->caps.pkey_table_len[1]; 557 props->max_mcast_grp = dev->dev->caps.num_mgms + dev->dev->caps.num_amgms; 558 props->max_mcast_qp_attach = dev->dev->caps.num_qp_per_mgm; 559 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 560 props->max_mcast_grp; 561 props->hca_core_clock = dev->dev->caps.hca_core_clock * 1000UL; 562 props->timestamp_mask = 0xFFFFFFFFFFFFULL; 563 props->max_ah = INT_MAX; 564 565 if (mlx4_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET || 566 mlx4_ib_port_link_layer(ibdev, 2) == IB_LINK_LAYER_ETHERNET) { 567 if (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) { 568 props->rss_caps.max_rwq_indirection_tables = 569 props->max_qp; 570 props->rss_caps.max_rwq_indirection_table_size = 571 dev->dev->caps.max_rss_tbl_sz; 572 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 573 props->max_wq_type_rq = props->max_qp; 574 } 575 576 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) 577 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 578 } 579 580 props->cq_caps.max_cq_moderation_count = MLX4_MAX_CQ_COUNT; 581 props->cq_caps.max_cq_moderation_period = MLX4_MAX_CQ_PERIOD; 582 583 if (!mlx4_is_slave(dev->dev)) 584 err = mlx4_get_internal_clock_params(dev->dev, &clock_params); 585 586 if (uhw->outlen >= resp.response_length + sizeof(resp.hca_core_clock_offset)) { 587 resp.response_length += sizeof(resp.hca_core_clock_offset); 588 if (!err && !mlx4_is_slave(dev->dev)) { 589 resp.comp_mask |= MLX4_IB_QUERY_DEV_RESP_MASK_CORE_CLOCK_OFFSET; 590 resp.hca_core_clock_offset = clock_params.offset % PAGE_SIZE; 591 } 592 } 593 594 if (uhw->outlen >= resp.response_length + 595 sizeof(resp.max_inl_recv_sz)) { 596 resp.response_length += sizeof(resp.max_inl_recv_sz); 597 resp.max_inl_recv_sz = dev->dev->caps.max_rq_sg * 598 sizeof(struct mlx4_wqe_data_seg); 599 } 600 601 if (offsetofend(typeof(resp), rss_caps) <= uhw->outlen) { 602 if (props->rss_caps.supported_qpts) { 603 resp.rss_caps.rx_hash_function = 604 MLX4_IB_RX_HASH_FUNC_TOEPLITZ; 605 606 resp.rss_caps.rx_hash_fields_mask = 607 MLX4_IB_RX_HASH_SRC_IPV4 | 608 MLX4_IB_RX_HASH_DST_IPV4 | 609 MLX4_IB_RX_HASH_SRC_IPV6 | 610 MLX4_IB_RX_HASH_DST_IPV6 | 611 MLX4_IB_RX_HASH_SRC_PORT_TCP | 612 MLX4_IB_RX_HASH_DST_PORT_TCP | 613 MLX4_IB_RX_HASH_SRC_PORT_UDP | 614 MLX4_IB_RX_HASH_DST_PORT_UDP; 615 616 if (dev->dev->caps.tunnel_offload_mode == 617 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) 618 resp.rss_caps.rx_hash_fields_mask |= 619 MLX4_IB_RX_HASH_INNER; 620 } 621 resp.response_length = offsetof(typeof(resp), rss_caps) + 622 sizeof(resp.rss_caps); 623 } 624 625 if (offsetofend(typeof(resp), tso_caps) <= uhw->outlen) { 626 if (dev->dev->caps.max_gso_sz && 627 ((mlx4_ib_port_link_layer(ibdev, 1) == 628 IB_LINK_LAYER_ETHERNET) || 629 (mlx4_ib_port_link_layer(ibdev, 2) == 630 IB_LINK_LAYER_ETHERNET))) { 631 resp.tso_caps.max_tso = dev->dev->caps.max_gso_sz; 632 resp.tso_caps.supported_qpts |= 633 1 << IB_QPT_RAW_PACKET; 634 } 635 resp.response_length = offsetof(typeof(resp), tso_caps) + 636 sizeof(resp.tso_caps); 637 } 638 639 if (uhw->outlen) { 640 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 641 if (err) 642 goto out; 643 } 644 out: 645 kfree(in_mad); 646 kfree(out_mad); 647 648 return err; 649 } 650 651 static enum rdma_link_layer 652 mlx4_ib_port_link_layer(struct ib_device *device, u8 port_num) 653 { 654 struct mlx4_dev *dev = to_mdev(device)->dev; 655 656 return dev->caps.port_mask[port_num] == MLX4_PORT_TYPE_IB ? 657 IB_LINK_LAYER_INFINIBAND : IB_LINK_LAYER_ETHERNET; 658 } 659 660 static int ib_link_query_port(struct ib_device *ibdev, u8 port, 661 struct ib_port_attr *props, int netw_view) 662 { 663 struct ib_smp *in_mad = NULL; 664 struct ib_smp *out_mad = NULL; 665 int ext_active_speed; 666 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 667 int err = -ENOMEM; 668 669 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 670 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 671 if (!in_mad || !out_mad) 672 goto out; 673 674 init_query_mad(in_mad); 675 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO; 676 in_mad->attr_mod = cpu_to_be32(port); 677 678 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view) 679 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 680 681 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL, 682 in_mad, out_mad); 683 if (err) 684 goto out; 685 686 687 props->lid = be16_to_cpup((__be16 *) (out_mad->data + 16)); 688 props->lmc = out_mad->data[34] & 0x7; 689 props->sm_lid = be16_to_cpup((__be16 *) (out_mad->data + 18)); 690 props->sm_sl = out_mad->data[36] & 0xf; 691 props->state = out_mad->data[32] & 0xf; 692 props->phys_state = out_mad->data[33] >> 4; 693 props->port_cap_flags = be32_to_cpup((__be32 *) (out_mad->data + 20)); 694 if (netw_view) 695 props->gid_tbl_len = out_mad->data[50]; 696 else 697 props->gid_tbl_len = to_mdev(ibdev)->dev->caps.gid_table_len[port]; 698 props->max_msg_sz = to_mdev(ibdev)->dev->caps.max_msg_sz; 699 props->pkey_tbl_len = to_mdev(ibdev)->dev->caps.pkey_table_len[port]; 700 props->bad_pkey_cntr = be16_to_cpup((__be16 *) (out_mad->data + 46)); 701 props->qkey_viol_cntr = be16_to_cpup((__be16 *) (out_mad->data + 48)); 702 props->active_width = out_mad->data[31] & 0xf; 703 props->active_speed = out_mad->data[35] >> 4; 704 props->max_mtu = out_mad->data[41] & 0xf; 705 props->active_mtu = out_mad->data[36] >> 4; 706 props->subnet_timeout = out_mad->data[51] & 0x1f; 707 props->max_vl_num = out_mad->data[37] >> 4; 708 props->init_type_reply = out_mad->data[41] >> 4; 709 710 /* Check if extended speeds (EDR/FDR/...) are supported */ 711 if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) { 712 ext_active_speed = out_mad->data[62] >> 4; 713 714 switch (ext_active_speed) { 715 case 1: 716 props->active_speed = IB_SPEED_FDR; 717 break; 718 case 2: 719 props->active_speed = IB_SPEED_EDR; 720 break; 721 } 722 } 723 724 /* If reported active speed is QDR, check if is FDR-10 */ 725 if (props->active_speed == IB_SPEED_QDR) { 726 init_query_mad(in_mad); 727 in_mad->attr_id = MLX4_ATTR_EXTENDED_PORT_INFO; 728 in_mad->attr_mod = cpu_to_be32(port); 729 730 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, 731 NULL, NULL, in_mad, out_mad); 732 if (err) 733 goto out; 734 735 /* Checking LinkSpeedActive for FDR-10 */ 736 if (out_mad->data[15] & 0x1) 737 props->active_speed = IB_SPEED_FDR10; 738 } 739 740 /* Avoid wrong speed value returned by FW if the IB link is down. */ 741 if (props->state == IB_PORT_DOWN) 742 props->active_speed = IB_SPEED_SDR; 743 744 out: 745 kfree(in_mad); 746 kfree(out_mad); 747 return err; 748 } 749 750 static u8 state_to_phys_state(enum ib_port_state state) 751 { 752 return state == IB_PORT_ACTIVE ? 753 IB_PORT_PHYS_STATE_LINK_UP : IB_PORT_PHYS_STATE_DISABLED; 754 } 755 756 static int eth_link_query_port(struct ib_device *ibdev, u8 port, 757 struct ib_port_attr *props) 758 { 759 760 struct mlx4_ib_dev *mdev = to_mdev(ibdev); 761 struct mlx4_ib_iboe *iboe = &mdev->iboe; 762 struct net_device *ndev; 763 enum ib_mtu tmp; 764 struct mlx4_cmd_mailbox *mailbox; 765 int err = 0; 766 int is_bonded = mlx4_is_bonded(mdev->dev); 767 768 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev); 769 if (IS_ERR(mailbox)) 770 return PTR_ERR(mailbox); 771 772 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0, 773 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 774 MLX4_CMD_WRAPPED); 775 if (err) 776 goto out; 777 778 props->active_width = (((u8 *)mailbox->buf)[5] == 0x40) || 779 (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ? 780 IB_WIDTH_4X : IB_WIDTH_1X; 781 props->active_speed = (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ? 782 IB_SPEED_FDR : IB_SPEED_QDR; 783 props->port_cap_flags = IB_PORT_CM_SUP; 784 props->ip_gids = true; 785 props->gid_tbl_len = mdev->dev->caps.gid_table_len[port]; 786 props->max_msg_sz = mdev->dev->caps.max_msg_sz; 787 props->pkey_tbl_len = 1; 788 props->max_mtu = IB_MTU_4096; 789 props->max_vl_num = 2; 790 props->state = IB_PORT_DOWN; 791 props->phys_state = state_to_phys_state(props->state); 792 props->active_mtu = IB_MTU_256; 793 spin_lock_bh(&iboe->lock); 794 ndev = iboe->netdevs[port - 1]; 795 if (ndev && is_bonded) { 796 rcu_read_lock(); /* required to get upper dev */ 797 ndev = netdev_master_upper_dev_get_rcu(ndev); 798 rcu_read_unlock(); 799 } 800 if (!ndev) 801 goto out_unlock; 802 803 tmp = iboe_get_mtu(ndev->mtu); 804 props->active_mtu = tmp ? min(props->max_mtu, tmp) : IB_MTU_256; 805 806 props->state = (netif_running(ndev) && netif_carrier_ok(ndev)) ? 807 IB_PORT_ACTIVE : IB_PORT_DOWN; 808 props->phys_state = state_to_phys_state(props->state); 809 out_unlock: 810 spin_unlock_bh(&iboe->lock); 811 out: 812 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 813 return err; 814 } 815 816 int __mlx4_ib_query_port(struct ib_device *ibdev, u8 port, 817 struct ib_port_attr *props, int netw_view) 818 { 819 int err; 820 821 /* props being zeroed by the caller, avoid zeroing it here */ 822 823 err = mlx4_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND ? 824 ib_link_query_port(ibdev, port, props, netw_view) : 825 eth_link_query_port(ibdev, port, props); 826 827 return err; 828 } 829 830 static int mlx4_ib_query_port(struct ib_device *ibdev, u8 port, 831 struct ib_port_attr *props) 832 { 833 /* returns host view */ 834 return __mlx4_ib_query_port(ibdev, port, props, 0); 835 } 836 837 int __mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 838 union ib_gid *gid, int netw_view) 839 { 840 struct ib_smp *in_mad = NULL; 841 struct ib_smp *out_mad = NULL; 842 int err = -ENOMEM; 843 struct mlx4_ib_dev *dev = to_mdev(ibdev); 844 int clear = 0; 845 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 846 847 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 848 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 849 if (!in_mad || !out_mad) 850 goto out; 851 852 init_query_mad(in_mad); 853 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO; 854 in_mad->attr_mod = cpu_to_be32(port); 855 856 if (mlx4_is_mfunc(dev->dev) && netw_view) 857 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 858 859 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, NULL, NULL, in_mad, out_mad); 860 if (err) 861 goto out; 862 863 memcpy(gid->raw, out_mad->data + 8, 8); 864 865 if (mlx4_is_mfunc(dev->dev) && !netw_view) { 866 if (index) { 867 /* For any index > 0, return the null guid */ 868 err = 0; 869 clear = 1; 870 goto out; 871 } 872 } 873 874 init_query_mad(in_mad); 875 in_mad->attr_id = IB_SMP_ATTR_GUID_INFO; 876 in_mad->attr_mod = cpu_to_be32(index / 8); 877 878 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, 879 NULL, NULL, in_mad, out_mad); 880 if (err) 881 goto out; 882 883 memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8); 884 885 out: 886 if (clear) 887 memset(gid->raw + 8, 0, 8); 888 kfree(in_mad); 889 kfree(out_mad); 890 return err; 891 } 892 893 static int mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 894 union ib_gid *gid) 895 { 896 if (rdma_protocol_ib(ibdev, port)) 897 return __mlx4_ib_query_gid(ibdev, port, index, gid, 0); 898 return 0; 899 } 900 901 static int mlx4_ib_query_sl2vl(struct ib_device *ibdev, u8 port, u64 *sl2vl_tbl) 902 { 903 union sl2vl_tbl_to_u64 sl2vl64; 904 struct ib_smp *in_mad = NULL; 905 struct ib_smp *out_mad = NULL; 906 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 907 int err = -ENOMEM; 908 int jj; 909 910 if (mlx4_is_slave(to_mdev(ibdev)->dev)) { 911 *sl2vl_tbl = 0; 912 return 0; 913 } 914 915 in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL); 916 out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL); 917 if (!in_mad || !out_mad) 918 goto out; 919 920 init_query_mad(in_mad); 921 in_mad->attr_id = IB_SMP_ATTR_SL_TO_VL_TABLE; 922 in_mad->attr_mod = 0; 923 924 if (mlx4_is_mfunc(to_mdev(ibdev)->dev)) 925 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 926 927 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL, 928 in_mad, out_mad); 929 if (err) 930 goto out; 931 932 for (jj = 0; jj < 8; jj++) 933 sl2vl64.sl8[jj] = ((struct ib_smp *)out_mad)->data[jj]; 934 *sl2vl_tbl = sl2vl64.sl64; 935 936 out: 937 kfree(in_mad); 938 kfree(out_mad); 939 return err; 940 } 941 942 static void mlx4_init_sl2vl_tbl(struct mlx4_ib_dev *mdev) 943 { 944 u64 sl2vl; 945 int i; 946 int err; 947 948 for (i = 1; i <= mdev->dev->caps.num_ports; i++) { 949 if (mdev->dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) 950 continue; 951 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, i, &sl2vl); 952 if (err) { 953 pr_err("Unable to get default sl to vl mapping for port %d. Using all zeroes (%d)\n", 954 i, err); 955 sl2vl = 0; 956 } 957 atomic64_set(&mdev->sl2vl[i - 1], sl2vl); 958 } 959 } 960 961 int __mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 962 u16 *pkey, int netw_view) 963 { 964 struct ib_smp *in_mad = NULL; 965 struct ib_smp *out_mad = NULL; 966 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 967 int err = -ENOMEM; 968 969 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 970 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 971 if (!in_mad || !out_mad) 972 goto out; 973 974 init_query_mad(in_mad); 975 in_mad->attr_id = IB_SMP_ATTR_PKEY_TABLE; 976 in_mad->attr_mod = cpu_to_be32(index / 32); 977 978 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view) 979 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 980 981 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL, 982 in_mad, out_mad); 983 if (err) 984 goto out; 985 986 *pkey = be16_to_cpu(((__be16 *) out_mad->data)[index % 32]); 987 988 out: 989 kfree(in_mad); 990 kfree(out_mad); 991 return err; 992 } 993 994 static int mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey) 995 { 996 return __mlx4_ib_query_pkey(ibdev, port, index, pkey, 0); 997 } 998 999 static int mlx4_ib_modify_device(struct ib_device *ibdev, int mask, 1000 struct ib_device_modify *props) 1001 { 1002 struct mlx4_cmd_mailbox *mailbox; 1003 unsigned long flags; 1004 1005 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1006 return -EOPNOTSUPP; 1007 1008 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1009 return 0; 1010 1011 if (mlx4_is_slave(to_mdev(ibdev)->dev)) 1012 return -EOPNOTSUPP; 1013 1014 spin_lock_irqsave(&to_mdev(ibdev)->sm_lock, flags); 1015 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1016 spin_unlock_irqrestore(&to_mdev(ibdev)->sm_lock, flags); 1017 1018 /* 1019 * If possible, pass node desc to FW, so it can generate 1020 * a 144 trap. If cmd fails, just ignore. 1021 */ 1022 mailbox = mlx4_alloc_cmd_mailbox(to_mdev(ibdev)->dev); 1023 if (IS_ERR(mailbox)) 1024 return 0; 1025 1026 memcpy(mailbox->buf, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1027 mlx4_cmd(to_mdev(ibdev)->dev, mailbox->dma, 1, 0, 1028 MLX4_CMD_SET_NODE, MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1029 1030 mlx4_free_cmd_mailbox(to_mdev(ibdev)->dev, mailbox); 1031 1032 return 0; 1033 } 1034 1035 static int mlx4_ib_SET_PORT(struct mlx4_ib_dev *dev, u8 port, int reset_qkey_viols, 1036 u32 cap_mask) 1037 { 1038 struct mlx4_cmd_mailbox *mailbox; 1039 int err; 1040 1041 mailbox = mlx4_alloc_cmd_mailbox(dev->dev); 1042 if (IS_ERR(mailbox)) 1043 return PTR_ERR(mailbox); 1044 1045 if (dev->dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 1046 *(u8 *) mailbox->buf = !!reset_qkey_viols << 6; 1047 ((__be32 *) mailbox->buf)[2] = cpu_to_be32(cap_mask); 1048 } else { 1049 ((u8 *) mailbox->buf)[3] = !!reset_qkey_viols; 1050 ((__be32 *) mailbox->buf)[1] = cpu_to_be32(cap_mask); 1051 } 1052 1053 err = mlx4_cmd(dev->dev, mailbox->dma, port, MLX4_SET_PORT_IB_OPCODE, 1054 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 1055 MLX4_CMD_WRAPPED); 1056 1057 mlx4_free_cmd_mailbox(dev->dev, mailbox); 1058 return err; 1059 } 1060 1061 static int mlx4_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1062 struct ib_port_modify *props) 1063 { 1064 struct mlx4_ib_dev *mdev = to_mdev(ibdev); 1065 u8 is_eth = mdev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH; 1066 struct ib_port_attr attr; 1067 u32 cap_mask; 1068 int err; 1069 1070 /* return OK if this is RoCE. CM calls ib_modify_port() regardless 1071 * of whether port link layer is ETH or IB. For ETH ports, qkey 1072 * violations and port capabilities are not meaningful. 1073 */ 1074 if (is_eth) 1075 return 0; 1076 1077 mutex_lock(&mdev->cap_mask_mutex); 1078 1079 err = ib_query_port(ibdev, port, &attr); 1080 if (err) 1081 goto out; 1082 1083 cap_mask = (attr.port_cap_flags | props->set_port_cap_mask) & 1084 ~props->clr_port_cap_mask; 1085 1086 err = mlx4_ib_SET_PORT(mdev, port, 1087 !!(mask & IB_PORT_RESET_QKEY_CNTR), 1088 cap_mask); 1089 1090 out: 1091 mutex_unlock(&to_mdev(ibdev)->cap_mask_mutex); 1092 return err; 1093 } 1094 1095 static int mlx4_ib_alloc_ucontext(struct ib_ucontext *uctx, 1096 struct ib_udata *udata) 1097 { 1098 struct ib_device *ibdev = uctx->device; 1099 struct mlx4_ib_dev *dev = to_mdev(ibdev); 1100 struct mlx4_ib_ucontext *context = to_mucontext(uctx); 1101 struct mlx4_ib_alloc_ucontext_resp_v3 resp_v3; 1102 struct mlx4_ib_alloc_ucontext_resp resp; 1103 int err; 1104 1105 if (!dev->ib_active) 1106 return -EAGAIN; 1107 1108 if (ibdev->ops.uverbs_abi_ver == 1109 MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) { 1110 resp_v3.qp_tab_size = dev->dev->caps.num_qps; 1111 resp_v3.bf_reg_size = dev->dev->caps.bf_reg_size; 1112 resp_v3.bf_regs_per_page = dev->dev->caps.bf_regs_per_page; 1113 } else { 1114 resp.dev_caps = dev->dev->caps.userspace_caps; 1115 resp.qp_tab_size = dev->dev->caps.num_qps; 1116 resp.bf_reg_size = dev->dev->caps.bf_reg_size; 1117 resp.bf_regs_per_page = dev->dev->caps.bf_regs_per_page; 1118 resp.cqe_size = dev->dev->caps.cqe_size; 1119 } 1120 1121 err = mlx4_uar_alloc(to_mdev(ibdev)->dev, &context->uar); 1122 if (err) 1123 return err; 1124 1125 INIT_LIST_HEAD(&context->db_page_list); 1126 mutex_init(&context->db_page_mutex); 1127 1128 INIT_LIST_HEAD(&context->wqn_ranges_list); 1129 mutex_init(&context->wqn_ranges_mutex); 1130 1131 if (ibdev->ops.uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) 1132 err = ib_copy_to_udata(udata, &resp_v3, sizeof(resp_v3)); 1133 else 1134 err = ib_copy_to_udata(udata, &resp, sizeof(resp)); 1135 1136 if (err) { 1137 mlx4_uar_free(to_mdev(ibdev)->dev, &context->uar); 1138 return -EFAULT; 1139 } 1140 1141 return err; 1142 } 1143 1144 static void mlx4_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1145 { 1146 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext); 1147 1148 mlx4_uar_free(to_mdev(ibcontext->device)->dev, &context->uar); 1149 } 1150 1151 static void mlx4_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1152 { 1153 } 1154 1155 static int mlx4_ib_mmap(struct ib_ucontext *context, struct vm_area_struct *vma) 1156 { 1157 struct mlx4_ib_dev *dev = to_mdev(context->device); 1158 1159 switch (vma->vm_pgoff) { 1160 case 0: 1161 return rdma_user_mmap_io(context, vma, 1162 to_mucontext(context)->uar.pfn, 1163 PAGE_SIZE, 1164 pgprot_noncached(vma->vm_page_prot), 1165 NULL); 1166 1167 case 1: 1168 if (dev->dev->caps.bf_reg_size == 0) 1169 return -EINVAL; 1170 return rdma_user_mmap_io( 1171 context, vma, 1172 to_mucontext(context)->uar.pfn + 1173 dev->dev->caps.num_uars, 1174 PAGE_SIZE, pgprot_writecombine(vma->vm_page_prot), 1175 NULL); 1176 1177 case 3: { 1178 struct mlx4_clock_params params; 1179 int ret; 1180 1181 ret = mlx4_get_internal_clock_params(dev->dev, ¶ms); 1182 if (ret) 1183 return ret; 1184 1185 return rdma_user_mmap_io( 1186 context, vma, 1187 (pci_resource_start(dev->dev->persist->pdev, 1188 params.bar) + 1189 params.offset) >> 1190 PAGE_SHIFT, 1191 PAGE_SIZE, pgprot_noncached(vma->vm_page_prot), 1192 NULL); 1193 } 1194 1195 default: 1196 return -EINVAL; 1197 } 1198 } 1199 1200 static int mlx4_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 1201 { 1202 struct mlx4_ib_pd *pd = to_mpd(ibpd); 1203 struct ib_device *ibdev = ibpd->device; 1204 int err; 1205 1206 err = mlx4_pd_alloc(to_mdev(ibdev)->dev, &pd->pdn); 1207 if (err) 1208 return err; 1209 1210 if (udata && ib_copy_to_udata(udata, &pd->pdn, sizeof(__u32))) { 1211 mlx4_pd_free(to_mdev(ibdev)->dev, pd->pdn); 1212 return -EFAULT; 1213 } 1214 return 0; 1215 } 1216 1217 static void mlx4_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata) 1218 { 1219 mlx4_pd_free(to_mdev(pd->device)->dev, to_mpd(pd)->pdn); 1220 } 1221 1222 static int mlx4_ib_alloc_xrcd(struct ib_xrcd *ibxrcd, struct ib_udata *udata) 1223 { 1224 struct mlx4_ib_dev *dev = to_mdev(ibxrcd->device); 1225 struct mlx4_ib_xrcd *xrcd = to_mxrcd(ibxrcd); 1226 struct ib_cq_init_attr cq_attr = {}; 1227 int err; 1228 1229 if (!(dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)) 1230 return -EOPNOTSUPP; 1231 1232 err = mlx4_xrcd_alloc(dev->dev, &xrcd->xrcdn); 1233 if (err) 1234 return err; 1235 1236 xrcd->pd = ib_alloc_pd(ibxrcd->device, 0); 1237 if (IS_ERR(xrcd->pd)) { 1238 err = PTR_ERR(xrcd->pd); 1239 goto err2; 1240 } 1241 1242 cq_attr.cqe = 1; 1243 xrcd->cq = ib_create_cq(ibxrcd->device, NULL, NULL, xrcd, &cq_attr); 1244 if (IS_ERR(xrcd->cq)) { 1245 err = PTR_ERR(xrcd->cq); 1246 goto err3; 1247 } 1248 1249 return 0; 1250 1251 err3: 1252 ib_dealloc_pd(xrcd->pd); 1253 err2: 1254 mlx4_xrcd_free(dev->dev, xrcd->xrcdn); 1255 return err; 1256 } 1257 1258 static void mlx4_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata) 1259 { 1260 ib_destroy_cq(to_mxrcd(xrcd)->cq); 1261 ib_dealloc_pd(to_mxrcd(xrcd)->pd); 1262 mlx4_xrcd_free(to_mdev(xrcd->device)->dev, to_mxrcd(xrcd)->xrcdn); 1263 } 1264 1265 static int add_gid_entry(struct ib_qp *ibqp, union ib_gid *gid) 1266 { 1267 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 1268 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 1269 struct mlx4_ib_gid_entry *ge; 1270 1271 ge = kzalloc(sizeof *ge, GFP_KERNEL); 1272 if (!ge) 1273 return -ENOMEM; 1274 1275 ge->gid = *gid; 1276 if (mlx4_ib_add_mc(mdev, mqp, gid)) { 1277 ge->port = mqp->port; 1278 ge->added = 1; 1279 } 1280 1281 mutex_lock(&mqp->mutex); 1282 list_add_tail(&ge->list, &mqp->gid_list); 1283 mutex_unlock(&mqp->mutex); 1284 1285 return 0; 1286 } 1287 1288 static void mlx4_ib_delete_counters_table(struct mlx4_ib_dev *ibdev, 1289 struct mlx4_ib_counters *ctr_table) 1290 { 1291 struct counter_index *counter, *tmp_count; 1292 1293 mutex_lock(&ctr_table->mutex); 1294 list_for_each_entry_safe(counter, tmp_count, &ctr_table->counters_list, 1295 list) { 1296 if (counter->allocated) 1297 mlx4_counter_free(ibdev->dev, counter->index); 1298 list_del(&counter->list); 1299 kfree(counter); 1300 } 1301 mutex_unlock(&ctr_table->mutex); 1302 } 1303 1304 int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp, 1305 union ib_gid *gid) 1306 { 1307 struct net_device *ndev; 1308 int ret = 0; 1309 1310 if (!mqp->port) 1311 return 0; 1312 1313 spin_lock_bh(&mdev->iboe.lock); 1314 ndev = mdev->iboe.netdevs[mqp->port - 1]; 1315 if (ndev) 1316 dev_hold(ndev); 1317 spin_unlock_bh(&mdev->iboe.lock); 1318 1319 if (ndev) { 1320 ret = 1; 1321 dev_put(ndev); 1322 } 1323 1324 return ret; 1325 } 1326 1327 struct mlx4_ib_steering { 1328 struct list_head list; 1329 struct mlx4_flow_reg_id reg_id; 1330 union ib_gid gid; 1331 }; 1332 1333 #define LAST_ETH_FIELD vlan_tag 1334 #define LAST_IB_FIELD sl 1335 #define LAST_IPV4_FIELD dst_ip 1336 #define LAST_TCP_UDP_FIELD src_port 1337 1338 /* Field is the last supported field */ 1339 #define FIELDS_NOT_SUPPORTED(filter, field)\ 1340 memchr_inv((void *)&filter.field +\ 1341 sizeof(filter.field), 0,\ 1342 sizeof(filter) -\ 1343 offsetof(typeof(filter), field) -\ 1344 sizeof(filter.field)) 1345 1346 static int parse_flow_attr(struct mlx4_dev *dev, 1347 u32 qp_num, 1348 union ib_flow_spec *ib_spec, 1349 struct _rule_hw *mlx4_spec) 1350 { 1351 enum mlx4_net_trans_rule_id type; 1352 1353 switch (ib_spec->type) { 1354 case IB_FLOW_SPEC_ETH: 1355 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 1356 return -ENOTSUPP; 1357 1358 type = MLX4_NET_TRANS_RULE_ID_ETH; 1359 memcpy(mlx4_spec->eth.dst_mac, ib_spec->eth.val.dst_mac, 1360 ETH_ALEN); 1361 memcpy(mlx4_spec->eth.dst_mac_msk, ib_spec->eth.mask.dst_mac, 1362 ETH_ALEN); 1363 mlx4_spec->eth.vlan_tag = ib_spec->eth.val.vlan_tag; 1364 mlx4_spec->eth.vlan_tag_msk = ib_spec->eth.mask.vlan_tag; 1365 break; 1366 case IB_FLOW_SPEC_IB: 1367 if (FIELDS_NOT_SUPPORTED(ib_spec->ib.mask, LAST_IB_FIELD)) 1368 return -ENOTSUPP; 1369 1370 type = MLX4_NET_TRANS_RULE_ID_IB; 1371 mlx4_spec->ib.l3_qpn = 1372 cpu_to_be32(qp_num); 1373 mlx4_spec->ib.qpn_mask = 1374 cpu_to_be32(MLX4_IB_FLOW_QPN_MASK); 1375 break; 1376 1377 1378 case IB_FLOW_SPEC_IPV4: 1379 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 1380 return -ENOTSUPP; 1381 1382 type = MLX4_NET_TRANS_RULE_ID_IPV4; 1383 mlx4_spec->ipv4.src_ip = ib_spec->ipv4.val.src_ip; 1384 mlx4_spec->ipv4.src_ip_msk = ib_spec->ipv4.mask.src_ip; 1385 mlx4_spec->ipv4.dst_ip = ib_spec->ipv4.val.dst_ip; 1386 mlx4_spec->ipv4.dst_ip_msk = ib_spec->ipv4.mask.dst_ip; 1387 break; 1388 1389 case IB_FLOW_SPEC_TCP: 1390 case IB_FLOW_SPEC_UDP: 1391 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, LAST_TCP_UDP_FIELD)) 1392 return -ENOTSUPP; 1393 1394 type = ib_spec->type == IB_FLOW_SPEC_TCP ? 1395 MLX4_NET_TRANS_RULE_ID_TCP : 1396 MLX4_NET_TRANS_RULE_ID_UDP; 1397 mlx4_spec->tcp_udp.dst_port = ib_spec->tcp_udp.val.dst_port; 1398 mlx4_spec->tcp_udp.dst_port_msk = ib_spec->tcp_udp.mask.dst_port; 1399 mlx4_spec->tcp_udp.src_port = ib_spec->tcp_udp.val.src_port; 1400 mlx4_spec->tcp_udp.src_port_msk = ib_spec->tcp_udp.mask.src_port; 1401 break; 1402 1403 default: 1404 return -EINVAL; 1405 } 1406 if (mlx4_map_sw_to_hw_steering_id(dev, type) < 0 || 1407 mlx4_hw_rule_sz(dev, type) < 0) 1408 return -EINVAL; 1409 mlx4_spec->id = cpu_to_be16(mlx4_map_sw_to_hw_steering_id(dev, type)); 1410 mlx4_spec->size = mlx4_hw_rule_sz(dev, type) >> 2; 1411 return mlx4_hw_rule_sz(dev, type); 1412 } 1413 1414 struct default_rules { 1415 __u32 mandatory_fields[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1416 __u32 mandatory_not_fields[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1417 __u32 rules_create_list[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1418 __u8 link_layer; 1419 }; 1420 static const struct default_rules default_table[] = { 1421 { 1422 .mandatory_fields = {IB_FLOW_SPEC_IPV4}, 1423 .mandatory_not_fields = {IB_FLOW_SPEC_ETH}, 1424 .rules_create_list = {IB_FLOW_SPEC_IB}, 1425 .link_layer = IB_LINK_LAYER_INFINIBAND 1426 } 1427 }; 1428 1429 static int __mlx4_ib_default_rules_match(struct ib_qp *qp, 1430 struct ib_flow_attr *flow_attr) 1431 { 1432 int i, j, k; 1433 void *ib_flow; 1434 const struct default_rules *pdefault_rules = default_table; 1435 u8 link_layer = rdma_port_get_link_layer(qp->device, flow_attr->port); 1436 1437 for (i = 0; i < ARRAY_SIZE(default_table); i++, pdefault_rules++) { 1438 __u32 field_types[IB_FLOW_SPEC_SUPPORT_LAYERS]; 1439 memset(&field_types, 0, sizeof(field_types)); 1440 1441 if (link_layer != pdefault_rules->link_layer) 1442 continue; 1443 1444 ib_flow = flow_attr + 1; 1445 /* we assume the specs are sorted */ 1446 for (j = 0, k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS && 1447 j < flow_attr->num_of_specs; k++) { 1448 union ib_flow_spec *current_flow = 1449 (union ib_flow_spec *)ib_flow; 1450 1451 /* same layer but different type */ 1452 if (((current_flow->type & IB_FLOW_SPEC_LAYER_MASK) == 1453 (pdefault_rules->mandatory_fields[k] & 1454 IB_FLOW_SPEC_LAYER_MASK)) && 1455 (current_flow->type != 1456 pdefault_rules->mandatory_fields[k])) 1457 goto out; 1458 1459 /* same layer, try match next one */ 1460 if (current_flow->type == 1461 pdefault_rules->mandatory_fields[k]) { 1462 j++; 1463 ib_flow += 1464 ((union ib_flow_spec *)ib_flow)->size; 1465 } 1466 } 1467 1468 ib_flow = flow_attr + 1; 1469 for (j = 0; j < flow_attr->num_of_specs; 1470 j++, ib_flow += ((union ib_flow_spec *)ib_flow)->size) 1471 for (k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS; k++) 1472 /* same layer and same type */ 1473 if (((union ib_flow_spec *)ib_flow)->type == 1474 pdefault_rules->mandatory_not_fields[k]) 1475 goto out; 1476 1477 return i; 1478 } 1479 out: 1480 return -1; 1481 } 1482 1483 static int __mlx4_ib_create_default_rules( 1484 struct mlx4_ib_dev *mdev, 1485 struct ib_qp *qp, 1486 const struct default_rules *pdefault_rules, 1487 struct _rule_hw *mlx4_spec) { 1488 int size = 0; 1489 int i; 1490 1491 for (i = 0; i < ARRAY_SIZE(pdefault_rules->rules_create_list); i++) { 1492 union ib_flow_spec ib_spec = {}; 1493 int ret; 1494 1495 switch (pdefault_rules->rules_create_list[i]) { 1496 case 0: 1497 /* no rule */ 1498 continue; 1499 case IB_FLOW_SPEC_IB: 1500 ib_spec.type = IB_FLOW_SPEC_IB; 1501 ib_spec.size = sizeof(struct ib_flow_spec_ib); 1502 1503 break; 1504 default: 1505 /* invalid rule */ 1506 return -EINVAL; 1507 } 1508 /* We must put empty rule, qpn is being ignored */ 1509 ret = parse_flow_attr(mdev->dev, 0, &ib_spec, 1510 mlx4_spec); 1511 if (ret < 0) { 1512 pr_info("invalid parsing\n"); 1513 return -EINVAL; 1514 } 1515 1516 mlx4_spec = (void *)mlx4_spec + ret; 1517 size += ret; 1518 } 1519 return size; 1520 } 1521 1522 static int __mlx4_ib_create_flow(struct ib_qp *qp, struct ib_flow_attr *flow_attr, 1523 int domain, 1524 enum mlx4_net_trans_promisc_mode flow_type, 1525 u64 *reg_id) 1526 { 1527 int ret, i; 1528 int size = 0; 1529 void *ib_flow; 1530 struct mlx4_ib_dev *mdev = to_mdev(qp->device); 1531 struct mlx4_cmd_mailbox *mailbox; 1532 struct mlx4_net_trans_rule_hw_ctrl *ctrl; 1533 int default_flow; 1534 1535 static const u16 __mlx4_domain[] = { 1536 [IB_FLOW_DOMAIN_USER] = MLX4_DOMAIN_UVERBS, 1537 [IB_FLOW_DOMAIN_ETHTOOL] = MLX4_DOMAIN_ETHTOOL, 1538 [IB_FLOW_DOMAIN_RFS] = MLX4_DOMAIN_RFS, 1539 [IB_FLOW_DOMAIN_NIC] = MLX4_DOMAIN_NIC, 1540 }; 1541 1542 if (flow_attr->priority > MLX4_IB_FLOW_MAX_PRIO) { 1543 pr_err("Invalid priority value %d\n", flow_attr->priority); 1544 return -EINVAL; 1545 } 1546 1547 if (domain >= IB_FLOW_DOMAIN_NUM) { 1548 pr_err("Invalid domain value %d\n", domain); 1549 return -EINVAL; 1550 } 1551 1552 if (mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type) < 0) 1553 return -EINVAL; 1554 1555 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev); 1556 if (IS_ERR(mailbox)) 1557 return PTR_ERR(mailbox); 1558 ctrl = mailbox->buf; 1559 1560 ctrl->prio = cpu_to_be16(__mlx4_domain[domain] | 1561 flow_attr->priority); 1562 ctrl->type = mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type); 1563 ctrl->port = flow_attr->port; 1564 ctrl->qpn = cpu_to_be32(qp->qp_num); 1565 1566 ib_flow = flow_attr + 1; 1567 size += sizeof(struct mlx4_net_trans_rule_hw_ctrl); 1568 /* Add default flows */ 1569 default_flow = __mlx4_ib_default_rules_match(qp, flow_attr); 1570 if (default_flow >= 0) { 1571 ret = __mlx4_ib_create_default_rules( 1572 mdev, qp, default_table + default_flow, 1573 mailbox->buf + size); 1574 if (ret < 0) { 1575 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 1576 return -EINVAL; 1577 } 1578 size += ret; 1579 } 1580 for (i = 0; i < flow_attr->num_of_specs; i++) { 1581 ret = parse_flow_attr(mdev->dev, qp->qp_num, ib_flow, 1582 mailbox->buf + size); 1583 if (ret < 0) { 1584 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 1585 return -EINVAL; 1586 } 1587 ib_flow += ((union ib_flow_spec *) ib_flow)->size; 1588 size += ret; 1589 } 1590 1591 if (mlx4_is_master(mdev->dev) && flow_type == MLX4_FS_REGULAR && 1592 flow_attr->num_of_specs == 1) { 1593 struct _rule_hw *rule_header = (struct _rule_hw *)(ctrl + 1); 1594 enum ib_flow_spec_type header_spec = 1595 ((union ib_flow_spec *)(flow_attr + 1))->type; 1596 1597 if (header_spec == IB_FLOW_SPEC_ETH) 1598 mlx4_handle_eth_header_mcast_prio(ctrl, rule_header); 1599 } 1600 1601 ret = mlx4_cmd_imm(mdev->dev, mailbox->dma, reg_id, size >> 2, 0, 1602 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A, 1603 MLX4_CMD_NATIVE); 1604 if (ret == -ENOMEM) 1605 pr_err("mcg table is full. Fail to register network rule.\n"); 1606 else if (ret == -ENXIO) 1607 pr_err("Device managed flow steering is disabled. Fail to register network rule.\n"); 1608 else if (ret) 1609 pr_err("Invalid argument. Fail to register network rule.\n"); 1610 1611 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 1612 return ret; 1613 } 1614 1615 static int __mlx4_ib_destroy_flow(struct mlx4_dev *dev, u64 reg_id) 1616 { 1617 int err; 1618 err = mlx4_cmd(dev, reg_id, 0, 0, 1619 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A, 1620 MLX4_CMD_NATIVE); 1621 if (err) 1622 pr_err("Fail to detach network rule. registration id = 0x%llx\n", 1623 reg_id); 1624 return err; 1625 } 1626 1627 static int mlx4_ib_tunnel_steer_add(struct ib_qp *qp, struct ib_flow_attr *flow_attr, 1628 u64 *reg_id) 1629 { 1630 void *ib_flow; 1631 union ib_flow_spec *ib_spec; 1632 struct mlx4_dev *dev = to_mdev(qp->device)->dev; 1633 int err = 0; 1634 1635 if (dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN || 1636 dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) 1637 return 0; /* do nothing */ 1638 1639 ib_flow = flow_attr + 1; 1640 ib_spec = (union ib_flow_spec *)ib_flow; 1641 1642 if (ib_spec->type != IB_FLOW_SPEC_ETH || flow_attr->num_of_specs != 1) 1643 return 0; /* do nothing */ 1644 1645 err = mlx4_tunnel_steer_add(to_mdev(qp->device)->dev, ib_spec->eth.val.dst_mac, 1646 flow_attr->port, qp->qp_num, 1647 MLX4_DOMAIN_UVERBS | (flow_attr->priority & 0xff), 1648 reg_id); 1649 return err; 1650 } 1651 1652 static int mlx4_ib_add_dont_trap_rule(struct mlx4_dev *dev, 1653 struct ib_flow_attr *flow_attr, 1654 enum mlx4_net_trans_promisc_mode *type) 1655 { 1656 int err = 0; 1657 1658 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER) || 1659 (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) || 1660 (flow_attr->num_of_specs > 1) || (flow_attr->priority != 0)) { 1661 return -EOPNOTSUPP; 1662 } 1663 1664 if (flow_attr->num_of_specs == 0) { 1665 type[0] = MLX4_FS_MC_SNIFFER; 1666 type[1] = MLX4_FS_UC_SNIFFER; 1667 } else { 1668 union ib_flow_spec *ib_spec; 1669 1670 ib_spec = (union ib_flow_spec *)(flow_attr + 1); 1671 if (ib_spec->type != IB_FLOW_SPEC_ETH) 1672 return -EINVAL; 1673 1674 /* if all is zero than MC and UC */ 1675 if (is_zero_ether_addr(ib_spec->eth.mask.dst_mac)) { 1676 type[0] = MLX4_FS_MC_SNIFFER; 1677 type[1] = MLX4_FS_UC_SNIFFER; 1678 } else { 1679 u8 mac[ETH_ALEN] = {ib_spec->eth.mask.dst_mac[0] ^ 0x01, 1680 ib_spec->eth.mask.dst_mac[1], 1681 ib_spec->eth.mask.dst_mac[2], 1682 ib_spec->eth.mask.dst_mac[3], 1683 ib_spec->eth.mask.dst_mac[4], 1684 ib_spec->eth.mask.dst_mac[5]}; 1685 1686 /* Above xor was only on MC bit, non empty mask is valid 1687 * only if this bit is set and rest are zero. 1688 */ 1689 if (!is_zero_ether_addr(&mac[0])) 1690 return -EINVAL; 1691 1692 if (is_multicast_ether_addr(ib_spec->eth.val.dst_mac)) 1693 type[0] = MLX4_FS_MC_SNIFFER; 1694 else 1695 type[0] = MLX4_FS_UC_SNIFFER; 1696 } 1697 } 1698 1699 return err; 1700 } 1701 1702 static struct ib_flow *mlx4_ib_create_flow(struct ib_qp *qp, 1703 struct ib_flow_attr *flow_attr, 1704 int domain, struct ib_udata *udata) 1705 { 1706 int err = 0, i = 0, j = 0; 1707 struct mlx4_ib_flow *mflow; 1708 enum mlx4_net_trans_promisc_mode type[2]; 1709 struct mlx4_dev *dev = (to_mdev(qp->device))->dev; 1710 int is_bonded = mlx4_is_bonded(dev); 1711 1712 if (flow_attr->port < 1 || flow_attr->port > qp->device->phys_port_cnt) 1713 return ERR_PTR(-EINVAL); 1714 1715 if (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP) 1716 return ERR_PTR(-EOPNOTSUPP); 1717 1718 if ((flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) && 1719 (flow_attr->type != IB_FLOW_ATTR_NORMAL)) 1720 return ERR_PTR(-EOPNOTSUPP); 1721 1722 if (udata && 1723 udata->inlen && !ib_is_udata_cleared(udata, 0, udata->inlen)) 1724 return ERR_PTR(-EOPNOTSUPP); 1725 1726 memset(type, 0, sizeof(type)); 1727 1728 mflow = kzalloc(sizeof(*mflow), GFP_KERNEL); 1729 if (!mflow) { 1730 err = -ENOMEM; 1731 goto err_free; 1732 } 1733 1734 switch (flow_attr->type) { 1735 case IB_FLOW_ATTR_NORMAL: 1736 /* If dont trap flag (continue match) is set, under specific 1737 * condition traffic be replicated to given qp, 1738 * without stealing it 1739 */ 1740 if (unlikely(flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)) { 1741 err = mlx4_ib_add_dont_trap_rule(dev, 1742 flow_attr, 1743 type); 1744 if (err) 1745 goto err_free; 1746 } else { 1747 type[0] = MLX4_FS_REGULAR; 1748 } 1749 break; 1750 1751 case IB_FLOW_ATTR_ALL_DEFAULT: 1752 type[0] = MLX4_FS_ALL_DEFAULT; 1753 break; 1754 1755 case IB_FLOW_ATTR_MC_DEFAULT: 1756 type[0] = MLX4_FS_MC_DEFAULT; 1757 break; 1758 1759 case IB_FLOW_ATTR_SNIFFER: 1760 type[0] = MLX4_FS_MIRROR_RX_PORT; 1761 type[1] = MLX4_FS_MIRROR_SX_PORT; 1762 break; 1763 1764 default: 1765 err = -EINVAL; 1766 goto err_free; 1767 } 1768 1769 while (i < ARRAY_SIZE(type) && type[i]) { 1770 err = __mlx4_ib_create_flow(qp, flow_attr, domain, type[i], 1771 &mflow->reg_id[i].id); 1772 if (err) 1773 goto err_create_flow; 1774 if (is_bonded) { 1775 /* Application always sees one port so the mirror rule 1776 * must be on port #2 1777 */ 1778 flow_attr->port = 2; 1779 err = __mlx4_ib_create_flow(qp, flow_attr, 1780 domain, type[j], 1781 &mflow->reg_id[j].mirror); 1782 flow_attr->port = 1; 1783 if (err) 1784 goto err_create_flow; 1785 j++; 1786 } 1787 1788 i++; 1789 } 1790 1791 if (i < ARRAY_SIZE(type) && flow_attr->type == IB_FLOW_ATTR_NORMAL) { 1792 err = mlx4_ib_tunnel_steer_add(qp, flow_attr, 1793 &mflow->reg_id[i].id); 1794 if (err) 1795 goto err_create_flow; 1796 1797 if (is_bonded) { 1798 flow_attr->port = 2; 1799 err = mlx4_ib_tunnel_steer_add(qp, flow_attr, 1800 &mflow->reg_id[j].mirror); 1801 flow_attr->port = 1; 1802 if (err) 1803 goto err_create_flow; 1804 j++; 1805 } 1806 /* function to create mirror rule */ 1807 i++; 1808 } 1809 1810 return &mflow->ibflow; 1811 1812 err_create_flow: 1813 while (i) { 1814 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev, 1815 mflow->reg_id[i].id); 1816 i--; 1817 } 1818 1819 while (j) { 1820 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev, 1821 mflow->reg_id[j].mirror); 1822 j--; 1823 } 1824 err_free: 1825 kfree(mflow); 1826 return ERR_PTR(err); 1827 } 1828 1829 static int mlx4_ib_destroy_flow(struct ib_flow *flow_id) 1830 { 1831 int err, ret = 0; 1832 int i = 0; 1833 struct mlx4_ib_dev *mdev = to_mdev(flow_id->qp->device); 1834 struct mlx4_ib_flow *mflow = to_mflow(flow_id); 1835 1836 while (i < ARRAY_SIZE(mflow->reg_id) && mflow->reg_id[i].id) { 1837 err = __mlx4_ib_destroy_flow(mdev->dev, mflow->reg_id[i].id); 1838 if (err) 1839 ret = err; 1840 if (mflow->reg_id[i].mirror) { 1841 err = __mlx4_ib_destroy_flow(mdev->dev, 1842 mflow->reg_id[i].mirror); 1843 if (err) 1844 ret = err; 1845 } 1846 i++; 1847 } 1848 1849 kfree(mflow); 1850 return ret; 1851 } 1852 1853 static int mlx4_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 1854 { 1855 int err; 1856 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 1857 struct mlx4_dev *dev = mdev->dev; 1858 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 1859 struct mlx4_ib_steering *ib_steering = NULL; 1860 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6; 1861 struct mlx4_flow_reg_id reg_id; 1862 1863 if (mdev->dev->caps.steering_mode == 1864 MLX4_STEERING_MODE_DEVICE_MANAGED) { 1865 ib_steering = kmalloc(sizeof(*ib_steering), GFP_KERNEL); 1866 if (!ib_steering) 1867 return -ENOMEM; 1868 } 1869 1870 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, mqp->port, 1871 !!(mqp->flags & 1872 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK), 1873 prot, ®_id.id); 1874 if (err) { 1875 pr_err("multicast attach op failed, err %d\n", err); 1876 goto err_malloc; 1877 } 1878 1879 reg_id.mirror = 0; 1880 if (mlx4_is_bonded(dev)) { 1881 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, 1882 (mqp->port == 1) ? 2 : 1, 1883 !!(mqp->flags & 1884 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK), 1885 prot, ®_id.mirror); 1886 if (err) 1887 goto err_add; 1888 } 1889 1890 err = add_gid_entry(ibqp, gid); 1891 if (err) 1892 goto err_add; 1893 1894 if (ib_steering) { 1895 memcpy(ib_steering->gid.raw, gid->raw, 16); 1896 ib_steering->reg_id = reg_id; 1897 mutex_lock(&mqp->mutex); 1898 list_add(&ib_steering->list, &mqp->steering_rules); 1899 mutex_unlock(&mqp->mutex); 1900 } 1901 return 0; 1902 1903 err_add: 1904 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 1905 prot, reg_id.id); 1906 if (reg_id.mirror) 1907 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 1908 prot, reg_id.mirror); 1909 err_malloc: 1910 kfree(ib_steering); 1911 1912 return err; 1913 } 1914 1915 static struct mlx4_ib_gid_entry *find_gid_entry(struct mlx4_ib_qp *qp, u8 *raw) 1916 { 1917 struct mlx4_ib_gid_entry *ge; 1918 struct mlx4_ib_gid_entry *tmp; 1919 struct mlx4_ib_gid_entry *ret = NULL; 1920 1921 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { 1922 if (!memcmp(raw, ge->gid.raw, 16)) { 1923 ret = ge; 1924 break; 1925 } 1926 } 1927 1928 return ret; 1929 } 1930 1931 static int mlx4_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 1932 { 1933 int err; 1934 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 1935 struct mlx4_dev *dev = mdev->dev; 1936 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 1937 struct net_device *ndev; 1938 struct mlx4_ib_gid_entry *ge; 1939 struct mlx4_flow_reg_id reg_id = {0, 0}; 1940 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6; 1941 1942 if (mdev->dev->caps.steering_mode == 1943 MLX4_STEERING_MODE_DEVICE_MANAGED) { 1944 struct mlx4_ib_steering *ib_steering; 1945 1946 mutex_lock(&mqp->mutex); 1947 list_for_each_entry(ib_steering, &mqp->steering_rules, list) { 1948 if (!memcmp(ib_steering->gid.raw, gid->raw, 16)) { 1949 list_del(&ib_steering->list); 1950 break; 1951 } 1952 } 1953 mutex_unlock(&mqp->mutex); 1954 if (&ib_steering->list == &mqp->steering_rules) { 1955 pr_err("Couldn't find reg_id for mgid. Steering rule is left attached\n"); 1956 return -EINVAL; 1957 } 1958 reg_id = ib_steering->reg_id; 1959 kfree(ib_steering); 1960 } 1961 1962 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 1963 prot, reg_id.id); 1964 if (err) 1965 return err; 1966 1967 if (mlx4_is_bonded(dev)) { 1968 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw, 1969 prot, reg_id.mirror); 1970 if (err) 1971 return err; 1972 } 1973 1974 mutex_lock(&mqp->mutex); 1975 ge = find_gid_entry(mqp, gid->raw); 1976 if (ge) { 1977 spin_lock_bh(&mdev->iboe.lock); 1978 ndev = ge->added ? mdev->iboe.netdevs[ge->port - 1] : NULL; 1979 if (ndev) 1980 dev_hold(ndev); 1981 spin_unlock_bh(&mdev->iboe.lock); 1982 if (ndev) 1983 dev_put(ndev); 1984 list_del(&ge->list); 1985 kfree(ge); 1986 } else 1987 pr_warn("could not find mgid entry\n"); 1988 1989 mutex_unlock(&mqp->mutex); 1990 1991 return 0; 1992 } 1993 1994 static int init_node_data(struct mlx4_ib_dev *dev) 1995 { 1996 struct ib_smp *in_mad = NULL; 1997 struct ib_smp *out_mad = NULL; 1998 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS; 1999 int err = -ENOMEM; 2000 2001 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 2002 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 2003 if (!in_mad || !out_mad) 2004 goto out; 2005 2006 init_query_mad(in_mad); 2007 in_mad->attr_id = IB_SMP_ATTR_NODE_DESC; 2008 if (mlx4_is_master(dev->dev)) 2009 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW; 2010 2011 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad); 2012 if (err) 2013 goto out; 2014 2015 memcpy(dev->ib_dev.node_desc, out_mad->data, IB_DEVICE_NODE_DESC_MAX); 2016 2017 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO; 2018 2019 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad); 2020 if (err) 2021 goto out; 2022 2023 dev->dev->rev_id = be32_to_cpup((__be32 *) (out_mad->data + 32)); 2024 memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8); 2025 2026 out: 2027 kfree(in_mad); 2028 kfree(out_mad); 2029 return err; 2030 } 2031 2032 static ssize_t hca_type_show(struct device *device, 2033 struct device_attribute *attr, char *buf) 2034 { 2035 struct mlx4_ib_dev *dev = 2036 rdma_device_to_drv_device(device, struct mlx4_ib_dev, ib_dev); 2037 return sprintf(buf, "MT%d\n", dev->dev->persist->pdev->device); 2038 } 2039 static DEVICE_ATTR_RO(hca_type); 2040 2041 static ssize_t hw_rev_show(struct device *device, 2042 struct device_attribute *attr, char *buf) 2043 { 2044 struct mlx4_ib_dev *dev = 2045 rdma_device_to_drv_device(device, struct mlx4_ib_dev, ib_dev); 2046 return sprintf(buf, "%x\n", dev->dev->rev_id); 2047 } 2048 static DEVICE_ATTR_RO(hw_rev); 2049 2050 static ssize_t board_id_show(struct device *device, 2051 struct device_attribute *attr, char *buf) 2052 { 2053 struct mlx4_ib_dev *dev = 2054 rdma_device_to_drv_device(device, struct mlx4_ib_dev, ib_dev); 2055 2056 return sprintf(buf, "%.*s\n", MLX4_BOARD_ID_LEN, 2057 dev->dev->board_id); 2058 } 2059 static DEVICE_ATTR_RO(board_id); 2060 2061 static struct attribute *mlx4_class_attributes[] = { 2062 &dev_attr_hw_rev.attr, 2063 &dev_attr_hca_type.attr, 2064 &dev_attr_board_id.attr, 2065 NULL 2066 }; 2067 2068 static const struct attribute_group mlx4_attr_group = { 2069 .attrs = mlx4_class_attributes, 2070 }; 2071 2072 struct diag_counter { 2073 const char *name; 2074 u32 offset; 2075 }; 2076 2077 #define DIAG_COUNTER(_name, _offset) \ 2078 { .name = #_name, .offset = _offset } 2079 2080 static const struct diag_counter diag_basic[] = { 2081 DIAG_COUNTER(rq_num_lle, 0x00), 2082 DIAG_COUNTER(sq_num_lle, 0x04), 2083 DIAG_COUNTER(rq_num_lqpoe, 0x08), 2084 DIAG_COUNTER(sq_num_lqpoe, 0x0C), 2085 DIAG_COUNTER(rq_num_lpe, 0x18), 2086 DIAG_COUNTER(sq_num_lpe, 0x1C), 2087 DIAG_COUNTER(rq_num_wrfe, 0x20), 2088 DIAG_COUNTER(sq_num_wrfe, 0x24), 2089 DIAG_COUNTER(sq_num_mwbe, 0x2C), 2090 DIAG_COUNTER(sq_num_bre, 0x34), 2091 DIAG_COUNTER(sq_num_rire, 0x44), 2092 DIAG_COUNTER(rq_num_rire, 0x48), 2093 DIAG_COUNTER(sq_num_rae, 0x4C), 2094 DIAG_COUNTER(rq_num_rae, 0x50), 2095 DIAG_COUNTER(sq_num_roe, 0x54), 2096 DIAG_COUNTER(sq_num_tree, 0x5C), 2097 DIAG_COUNTER(sq_num_rree, 0x64), 2098 DIAG_COUNTER(rq_num_rnr, 0x68), 2099 DIAG_COUNTER(sq_num_rnr, 0x6C), 2100 DIAG_COUNTER(rq_num_oos, 0x100), 2101 DIAG_COUNTER(sq_num_oos, 0x104), 2102 }; 2103 2104 static const struct diag_counter diag_ext[] = { 2105 DIAG_COUNTER(rq_num_dup, 0x130), 2106 DIAG_COUNTER(sq_num_to, 0x134), 2107 }; 2108 2109 static const struct diag_counter diag_device_only[] = { 2110 DIAG_COUNTER(num_cqovf, 0x1A0), 2111 DIAG_COUNTER(rq_num_udsdprd, 0x118), 2112 }; 2113 2114 static struct rdma_hw_stats *mlx4_ib_alloc_hw_stats(struct ib_device *ibdev, 2115 u8 port_num) 2116 { 2117 struct mlx4_ib_dev *dev = to_mdev(ibdev); 2118 struct mlx4_ib_diag_counters *diag = dev->diag_counters; 2119 2120 if (!diag[!!port_num].name) 2121 return NULL; 2122 2123 return rdma_alloc_hw_stats_struct(diag[!!port_num].name, 2124 diag[!!port_num].num_counters, 2125 RDMA_HW_STATS_DEFAULT_LIFESPAN); 2126 } 2127 2128 static int mlx4_ib_get_hw_stats(struct ib_device *ibdev, 2129 struct rdma_hw_stats *stats, 2130 u8 port, int index) 2131 { 2132 struct mlx4_ib_dev *dev = to_mdev(ibdev); 2133 struct mlx4_ib_diag_counters *diag = dev->diag_counters; 2134 u32 hw_value[ARRAY_SIZE(diag_device_only) + 2135 ARRAY_SIZE(diag_ext) + ARRAY_SIZE(diag_basic)] = {}; 2136 int ret; 2137 int i; 2138 2139 ret = mlx4_query_diag_counters(dev->dev, 2140 MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS, 2141 diag[!!port].offset, hw_value, 2142 diag[!!port].num_counters, port); 2143 2144 if (ret) 2145 return ret; 2146 2147 for (i = 0; i < diag[!!port].num_counters; i++) 2148 stats->value[i] = hw_value[i]; 2149 2150 return diag[!!port].num_counters; 2151 } 2152 2153 static int __mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev, 2154 const char ***name, 2155 u32 **offset, 2156 u32 *num, 2157 bool port) 2158 { 2159 u32 num_counters; 2160 2161 num_counters = ARRAY_SIZE(diag_basic); 2162 2163 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) 2164 num_counters += ARRAY_SIZE(diag_ext); 2165 2166 if (!port) 2167 num_counters += ARRAY_SIZE(diag_device_only); 2168 2169 *name = kcalloc(num_counters, sizeof(**name), GFP_KERNEL); 2170 if (!*name) 2171 return -ENOMEM; 2172 2173 *offset = kcalloc(num_counters, sizeof(**offset), GFP_KERNEL); 2174 if (!*offset) 2175 goto err_name; 2176 2177 *num = num_counters; 2178 2179 return 0; 2180 2181 err_name: 2182 kfree(*name); 2183 return -ENOMEM; 2184 } 2185 2186 static void mlx4_ib_fill_diag_counters(struct mlx4_ib_dev *ibdev, 2187 const char **name, 2188 u32 *offset, 2189 bool port) 2190 { 2191 int i; 2192 int j; 2193 2194 for (i = 0, j = 0; i < ARRAY_SIZE(diag_basic); i++, j++) { 2195 name[i] = diag_basic[i].name; 2196 offset[i] = diag_basic[i].offset; 2197 } 2198 2199 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) { 2200 for (i = 0; i < ARRAY_SIZE(diag_ext); i++, j++) { 2201 name[j] = diag_ext[i].name; 2202 offset[j] = diag_ext[i].offset; 2203 } 2204 } 2205 2206 if (!port) { 2207 for (i = 0; i < ARRAY_SIZE(diag_device_only); i++, j++) { 2208 name[j] = diag_device_only[i].name; 2209 offset[j] = diag_device_only[i].offset; 2210 } 2211 } 2212 } 2213 2214 static const struct ib_device_ops mlx4_ib_hw_stats_ops = { 2215 .alloc_hw_stats = mlx4_ib_alloc_hw_stats, 2216 .get_hw_stats = mlx4_ib_get_hw_stats, 2217 }; 2218 2219 static int mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev) 2220 { 2221 struct mlx4_ib_diag_counters *diag = ibdev->diag_counters; 2222 int i; 2223 int ret; 2224 bool per_port = !!(ibdev->dev->caps.flags2 & 2225 MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT); 2226 2227 if (mlx4_is_slave(ibdev->dev)) 2228 return 0; 2229 2230 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) { 2231 /* i == 1 means we are building port counters */ 2232 if (i && !per_port) 2233 continue; 2234 2235 ret = __mlx4_ib_alloc_diag_counters(ibdev, &diag[i].name, 2236 &diag[i].offset, 2237 &diag[i].num_counters, i); 2238 if (ret) 2239 goto err_alloc; 2240 2241 mlx4_ib_fill_diag_counters(ibdev, diag[i].name, 2242 diag[i].offset, i); 2243 } 2244 2245 ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_hw_stats_ops); 2246 2247 return 0; 2248 2249 err_alloc: 2250 if (i) { 2251 kfree(diag[i - 1].name); 2252 kfree(diag[i - 1].offset); 2253 } 2254 2255 return ret; 2256 } 2257 2258 static void mlx4_ib_diag_cleanup(struct mlx4_ib_dev *ibdev) 2259 { 2260 int i; 2261 2262 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) { 2263 kfree(ibdev->diag_counters[i].offset); 2264 kfree(ibdev->diag_counters[i].name); 2265 } 2266 } 2267 2268 #define MLX4_IB_INVALID_MAC ((u64)-1) 2269 static void mlx4_ib_update_qps(struct mlx4_ib_dev *ibdev, 2270 struct net_device *dev, 2271 int port) 2272 { 2273 u64 new_smac = 0; 2274 u64 release_mac = MLX4_IB_INVALID_MAC; 2275 struct mlx4_ib_qp *qp; 2276 2277 read_lock(&dev_base_lock); 2278 new_smac = mlx4_mac_to_u64(dev->dev_addr); 2279 read_unlock(&dev_base_lock); 2280 2281 atomic64_set(&ibdev->iboe.mac[port - 1], new_smac); 2282 2283 /* no need for update QP1 and mac registration in non-SRIOV */ 2284 if (!mlx4_is_mfunc(ibdev->dev)) 2285 return; 2286 2287 mutex_lock(&ibdev->qp1_proxy_lock[port - 1]); 2288 qp = ibdev->qp1_proxy[port - 1]; 2289 if (qp) { 2290 int new_smac_index; 2291 u64 old_smac; 2292 struct mlx4_update_qp_params update_params; 2293 2294 mutex_lock(&qp->mutex); 2295 old_smac = qp->pri.smac; 2296 if (new_smac == old_smac) 2297 goto unlock; 2298 2299 new_smac_index = mlx4_register_mac(ibdev->dev, port, new_smac); 2300 2301 if (new_smac_index < 0) 2302 goto unlock; 2303 2304 update_params.smac_index = new_smac_index; 2305 if (mlx4_update_qp(ibdev->dev, qp->mqp.qpn, MLX4_UPDATE_QP_SMAC, 2306 &update_params)) { 2307 release_mac = new_smac; 2308 goto unlock; 2309 } 2310 /* if old port was zero, no mac was yet registered for this QP */ 2311 if (qp->pri.smac_port) 2312 release_mac = old_smac; 2313 qp->pri.smac = new_smac; 2314 qp->pri.smac_port = port; 2315 qp->pri.smac_index = new_smac_index; 2316 } 2317 2318 unlock: 2319 if (release_mac != MLX4_IB_INVALID_MAC) 2320 mlx4_unregister_mac(ibdev->dev, port, release_mac); 2321 if (qp) 2322 mutex_unlock(&qp->mutex); 2323 mutex_unlock(&ibdev->qp1_proxy_lock[port - 1]); 2324 } 2325 2326 static void mlx4_ib_scan_netdevs(struct mlx4_ib_dev *ibdev, 2327 struct net_device *dev, 2328 unsigned long event) 2329 2330 { 2331 struct mlx4_ib_iboe *iboe; 2332 int update_qps_port = -1; 2333 int port; 2334 2335 ASSERT_RTNL(); 2336 2337 iboe = &ibdev->iboe; 2338 2339 spin_lock_bh(&iboe->lock); 2340 mlx4_foreach_ib_transport_port(port, ibdev->dev) { 2341 2342 iboe->netdevs[port - 1] = 2343 mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port); 2344 2345 if (dev == iboe->netdevs[port - 1] && 2346 (event == NETDEV_CHANGEADDR || event == NETDEV_REGISTER || 2347 event == NETDEV_UP || event == NETDEV_CHANGE)) 2348 update_qps_port = port; 2349 2350 if (dev == iboe->netdevs[port - 1] && 2351 (event == NETDEV_UP || event == NETDEV_DOWN)) { 2352 enum ib_port_state port_state; 2353 struct ib_event ibev = { }; 2354 2355 if (ib_get_cached_port_state(&ibdev->ib_dev, port, 2356 &port_state)) 2357 continue; 2358 2359 if (event == NETDEV_UP && 2360 (port_state != IB_PORT_ACTIVE || 2361 iboe->last_port_state[port - 1] != IB_PORT_DOWN)) 2362 continue; 2363 if (event == NETDEV_DOWN && 2364 (port_state != IB_PORT_DOWN || 2365 iboe->last_port_state[port - 1] != IB_PORT_ACTIVE)) 2366 continue; 2367 iboe->last_port_state[port - 1] = port_state; 2368 2369 ibev.device = &ibdev->ib_dev; 2370 ibev.element.port_num = port; 2371 ibev.event = event == NETDEV_UP ? IB_EVENT_PORT_ACTIVE : 2372 IB_EVENT_PORT_ERR; 2373 ib_dispatch_event(&ibev); 2374 } 2375 2376 } 2377 spin_unlock_bh(&iboe->lock); 2378 2379 if (update_qps_port > 0) 2380 mlx4_ib_update_qps(ibdev, dev, update_qps_port); 2381 } 2382 2383 static int mlx4_ib_netdev_event(struct notifier_block *this, 2384 unsigned long event, void *ptr) 2385 { 2386 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 2387 struct mlx4_ib_dev *ibdev; 2388 2389 if (!net_eq(dev_net(dev), &init_net)) 2390 return NOTIFY_DONE; 2391 2392 ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb); 2393 mlx4_ib_scan_netdevs(ibdev, dev, event); 2394 2395 return NOTIFY_DONE; 2396 } 2397 2398 static void init_pkeys(struct mlx4_ib_dev *ibdev) 2399 { 2400 int port; 2401 int slave; 2402 int i; 2403 2404 if (mlx4_is_master(ibdev->dev)) { 2405 for (slave = 0; slave <= ibdev->dev->persist->num_vfs; 2406 ++slave) { 2407 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) { 2408 for (i = 0; 2409 i < ibdev->dev->phys_caps.pkey_phys_table_len[port]; 2410 ++i) { 2411 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i] = 2412 /* master has the identity virt2phys pkey mapping */ 2413 (slave == mlx4_master_func_num(ibdev->dev) || !i) ? i : 2414 ibdev->dev->phys_caps.pkey_phys_table_len[port] - 1; 2415 mlx4_sync_pkey_table(ibdev->dev, slave, port, i, 2416 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i]); 2417 } 2418 } 2419 } 2420 /* initialize pkey cache */ 2421 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) { 2422 for (i = 0; 2423 i < ibdev->dev->phys_caps.pkey_phys_table_len[port]; 2424 ++i) 2425 ibdev->pkeys.phys_pkey_cache[port-1][i] = 2426 (i) ? 0 : 0xFFFF; 2427 } 2428 } 2429 } 2430 2431 static void mlx4_ib_alloc_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev) 2432 { 2433 int i, j, eq = 0, total_eqs = 0; 2434 2435 ibdev->eq_table = kcalloc(dev->caps.num_comp_vectors, 2436 sizeof(ibdev->eq_table[0]), GFP_KERNEL); 2437 if (!ibdev->eq_table) 2438 return; 2439 2440 for (i = 1; i <= dev->caps.num_ports; i++) { 2441 for (j = 0; j < mlx4_get_eqs_per_port(dev, i); 2442 j++, total_eqs++) { 2443 if (i > 1 && mlx4_is_eq_shared(dev, total_eqs)) 2444 continue; 2445 ibdev->eq_table[eq] = total_eqs; 2446 if (!mlx4_assign_eq(dev, i, 2447 &ibdev->eq_table[eq])) 2448 eq++; 2449 else 2450 ibdev->eq_table[eq] = -1; 2451 } 2452 } 2453 2454 for (i = eq; i < dev->caps.num_comp_vectors; 2455 ibdev->eq_table[i++] = -1) 2456 ; 2457 2458 /* Advertise the new number of EQs to clients */ 2459 ibdev->ib_dev.num_comp_vectors = eq; 2460 } 2461 2462 static void mlx4_ib_free_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev) 2463 { 2464 int i; 2465 int total_eqs = ibdev->ib_dev.num_comp_vectors; 2466 2467 /* no eqs were allocated */ 2468 if (!ibdev->eq_table) 2469 return; 2470 2471 /* Reset the advertised EQ number */ 2472 ibdev->ib_dev.num_comp_vectors = 0; 2473 2474 for (i = 0; i < total_eqs; i++) 2475 mlx4_release_eq(dev, ibdev->eq_table[i]); 2476 2477 kfree(ibdev->eq_table); 2478 ibdev->eq_table = NULL; 2479 } 2480 2481 static int mlx4_port_immutable(struct ib_device *ibdev, u8 port_num, 2482 struct ib_port_immutable *immutable) 2483 { 2484 struct ib_port_attr attr; 2485 struct mlx4_ib_dev *mdev = to_mdev(ibdev); 2486 int err; 2487 2488 if (mlx4_ib_port_link_layer(ibdev, port_num) == IB_LINK_LAYER_INFINIBAND) { 2489 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_IB; 2490 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2491 } else { 2492 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE) 2493 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; 2494 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) 2495 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE | 2496 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 2497 immutable->core_cap_flags |= RDMA_CORE_PORT_RAW_PACKET; 2498 if (immutable->core_cap_flags & (RDMA_CORE_PORT_IBA_ROCE | 2499 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP)) 2500 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2501 } 2502 2503 err = ib_query_port(ibdev, port_num, &attr); 2504 if (err) 2505 return err; 2506 2507 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2508 immutable->gid_tbl_len = attr.gid_tbl_len; 2509 2510 return 0; 2511 } 2512 2513 static void get_fw_ver_str(struct ib_device *device, char *str) 2514 { 2515 struct mlx4_ib_dev *dev = 2516 container_of(device, struct mlx4_ib_dev, ib_dev); 2517 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d", 2518 (int) (dev->dev->caps.fw_ver >> 32), 2519 (int) (dev->dev->caps.fw_ver >> 16) & 0xffff, 2520 (int) dev->dev->caps.fw_ver & 0xffff); 2521 } 2522 2523 static const struct ib_device_ops mlx4_ib_dev_ops = { 2524 .owner = THIS_MODULE, 2525 .driver_id = RDMA_DRIVER_MLX4, 2526 .uverbs_abi_ver = MLX4_IB_UVERBS_ABI_VERSION, 2527 2528 .add_gid = mlx4_ib_add_gid, 2529 .alloc_mr = mlx4_ib_alloc_mr, 2530 .alloc_pd = mlx4_ib_alloc_pd, 2531 .alloc_ucontext = mlx4_ib_alloc_ucontext, 2532 .attach_mcast = mlx4_ib_mcg_attach, 2533 .create_ah = mlx4_ib_create_ah, 2534 .create_cq = mlx4_ib_create_cq, 2535 .create_qp = mlx4_ib_create_qp, 2536 .create_srq = mlx4_ib_create_srq, 2537 .dealloc_pd = mlx4_ib_dealloc_pd, 2538 .dealloc_ucontext = mlx4_ib_dealloc_ucontext, 2539 .del_gid = mlx4_ib_del_gid, 2540 .dereg_mr = mlx4_ib_dereg_mr, 2541 .destroy_ah = mlx4_ib_destroy_ah, 2542 .destroy_cq = mlx4_ib_destroy_cq, 2543 .destroy_qp = mlx4_ib_destroy_qp, 2544 .destroy_srq = mlx4_ib_destroy_srq, 2545 .detach_mcast = mlx4_ib_mcg_detach, 2546 .disassociate_ucontext = mlx4_ib_disassociate_ucontext, 2547 .drain_rq = mlx4_ib_drain_rq, 2548 .drain_sq = mlx4_ib_drain_sq, 2549 .get_dev_fw_str = get_fw_ver_str, 2550 .get_dma_mr = mlx4_ib_get_dma_mr, 2551 .get_link_layer = mlx4_ib_port_link_layer, 2552 .get_netdev = mlx4_ib_get_netdev, 2553 .get_port_immutable = mlx4_port_immutable, 2554 .map_mr_sg = mlx4_ib_map_mr_sg, 2555 .mmap = mlx4_ib_mmap, 2556 .modify_cq = mlx4_ib_modify_cq, 2557 .modify_device = mlx4_ib_modify_device, 2558 .modify_port = mlx4_ib_modify_port, 2559 .modify_qp = mlx4_ib_modify_qp, 2560 .modify_srq = mlx4_ib_modify_srq, 2561 .poll_cq = mlx4_ib_poll_cq, 2562 .post_recv = mlx4_ib_post_recv, 2563 .post_send = mlx4_ib_post_send, 2564 .post_srq_recv = mlx4_ib_post_srq_recv, 2565 .process_mad = mlx4_ib_process_mad, 2566 .query_ah = mlx4_ib_query_ah, 2567 .query_device = mlx4_ib_query_device, 2568 .query_gid = mlx4_ib_query_gid, 2569 .query_pkey = mlx4_ib_query_pkey, 2570 .query_port = mlx4_ib_query_port, 2571 .query_qp = mlx4_ib_query_qp, 2572 .query_srq = mlx4_ib_query_srq, 2573 .reg_user_mr = mlx4_ib_reg_user_mr, 2574 .req_notify_cq = mlx4_ib_arm_cq, 2575 .rereg_user_mr = mlx4_ib_rereg_user_mr, 2576 .resize_cq = mlx4_ib_resize_cq, 2577 2578 INIT_RDMA_OBJ_SIZE(ib_ah, mlx4_ib_ah, ibah), 2579 INIT_RDMA_OBJ_SIZE(ib_cq, mlx4_ib_cq, ibcq), 2580 INIT_RDMA_OBJ_SIZE(ib_pd, mlx4_ib_pd, ibpd), 2581 INIT_RDMA_OBJ_SIZE(ib_srq, mlx4_ib_srq, ibsrq), 2582 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx4_ib_ucontext, ibucontext), 2583 }; 2584 2585 static const struct ib_device_ops mlx4_ib_dev_wq_ops = { 2586 .create_rwq_ind_table = mlx4_ib_create_rwq_ind_table, 2587 .create_wq = mlx4_ib_create_wq, 2588 .destroy_rwq_ind_table = mlx4_ib_destroy_rwq_ind_table, 2589 .destroy_wq = mlx4_ib_destroy_wq, 2590 .modify_wq = mlx4_ib_modify_wq, 2591 }; 2592 2593 static const struct ib_device_ops mlx4_ib_dev_mw_ops = { 2594 .alloc_mw = mlx4_ib_alloc_mw, 2595 .dealloc_mw = mlx4_ib_dealloc_mw, 2596 }; 2597 2598 static const struct ib_device_ops mlx4_ib_dev_xrc_ops = { 2599 .alloc_xrcd = mlx4_ib_alloc_xrcd, 2600 .dealloc_xrcd = mlx4_ib_dealloc_xrcd, 2601 2602 INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx4_ib_xrcd, ibxrcd), 2603 }; 2604 2605 static const struct ib_device_ops mlx4_ib_dev_fs_ops = { 2606 .create_flow = mlx4_ib_create_flow, 2607 .destroy_flow = mlx4_ib_destroy_flow, 2608 }; 2609 2610 static void *mlx4_ib_add(struct mlx4_dev *dev) 2611 { 2612 struct mlx4_ib_dev *ibdev; 2613 int num_ports = 0; 2614 int i, j; 2615 int err; 2616 struct mlx4_ib_iboe *iboe; 2617 int ib_num_ports = 0; 2618 int num_req_counters; 2619 int allocated; 2620 u32 counter_index; 2621 struct counter_index *new_counter_index = NULL; 2622 2623 pr_info_once("%s", mlx4_ib_version); 2624 2625 num_ports = 0; 2626 mlx4_foreach_ib_transport_port(i, dev) 2627 num_ports++; 2628 2629 /* No point in registering a device with no ports... */ 2630 if (num_ports == 0) 2631 return NULL; 2632 2633 ibdev = ib_alloc_device(mlx4_ib_dev, ib_dev); 2634 if (!ibdev) { 2635 dev_err(&dev->persist->pdev->dev, 2636 "Device struct alloc failed\n"); 2637 return NULL; 2638 } 2639 2640 iboe = &ibdev->iboe; 2641 2642 if (mlx4_pd_alloc(dev, &ibdev->priv_pdn)) 2643 goto err_dealloc; 2644 2645 if (mlx4_uar_alloc(dev, &ibdev->priv_uar)) 2646 goto err_pd; 2647 2648 ibdev->uar_map = ioremap((phys_addr_t) ibdev->priv_uar.pfn << PAGE_SHIFT, 2649 PAGE_SIZE); 2650 if (!ibdev->uar_map) 2651 goto err_uar; 2652 MLX4_INIT_DOORBELL_LOCK(&ibdev->uar_lock); 2653 2654 ibdev->dev = dev; 2655 ibdev->bond_next_port = 0; 2656 2657 ibdev->ib_dev.node_type = RDMA_NODE_IB_CA; 2658 ibdev->ib_dev.local_dma_lkey = dev->caps.reserved_lkey; 2659 ibdev->num_ports = num_ports; 2660 ibdev->ib_dev.phys_port_cnt = mlx4_is_bonded(dev) ? 2661 1 : ibdev->num_ports; 2662 ibdev->ib_dev.num_comp_vectors = dev->caps.num_comp_vectors; 2663 ibdev->ib_dev.dev.parent = &dev->persist->pdev->dev; 2664 2665 ibdev->ib_dev.uverbs_cmd_mask = 2666 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 2667 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 2668 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 2669 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 2670 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 2671 (1ull << IB_USER_VERBS_CMD_REG_MR) | 2672 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 2673 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 2674 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 2675 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 2676 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 2677 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 2678 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 2679 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 2680 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 2681 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 2682 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 2683 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 2684 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 2685 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 2686 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 2687 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 2688 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 2689 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 2690 2691 ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_dev_ops); 2692 ibdev->ib_dev.uverbs_ex_cmd_mask |= 2693 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ) | 2694 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 2695 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 2696 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP); 2697 2698 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) && 2699 ((mlx4_ib_port_link_layer(&ibdev->ib_dev, 1) == 2700 IB_LINK_LAYER_ETHERNET) || 2701 (mlx4_ib_port_link_layer(&ibdev->ib_dev, 2) == 2702 IB_LINK_LAYER_ETHERNET))) { 2703 ibdev->ib_dev.uverbs_ex_cmd_mask |= 2704 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 2705 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 2706 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 2707 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 2708 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 2709 ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_dev_wq_ops); 2710 } 2711 2712 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW || 2713 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) { 2714 ibdev->ib_dev.uverbs_cmd_mask |= 2715 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 2716 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 2717 ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_dev_mw_ops); 2718 } 2719 2720 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) { 2721 ibdev->ib_dev.uverbs_cmd_mask |= 2722 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 2723 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 2724 ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_dev_xrc_ops); 2725 } 2726 2727 if (check_flow_steering_support(dev)) { 2728 ibdev->steering_support = MLX4_STEERING_MODE_DEVICE_MANAGED; 2729 ibdev->ib_dev.uverbs_ex_cmd_mask |= 2730 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 2731 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); 2732 ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_dev_fs_ops); 2733 } 2734 2735 if (!dev->caps.userspace_caps) 2736 ibdev->ib_dev.ops.uverbs_abi_ver = 2737 MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION; 2738 2739 mlx4_ib_alloc_eqs(dev, ibdev); 2740 2741 spin_lock_init(&iboe->lock); 2742 2743 if (init_node_data(ibdev)) 2744 goto err_map; 2745 mlx4_init_sl2vl_tbl(ibdev); 2746 2747 for (i = 0; i < ibdev->num_ports; ++i) { 2748 mutex_init(&ibdev->counters_table[i].mutex); 2749 INIT_LIST_HEAD(&ibdev->counters_table[i].counters_list); 2750 iboe->last_port_state[i] = IB_PORT_DOWN; 2751 } 2752 2753 num_req_counters = mlx4_is_bonded(dev) ? 1 : ibdev->num_ports; 2754 for (i = 0; i < num_req_counters; ++i) { 2755 mutex_init(&ibdev->qp1_proxy_lock[i]); 2756 allocated = 0; 2757 if (mlx4_ib_port_link_layer(&ibdev->ib_dev, i + 1) == 2758 IB_LINK_LAYER_ETHERNET) { 2759 err = mlx4_counter_alloc(ibdev->dev, &counter_index, 2760 MLX4_RES_USAGE_DRIVER); 2761 /* if failed to allocate a new counter, use default */ 2762 if (err) 2763 counter_index = 2764 mlx4_get_default_counter_index(dev, 2765 i + 1); 2766 else 2767 allocated = 1; 2768 } else { /* IB_LINK_LAYER_INFINIBAND use the default counter */ 2769 counter_index = mlx4_get_default_counter_index(dev, 2770 i + 1); 2771 } 2772 new_counter_index = kmalloc(sizeof(*new_counter_index), 2773 GFP_KERNEL); 2774 if (!new_counter_index) { 2775 if (allocated) 2776 mlx4_counter_free(ibdev->dev, counter_index); 2777 goto err_counter; 2778 } 2779 new_counter_index->index = counter_index; 2780 new_counter_index->allocated = allocated; 2781 list_add_tail(&new_counter_index->list, 2782 &ibdev->counters_table[i].counters_list); 2783 ibdev->counters_table[i].default_counter = counter_index; 2784 pr_info("counter index %d for port %d allocated %d\n", 2785 counter_index, i + 1, allocated); 2786 } 2787 if (mlx4_is_bonded(dev)) 2788 for (i = 1; i < ibdev->num_ports ; ++i) { 2789 new_counter_index = 2790 kmalloc(sizeof(struct counter_index), 2791 GFP_KERNEL); 2792 if (!new_counter_index) 2793 goto err_counter; 2794 new_counter_index->index = counter_index; 2795 new_counter_index->allocated = 0; 2796 list_add_tail(&new_counter_index->list, 2797 &ibdev->counters_table[i].counters_list); 2798 ibdev->counters_table[i].default_counter = 2799 counter_index; 2800 } 2801 2802 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 2803 ib_num_ports++; 2804 2805 spin_lock_init(&ibdev->sm_lock); 2806 mutex_init(&ibdev->cap_mask_mutex); 2807 INIT_LIST_HEAD(&ibdev->qp_list); 2808 spin_lock_init(&ibdev->reset_flow_resource_lock); 2809 2810 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED && 2811 ib_num_ports) { 2812 ibdev->steer_qpn_count = MLX4_IB_UC_MAX_NUM_QPS; 2813 err = mlx4_qp_reserve_range(dev, ibdev->steer_qpn_count, 2814 MLX4_IB_UC_STEER_QPN_ALIGN, 2815 &ibdev->steer_qpn_base, 0, 2816 MLX4_RES_USAGE_DRIVER); 2817 if (err) 2818 goto err_counter; 2819 2820 ibdev->ib_uc_qpns_bitmap = 2821 kmalloc_array(BITS_TO_LONGS(ibdev->steer_qpn_count), 2822 sizeof(long), 2823 GFP_KERNEL); 2824 if (!ibdev->ib_uc_qpns_bitmap) 2825 goto err_steer_qp_release; 2826 2827 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB) { 2828 bitmap_zero(ibdev->ib_uc_qpns_bitmap, 2829 ibdev->steer_qpn_count); 2830 err = mlx4_FLOW_STEERING_IB_UC_QP_RANGE( 2831 dev, ibdev->steer_qpn_base, 2832 ibdev->steer_qpn_base + 2833 ibdev->steer_qpn_count - 1); 2834 if (err) 2835 goto err_steer_free_bitmap; 2836 } else { 2837 bitmap_fill(ibdev->ib_uc_qpns_bitmap, 2838 ibdev->steer_qpn_count); 2839 } 2840 } 2841 2842 for (j = 1; j <= ibdev->dev->caps.num_ports; j++) 2843 atomic64_set(&iboe->mac[j - 1], ibdev->dev->caps.def_mac[j]); 2844 2845 if (mlx4_ib_alloc_diag_counters(ibdev)) 2846 goto err_steer_free_bitmap; 2847 2848 rdma_set_device_sysfs_group(&ibdev->ib_dev, &mlx4_attr_group); 2849 if (ib_register_device(&ibdev->ib_dev, "mlx4_%d")) 2850 goto err_diag_counters; 2851 2852 if (mlx4_ib_mad_init(ibdev)) 2853 goto err_reg; 2854 2855 if (mlx4_ib_init_sriov(ibdev)) 2856 goto err_mad; 2857 2858 if (!iboe->nb.notifier_call) { 2859 iboe->nb.notifier_call = mlx4_ib_netdev_event; 2860 err = register_netdevice_notifier(&iboe->nb); 2861 if (err) { 2862 iboe->nb.notifier_call = NULL; 2863 goto err_notif; 2864 } 2865 } 2866 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) { 2867 err = mlx4_config_roce_v2_port(dev, ROCE_V2_UDP_DPORT); 2868 if (err) 2869 goto err_notif; 2870 } 2871 2872 ibdev->ib_active = true; 2873 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 2874 devlink_port_type_ib_set(mlx4_get_devlink_port(dev, i), 2875 &ibdev->ib_dev); 2876 2877 if (mlx4_is_mfunc(ibdev->dev)) 2878 init_pkeys(ibdev); 2879 2880 /* create paravirt contexts for any VFs which are active */ 2881 if (mlx4_is_master(ibdev->dev)) { 2882 for (j = 0; j < MLX4_MFUNC_MAX; j++) { 2883 if (j == mlx4_master_func_num(ibdev->dev)) 2884 continue; 2885 if (mlx4_is_slave_active(ibdev->dev, j)) 2886 do_slave_init(ibdev, j, 1); 2887 } 2888 } 2889 return ibdev; 2890 2891 err_notif: 2892 if (ibdev->iboe.nb.notifier_call) { 2893 if (unregister_netdevice_notifier(&ibdev->iboe.nb)) 2894 pr_warn("failure unregistering notifier\n"); 2895 ibdev->iboe.nb.notifier_call = NULL; 2896 } 2897 flush_workqueue(wq); 2898 2899 mlx4_ib_close_sriov(ibdev); 2900 2901 err_mad: 2902 mlx4_ib_mad_cleanup(ibdev); 2903 2904 err_reg: 2905 ib_unregister_device(&ibdev->ib_dev); 2906 2907 err_diag_counters: 2908 mlx4_ib_diag_cleanup(ibdev); 2909 2910 err_steer_free_bitmap: 2911 kfree(ibdev->ib_uc_qpns_bitmap); 2912 2913 err_steer_qp_release: 2914 mlx4_qp_release_range(dev, ibdev->steer_qpn_base, 2915 ibdev->steer_qpn_count); 2916 err_counter: 2917 for (i = 0; i < ibdev->num_ports; ++i) 2918 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[i]); 2919 2920 err_map: 2921 mlx4_ib_free_eqs(dev, ibdev); 2922 iounmap(ibdev->uar_map); 2923 2924 err_uar: 2925 mlx4_uar_free(dev, &ibdev->priv_uar); 2926 2927 err_pd: 2928 mlx4_pd_free(dev, ibdev->priv_pdn); 2929 2930 err_dealloc: 2931 ib_dealloc_device(&ibdev->ib_dev); 2932 2933 return NULL; 2934 } 2935 2936 int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn) 2937 { 2938 int offset; 2939 2940 WARN_ON(!dev->ib_uc_qpns_bitmap); 2941 2942 offset = bitmap_find_free_region(dev->ib_uc_qpns_bitmap, 2943 dev->steer_qpn_count, 2944 get_count_order(count)); 2945 if (offset < 0) 2946 return offset; 2947 2948 *qpn = dev->steer_qpn_base + offset; 2949 return 0; 2950 } 2951 2952 void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count) 2953 { 2954 if (!qpn || 2955 dev->steering_support != MLX4_STEERING_MODE_DEVICE_MANAGED) 2956 return; 2957 2958 if (WARN(qpn < dev->steer_qpn_base, "qpn = %u, steer_qpn_base = %u\n", 2959 qpn, dev->steer_qpn_base)) 2960 /* not supposed to be here */ 2961 return; 2962 2963 bitmap_release_region(dev->ib_uc_qpns_bitmap, 2964 qpn - dev->steer_qpn_base, 2965 get_count_order(count)); 2966 } 2967 2968 int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp, 2969 int is_attach) 2970 { 2971 int err; 2972 size_t flow_size; 2973 struct ib_flow_attr *flow = NULL; 2974 struct ib_flow_spec_ib *ib_spec; 2975 2976 if (is_attach) { 2977 flow_size = sizeof(struct ib_flow_attr) + 2978 sizeof(struct ib_flow_spec_ib); 2979 flow = kzalloc(flow_size, GFP_KERNEL); 2980 if (!flow) 2981 return -ENOMEM; 2982 flow->port = mqp->port; 2983 flow->num_of_specs = 1; 2984 flow->size = flow_size; 2985 ib_spec = (struct ib_flow_spec_ib *)(flow + 1); 2986 ib_spec->type = IB_FLOW_SPEC_IB; 2987 ib_spec->size = sizeof(struct ib_flow_spec_ib); 2988 /* Add an empty rule for IB L2 */ 2989 memset(&ib_spec->mask, 0, sizeof(ib_spec->mask)); 2990 2991 err = __mlx4_ib_create_flow(&mqp->ibqp, flow, 2992 IB_FLOW_DOMAIN_NIC, 2993 MLX4_FS_REGULAR, 2994 &mqp->reg_id); 2995 } else { 2996 err = __mlx4_ib_destroy_flow(mdev->dev, mqp->reg_id); 2997 } 2998 kfree(flow); 2999 return err; 3000 } 3001 3002 static void mlx4_ib_remove(struct mlx4_dev *dev, void *ibdev_ptr) 3003 { 3004 struct mlx4_ib_dev *ibdev = ibdev_ptr; 3005 int p; 3006 int i; 3007 3008 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) 3009 devlink_port_type_clear(mlx4_get_devlink_port(dev, i)); 3010 ibdev->ib_active = false; 3011 flush_workqueue(wq); 3012 3013 if (ibdev->iboe.nb.notifier_call) { 3014 if (unregister_netdevice_notifier(&ibdev->iboe.nb)) 3015 pr_warn("failure unregistering notifier\n"); 3016 ibdev->iboe.nb.notifier_call = NULL; 3017 } 3018 3019 mlx4_ib_close_sriov(ibdev); 3020 mlx4_ib_mad_cleanup(ibdev); 3021 ib_unregister_device(&ibdev->ib_dev); 3022 mlx4_ib_diag_cleanup(ibdev); 3023 3024 mlx4_qp_release_range(dev, ibdev->steer_qpn_base, 3025 ibdev->steer_qpn_count); 3026 kfree(ibdev->ib_uc_qpns_bitmap); 3027 3028 iounmap(ibdev->uar_map); 3029 for (p = 0; p < ibdev->num_ports; ++p) 3030 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[p]); 3031 3032 mlx4_foreach_port(p, dev, MLX4_PORT_TYPE_IB) 3033 mlx4_CLOSE_PORT(dev, p); 3034 3035 mlx4_ib_free_eqs(dev, ibdev); 3036 3037 mlx4_uar_free(dev, &ibdev->priv_uar); 3038 mlx4_pd_free(dev, ibdev->priv_pdn); 3039 ib_dealloc_device(&ibdev->ib_dev); 3040 } 3041 3042 static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init) 3043 { 3044 struct mlx4_ib_demux_work **dm = NULL; 3045 struct mlx4_dev *dev = ibdev->dev; 3046 int i; 3047 unsigned long flags; 3048 struct mlx4_active_ports actv_ports; 3049 unsigned int ports; 3050 unsigned int first_port; 3051 3052 if (!mlx4_is_master(dev)) 3053 return; 3054 3055 actv_ports = mlx4_get_active_ports(dev, slave); 3056 ports = bitmap_weight(actv_ports.ports, dev->caps.num_ports); 3057 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports); 3058 3059 dm = kcalloc(ports, sizeof(*dm), GFP_ATOMIC); 3060 if (!dm) 3061 return; 3062 3063 for (i = 0; i < ports; i++) { 3064 dm[i] = kmalloc(sizeof (struct mlx4_ib_demux_work), GFP_ATOMIC); 3065 if (!dm[i]) { 3066 while (--i >= 0) 3067 kfree(dm[i]); 3068 goto out; 3069 } 3070 INIT_WORK(&dm[i]->work, mlx4_ib_tunnels_update_work); 3071 dm[i]->port = first_port + i + 1; 3072 dm[i]->slave = slave; 3073 dm[i]->do_init = do_init; 3074 dm[i]->dev = ibdev; 3075 } 3076 /* initialize or tear down tunnel QPs for the slave */ 3077 spin_lock_irqsave(&ibdev->sriov.going_down_lock, flags); 3078 if (!ibdev->sriov.is_going_down) { 3079 for (i = 0; i < ports; i++) 3080 queue_work(ibdev->sriov.demux[i].ud_wq, &dm[i]->work); 3081 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags); 3082 } else { 3083 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags); 3084 for (i = 0; i < ports; i++) 3085 kfree(dm[i]); 3086 } 3087 out: 3088 kfree(dm); 3089 return; 3090 } 3091 3092 static void mlx4_ib_handle_catas_error(struct mlx4_ib_dev *ibdev) 3093 { 3094 struct mlx4_ib_qp *mqp; 3095 unsigned long flags_qp; 3096 unsigned long flags_cq; 3097 struct mlx4_ib_cq *send_mcq, *recv_mcq; 3098 struct list_head cq_notify_list; 3099 struct mlx4_cq *mcq; 3100 unsigned long flags; 3101 3102 pr_warn("mlx4_ib_handle_catas_error was started\n"); 3103 INIT_LIST_HEAD(&cq_notify_list); 3104 3105 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 3106 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 3107 3108 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 3109 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 3110 if (mqp->sq.tail != mqp->sq.head) { 3111 send_mcq = to_mcq(mqp->ibqp.send_cq); 3112 spin_lock_irqsave(&send_mcq->lock, flags_cq); 3113 if (send_mcq->mcq.comp && 3114 mqp->ibqp.send_cq->comp_handler) { 3115 if (!send_mcq->mcq.reset_notify_added) { 3116 send_mcq->mcq.reset_notify_added = 1; 3117 list_add_tail(&send_mcq->mcq.reset_notify, 3118 &cq_notify_list); 3119 } 3120 } 3121 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 3122 } 3123 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 3124 /* Now, handle the QP's receive queue */ 3125 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 3126 /* no handling is needed for SRQ */ 3127 if (!mqp->ibqp.srq) { 3128 if (mqp->rq.tail != mqp->rq.head) { 3129 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 3130 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 3131 if (recv_mcq->mcq.comp && 3132 mqp->ibqp.recv_cq->comp_handler) { 3133 if (!recv_mcq->mcq.reset_notify_added) { 3134 recv_mcq->mcq.reset_notify_added = 1; 3135 list_add_tail(&recv_mcq->mcq.reset_notify, 3136 &cq_notify_list); 3137 } 3138 } 3139 spin_unlock_irqrestore(&recv_mcq->lock, 3140 flags_cq); 3141 } 3142 } 3143 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 3144 } 3145 3146 list_for_each_entry(mcq, &cq_notify_list, reset_notify) { 3147 mcq->comp(mcq); 3148 } 3149 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 3150 pr_warn("mlx4_ib_handle_catas_error ended\n"); 3151 } 3152 3153 static void handle_bonded_port_state_event(struct work_struct *work) 3154 { 3155 struct ib_event_work *ew = 3156 container_of(work, struct ib_event_work, work); 3157 struct mlx4_ib_dev *ibdev = ew->ib_dev; 3158 enum ib_port_state bonded_port_state = IB_PORT_NOP; 3159 int i; 3160 struct ib_event ibev; 3161 3162 kfree(ew); 3163 spin_lock_bh(&ibdev->iboe.lock); 3164 for (i = 0; i < MLX4_MAX_PORTS; ++i) { 3165 struct net_device *curr_netdev = ibdev->iboe.netdevs[i]; 3166 enum ib_port_state curr_port_state; 3167 3168 if (!curr_netdev) 3169 continue; 3170 3171 curr_port_state = 3172 (netif_running(curr_netdev) && 3173 netif_carrier_ok(curr_netdev)) ? 3174 IB_PORT_ACTIVE : IB_PORT_DOWN; 3175 3176 bonded_port_state = (bonded_port_state != IB_PORT_ACTIVE) ? 3177 curr_port_state : IB_PORT_ACTIVE; 3178 } 3179 spin_unlock_bh(&ibdev->iboe.lock); 3180 3181 ibev.device = &ibdev->ib_dev; 3182 ibev.element.port_num = 1; 3183 ibev.event = (bonded_port_state == IB_PORT_ACTIVE) ? 3184 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 3185 3186 ib_dispatch_event(&ibev); 3187 } 3188 3189 void mlx4_ib_sl2vl_update(struct mlx4_ib_dev *mdev, int port) 3190 { 3191 u64 sl2vl; 3192 int err; 3193 3194 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, port, &sl2vl); 3195 if (err) { 3196 pr_err("Unable to get current sl to vl mapping for port %d. Using all zeroes (%d)\n", 3197 port, err); 3198 sl2vl = 0; 3199 } 3200 atomic64_set(&mdev->sl2vl[port - 1], sl2vl); 3201 } 3202 3203 static void ib_sl2vl_update_work(struct work_struct *work) 3204 { 3205 struct ib_event_work *ew = container_of(work, struct ib_event_work, work); 3206 struct mlx4_ib_dev *mdev = ew->ib_dev; 3207 int port = ew->port; 3208 3209 mlx4_ib_sl2vl_update(mdev, port); 3210 3211 kfree(ew); 3212 } 3213 3214 void mlx4_sched_ib_sl2vl_update_work(struct mlx4_ib_dev *ibdev, 3215 int port) 3216 { 3217 struct ib_event_work *ew; 3218 3219 ew = kmalloc(sizeof(*ew), GFP_ATOMIC); 3220 if (ew) { 3221 INIT_WORK(&ew->work, ib_sl2vl_update_work); 3222 ew->port = port; 3223 ew->ib_dev = ibdev; 3224 queue_work(wq, &ew->work); 3225 } 3226 } 3227 3228 static void mlx4_ib_event(struct mlx4_dev *dev, void *ibdev_ptr, 3229 enum mlx4_dev_event event, unsigned long param) 3230 { 3231 struct ib_event ibev; 3232 struct mlx4_ib_dev *ibdev = to_mdev((struct ib_device *) ibdev_ptr); 3233 struct mlx4_eqe *eqe = NULL; 3234 struct ib_event_work *ew; 3235 int p = 0; 3236 3237 if (mlx4_is_bonded(dev) && 3238 ((event == MLX4_DEV_EVENT_PORT_UP) || 3239 (event == MLX4_DEV_EVENT_PORT_DOWN))) { 3240 ew = kmalloc(sizeof(*ew), GFP_ATOMIC); 3241 if (!ew) 3242 return; 3243 INIT_WORK(&ew->work, handle_bonded_port_state_event); 3244 ew->ib_dev = ibdev; 3245 queue_work(wq, &ew->work); 3246 return; 3247 } 3248 3249 if (event == MLX4_DEV_EVENT_PORT_MGMT_CHANGE) 3250 eqe = (struct mlx4_eqe *)param; 3251 else 3252 p = (int) param; 3253 3254 switch (event) { 3255 case MLX4_DEV_EVENT_PORT_UP: 3256 if (p > ibdev->num_ports) 3257 return; 3258 if (!mlx4_is_slave(dev) && 3259 rdma_port_get_link_layer(&ibdev->ib_dev, p) == 3260 IB_LINK_LAYER_INFINIBAND) { 3261 if (mlx4_is_master(dev)) 3262 mlx4_ib_invalidate_all_guid_record(ibdev, p); 3263 if (ibdev->dev->flags & MLX4_FLAG_SECURE_HOST && 3264 !(ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT)) 3265 mlx4_sched_ib_sl2vl_update_work(ibdev, p); 3266 } 3267 ibev.event = IB_EVENT_PORT_ACTIVE; 3268 break; 3269 3270 case MLX4_DEV_EVENT_PORT_DOWN: 3271 if (p > ibdev->num_ports) 3272 return; 3273 ibev.event = IB_EVENT_PORT_ERR; 3274 break; 3275 3276 case MLX4_DEV_EVENT_CATASTROPHIC_ERROR: 3277 ibdev->ib_active = false; 3278 ibev.event = IB_EVENT_DEVICE_FATAL; 3279 mlx4_ib_handle_catas_error(ibdev); 3280 break; 3281 3282 case MLX4_DEV_EVENT_PORT_MGMT_CHANGE: 3283 ew = kmalloc(sizeof *ew, GFP_ATOMIC); 3284 if (!ew) 3285 break; 3286 3287 INIT_WORK(&ew->work, handle_port_mgmt_change_event); 3288 memcpy(&ew->ib_eqe, eqe, sizeof *eqe); 3289 ew->ib_dev = ibdev; 3290 /* need to queue only for port owner, which uses GEN_EQE */ 3291 if (mlx4_is_master(dev)) 3292 queue_work(wq, &ew->work); 3293 else 3294 handle_port_mgmt_change_event(&ew->work); 3295 return; 3296 3297 case MLX4_DEV_EVENT_SLAVE_INIT: 3298 /* here, p is the slave id */ 3299 do_slave_init(ibdev, p, 1); 3300 if (mlx4_is_master(dev)) { 3301 int i; 3302 3303 for (i = 1; i <= ibdev->num_ports; i++) { 3304 if (rdma_port_get_link_layer(&ibdev->ib_dev, i) 3305 == IB_LINK_LAYER_INFINIBAND) 3306 mlx4_ib_slave_alias_guid_event(ibdev, 3307 p, i, 3308 1); 3309 } 3310 } 3311 return; 3312 3313 case MLX4_DEV_EVENT_SLAVE_SHUTDOWN: 3314 if (mlx4_is_master(dev)) { 3315 int i; 3316 3317 for (i = 1; i <= ibdev->num_ports; i++) { 3318 if (rdma_port_get_link_layer(&ibdev->ib_dev, i) 3319 == IB_LINK_LAYER_INFINIBAND) 3320 mlx4_ib_slave_alias_guid_event(ibdev, 3321 p, i, 3322 0); 3323 } 3324 } 3325 /* here, p is the slave id */ 3326 do_slave_init(ibdev, p, 0); 3327 return; 3328 3329 default: 3330 return; 3331 } 3332 3333 ibev.device = ibdev_ptr; 3334 ibev.element.port_num = mlx4_is_bonded(ibdev->dev) ? 1 : (u8)p; 3335 3336 ib_dispatch_event(&ibev); 3337 } 3338 3339 static struct mlx4_interface mlx4_ib_interface = { 3340 .add = mlx4_ib_add, 3341 .remove = mlx4_ib_remove, 3342 .event = mlx4_ib_event, 3343 .protocol = MLX4_PROT_IB_IPV6, 3344 .flags = MLX4_INTFF_BONDING 3345 }; 3346 3347 static int __init mlx4_ib_init(void) 3348 { 3349 int err; 3350 3351 wq = alloc_ordered_workqueue("mlx4_ib", WQ_MEM_RECLAIM); 3352 if (!wq) 3353 return -ENOMEM; 3354 3355 err = mlx4_ib_mcg_init(); 3356 if (err) 3357 goto clean_wq; 3358 3359 err = mlx4_register_interface(&mlx4_ib_interface); 3360 if (err) 3361 goto clean_mcg; 3362 3363 return 0; 3364 3365 clean_mcg: 3366 mlx4_ib_mcg_destroy(); 3367 3368 clean_wq: 3369 destroy_workqueue(wq); 3370 return err; 3371 } 3372 3373 static void __exit mlx4_ib_cleanup(void) 3374 { 3375 mlx4_unregister_interface(&mlx4_ib_interface); 3376 mlx4_ib_mcg_destroy(); 3377 destroy_workqueue(wq); 3378 } 3379 3380 module_init(mlx4_ib_init); 3381 module_exit(mlx4_ib_cleanup); 3382