1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1028A family SoC. 4 * 5 * Copyright 2018 NXP 6 * 7 * Harninder Rai <harninder.rai@nxp.com> 8 * 9 */ 10 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "fsl,ls1028a"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu0: cpu@0 { 25 device_type = "cpu"; 26 compatible = "arm,cortex-a72"; 27 reg = <0x0>; 28 enable-method = "psci"; 29 clocks = <&clockgen 1 0>; 30 next-level-cache = <&l2>; 31 cpu-idle-states = <&CPU_PW20>; 32 }; 33 34 cpu1: cpu@1 { 35 device_type = "cpu"; 36 compatible = "arm,cortex-a72"; 37 reg = <0x1>; 38 enable-method = "psci"; 39 clocks = <&clockgen 1 0>; 40 next-level-cache = <&l2>; 41 cpu-idle-states = <&CPU_PW20>; 42 }; 43 44 l2: l2-cache { 45 compatible = "cache"; 46 }; 47 }; 48 49 idle-states { 50 /* 51 * PSCI node is not added default, U-boot will add missing 52 * parts if it determines to use PSCI. 53 */ 54 entry-method = "arm,psci"; 55 56 CPU_PW20: cpu-pw20 { 57 compatible = "arm,idle-state"; 58 idle-state-name = "PW20"; 59 arm,psci-suspend-param = <0x0>; 60 entry-latency-us = <2000>; 61 exit-latency-us = <2000>; 62 min-residency-us = <6000>; 63 }; 64 }; 65 66 sysclk: clock-sysclk { 67 compatible = "fixed-clock"; 68 #clock-cells = <0>; 69 clock-frequency = <100000000>; 70 clock-output-names = "sysclk"; 71 }; 72 73 dpclk: clock-dp { 74 compatible = "fixed-clock"; 75 #clock-cells = <0>; 76 clock-frequency = <27000000>; 77 clock-output-names= "dpclk"; 78 }; 79 80 aclk: clock-axi { 81 compatible = "fixed-clock"; 82 #clock-cells = <0>; 83 clock-frequency = <650000000>; 84 clock-output-names= "aclk"; 85 }; 86 87 pclk: clock-apb { 88 compatible = "fixed-clock"; 89 #clock-cells = <0>; 90 clock-frequency = <650000000>; 91 clock-output-names= "pclk"; 92 }; 93 94 reboot { 95 compatible ="syscon-reboot"; 96 regmap = <&dcfg>; 97 offset = <0xb0>; 98 mask = <0x02>; 99 }; 100 101 timer { 102 compatible = "arm,armv8-timer"; 103 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 104 IRQ_TYPE_LEVEL_LOW)>, 105 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 106 IRQ_TYPE_LEVEL_LOW)>, 107 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 108 IRQ_TYPE_LEVEL_LOW)>, 109 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 110 IRQ_TYPE_LEVEL_LOW)>; 111 }; 112 113 pmu { 114 compatible = "arm,cortex-a72-pmu"; 115 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 116 }; 117 118 gic: interrupt-controller@6000000 { 119 compatible= "arm,gic-v3"; 120 #address-cells = <2>; 121 #size-cells = <2>; 122 ranges; 123 reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 124 <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ 125 #interrupt-cells= <3>; 126 interrupt-controller; 127 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 128 IRQ_TYPE_LEVEL_LOW)>; 129 its: gic-its@6020000 { 130 compatible = "arm,gic-v3-its"; 131 msi-controller; 132 reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ 133 }; 134 }; 135 136 soc: soc { 137 compatible = "simple-bus"; 138 #address-cells = <2>; 139 #size-cells = <2>; 140 ranges; 141 142 ddr: memory-controller@1080000 { 143 compatible = "fsl,qoriq-memory-controller"; 144 reg = <0x0 0x1080000 0x0 0x1000>; 145 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 146 big-endian; 147 }; 148 149 dcfg: syscon@1e00000 { 150 compatible = "fsl,ls1028a-dcfg", "syscon"; 151 reg = <0x0 0x1e00000 0x0 0x10000>; 152 big-endian; 153 }; 154 155 scfg: syscon@1fc0000 { 156 compatible = "fsl,ls1028a-scfg", "syscon"; 157 reg = <0x0 0x1fc0000 0x0 0x10000>; 158 big-endian; 159 }; 160 161 clockgen: clock-controller@1300000 { 162 compatible = "fsl,ls1028a-clockgen"; 163 reg = <0x0 0x1300000 0x0 0xa0000>; 164 #clock-cells = <2>; 165 clocks = <&sysclk>; 166 }; 167 168 i2c0: i2c@2000000 { 169 compatible = "fsl,vf610-i2c"; 170 #address-cells = <1>; 171 #size-cells = <0>; 172 reg = <0x0 0x2000000 0x0 0x10000>; 173 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 174 clocks = <&clockgen 4 1>; 175 status = "disabled"; 176 }; 177 178 i2c1: i2c@2010000 { 179 compatible = "fsl,vf610-i2c"; 180 #address-cells = <1>; 181 #size-cells = <0>; 182 reg = <0x0 0x2010000 0x0 0x10000>; 183 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 184 clocks = <&clockgen 4 1>; 185 status = "disabled"; 186 }; 187 188 i2c2: i2c@2020000 { 189 compatible = "fsl,vf610-i2c"; 190 #address-cells = <1>; 191 #size-cells = <0>; 192 reg = <0x0 0x2020000 0x0 0x10000>; 193 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 194 clocks = <&clockgen 4 1>; 195 status = "disabled"; 196 }; 197 198 i2c3: i2c@2030000 { 199 compatible = "fsl,vf610-i2c"; 200 #address-cells = <1>; 201 #size-cells = <0>; 202 reg = <0x0 0x2030000 0x0 0x10000>; 203 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 204 clocks = <&clockgen 4 1>; 205 status = "disabled"; 206 }; 207 208 i2c4: i2c@2040000 { 209 compatible = "fsl,vf610-i2c"; 210 #address-cells = <1>; 211 #size-cells = <0>; 212 reg = <0x0 0x2040000 0x0 0x10000>; 213 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 214 clocks = <&clockgen 4 1>; 215 status = "disabled"; 216 }; 217 218 i2c5: i2c@2050000 { 219 compatible = "fsl,vf610-i2c"; 220 #address-cells = <1>; 221 #size-cells = <0>; 222 reg = <0x0 0x2050000 0x0 0x10000>; 223 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 224 clocks = <&clockgen 4 1>; 225 status = "disabled"; 226 }; 227 228 i2c6: i2c@2060000 { 229 compatible = "fsl,vf610-i2c"; 230 #address-cells = <1>; 231 #size-cells = <0>; 232 reg = <0x0 0x2060000 0x0 0x10000>; 233 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 234 clocks = <&clockgen 4 1>; 235 status = "disabled"; 236 }; 237 238 i2c7: i2c@2070000 { 239 compatible = "fsl,vf610-i2c"; 240 #address-cells = <1>; 241 #size-cells = <0>; 242 reg = <0x0 0x2070000 0x0 0x10000>; 243 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&clockgen 4 1>; 245 status = "disabled"; 246 }; 247 248 duart0: serial@21c0500 { 249 compatible = "fsl,ns16550", "ns16550a"; 250 reg = <0x00 0x21c0500 0x0 0x100>; 251 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&clockgen 4 1>; 253 status = "disabled"; 254 }; 255 256 duart1: serial@21c0600 { 257 compatible = "fsl,ns16550", "ns16550a"; 258 reg = <0x00 0x21c0600 0x0 0x100>; 259 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 260 clocks = <&clockgen 4 1>; 261 status = "disabled"; 262 }; 263 264 edma0: dma-controller@22c0000 { 265 #dma-cells = <2>; 266 compatible = "fsl,vf610-edma"; 267 reg = <0x0 0x22c0000 0x0 0x10000>, 268 <0x0 0x22d0000 0x0 0x10000>, 269 <0x0 0x22e0000 0x0 0x10000>; 270 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 272 interrupt-names = "edma-tx", "edma-err"; 273 dma-channels = <32>; 274 clock-names = "dmamux0", "dmamux1"; 275 clocks = <&clockgen 4 1>, 276 <&clockgen 4 1>; 277 }; 278 279 gpio1: gpio@2300000 { 280 compatible = "fsl,qoriq-gpio"; 281 reg = <0x0 0x2300000 0x0 0x10000>; 282 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 283 gpio-controller; 284 #gpio-cells = <2>; 285 interrupt-controller; 286 #interrupt-cells = <2>; 287 }; 288 289 gpio2: gpio@2310000 { 290 compatible = "fsl,qoriq-gpio"; 291 reg = <0x0 0x2310000 0x0 0x10000>; 292 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 293 gpio-controller; 294 #gpio-cells = <2>; 295 interrupt-controller; 296 #interrupt-cells = <2>; 297 }; 298 299 gpio3: gpio@2320000 { 300 compatible = "fsl,qoriq-gpio"; 301 reg = <0x0 0x2320000 0x0 0x10000>; 302 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 303 gpio-controller; 304 #gpio-cells = <2>; 305 interrupt-controller; 306 #interrupt-cells = <2>; 307 }; 308 309 usb0: usb@3100000 { 310 compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 311 reg = <0x0 0x3100000 0x0 0x10000>; 312 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 313 dr_mode = "host"; 314 snps,dis_rxdet_inp3_quirk; 315 snps,quirk-frame-length-adjustment = <0x20>; 316 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 317 }; 318 319 usb1: usb@3110000 { 320 compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 321 reg = <0x0 0x3110000 0x0 0x10000>; 322 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 323 dr_mode = "host"; 324 snps,dis_rxdet_inp3_quirk; 325 snps,quirk-frame-length-adjustment = <0x20>; 326 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 327 }; 328 329 sata: sata@3200000 { 330 compatible = "fsl,ls1028a-ahci"; 331 reg = <0x0 0x3200000 0x0 0x10000>, 332 <0x7 0x100520 0x0 0x4>; 333 reg-names = "ahci", "sata-ecc"; 334 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 335 clocks = <&clockgen 4 1>; 336 status = "disabled"; 337 }; 338 339 smmu: iommu@5000000 { 340 compatible = "arm,mmu-500"; 341 reg = <0 0x5000000 0 0x800000>; 342 #global-interrupts = <8>; 343 #iommu-cells = <1>; 344 stream-match-mask = <0x7c00>; 345 /* global secure fault */ 346 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 347 /* combined secure interrupt */ 348 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 349 /* global non-secure fault */ 350 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 351 /* combined non-secure interrupt */ 352 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 353 /* performance counter interrupts 0-7 */ 354 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 355 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 356 /* per context interrupt, 64 interrupts */ 357 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 361 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 365 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 366 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 367 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 368 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 369 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 370 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 371 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 373 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 375 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 378 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 379 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 381 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 382 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 383 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 386 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 388 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 389 }; 390 391 crypto: crypto@8000000 { 392 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 393 fsl,sec-era = <10>; 394 #address-cells = <1>; 395 #size-cells = <1>; 396 ranges = <0x0 0x00 0x8000000 0x100000>; 397 reg = <0x00 0x8000000 0x0 0x100000>; 398 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 399 dma-coherent; 400 401 sec_jr0: jr@10000 { 402 compatible = "fsl,sec-v5.0-job-ring", 403 "fsl,sec-v4.0-job-ring"; 404 reg = <0x10000 0x10000>; 405 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 406 }; 407 408 sec_jr1: jr@20000 { 409 compatible = "fsl,sec-v5.0-job-ring", 410 "fsl,sec-v4.0-job-ring"; 411 reg = <0x20000 0x10000>; 412 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 413 }; 414 415 sec_jr2: jr@30000 { 416 compatible = "fsl,sec-v5.0-job-ring", 417 "fsl,sec-v4.0-job-ring"; 418 reg = <0x30000 0x10000>; 419 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 420 }; 421 422 sec_jr3: jr@40000 { 423 compatible = "fsl,sec-v5.0-job-ring", 424 "fsl,sec-v4.0-job-ring"; 425 reg = <0x40000 0x10000>; 426 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 427 }; 428 }; 429 430 qdma: dma-controller@8380000 { 431 compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma"; 432 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 433 <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 434 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 435 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 440 interrupt-names = "qdma-error", "qdma-queue0", 441 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 442 dma-channels = <8>; 443 block-number = <1>; 444 block-offset = <0x10000>; 445 fsl,dma-queues = <2>; 446 status-sizes = <64>; 447 queue-sizes = <64 64>; 448 }; 449 450 cluster1_core0_watchdog: watchdog@c000000 { 451 compatible = "arm,sp805", "arm,primecell"; 452 reg = <0x0 0xc000000 0x0 0x1000>; 453 clocks = <&clockgen 4 15>, <&clockgen 4 15>; 454 clock-names = "apb_pclk", "wdog_clk"; 455 }; 456 457 cluster1_core1_watchdog: watchdog@c010000 { 458 compatible = "arm,sp805", "arm,primecell"; 459 reg = <0x0 0xc010000 0x0 0x1000>; 460 clocks = <&clockgen 4 15>, <&clockgen 4 15>; 461 clock-names = "apb_pclk", "wdog_clk"; 462 }; 463 464 sai1: audio-controller@f100000 { 465 #sound-dai-cells = <0>; 466 compatible = "fsl,vf610-sai"; 467 reg = <0x0 0xf100000 0x0 0x10000>; 468 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 469 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 470 <&clockgen 4 1>, <&clockgen 4 1>; 471 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 472 dma-names = "tx", "rx"; 473 dmas = <&edma0 1 4>, 474 <&edma0 1 3>; 475 status = "disabled"; 476 }; 477 478 sai2: audio-controller@f110000 { 479 #sound-dai-cells = <0>; 480 compatible = "fsl,vf610-sai"; 481 reg = <0x0 0xf110000 0x0 0x10000>; 482 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 483 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 484 <&clockgen 4 1>, <&clockgen 4 1>; 485 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 486 dma-names = "tx", "rx"; 487 dmas = <&edma0 1 6>, 488 <&edma0 1 5>; 489 status = "disabled"; 490 }; 491 492 sai4: audio-controller@f130000 { 493 #sound-dai-cells = <0>; 494 compatible = "fsl,vf610-sai"; 495 reg = <0x0 0xf130000 0x0 0x10000>; 496 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 497 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 498 <&clockgen 4 1>, <&clockgen 4 1>; 499 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 500 dma-names = "tx", "rx"; 501 dmas = <&edma0 1 10>, 502 <&edma0 1 9>; 503 status = "disabled"; 504 }; 505 506 pcie@1f0000000 { /* Integrated Endpoint Root Complex */ 507 compatible = "pci-host-ecam-generic"; 508 reg = <0x01 0xf0000000 0x0 0x100000>; 509 #address-cells = <3>; 510 #size-cells = <2>; 511 #interrupt-cells = <1>; 512 msi-parent = <&its>; 513 device_type = "pci"; 514 bus-range = <0x0 0x0>; 515 dma-coherent; 516 msi-map = <0 &its 0x17 0xe>; 517 iommu-map = <0 &smmu 0x17 0xe>; 518 /* PF0-6 BAR0 - non-prefetchable memory */ 519 ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000 520 /* PF0-6 BAR2 - prefetchable memory */ 521 0xc2000000 0x0 0x00000000 0x1 0xf8160000 0x0 0x070000 522 /* PF0: VF0-1 BAR0 - non-prefetchable memory */ 523 0x82000000 0x0 0x00000000 0x1 0xf81d0000 0x0 0x020000 524 /* PF0: VF0-1 BAR2 - prefetchable memory */ 525 0xc2000000 0x0 0x00000000 0x1 0xf81f0000 0x0 0x020000 526 /* PF1: VF0-1 BAR0 - non-prefetchable memory */ 527 0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000 528 /* PF1: VF0-1 BAR2 - prefetchable memory */ 529 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000>; 530 531 enetc_port0: ethernet@0,0 { 532 compatible = "fsl,enetc"; 533 reg = <0x000000 0 0 0 0>; 534 }; 535 enetc_port1: ethernet@0,1 { 536 compatible = "fsl,enetc"; 537 reg = <0x000100 0 0 0 0>; 538 }; 539 ethernet@0,4 { 540 compatible = "fsl,enetc-ptp"; 541 reg = <0x000400 0 0 0 0>; 542 clocks = <&clockgen 4 0>; 543 little-endian; 544 }; 545 }; 546 }; 547 548 malidp0: display@f080000 { 549 compatible = "arm,mali-dp500"; 550 reg = <0x0 0xf080000 0x0 0x10000>; 551 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, 552 <0 223 IRQ_TYPE_LEVEL_HIGH>; 553 interrupt-names = "DE", "SE"; 554 clocks = <&dpclk>, <&aclk>, <&aclk>, <&pclk>; 555 clock-names = "pxlclk", "mclk", "aclk", "pclk"; 556 arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; 557 558 port { 559 dp0_out: endpoint { 560 561 }; 562 }; 563 }; 564}; 565