1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2007 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 */ 28 29 #include <linux/delay.h> 30 #include <linux/export.h> 31 #include <linux/i2c.h> 32 #include <linux/slab.h> 33 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_crtc.h> 36 #include <drm/drm_edid.h> 37 38 #include "i915_drv.h" 39 #include "intel_atomic.h" 40 #include "intel_connector.h" 41 #include "intel_display_types.h" 42 #include "intel_fifo_underrun.h" 43 #include "intel_gmbus.h" 44 #include "intel_hdmi.h" 45 #include "intel_hotplug.h" 46 #include "intel_panel.h" 47 #include "intel_sdvo.h" 48 #include "intel_sdvo_regs.h" 49 50 #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) 51 #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) 52 #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) 53 #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0) 54 55 #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ 56 SDVO_TV_MASK) 57 58 #define IS_TV(c) (c->output_flag & SDVO_TV_MASK) 59 #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK) 60 #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) 61 #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) 62 #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK)) 63 64 65 static const char * const tv_format_names[] = { 66 "NTSC_M" , "NTSC_J" , "NTSC_443", 67 "PAL_B" , "PAL_D" , "PAL_G" , 68 "PAL_H" , "PAL_I" , "PAL_M" , 69 "PAL_N" , "PAL_NC" , "PAL_60" , 70 "SECAM_B" , "SECAM_D" , "SECAM_G" , 71 "SECAM_K" , "SECAM_K1", "SECAM_L" , 72 "SECAM_60" 73 }; 74 75 #define TV_FORMAT_NUM ARRAY_SIZE(tv_format_names) 76 77 struct intel_sdvo { 78 struct intel_encoder base; 79 80 struct i2c_adapter *i2c; 81 u8 slave_addr; 82 83 struct i2c_adapter ddc; 84 85 /* Register for the SDVO device: SDVOB or SDVOC */ 86 i915_reg_t sdvo_reg; 87 88 /* Active outputs controlled by this SDVO output */ 89 u16 controlled_output; 90 91 /* 92 * Capabilities of the SDVO device returned by 93 * intel_sdvo_get_capabilities() 94 */ 95 struct intel_sdvo_caps caps; 96 97 /* Pixel clock limitations reported by the SDVO device, in kHz */ 98 int pixel_clock_min, pixel_clock_max; 99 100 /* 101 * For multiple function SDVO device, 102 * this is for current attached outputs. 103 */ 104 u16 attached_output; 105 106 /* 107 * Hotplug activation bits for this device 108 */ 109 u16 hotplug_active; 110 111 enum port port; 112 113 bool has_hdmi_monitor; 114 bool has_hdmi_audio; 115 116 /* DDC bus used by this SDVO encoder */ 117 u8 ddc_bus; 118 119 /* 120 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd 121 */ 122 u8 dtd_sdvo_flags; 123 }; 124 125 struct intel_sdvo_connector { 126 struct intel_connector base; 127 128 /* Mark the type of connector */ 129 u16 output_flag; 130 131 /* This contains all current supported TV format */ 132 u8 tv_format_supported[TV_FORMAT_NUM]; 133 int format_supported_num; 134 struct drm_property *tv_format; 135 136 /* add the property for the SDVO-TV */ 137 struct drm_property *left; 138 struct drm_property *right; 139 struct drm_property *top; 140 struct drm_property *bottom; 141 struct drm_property *hpos; 142 struct drm_property *vpos; 143 struct drm_property *contrast; 144 struct drm_property *saturation; 145 struct drm_property *hue; 146 struct drm_property *sharpness; 147 struct drm_property *flicker_filter; 148 struct drm_property *flicker_filter_adaptive; 149 struct drm_property *flicker_filter_2d; 150 struct drm_property *tv_chroma_filter; 151 struct drm_property *tv_luma_filter; 152 struct drm_property *dot_crawl; 153 154 /* add the property for the SDVO-TV/LVDS */ 155 struct drm_property *brightness; 156 157 /* this is to get the range of margin.*/ 158 u32 max_hscan, max_vscan; 159 160 /** 161 * This is set if we treat the device as HDMI, instead of DVI. 162 */ 163 bool is_hdmi; 164 }; 165 166 struct intel_sdvo_connector_state { 167 /* base.base: tv.saturation/contrast/hue/brightness */ 168 struct intel_digital_connector_state base; 169 170 struct { 171 unsigned overscan_h, overscan_v, hpos, vpos, sharpness; 172 unsigned flicker_filter, flicker_filter_2d, flicker_filter_adaptive; 173 unsigned chroma_filter, luma_filter, dot_crawl; 174 } tv; 175 }; 176 177 static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder) 178 { 179 return container_of(encoder, struct intel_sdvo, base); 180 } 181 182 static struct intel_sdvo *intel_attached_sdvo(struct intel_connector *connector) 183 { 184 return to_sdvo(intel_attached_encoder(connector)); 185 } 186 187 static struct intel_sdvo_connector * 188 to_intel_sdvo_connector(struct drm_connector *connector) 189 { 190 return container_of(connector, struct intel_sdvo_connector, base.base); 191 } 192 193 #define to_intel_sdvo_connector_state(conn_state) \ 194 container_of((conn_state), struct intel_sdvo_connector_state, base.base) 195 196 static bool 197 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, u16 flags); 198 static bool 199 intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 200 struct intel_sdvo_connector *intel_sdvo_connector, 201 int type); 202 static bool 203 intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 204 struct intel_sdvo_connector *intel_sdvo_connector); 205 206 /* 207 * Writes the SDVOB or SDVOC with the given value, but always writes both 208 * SDVOB and SDVOC to work around apparent hardware issues (according to 209 * comments in the BIOS). 210 */ 211 static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) 212 { 213 struct drm_device *dev = intel_sdvo->base.base.dev; 214 struct drm_i915_private *dev_priv = to_i915(dev); 215 u32 bval = val, cval = val; 216 int i; 217 218 if (HAS_PCH_SPLIT(dev_priv)) { 219 intel_de_write(dev_priv, intel_sdvo->sdvo_reg, val); 220 intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg); 221 /* 222 * HW workaround, need to write this twice for issue 223 * that may result in first write getting masked. 224 */ 225 if (HAS_PCH_IBX(dev_priv)) { 226 intel_de_write(dev_priv, intel_sdvo->sdvo_reg, val); 227 intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg); 228 } 229 return; 230 } 231 232 if (intel_sdvo->port == PORT_B) 233 cval = intel_de_read(dev_priv, GEN3_SDVOC); 234 else 235 bval = intel_de_read(dev_priv, GEN3_SDVOB); 236 237 /* 238 * Write the registers twice for luck. Sometimes, 239 * writing them only once doesn't appear to 'stick'. 240 * The BIOS does this too. Yay, magic 241 */ 242 for (i = 0; i < 2; i++) { 243 intel_de_write(dev_priv, GEN3_SDVOB, bval); 244 intel_de_posting_read(dev_priv, GEN3_SDVOB); 245 246 intel_de_write(dev_priv, GEN3_SDVOC, cval); 247 intel_de_posting_read(dev_priv, GEN3_SDVOC); 248 } 249 } 250 251 static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) 252 { 253 struct i2c_msg msgs[] = { 254 { 255 .addr = intel_sdvo->slave_addr, 256 .flags = 0, 257 .len = 1, 258 .buf = &addr, 259 }, 260 { 261 .addr = intel_sdvo->slave_addr, 262 .flags = I2C_M_RD, 263 .len = 1, 264 .buf = ch, 265 } 266 }; 267 int ret; 268 269 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2) 270 return true; 271 272 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); 273 return false; 274 } 275 276 #define SDVO_CMD_NAME_ENTRY(cmd_) { .cmd = SDVO_CMD_ ## cmd_, .name = #cmd_ } 277 278 /** Mapping of command numbers to names, for debug output */ 279 static const struct { 280 u8 cmd; 281 const char *name; 282 } __attribute__ ((packed)) sdvo_cmd_names[] = { 283 SDVO_CMD_NAME_ENTRY(RESET), 284 SDVO_CMD_NAME_ENTRY(GET_DEVICE_CAPS), 285 SDVO_CMD_NAME_ENTRY(GET_FIRMWARE_REV), 286 SDVO_CMD_NAME_ENTRY(GET_TRAINED_INPUTS), 287 SDVO_CMD_NAME_ENTRY(GET_ACTIVE_OUTPUTS), 288 SDVO_CMD_NAME_ENTRY(SET_ACTIVE_OUTPUTS), 289 SDVO_CMD_NAME_ENTRY(GET_IN_OUT_MAP), 290 SDVO_CMD_NAME_ENTRY(SET_IN_OUT_MAP), 291 SDVO_CMD_NAME_ENTRY(GET_ATTACHED_DISPLAYS), 292 SDVO_CMD_NAME_ENTRY(GET_HOT_PLUG_SUPPORT), 293 SDVO_CMD_NAME_ENTRY(SET_ACTIVE_HOT_PLUG), 294 SDVO_CMD_NAME_ENTRY(GET_ACTIVE_HOT_PLUG), 295 SDVO_CMD_NAME_ENTRY(GET_INTERRUPT_EVENT_SOURCE), 296 SDVO_CMD_NAME_ENTRY(SET_TARGET_INPUT), 297 SDVO_CMD_NAME_ENTRY(SET_TARGET_OUTPUT), 298 SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART1), 299 SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART2), 300 SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART1), 301 SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART2), 302 SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART1), 303 SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART2), 304 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART1), 305 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART2), 306 SDVO_CMD_NAME_ENTRY(CREATE_PREFERRED_INPUT_TIMING), 307 SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART1), 308 SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART2), 309 SDVO_CMD_NAME_ENTRY(GET_INPUT_PIXEL_CLOCK_RANGE), 310 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_PIXEL_CLOCK_RANGE), 311 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_CLOCK_RATE_MULTS), 312 SDVO_CMD_NAME_ENTRY(GET_CLOCK_RATE_MULT), 313 SDVO_CMD_NAME_ENTRY(SET_CLOCK_RATE_MULT), 314 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_TV_FORMATS), 315 SDVO_CMD_NAME_ENTRY(GET_TV_FORMAT), 316 SDVO_CMD_NAME_ENTRY(SET_TV_FORMAT), 317 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_POWER_STATES), 318 SDVO_CMD_NAME_ENTRY(GET_POWER_STATE), 319 SDVO_CMD_NAME_ENTRY(SET_ENCODER_POWER_STATE), 320 SDVO_CMD_NAME_ENTRY(SET_DISPLAY_POWER_STATE), 321 SDVO_CMD_NAME_ENTRY(SET_CONTROL_BUS_SWITCH), 322 SDVO_CMD_NAME_ENTRY(GET_SDTV_RESOLUTION_SUPPORT), 323 SDVO_CMD_NAME_ENTRY(GET_SCALED_HDTV_RESOLUTION_SUPPORT), 324 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_ENHANCEMENTS), 325 326 /* Add the op code for SDVO enhancements */ 327 SDVO_CMD_NAME_ENTRY(GET_MAX_HPOS), 328 SDVO_CMD_NAME_ENTRY(GET_HPOS), 329 SDVO_CMD_NAME_ENTRY(SET_HPOS), 330 SDVO_CMD_NAME_ENTRY(GET_MAX_VPOS), 331 SDVO_CMD_NAME_ENTRY(GET_VPOS), 332 SDVO_CMD_NAME_ENTRY(SET_VPOS), 333 SDVO_CMD_NAME_ENTRY(GET_MAX_SATURATION), 334 SDVO_CMD_NAME_ENTRY(GET_SATURATION), 335 SDVO_CMD_NAME_ENTRY(SET_SATURATION), 336 SDVO_CMD_NAME_ENTRY(GET_MAX_HUE), 337 SDVO_CMD_NAME_ENTRY(GET_HUE), 338 SDVO_CMD_NAME_ENTRY(SET_HUE), 339 SDVO_CMD_NAME_ENTRY(GET_MAX_CONTRAST), 340 SDVO_CMD_NAME_ENTRY(GET_CONTRAST), 341 SDVO_CMD_NAME_ENTRY(SET_CONTRAST), 342 SDVO_CMD_NAME_ENTRY(GET_MAX_BRIGHTNESS), 343 SDVO_CMD_NAME_ENTRY(GET_BRIGHTNESS), 344 SDVO_CMD_NAME_ENTRY(SET_BRIGHTNESS), 345 SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_H), 346 SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_H), 347 SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_H), 348 SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_V), 349 SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_V), 350 SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_V), 351 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER), 352 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER), 353 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER), 354 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_ADAPTIVE), 355 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_ADAPTIVE), 356 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_ADAPTIVE), 357 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_2D), 358 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_2D), 359 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_2D), 360 SDVO_CMD_NAME_ENTRY(GET_MAX_SHARPNESS), 361 SDVO_CMD_NAME_ENTRY(GET_SHARPNESS), 362 SDVO_CMD_NAME_ENTRY(SET_SHARPNESS), 363 SDVO_CMD_NAME_ENTRY(GET_DOT_CRAWL), 364 SDVO_CMD_NAME_ENTRY(SET_DOT_CRAWL), 365 SDVO_CMD_NAME_ENTRY(GET_MAX_TV_CHROMA_FILTER), 366 SDVO_CMD_NAME_ENTRY(GET_TV_CHROMA_FILTER), 367 SDVO_CMD_NAME_ENTRY(SET_TV_CHROMA_FILTER), 368 SDVO_CMD_NAME_ENTRY(GET_MAX_TV_LUMA_FILTER), 369 SDVO_CMD_NAME_ENTRY(GET_TV_LUMA_FILTER), 370 SDVO_CMD_NAME_ENTRY(SET_TV_LUMA_FILTER), 371 372 /* HDMI op code */ 373 SDVO_CMD_NAME_ENTRY(GET_SUPP_ENCODE), 374 SDVO_CMD_NAME_ENTRY(GET_ENCODE), 375 SDVO_CMD_NAME_ENTRY(SET_ENCODE), 376 SDVO_CMD_NAME_ENTRY(SET_PIXEL_REPLI), 377 SDVO_CMD_NAME_ENTRY(GET_PIXEL_REPLI), 378 SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY_CAP), 379 SDVO_CMD_NAME_ENTRY(SET_COLORIMETRY), 380 SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY), 381 SDVO_CMD_NAME_ENTRY(GET_AUDIO_ENCRYPT_PREFER), 382 SDVO_CMD_NAME_ENTRY(SET_AUDIO_STAT), 383 SDVO_CMD_NAME_ENTRY(GET_AUDIO_STAT), 384 SDVO_CMD_NAME_ENTRY(GET_HBUF_INDEX), 385 SDVO_CMD_NAME_ENTRY(SET_HBUF_INDEX), 386 SDVO_CMD_NAME_ENTRY(GET_HBUF_INFO), 387 SDVO_CMD_NAME_ENTRY(GET_HBUF_AV_SPLIT), 388 SDVO_CMD_NAME_ENTRY(SET_HBUF_AV_SPLIT), 389 SDVO_CMD_NAME_ENTRY(GET_HBUF_TXRATE), 390 SDVO_CMD_NAME_ENTRY(SET_HBUF_TXRATE), 391 SDVO_CMD_NAME_ENTRY(SET_HBUF_DATA), 392 SDVO_CMD_NAME_ENTRY(GET_HBUF_DATA), 393 }; 394 395 #undef SDVO_CMD_NAME_ENTRY 396 397 static const char *sdvo_cmd_name(u8 cmd) 398 { 399 int i; 400 401 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { 402 if (cmd == sdvo_cmd_names[i].cmd) 403 return sdvo_cmd_names[i].name; 404 } 405 406 return NULL; 407 } 408 409 #define SDVO_NAME(svdo) ((svdo)->port == PORT_B ? "SDVOB" : "SDVOC") 410 411 static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, 412 const void *args, int args_len) 413 { 414 const char *cmd_name; 415 int i, pos = 0; 416 char buffer[64]; 417 418 #define BUF_PRINT(args...) \ 419 pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0), args) 420 421 for (i = 0; i < args_len; i++) { 422 BUF_PRINT("%02X ", ((u8 *)args)[i]); 423 } 424 for (; i < 8; i++) { 425 BUF_PRINT(" "); 426 } 427 428 cmd_name = sdvo_cmd_name(cmd); 429 if (cmd_name) 430 BUF_PRINT("(%s)", cmd_name); 431 else 432 BUF_PRINT("(%02X)", cmd); 433 434 WARN_ON(pos >= sizeof(buffer) - 1); 435 #undef BUF_PRINT 436 437 DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer); 438 } 439 440 static const char * const cmd_status_names[] = { 441 [SDVO_CMD_STATUS_POWER_ON] = "Power on", 442 [SDVO_CMD_STATUS_SUCCESS] = "Success", 443 [SDVO_CMD_STATUS_NOTSUPP] = "Not supported", 444 [SDVO_CMD_STATUS_INVALID_ARG] = "Invalid arg", 445 [SDVO_CMD_STATUS_PENDING] = "Pending", 446 [SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED] = "Target not specified", 447 [SDVO_CMD_STATUS_SCALING_NOT_SUPP] = "Scaling not supported", 448 }; 449 450 static const char *sdvo_cmd_status(u8 status) 451 { 452 if (status < ARRAY_SIZE(cmd_status_names)) 453 return cmd_status_names[status]; 454 else 455 return NULL; 456 } 457 458 static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, 459 const void *args, int args_len, 460 bool unlocked) 461 { 462 u8 *buf, status; 463 struct i2c_msg *msgs; 464 int i, ret = true; 465 466 /* Would be simpler to allocate both in one go ? */ 467 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL); 468 if (!buf) 469 return false; 470 471 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL); 472 if (!msgs) { 473 kfree(buf); 474 return false; 475 } 476 477 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); 478 479 for (i = 0; i < args_len; i++) { 480 msgs[i].addr = intel_sdvo->slave_addr; 481 msgs[i].flags = 0; 482 msgs[i].len = 2; 483 msgs[i].buf = buf + 2 *i; 484 buf[2*i + 0] = SDVO_I2C_ARG_0 - i; 485 buf[2*i + 1] = ((u8*)args)[i]; 486 } 487 msgs[i].addr = intel_sdvo->slave_addr; 488 msgs[i].flags = 0; 489 msgs[i].len = 2; 490 msgs[i].buf = buf + 2*i; 491 buf[2*i + 0] = SDVO_I2C_OPCODE; 492 buf[2*i + 1] = cmd; 493 494 /* the following two are to read the response */ 495 status = SDVO_I2C_CMD_STATUS; 496 msgs[i+1].addr = intel_sdvo->slave_addr; 497 msgs[i+1].flags = 0; 498 msgs[i+1].len = 1; 499 msgs[i+1].buf = &status; 500 501 msgs[i+2].addr = intel_sdvo->slave_addr; 502 msgs[i+2].flags = I2C_M_RD; 503 msgs[i+2].len = 1; 504 msgs[i+2].buf = &status; 505 506 if (unlocked) 507 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3); 508 else 509 ret = __i2c_transfer(intel_sdvo->i2c, msgs, i+3); 510 if (ret < 0) { 511 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); 512 ret = false; 513 goto out; 514 } 515 if (ret != i+3) { 516 /* failure in I2C transfer */ 517 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3); 518 ret = false; 519 } 520 521 out: 522 kfree(msgs); 523 kfree(buf); 524 return ret; 525 } 526 527 static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, 528 const void *args, int args_len) 529 { 530 return __intel_sdvo_write_cmd(intel_sdvo, cmd, args, args_len, true); 531 } 532 533 static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, 534 void *response, int response_len) 535 { 536 const char *cmd_status; 537 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */ 538 u8 status; 539 int i, pos = 0; 540 char buffer[64]; 541 542 buffer[0] = '\0'; 543 544 /* 545 * The documentation states that all commands will be 546 * processed within 15µs, and that we need only poll 547 * the status byte a maximum of 3 times in order for the 548 * command to be complete. 549 * 550 * Check 5 times in case the hardware failed to read the docs. 551 * 552 * Also beware that the first response by many devices is to 553 * reply PENDING and stall for time. TVs are notorious for 554 * requiring longer than specified to complete their replies. 555 * Originally (in the DDX long ago), the delay was only ever 15ms 556 * with an additional delay of 30ms applied for TVs added later after 557 * many experiments. To accommodate both sets of delays, we do a 558 * sequence of slow checks if the device is falling behind and fails 559 * to reply within 5*15µs. 560 */ 561 if (!intel_sdvo_read_byte(intel_sdvo, 562 SDVO_I2C_CMD_STATUS, 563 &status)) 564 goto log_fail; 565 566 while ((status == SDVO_CMD_STATUS_PENDING || 567 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) { 568 if (retry < 10) 569 msleep(15); 570 else 571 udelay(15); 572 573 if (!intel_sdvo_read_byte(intel_sdvo, 574 SDVO_I2C_CMD_STATUS, 575 &status)) 576 goto log_fail; 577 } 578 579 #define BUF_PRINT(args...) \ 580 pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0), args) 581 582 cmd_status = sdvo_cmd_status(status); 583 if (cmd_status) 584 BUF_PRINT("(%s)", cmd_status); 585 else 586 BUF_PRINT("(??? %d)", status); 587 588 if (status != SDVO_CMD_STATUS_SUCCESS) 589 goto log_fail; 590 591 /* Read the command response */ 592 for (i = 0; i < response_len; i++) { 593 if (!intel_sdvo_read_byte(intel_sdvo, 594 SDVO_I2C_RETURN_0 + i, 595 &((u8 *)response)[i])) 596 goto log_fail; 597 BUF_PRINT(" %02X", ((u8 *)response)[i]); 598 } 599 600 WARN_ON(pos >= sizeof(buffer) - 1); 601 #undef BUF_PRINT 602 603 DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer); 604 return true; 605 606 log_fail: 607 DRM_DEBUG_KMS("%s: R: ... failed %s\n", 608 SDVO_NAME(intel_sdvo), buffer); 609 return false; 610 } 611 612 static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode) 613 { 614 if (adjusted_mode->crtc_clock >= 100000) 615 return 1; 616 else if (adjusted_mode->crtc_clock >= 50000) 617 return 2; 618 else 619 return 4; 620 } 621 622 static bool __intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, 623 u8 ddc_bus) 624 { 625 /* This must be the immediately preceding write before the i2c xfer */ 626 return __intel_sdvo_write_cmd(intel_sdvo, 627 SDVO_CMD_SET_CONTROL_BUS_SWITCH, 628 &ddc_bus, 1, false); 629 } 630 631 static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) 632 { 633 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) 634 return false; 635 636 return intel_sdvo_read_response(intel_sdvo, NULL, 0); 637 } 638 639 static bool 640 intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) 641 { 642 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) 643 return false; 644 645 return intel_sdvo_read_response(intel_sdvo, value, len); 646 } 647 648 static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) 649 { 650 struct intel_sdvo_set_target_input_args targets = {0}; 651 return intel_sdvo_set_value(intel_sdvo, 652 SDVO_CMD_SET_TARGET_INPUT, 653 &targets, sizeof(targets)); 654 } 655 656 /* 657 * Return whether each input is trained. 658 * 659 * This function is making an assumption about the layout of the response, 660 * which should be checked against the docs. 661 */ 662 static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) 663 { 664 struct intel_sdvo_get_trained_inputs_response response; 665 666 BUILD_BUG_ON(sizeof(response) != 1); 667 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, 668 &response, sizeof(response))) 669 return false; 670 671 *input_1 = response.input0_trained; 672 *input_2 = response.input1_trained; 673 return true; 674 } 675 676 static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, 677 u16 outputs) 678 { 679 return intel_sdvo_set_value(intel_sdvo, 680 SDVO_CMD_SET_ACTIVE_OUTPUTS, 681 &outputs, sizeof(outputs)); 682 } 683 684 static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo, 685 u16 *outputs) 686 { 687 return intel_sdvo_get_value(intel_sdvo, 688 SDVO_CMD_GET_ACTIVE_OUTPUTS, 689 outputs, sizeof(*outputs)); 690 } 691 692 static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, 693 int mode) 694 { 695 u8 state = SDVO_ENCODER_STATE_ON; 696 697 switch (mode) { 698 case DRM_MODE_DPMS_ON: 699 state = SDVO_ENCODER_STATE_ON; 700 break; 701 case DRM_MODE_DPMS_STANDBY: 702 state = SDVO_ENCODER_STATE_STANDBY; 703 break; 704 case DRM_MODE_DPMS_SUSPEND: 705 state = SDVO_ENCODER_STATE_SUSPEND; 706 break; 707 case DRM_MODE_DPMS_OFF: 708 state = SDVO_ENCODER_STATE_OFF; 709 break; 710 } 711 712 return intel_sdvo_set_value(intel_sdvo, 713 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); 714 } 715 716 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, 717 int *clock_min, 718 int *clock_max) 719 { 720 struct intel_sdvo_pixel_clock_range clocks; 721 722 BUILD_BUG_ON(sizeof(clocks) != 4); 723 if (!intel_sdvo_get_value(intel_sdvo, 724 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, 725 &clocks, sizeof(clocks))) 726 return false; 727 728 /* Convert the values from units of 10 kHz to kHz. */ 729 *clock_min = clocks.min * 10; 730 *clock_max = clocks.max * 10; 731 return true; 732 } 733 734 static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, 735 u16 outputs) 736 { 737 return intel_sdvo_set_value(intel_sdvo, 738 SDVO_CMD_SET_TARGET_OUTPUT, 739 &outputs, sizeof(outputs)); 740 } 741 742 static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 743 struct intel_sdvo_dtd *dtd) 744 { 745 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 746 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 747 } 748 749 static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 750 struct intel_sdvo_dtd *dtd) 751 { 752 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 753 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 754 } 755 756 static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, 757 struct intel_sdvo_dtd *dtd) 758 { 759 return intel_sdvo_set_timing(intel_sdvo, 760 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); 761 } 762 763 static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, 764 struct intel_sdvo_dtd *dtd) 765 { 766 return intel_sdvo_set_timing(intel_sdvo, 767 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); 768 } 769 770 static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo, 771 struct intel_sdvo_dtd *dtd) 772 { 773 return intel_sdvo_get_timing(intel_sdvo, 774 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd); 775 } 776 777 static bool 778 intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, 779 struct intel_sdvo_connector *intel_sdvo_connector, 780 u16 clock, 781 u16 width, 782 u16 height) 783 { 784 struct intel_sdvo_preferred_input_timing_args args; 785 786 memset(&args, 0, sizeof(args)); 787 args.clock = clock; 788 args.width = width; 789 args.height = height; 790 args.interlace = 0; 791 792 if (IS_LVDS(intel_sdvo_connector)) { 793 const struct drm_display_mode *fixed_mode = 794 intel_sdvo_connector->base.panel.fixed_mode; 795 796 if (fixed_mode->hdisplay != width || 797 fixed_mode->vdisplay != height) 798 args.scaled = 1; 799 } 800 801 return intel_sdvo_set_value(intel_sdvo, 802 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, 803 &args, sizeof(args)); 804 } 805 806 static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, 807 struct intel_sdvo_dtd *dtd) 808 { 809 BUILD_BUG_ON(sizeof(dtd->part1) != 8); 810 BUILD_BUG_ON(sizeof(dtd->part2) != 8); 811 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, 812 &dtd->part1, sizeof(dtd->part1)) && 813 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, 814 &dtd->part2, sizeof(dtd->part2)); 815 } 816 817 static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) 818 { 819 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); 820 } 821 822 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, 823 const struct drm_display_mode *mode) 824 { 825 u16 width, height; 826 u16 h_blank_len, h_sync_len, v_blank_len, v_sync_len; 827 u16 h_sync_offset, v_sync_offset; 828 int mode_clock; 829 830 memset(dtd, 0, sizeof(*dtd)); 831 832 width = mode->hdisplay; 833 height = mode->vdisplay; 834 835 /* do some mode translations */ 836 h_blank_len = mode->htotal - mode->hdisplay; 837 h_sync_len = mode->hsync_end - mode->hsync_start; 838 839 v_blank_len = mode->vtotal - mode->vdisplay; 840 v_sync_len = mode->vsync_end - mode->vsync_start; 841 842 h_sync_offset = mode->hsync_start - mode->hdisplay; 843 v_sync_offset = mode->vsync_start - mode->vdisplay; 844 845 mode_clock = mode->clock; 846 mode_clock /= 10; 847 dtd->part1.clock = mode_clock; 848 849 dtd->part1.h_active = width & 0xff; 850 dtd->part1.h_blank = h_blank_len & 0xff; 851 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | 852 ((h_blank_len >> 8) & 0xf); 853 dtd->part1.v_active = height & 0xff; 854 dtd->part1.v_blank = v_blank_len & 0xff; 855 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | 856 ((v_blank_len >> 8) & 0xf); 857 858 dtd->part2.h_sync_off = h_sync_offset & 0xff; 859 dtd->part2.h_sync_width = h_sync_len & 0xff; 860 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | 861 (v_sync_len & 0xf); 862 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | 863 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | 864 ((v_sync_len & 0x30) >> 4); 865 866 dtd->part2.dtd_flags = 0x18; 867 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 868 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE; 869 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 870 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE; 871 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 872 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE; 873 874 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; 875 } 876 877 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode, 878 const struct intel_sdvo_dtd *dtd) 879 { 880 struct drm_display_mode mode = {}; 881 882 mode.hdisplay = dtd->part1.h_active; 883 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; 884 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off; 885 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; 886 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width; 887 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; 888 mode.htotal = mode.hdisplay + dtd->part1.h_blank; 889 mode.htotal += (dtd->part1.h_high & 0xf) << 8; 890 891 mode.vdisplay = dtd->part1.v_active; 892 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; 893 mode.vsync_start = mode.vdisplay; 894 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; 895 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; 896 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0; 897 mode.vsync_end = mode.vsync_start + 898 (dtd->part2.v_sync_off_width & 0xf); 899 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; 900 mode.vtotal = mode.vdisplay + dtd->part1.v_blank; 901 mode.vtotal += (dtd->part1.v_high & 0xf) << 8; 902 903 mode.clock = dtd->part1.clock * 10; 904 905 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE) 906 mode.flags |= DRM_MODE_FLAG_INTERLACE; 907 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 908 mode.flags |= DRM_MODE_FLAG_PHSYNC; 909 else 910 mode.flags |= DRM_MODE_FLAG_NHSYNC; 911 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 912 mode.flags |= DRM_MODE_FLAG_PVSYNC; 913 else 914 mode.flags |= DRM_MODE_FLAG_NVSYNC; 915 916 drm_mode_set_crtcinfo(&mode, 0); 917 918 drm_mode_copy(pmode, &mode); 919 } 920 921 static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo) 922 { 923 struct intel_sdvo_encode encode; 924 925 BUILD_BUG_ON(sizeof(encode) != 2); 926 return intel_sdvo_get_value(intel_sdvo, 927 SDVO_CMD_GET_SUPP_ENCODE, 928 &encode, sizeof(encode)); 929 } 930 931 static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, 932 u8 mode) 933 { 934 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); 935 } 936 937 static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, 938 u8 mode) 939 { 940 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); 941 } 942 943 static bool intel_sdvo_set_audio_state(struct intel_sdvo *intel_sdvo, 944 u8 audio_state) 945 { 946 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_AUDIO_STAT, 947 &audio_state, 1); 948 } 949 950 static bool intel_sdvo_get_hbuf_size(struct intel_sdvo *intel_sdvo, 951 u8 *hbuf_size) 952 { 953 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO, 954 hbuf_size, 1)) 955 return false; 956 957 /* Buffer size is 0 based, hooray! However zero means zero. */ 958 if (*hbuf_size) 959 (*hbuf_size)++; 960 961 return true; 962 } 963 964 #if 0 965 static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) 966 { 967 int i, j; 968 u8 set_buf_index[2]; 969 u8 av_split; 970 u8 buf_size; 971 u8 buf[48]; 972 u8 *pos; 973 974 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); 975 976 for (i = 0; i <= av_split; i++) { 977 set_buf_index[0] = i; set_buf_index[1] = 0; 978 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, 979 set_buf_index, 2); 980 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); 981 intel_sdvo_read_response(encoder, &buf_size, 1); 982 983 pos = buf; 984 for (j = 0; j <= buf_size; j += 8) { 985 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, 986 NULL, 0); 987 intel_sdvo_read_response(encoder, pos, 8); 988 pos += 8; 989 } 990 } 991 } 992 #endif 993 994 static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo, 995 unsigned int if_index, u8 tx_rate, 996 const u8 *data, unsigned int length) 997 { 998 u8 set_buf_index[2] = { if_index, 0 }; 999 u8 hbuf_size, tmp[8]; 1000 int i; 1001 1002 if (!intel_sdvo_set_value(intel_sdvo, 1003 SDVO_CMD_SET_HBUF_INDEX, 1004 set_buf_index, 2)) 1005 return false; 1006 1007 if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size)) 1008 return false; 1009 1010 DRM_DEBUG_KMS("writing sdvo hbuf: %i, length %u, hbuf_size: %i\n", 1011 if_index, length, hbuf_size); 1012 1013 if (hbuf_size < length) 1014 return false; 1015 1016 for (i = 0; i < hbuf_size; i += 8) { 1017 memset(tmp, 0, 8); 1018 if (i < length) 1019 memcpy(tmp, data + i, min_t(unsigned, 8, length - i)); 1020 1021 if (!intel_sdvo_set_value(intel_sdvo, 1022 SDVO_CMD_SET_HBUF_DATA, 1023 tmp, 8)) 1024 return false; 1025 } 1026 1027 return intel_sdvo_set_value(intel_sdvo, 1028 SDVO_CMD_SET_HBUF_TXRATE, 1029 &tx_rate, 1); 1030 } 1031 1032 static ssize_t intel_sdvo_read_infoframe(struct intel_sdvo *intel_sdvo, 1033 unsigned int if_index, 1034 u8 *data, unsigned int length) 1035 { 1036 u8 set_buf_index[2] = { if_index, 0 }; 1037 u8 hbuf_size, tx_rate, av_split; 1038 int i; 1039 1040 if (!intel_sdvo_get_value(intel_sdvo, 1041 SDVO_CMD_GET_HBUF_AV_SPLIT, 1042 &av_split, 1)) 1043 return -ENXIO; 1044 1045 if (av_split < if_index) 1046 return 0; 1047 1048 if (!intel_sdvo_set_value(intel_sdvo, 1049 SDVO_CMD_SET_HBUF_INDEX, 1050 set_buf_index, 2)) 1051 return -ENXIO; 1052 1053 if (!intel_sdvo_get_value(intel_sdvo, 1054 SDVO_CMD_GET_HBUF_TXRATE, 1055 &tx_rate, 1)) 1056 return -ENXIO; 1057 1058 if (tx_rate == SDVO_HBUF_TX_DISABLED) 1059 return 0; 1060 1061 if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size)) 1062 return false; 1063 1064 DRM_DEBUG_KMS("reading sdvo hbuf: %i, length %u, hbuf_size: %i\n", 1065 if_index, length, hbuf_size); 1066 1067 hbuf_size = min_t(unsigned int, length, hbuf_size); 1068 1069 for (i = 0; i < hbuf_size; i += 8) { 1070 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HBUF_DATA, NULL, 0)) 1071 return -ENXIO; 1072 if (!intel_sdvo_read_response(intel_sdvo, &data[i], 1073 min_t(unsigned int, 8, hbuf_size - i))) 1074 return -ENXIO; 1075 } 1076 1077 return hbuf_size; 1078 } 1079 1080 static bool intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo, 1081 struct intel_crtc_state *crtc_state, 1082 struct drm_connector_state *conn_state) 1083 { 1084 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; 1085 const struct drm_display_mode *adjusted_mode = 1086 &crtc_state->hw.adjusted_mode; 1087 int ret; 1088 1089 if (!crtc_state->has_hdmi_sink) 1090 return true; 1091 1092 crtc_state->infoframes.enable |= 1093 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 1094 1095 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, 1096 conn_state->connector, 1097 adjusted_mode); 1098 if (ret) 1099 return false; 1100 1101 drm_hdmi_avi_infoframe_quant_range(frame, 1102 conn_state->connector, 1103 adjusted_mode, 1104 crtc_state->limited_color_range ? 1105 HDMI_QUANTIZATION_RANGE_LIMITED : 1106 HDMI_QUANTIZATION_RANGE_FULL); 1107 1108 ret = hdmi_avi_infoframe_check(frame); 1109 if (WARN_ON(ret)) 1110 return false; 1111 1112 return true; 1113 } 1114 1115 static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, 1116 const struct intel_crtc_state *crtc_state) 1117 { 1118 u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; 1119 const union hdmi_infoframe *frame = &crtc_state->infoframes.avi; 1120 ssize_t len; 1121 1122 if ((crtc_state->infoframes.enable & 1123 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) == 0) 1124 return true; 1125 1126 if (WARN_ON(frame->any.type != HDMI_INFOFRAME_TYPE_AVI)) 1127 return false; 1128 1129 len = hdmi_infoframe_pack_only(frame, sdvo_data, sizeof(sdvo_data)); 1130 if (WARN_ON(len < 0)) 1131 return false; 1132 1133 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, 1134 SDVO_HBUF_TX_VSYNC, 1135 sdvo_data, len); 1136 } 1137 1138 static void intel_sdvo_get_avi_infoframe(struct intel_sdvo *intel_sdvo, 1139 struct intel_crtc_state *crtc_state) 1140 { 1141 u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; 1142 union hdmi_infoframe *frame = &crtc_state->infoframes.avi; 1143 ssize_t len; 1144 int ret; 1145 1146 if (!crtc_state->has_hdmi_sink) 1147 return; 1148 1149 len = intel_sdvo_read_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, 1150 sdvo_data, sizeof(sdvo_data)); 1151 if (len < 0) { 1152 DRM_DEBUG_KMS("failed to read AVI infoframe\n"); 1153 return; 1154 } else if (len == 0) { 1155 return; 1156 } 1157 1158 crtc_state->infoframes.enable |= 1159 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 1160 1161 ret = hdmi_infoframe_unpack(frame, sdvo_data, len); 1162 if (ret) { 1163 DRM_DEBUG_KMS("Failed to unpack AVI infoframe\n"); 1164 return; 1165 } 1166 1167 if (frame->any.type != HDMI_INFOFRAME_TYPE_AVI) 1168 DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n", 1169 frame->any.type, HDMI_INFOFRAME_TYPE_AVI); 1170 } 1171 1172 static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo, 1173 const struct drm_connector_state *conn_state) 1174 { 1175 struct intel_sdvo_tv_format format; 1176 u32 format_map; 1177 1178 format_map = 1 << conn_state->tv.mode; 1179 memset(&format, 0, sizeof(format)); 1180 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); 1181 1182 BUILD_BUG_ON(sizeof(format) != 6); 1183 return intel_sdvo_set_value(intel_sdvo, 1184 SDVO_CMD_SET_TV_FORMAT, 1185 &format, sizeof(format)); 1186 } 1187 1188 static bool 1189 intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, 1190 const struct drm_display_mode *mode) 1191 { 1192 struct intel_sdvo_dtd output_dtd; 1193 1194 if (!intel_sdvo_set_target_output(intel_sdvo, 1195 intel_sdvo->attached_output)) 1196 return false; 1197 1198 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1199 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1200 return false; 1201 1202 return true; 1203 } 1204 1205 /* 1206 * Asks the sdvo controller for the preferred input mode given the output mode. 1207 * Unfortunately we have to set up the full output mode to do that. 1208 */ 1209 static bool 1210 intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo, 1211 struct intel_sdvo_connector *intel_sdvo_connector, 1212 const struct drm_display_mode *mode, 1213 struct drm_display_mode *adjusted_mode) 1214 { 1215 struct intel_sdvo_dtd input_dtd; 1216 1217 /* Reset the input timing to the screen. Assume always input 0. */ 1218 if (!intel_sdvo_set_target_input(intel_sdvo)) 1219 return false; 1220 1221 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, 1222 intel_sdvo_connector, 1223 mode->clock / 10, 1224 mode->hdisplay, 1225 mode->vdisplay)) 1226 return false; 1227 1228 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, 1229 &input_dtd)) 1230 return false; 1231 1232 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); 1233 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags; 1234 1235 return true; 1236 } 1237 1238 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) 1239 { 1240 unsigned dotclock = pipe_config->port_clock; 1241 struct dpll *clock = &pipe_config->dpll; 1242 1243 /* 1244 * SDVO TV has fixed PLL values depend on its clock range, 1245 * this mirrors vbios setting. 1246 */ 1247 if (dotclock >= 100000 && dotclock < 140500) { 1248 clock->p1 = 2; 1249 clock->p2 = 10; 1250 clock->n = 3; 1251 clock->m1 = 16; 1252 clock->m2 = 8; 1253 } else if (dotclock >= 140500 && dotclock <= 200000) { 1254 clock->p1 = 1; 1255 clock->p2 = 10; 1256 clock->n = 6; 1257 clock->m1 = 12; 1258 clock->m2 = 8; 1259 } else { 1260 WARN(1, "SDVO TV clock out of range: %i\n", dotclock); 1261 } 1262 1263 pipe_config->clock_set = true; 1264 } 1265 1266 static bool intel_has_hdmi_sink(struct intel_sdvo *sdvo, 1267 const struct drm_connector_state *conn_state) 1268 { 1269 return sdvo->has_hdmi_monitor && 1270 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; 1271 } 1272 1273 static int intel_sdvo_compute_config(struct intel_encoder *encoder, 1274 struct intel_crtc_state *pipe_config, 1275 struct drm_connector_state *conn_state) 1276 { 1277 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1278 struct intel_sdvo_connector_state *intel_sdvo_state = 1279 to_intel_sdvo_connector_state(conn_state); 1280 struct intel_sdvo_connector *intel_sdvo_connector = 1281 to_intel_sdvo_connector(conn_state->connector); 1282 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 1283 struct drm_display_mode *mode = &pipe_config->hw.mode; 1284 1285 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n"); 1286 pipe_config->pipe_bpp = 8*3; 1287 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 1288 1289 if (HAS_PCH_SPLIT(to_i915(encoder->base.dev))) 1290 pipe_config->has_pch_encoder = true; 1291 1292 /* 1293 * We need to construct preferred input timings based on our 1294 * output timings. To do that, we have to set the output 1295 * timings, even though this isn't really the right place in 1296 * the sequence to do it. Oh well. 1297 */ 1298 if (IS_TV(intel_sdvo_connector)) { 1299 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) 1300 return -EINVAL; 1301 1302 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1303 intel_sdvo_connector, 1304 mode, 1305 adjusted_mode); 1306 pipe_config->sdvo_tv_clock = true; 1307 } else if (IS_LVDS(intel_sdvo_connector)) { 1308 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, 1309 intel_sdvo_connector->base.panel.fixed_mode)) 1310 return -EINVAL; 1311 1312 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1313 intel_sdvo_connector, 1314 mode, 1315 adjusted_mode); 1316 } 1317 1318 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 1319 return -EINVAL; 1320 1321 /* 1322 * Make the CRTC code factor in the SDVO pixel multiplier. The 1323 * SDVO device will factor out the multiplier during mode_set. 1324 */ 1325 pipe_config->pixel_multiplier = 1326 intel_sdvo_get_pixel_multiplier(adjusted_mode); 1327 1328 pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo, conn_state); 1329 1330 if (pipe_config->has_hdmi_sink) { 1331 if (intel_sdvo_state->base.force_audio == HDMI_AUDIO_AUTO) 1332 pipe_config->has_audio = intel_sdvo->has_hdmi_audio; 1333 else 1334 pipe_config->has_audio = 1335 intel_sdvo_state->base.force_audio == HDMI_AUDIO_ON; 1336 } 1337 1338 if (intel_sdvo_state->base.broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 1339 /* 1340 * See CEA-861-E - 5.1 Default Encoding Parameters 1341 * 1342 * FIXME: This bit is only valid when using TMDS encoding and 8 1343 * bit per color mode. 1344 */ 1345 if (pipe_config->has_hdmi_sink && 1346 drm_match_cea_mode(adjusted_mode) > 1) 1347 pipe_config->limited_color_range = true; 1348 } else { 1349 if (pipe_config->has_hdmi_sink && 1350 intel_sdvo_state->base.broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED) 1351 pipe_config->limited_color_range = true; 1352 } 1353 1354 /* Clock computation needs to happen after pixel multiplier. */ 1355 if (IS_TV(intel_sdvo_connector)) 1356 i9xx_adjust_sdvo_tv_clock(pipe_config); 1357 1358 if (conn_state->picture_aspect_ratio) 1359 adjusted_mode->picture_aspect_ratio = 1360 conn_state->picture_aspect_ratio; 1361 1362 if (!intel_sdvo_compute_avi_infoframe(intel_sdvo, 1363 pipe_config, conn_state)) { 1364 DRM_DEBUG_KMS("bad AVI infoframe\n"); 1365 return -EINVAL; 1366 } 1367 1368 return 0; 1369 } 1370 1371 #define UPDATE_PROPERTY(input, NAME) \ 1372 do { \ 1373 val = input; \ 1374 intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_##NAME, &val, sizeof(val)); \ 1375 } while (0) 1376 1377 static void intel_sdvo_update_props(struct intel_sdvo *intel_sdvo, 1378 const struct intel_sdvo_connector_state *sdvo_state) 1379 { 1380 const struct drm_connector_state *conn_state = &sdvo_state->base.base; 1381 struct intel_sdvo_connector *intel_sdvo_conn = 1382 to_intel_sdvo_connector(conn_state->connector); 1383 u16 val; 1384 1385 if (intel_sdvo_conn->left) 1386 UPDATE_PROPERTY(sdvo_state->tv.overscan_h, OVERSCAN_H); 1387 1388 if (intel_sdvo_conn->top) 1389 UPDATE_PROPERTY(sdvo_state->tv.overscan_v, OVERSCAN_V); 1390 1391 if (intel_sdvo_conn->hpos) 1392 UPDATE_PROPERTY(sdvo_state->tv.hpos, HPOS); 1393 1394 if (intel_sdvo_conn->vpos) 1395 UPDATE_PROPERTY(sdvo_state->tv.vpos, VPOS); 1396 1397 if (intel_sdvo_conn->saturation) 1398 UPDATE_PROPERTY(conn_state->tv.saturation, SATURATION); 1399 1400 if (intel_sdvo_conn->contrast) 1401 UPDATE_PROPERTY(conn_state->tv.contrast, CONTRAST); 1402 1403 if (intel_sdvo_conn->hue) 1404 UPDATE_PROPERTY(conn_state->tv.hue, HUE); 1405 1406 if (intel_sdvo_conn->brightness) 1407 UPDATE_PROPERTY(conn_state->tv.brightness, BRIGHTNESS); 1408 1409 if (intel_sdvo_conn->sharpness) 1410 UPDATE_PROPERTY(sdvo_state->tv.sharpness, SHARPNESS); 1411 1412 if (intel_sdvo_conn->flicker_filter) 1413 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter, FLICKER_FILTER); 1414 1415 if (intel_sdvo_conn->flicker_filter_2d) 1416 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_2d, FLICKER_FILTER_2D); 1417 1418 if (intel_sdvo_conn->flicker_filter_adaptive) 1419 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); 1420 1421 if (intel_sdvo_conn->tv_chroma_filter) 1422 UPDATE_PROPERTY(sdvo_state->tv.chroma_filter, TV_CHROMA_FILTER); 1423 1424 if (intel_sdvo_conn->tv_luma_filter) 1425 UPDATE_PROPERTY(sdvo_state->tv.luma_filter, TV_LUMA_FILTER); 1426 1427 if (intel_sdvo_conn->dot_crawl) 1428 UPDATE_PROPERTY(sdvo_state->tv.dot_crawl, DOT_CRAWL); 1429 1430 #undef UPDATE_PROPERTY 1431 } 1432 1433 static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder, 1434 const struct intel_crtc_state *crtc_state, 1435 const struct drm_connector_state *conn_state) 1436 { 1437 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); 1438 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1439 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1440 const struct intel_sdvo_connector_state *sdvo_state = 1441 to_intel_sdvo_connector_state(conn_state); 1442 const struct intel_sdvo_connector *intel_sdvo_connector = 1443 to_intel_sdvo_connector(conn_state->connector); 1444 const struct drm_display_mode *mode = &crtc_state->hw.mode; 1445 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder); 1446 u32 sdvox; 1447 struct intel_sdvo_in_out_map in_out; 1448 struct intel_sdvo_dtd input_dtd, output_dtd; 1449 int rate; 1450 1451 intel_sdvo_update_props(intel_sdvo, sdvo_state); 1452 1453 /* 1454 * First, set the input mapping for the first input to our controlled 1455 * output. This is only correct if we're a single-input device, in 1456 * which case the first input is the output from the appropriate SDVO 1457 * channel on the motherboard. In a two-input device, the first input 1458 * will be SDVOB and the second SDVOC. 1459 */ 1460 in_out.in0 = intel_sdvo->attached_output; 1461 in_out.in1 = 0; 1462 1463 intel_sdvo_set_value(intel_sdvo, 1464 SDVO_CMD_SET_IN_OUT_MAP, 1465 &in_out, sizeof(in_out)); 1466 1467 /* Set the output timings to the screen */ 1468 if (!intel_sdvo_set_target_output(intel_sdvo, 1469 intel_sdvo->attached_output)) 1470 return; 1471 1472 /* lvds has a special fixed output timing. */ 1473 if (IS_LVDS(intel_sdvo_connector)) 1474 intel_sdvo_get_dtd_from_mode(&output_dtd, 1475 intel_sdvo_connector->base.panel.fixed_mode); 1476 else 1477 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1478 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1479 drm_info(&dev_priv->drm, 1480 "Setting output timings on %s failed\n", 1481 SDVO_NAME(intel_sdvo)); 1482 1483 /* Set the input timing to the screen. Assume always input 0. */ 1484 if (!intel_sdvo_set_target_input(intel_sdvo)) 1485 return; 1486 1487 if (crtc_state->has_hdmi_sink) { 1488 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); 1489 intel_sdvo_set_colorimetry(intel_sdvo, 1490 SDVO_COLORIMETRY_RGB256); 1491 intel_sdvo_set_avi_infoframe(intel_sdvo, crtc_state); 1492 } else 1493 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI); 1494 1495 if (IS_TV(intel_sdvo_connector) && 1496 !intel_sdvo_set_tv_format(intel_sdvo, conn_state)) 1497 return; 1498 1499 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); 1500 1501 if (IS_TV(intel_sdvo_connector) || IS_LVDS(intel_sdvo_connector)) 1502 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags; 1503 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd)) 1504 drm_info(&dev_priv->drm, 1505 "Setting input timings on %s failed\n", 1506 SDVO_NAME(intel_sdvo)); 1507 1508 switch (crtc_state->pixel_multiplier) { 1509 default: 1510 drm_WARN(&dev_priv->drm, 1, 1511 "unknown pixel multiplier specified\n"); 1512 /* fall through */ 1513 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; 1514 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; 1515 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; 1516 } 1517 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) 1518 return; 1519 1520 /* Set the SDVO control regs. */ 1521 if (INTEL_GEN(dev_priv) >= 4) { 1522 /* The real mode polarity is set by the SDVO commands, using 1523 * struct intel_sdvo_dtd. */ 1524 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; 1525 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) 1526 sdvox |= HDMI_COLOR_RANGE_16_235; 1527 if (INTEL_GEN(dev_priv) < 5) 1528 sdvox |= SDVO_BORDER_ENABLE; 1529 } else { 1530 sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg); 1531 if (intel_sdvo->port == PORT_B) 1532 sdvox &= SDVOB_PRESERVE_MASK; 1533 else 1534 sdvox &= SDVOC_PRESERVE_MASK; 1535 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; 1536 } 1537 1538 if (HAS_PCH_CPT(dev_priv)) 1539 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe); 1540 else 1541 sdvox |= SDVO_PIPE_SEL(crtc->pipe); 1542 1543 if (INTEL_GEN(dev_priv) >= 4) { 1544 /* done in crtc_mode_set as the dpll_md reg must be written early */ 1545 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 1546 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 1547 /* done in crtc_mode_set as it lives inside the dpll register */ 1548 } else { 1549 sdvox |= (crtc_state->pixel_multiplier - 1) 1550 << SDVO_PORT_MULTIPLY_SHIFT; 1551 } 1552 1553 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && 1554 INTEL_GEN(dev_priv) < 5) 1555 sdvox |= SDVO_STALL_SELECT; 1556 intel_sdvo_write_sdvox(intel_sdvo, sdvox); 1557 } 1558 1559 static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector) 1560 { 1561 struct intel_sdvo_connector *intel_sdvo_connector = 1562 to_intel_sdvo_connector(&connector->base); 1563 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1564 u16 active_outputs = 0; 1565 1566 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1567 1568 return active_outputs & intel_sdvo_connector->output_flag; 1569 } 1570 1571 bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv, 1572 i915_reg_t sdvo_reg, enum pipe *pipe) 1573 { 1574 u32 val; 1575 1576 val = intel_de_read(dev_priv, sdvo_reg); 1577 1578 /* asserts want to know the pipe even if the port is disabled */ 1579 if (HAS_PCH_CPT(dev_priv)) 1580 *pipe = (val & SDVO_PIPE_SEL_MASK_CPT) >> SDVO_PIPE_SEL_SHIFT_CPT; 1581 else if (IS_CHERRYVIEW(dev_priv)) 1582 *pipe = (val & SDVO_PIPE_SEL_MASK_CHV) >> SDVO_PIPE_SEL_SHIFT_CHV; 1583 else 1584 *pipe = (val & SDVO_PIPE_SEL_MASK) >> SDVO_PIPE_SEL_SHIFT; 1585 1586 return val & SDVO_ENABLE; 1587 } 1588 1589 static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder, 1590 enum pipe *pipe) 1591 { 1592 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1593 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1594 u16 active_outputs = 0; 1595 bool ret; 1596 1597 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1598 1599 ret = intel_sdvo_port_enabled(dev_priv, intel_sdvo->sdvo_reg, pipe); 1600 1601 return ret || active_outputs; 1602 } 1603 1604 static void intel_sdvo_get_config(struct intel_encoder *encoder, 1605 struct intel_crtc_state *pipe_config) 1606 { 1607 struct drm_device *dev = encoder->base.dev; 1608 struct drm_i915_private *dev_priv = to_i915(dev); 1609 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1610 struct intel_sdvo_dtd dtd; 1611 int encoder_pixel_multiplier = 0; 1612 int dotclock; 1613 u32 flags = 0, sdvox; 1614 u8 val; 1615 bool ret; 1616 1617 pipe_config->output_types |= BIT(INTEL_OUTPUT_SDVO); 1618 1619 sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg); 1620 1621 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd); 1622 if (!ret) { 1623 /* 1624 * Some sdvo encoders are not spec compliant and don't 1625 * implement the mandatory get_timings function. 1626 */ 1627 drm_dbg(&dev_priv->drm, "failed to retrieve SDVO DTD\n"); 1628 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS; 1629 } else { 1630 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 1631 flags |= DRM_MODE_FLAG_PHSYNC; 1632 else 1633 flags |= DRM_MODE_FLAG_NHSYNC; 1634 1635 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 1636 flags |= DRM_MODE_FLAG_PVSYNC; 1637 else 1638 flags |= DRM_MODE_FLAG_NVSYNC; 1639 } 1640 1641 pipe_config->hw.adjusted_mode.flags |= flags; 1642 1643 /* 1644 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in 1645 * the sdvo port register, on all other platforms it is part of the dpll 1646 * state. Since the general pipe state readout happens before the 1647 * encoder->get_config we so already have a valid pixel multplier on all 1648 * other platfroms. 1649 */ 1650 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { 1651 pipe_config->pixel_multiplier = 1652 ((sdvox & SDVO_PORT_MULTIPLY_MASK) 1653 >> SDVO_PORT_MULTIPLY_SHIFT) + 1; 1654 } 1655 1656 dotclock = pipe_config->port_clock; 1657 1658 if (pipe_config->pixel_multiplier) 1659 dotclock /= pipe_config->pixel_multiplier; 1660 1661 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 1662 1663 /* Cross check the port pixel multiplier with the sdvo encoder state. */ 1664 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, 1665 &val, 1)) { 1666 switch (val) { 1667 case SDVO_CLOCK_RATE_MULT_1X: 1668 encoder_pixel_multiplier = 1; 1669 break; 1670 case SDVO_CLOCK_RATE_MULT_2X: 1671 encoder_pixel_multiplier = 2; 1672 break; 1673 case SDVO_CLOCK_RATE_MULT_4X: 1674 encoder_pixel_multiplier = 4; 1675 break; 1676 } 1677 } 1678 1679 drm_WARN(dev, 1680 encoder_pixel_multiplier != pipe_config->pixel_multiplier, 1681 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n", 1682 pipe_config->pixel_multiplier, encoder_pixel_multiplier); 1683 1684 if (sdvox & HDMI_COLOR_RANGE_16_235) 1685 pipe_config->limited_color_range = true; 1686 1687 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_AUDIO_STAT, 1688 &val, 1)) { 1689 u8 mask = SDVO_AUDIO_ELD_VALID | SDVO_AUDIO_PRESENCE_DETECT; 1690 1691 if ((val & mask) == mask) 1692 pipe_config->has_audio = true; 1693 } 1694 1695 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE, 1696 &val, 1)) { 1697 if (val == SDVO_ENCODE_HDMI) 1698 pipe_config->has_hdmi_sink = true; 1699 } 1700 1701 intel_sdvo_get_avi_infoframe(intel_sdvo, pipe_config); 1702 } 1703 1704 static void intel_sdvo_disable_audio(struct intel_sdvo *intel_sdvo) 1705 { 1706 intel_sdvo_set_audio_state(intel_sdvo, 0); 1707 } 1708 1709 static void intel_sdvo_enable_audio(struct intel_sdvo *intel_sdvo, 1710 const struct intel_crtc_state *crtc_state, 1711 const struct drm_connector_state *conn_state) 1712 { 1713 const struct drm_display_mode *adjusted_mode = 1714 &crtc_state->hw.adjusted_mode; 1715 struct drm_connector *connector = conn_state->connector; 1716 u8 *eld = connector->eld; 1717 1718 eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2; 1719 1720 intel_sdvo_set_audio_state(intel_sdvo, 0); 1721 1722 intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_ELD, 1723 SDVO_HBUF_TX_DISABLED, 1724 eld, drm_eld_size(eld)); 1725 1726 intel_sdvo_set_audio_state(intel_sdvo, SDVO_AUDIO_ELD_VALID | 1727 SDVO_AUDIO_PRESENCE_DETECT); 1728 } 1729 1730 static void intel_disable_sdvo(struct intel_encoder *encoder, 1731 const struct intel_crtc_state *old_crtc_state, 1732 const struct drm_connector_state *conn_state) 1733 { 1734 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1735 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1736 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1737 u32 temp; 1738 1739 if (old_crtc_state->has_audio) 1740 intel_sdvo_disable_audio(intel_sdvo); 1741 1742 intel_sdvo_set_active_outputs(intel_sdvo, 0); 1743 if (0) 1744 intel_sdvo_set_encoder_power_state(intel_sdvo, 1745 DRM_MODE_DPMS_OFF); 1746 1747 temp = intel_de_read(dev_priv, intel_sdvo->sdvo_reg); 1748 1749 temp &= ~SDVO_ENABLE; 1750 intel_sdvo_write_sdvox(intel_sdvo, temp); 1751 1752 /* 1753 * HW workaround for IBX, we need to move the port 1754 * to transcoder A after disabling it to allow the 1755 * matching DP port to be enabled on transcoder A. 1756 */ 1757 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { 1758 /* 1759 * We get CPU/PCH FIFO underruns on the other pipe when 1760 * doing the workaround. Sweep them under the rug. 1761 */ 1762 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); 1763 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 1764 1765 temp &= ~SDVO_PIPE_SEL_MASK; 1766 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); 1767 intel_sdvo_write_sdvox(intel_sdvo, temp); 1768 1769 temp &= ~SDVO_ENABLE; 1770 intel_sdvo_write_sdvox(intel_sdvo, temp); 1771 1772 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); 1773 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); 1774 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 1775 } 1776 } 1777 1778 static void pch_disable_sdvo(struct intel_encoder *encoder, 1779 const struct intel_crtc_state *old_crtc_state, 1780 const struct drm_connector_state *old_conn_state) 1781 { 1782 } 1783 1784 static void pch_post_disable_sdvo(struct intel_encoder *encoder, 1785 const struct intel_crtc_state *old_crtc_state, 1786 const struct drm_connector_state *old_conn_state) 1787 { 1788 intel_disable_sdvo(encoder, old_crtc_state, old_conn_state); 1789 } 1790 1791 static void intel_enable_sdvo(struct intel_encoder *encoder, 1792 const struct intel_crtc_state *pipe_config, 1793 const struct drm_connector_state *conn_state) 1794 { 1795 struct drm_device *dev = encoder->base.dev; 1796 struct drm_i915_private *dev_priv = to_i915(dev); 1797 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1798 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); 1799 u32 temp; 1800 bool input1, input2; 1801 int i; 1802 bool success; 1803 1804 temp = intel_de_read(dev_priv, intel_sdvo->sdvo_reg); 1805 temp |= SDVO_ENABLE; 1806 intel_sdvo_write_sdvox(intel_sdvo, temp); 1807 1808 for (i = 0; i < 2; i++) 1809 intel_wait_for_vblank(dev_priv, intel_crtc->pipe); 1810 1811 success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); 1812 /* 1813 * Warn if the device reported failure to sync. 1814 * 1815 * A lot of SDVO devices fail to notify of sync, but it's 1816 * a given it the status is a success, we succeeded. 1817 */ 1818 if (success && !input1) { 1819 drm_dbg_kms(&dev_priv->drm, 1820 "First %s output reported failure to " 1821 "sync\n", SDVO_NAME(intel_sdvo)); 1822 } 1823 1824 if (0) 1825 intel_sdvo_set_encoder_power_state(intel_sdvo, 1826 DRM_MODE_DPMS_ON); 1827 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); 1828 1829 if (pipe_config->has_audio) 1830 intel_sdvo_enable_audio(intel_sdvo, pipe_config, conn_state); 1831 } 1832 1833 static enum drm_mode_status 1834 intel_sdvo_mode_valid(struct drm_connector *connector, 1835 struct drm_display_mode *mode) 1836 { 1837 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 1838 struct intel_sdvo_connector *intel_sdvo_connector = 1839 to_intel_sdvo_connector(connector); 1840 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 1841 1842 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1843 return MODE_NO_DBLESCAN; 1844 1845 if (intel_sdvo->pixel_clock_min > mode->clock) 1846 return MODE_CLOCK_LOW; 1847 1848 if (intel_sdvo->pixel_clock_max < mode->clock) 1849 return MODE_CLOCK_HIGH; 1850 1851 if (mode->clock > max_dotclk) 1852 return MODE_CLOCK_HIGH; 1853 1854 if (IS_LVDS(intel_sdvo_connector)) { 1855 const struct drm_display_mode *fixed_mode = 1856 intel_sdvo_connector->base.panel.fixed_mode; 1857 1858 if (mode->hdisplay > fixed_mode->hdisplay) 1859 return MODE_PANEL; 1860 1861 if (mode->vdisplay > fixed_mode->vdisplay) 1862 return MODE_PANEL; 1863 } 1864 1865 return MODE_OK; 1866 } 1867 1868 static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) 1869 { 1870 BUILD_BUG_ON(sizeof(*caps) != 8); 1871 if (!intel_sdvo_get_value(intel_sdvo, 1872 SDVO_CMD_GET_DEVICE_CAPS, 1873 caps, sizeof(*caps))) 1874 return false; 1875 1876 DRM_DEBUG_KMS("SDVO capabilities:\n" 1877 " vendor_id: %d\n" 1878 " device_id: %d\n" 1879 " device_rev_id: %d\n" 1880 " sdvo_version_major: %d\n" 1881 " sdvo_version_minor: %d\n" 1882 " sdvo_inputs_mask: %d\n" 1883 " smooth_scaling: %d\n" 1884 " sharp_scaling: %d\n" 1885 " up_scaling: %d\n" 1886 " down_scaling: %d\n" 1887 " stall_support: %d\n" 1888 " output_flags: %d\n", 1889 caps->vendor_id, 1890 caps->device_id, 1891 caps->device_rev_id, 1892 caps->sdvo_version_major, 1893 caps->sdvo_version_minor, 1894 caps->sdvo_inputs_mask, 1895 caps->smooth_scaling, 1896 caps->sharp_scaling, 1897 caps->up_scaling, 1898 caps->down_scaling, 1899 caps->stall_support, 1900 caps->output_flags); 1901 1902 return true; 1903 } 1904 1905 static u16 intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo) 1906 { 1907 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); 1908 u16 hotplug; 1909 1910 if (!I915_HAS_HOTPLUG(dev_priv)) 1911 return 0; 1912 1913 /* 1914 * HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise 1915 * on the line. 1916 */ 1917 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) 1918 return 0; 1919 1920 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, 1921 &hotplug, sizeof(hotplug))) 1922 return 0; 1923 1924 return hotplug; 1925 } 1926 1927 static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder) 1928 { 1929 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1930 1931 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, 1932 &intel_sdvo->hotplug_active, 2); 1933 } 1934 1935 static enum intel_hotplug_state 1936 intel_sdvo_hotplug(struct intel_encoder *encoder, 1937 struct intel_connector *connector, 1938 bool irq_received) 1939 { 1940 intel_sdvo_enable_hotplug(encoder); 1941 1942 return intel_encoder_hotplug(encoder, connector, irq_received); 1943 } 1944 1945 static bool 1946 intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo) 1947 { 1948 /* Is there more than one type of output? */ 1949 return hweight16(intel_sdvo->caps.output_flags) > 1; 1950 } 1951 1952 static struct edid * 1953 intel_sdvo_get_edid(struct drm_connector *connector) 1954 { 1955 struct intel_sdvo *sdvo = intel_attached_sdvo(to_intel_connector(connector)); 1956 return drm_get_edid(connector, &sdvo->ddc); 1957 } 1958 1959 /* Mac mini hack -- use the same DDC as the analog connector */ 1960 static struct edid * 1961 intel_sdvo_get_analog_edid(struct drm_connector *connector) 1962 { 1963 struct drm_i915_private *dev_priv = to_i915(connector->dev); 1964 1965 return drm_get_edid(connector, 1966 intel_gmbus_get_adapter(dev_priv, 1967 dev_priv->vbt.crt_ddc_pin)); 1968 } 1969 1970 static enum drm_connector_status 1971 intel_sdvo_tmds_sink_detect(struct drm_connector *connector) 1972 { 1973 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 1974 struct intel_sdvo_connector *intel_sdvo_connector = 1975 to_intel_sdvo_connector(connector); 1976 enum drm_connector_status status; 1977 struct edid *edid; 1978 1979 edid = intel_sdvo_get_edid(connector); 1980 1981 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) { 1982 u8 ddc, saved_ddc = intel_sdvo->ddc_bus; 1983 1984 /* 1985 * Don't use the 1 as the argument of DDC bus switch to get 1986 * the EDID. It is used for SDVO SPD ROM. 1987 */ 1988 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) { 1989 intel_sdvo->ddc_bus = ddc; 1990 edid = intel_sdvo_get_edid(connector); 1991 if (edid) 1992 break; 1993 } 1994 /* 1995 * If we found the EDID on the other bus, 1996 * assume that is the correct DDC bus. 1997 */ 1998 if (edid == NULL) 1999 intel_sdvo->ddc_bus = saved_ddc; 2000 } 2001 2002 /* 2003 * When there is no edid and no monitor is connected with VGA 2004 * port, try to use the CRT ddc to read the EDID for DVI-connector. 2005 */ 2006 if (edid == NULL) 2007 edid = intel_sdvo_get_analog_edid(connector); 2008 2009 status = connector_status_unknown; 2010 if (edid != NULL) { 2011 /* DDC bus is shared, match EDID to connector type */ 2012 if (edid->input & DRM_EDID_INPUT_DIGITAL) { 2013 status = connector_status_connected; 2014 if (intel_sdvo_connector->is_hdmi) { 2015 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid); 2016 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid); 2017 } 2018 } else 2019 status = connector_status_disconnected; 2020 kfree(edid); 2021 } 2022 2023 return status; 2024 } 2025 2026 static bool 2027 intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo, 2028 struct edid *edid) 2029 { 2030 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); 2031 bool connector_is_digital = !!IS_DIGITAL(sdvo); 2032 2033 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n", 2034 connector_is_digital, monitor_is_digital); 2035 return connector_is_digital == monitor_is_digital; 2036 } 2037 2038 static enum drm_connector_status 2039 intel_sdvo_detect(struct drm_connector *connector, bool force) 2040 { 2041 u16 response; 2042 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2043 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2044 enum drm_connector_status ret; 2045 2046 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 2047 connector->base.id, connector->name); 2048 2049 if (!intel_sdvo_get_value(intel_sdvo, 2050 SDVO_CMD_GET_ATTACHED_DISPLAYS, 2051 &response, 2)) 2052 return connector_status_unknown; 2053 2054 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n", 2055 response & 0xff, response >> 8, 2056 intel_sdvo_connector->output_flag); 2057 2058 if (response == 0) 2059 return connector_status_disconnected; 2060 2061 intel_sdvo->attached_output = response; 2062 2063 intel_sdvo->has_hdmi_monitor = false; 2064 intel_sdvo->has_hdmi_audio = false; 2065 2066 if ((intel_sdvo_connector->output_flag & response) == 0) 2067 ret = connector_status_disconnected; 2068 else if (IS_TMDS(intel_sdvo_connector)) 2069 ret = intel_sdvo_tmds_sink_detect(connector); 2070 else { 2071 struct edid *edid; 2072 2073 /* if we have an edid check it matches the connection */ 2074 edid = intel_sdvo_get_edid(connector); 2075 if (edid == NULL) 2076 edid = intel_sdvo_get_analog_edid(connector); 2077 if (edid != NULL) { 2078 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector, 2079 edid)) 2080 ret = connector_status_connected; 2081 else 2082 ret = connector_status_disconnected; 2083 2084 kfree(edid); 2085 } else 2086 ret = connector_status_connected; 2087 } 2088 2089 return ret; 2090 } 2091 2092 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) 2093 { 2094 struct edid *edid; 2095 2096 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 2097 connector->base.id, connector->name); 2098 2099 /* set the bus switch and get the modes */ 2100 edid = intel_sdvo_get_edid(connector); 2101 2102 /* 2103 * Mac mini hack. On this device, the DVI-I connector shares one DDC 2104 * link between analog and digital outputs. So, if the regular SDVO 2105 * DDC fails, check to see if the analog output is disconnected, in 2106 * which case we'll look there for the digital DDC data. 2107 */ 2108 if (edid == NULL) 2109 edid = intel_sdvo_get_analog_edid(connector); 2110 2111 if (edid != NULL) { 2112 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector), 2113 edid)) { 2114 drm_connector_update_edid_property(connector, edid); 2115 drm_add_edid_modes(connector, edid); 2116 } 2117 2118 kfree(edid); 2119 } 2120 } 2121 2122 /* 2123 * Set of SDVO TV modes. 2124 * Note! This is in reply order (see loop in get_tv_modes). 2125 * XXX: all 60Hz refresh? 2126 */ 2127 static const struct drm_display_mode sdvo_tv_modes[] = { 2128 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, 2129 416, 0, 200, 201, 232, 233, 0, 2130 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2131 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, 2132 416, 0, 240, 241, 272, 273, 0, 2133 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2134 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, 2135 496, 0, 300, 301, 332, 333, 0, 2136 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2137 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, 2138 736, 0, 350, 351, 382, 383, 0, 2139 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2140 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, 2141 736, 0, 400, 401, 432, 433, 0, 2142 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2143 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, 2144 736, 0, 480, 481, 512, 513, 0, 2145 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2146 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, 2147 800, 0, 480, 481, 512, 513, 0, 2148 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2149 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, 2150 800, 0, 576, 577, 608, 609, 0, 2151 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2152 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, 2153 816, 0, 350, 351, 382, 383, 0, 2154 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2155 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, 2156 816, 0, 400, 401, 432, 433, 0, 2157 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2158 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, 2159 816, 0, 480, 481, 512, 513, 0, 2160 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2161 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, 2162 816, 0, 540, 541, 572, 573, 0, 2163 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2164 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, 2165 816, 0, 576, 577, 608, 609, 0, 2166 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2167 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, 2168 864, 0, 576, 577, 608, 609, 0, 2169 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2170 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, 2171 896, 0, 600, 601, 632, 633, 0, 2172 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2173 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, 2174 928, 0, 624, 625, 656, 657, 0, 2175 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2176 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, 2177 1016, 0, 766, 767, 798, 799, 0, 2178 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2179 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, 2180 1120, 0, 768, 769, 800, 801, 0, 2181 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2182 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, 2183 1376, 0, 1024, 1025, 1056, 1057, 0, 2184 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 2185 }; 2186 2187 static void intel_sdvo_get_tv_modes(struct drm_connector *connector) 2188 { 2189 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2190 const struct drm_connector_state *conn_state = connector->state; 2191 struct intel_sdvo_sdtv_resolution_request tv_res; 2192 u32 reply = 0, format_map = 0; 2193 int i; 2194 2195 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 2196 connector->base.id, connector->name); 2197 2198 /* 2199 * Read the list of supported input resolutions for the selected TV 2200 * format. 2201 */ 2202 format_map = 1 << conn_state->tv.mode; 2203 memcpy(&tv_res, &format_map, 2204 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); 2205 2206 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output)) 2207 return; 2208 2209 BUILD_BUG_ON(sizeof(tv_res) != 3); 2210 if (!intel_sdvo_write_cmd(intel_sdvo, 2211 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, 2212 &tv_res, sizeof(tv_res))) 2213 return; 2214 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) 2215 return; 2216 2217 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) 2218 if (reply & (1 << i)) { 2219 struct drm_display_mode *nmode; 2220 nmode = drm_mode_duplicate(connector->dev, 2221 &sdvo_tv_modes[i]); 2222 if (nmode) 2223 drm_mode_probed_add(connector, nmode); 2224 } 2225 } 2226 2227 static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) 2228 { 2229 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2230 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2231 struct drm_display_mode *newmode; 2232 2233 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", 2234 connector->base.id, connector->name); 2235 2236 /* 2237 * Fetch modes from VBT. For SDVO prefer the VBT mode since some 2238 * SDVO->LVDS transcoders can't cope with the EDID mode. 2239 */ 2240 if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) { 2241 newmode = drm_mode_duplicate(connector->dev, 2242 dev_priv->vbt.sdvo_lvds_vbt_mode); 2243 if (newmode != NULL) { 2244 /* Guarantee the mode is preferred */ 2245 newmode->type = (DRM_MODE_TYPE_PREFERRED | 2246 DRM_MODE_TYPE_DRIVER); 2247 drm_mode_probed_add(connector, newmode); 2248 } 2249 } 2250 2251 /* 2252 * Attempt to get the mode list from DDC. 2253 * Assume that the preferred modes are 2254 * arranged in priority order. 2255 */ 2256 intel_ddc_get_modes(connector, &intel_sdvo->ddc); 2257 } 2258 2259 static int intel_sdvo_get_modes(struct drm_connector *connector) 2260 { 2261 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2262 2263 if (IS_TV(intel_sdvo_connector)) 2264 intel_sdvo_get_tv_modes(connector); 2265 else if (IS_LVDS(intel_sdvo_connector)) 2266 intel_sdvo_get_lvds_modes(connector); 2267 else 2268 intel_sdvo_get_ddc_modes(connector); 2269 2270 return !list_empty(&connector->probed_modes); 2271 } 2272 2273 static int 2274 intel_sdvo_connector_atomic_get_property(struct drm_connector *connector, 2275 const struct drm_connector_state *state, 2276 struct drm_property *property, 2277 u64 *val) 2278 { 2279 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2280 const struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state((void *)state); 2281 2282 if (property == intel_sdvo_connector->tv_format) { 2283 int i; 2284 2285 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) 2286 if (state->tv.mode == intel_sdvo_connector->tv_format_supported[i]) { 2287 *val = i; 2288 2289 return 0; 2290 } 2291 2292 WARN_ON(1); 2293 *val = 0; 2294 } else if (property == intel_sdvo_connector->top || 2295 property == intel_sdvo_connector->bottom) 2296 *val = intel_sdvo_connector->max_vscan - sdvo_state->tv.overscan_v; 2297 else if (property == intel_sdvo_connector->left || 2298 property == intel_sdvo_connector->right) 2299 *val = intel_sdvo_connector->max_hscan - sdvo_state->tv.overscan_h; 2300 else if (property == intel_sdvo_connector->hpos) 2301 *val = sdvo_state->tv.hpos; 2302 else if (property == intel_sdvo_connector->vpos) 2303 *val = sdvo_state->tv.vpos; 2304 else if (property == intel_sdvo_connector->saturation) 2305 *val = state->tv.saturation; 2306 else if (property == intel_sdvo_connector->contrast) 2307 *val = state->tv.contrast; 2308 else if (property == intel_sdvo_connector->hue) 2309 *val = state->tv.hue; 2310 else if (property == intel_sdvo_connector->brightness) 2311 *val = state->tv.brightness; 2312 else if (property == intel_sdvo_connector->sharpness) 2313 *val = sdvo_state->tv.sharpness; 2314 else if (property == intel_sdvo_connector->flicker_filter) 2315 *val = sdvo_state->tv.flicker_filter; 2316 else if (property == intel_sdvo_connector->flicker_filter_2d) 2317 *val = sdvo_state->tv.flicker_filter_2d; 2318 else if (property == intel_sdvo_connector->flicker_filter_adaptive) 2319 *val = sdvo_state->tv.flicker_filter_adaptive; 2320 else if (property == intel_sdvo_connector->tv_chroma_filter) 2321 *val = sdvo_state->tv.chroma_filter; 2322 else if (property == intel_sdvo_connector->tv_luma_filter) 2323 *val = sdvo_state->tv.luma_filter; 2324 else if (property == intel_sdvo_connector->dot_crawl) 2325 *val = sdvo_state->tv.dot_crawl; 2326 else 2327 return intel_digital_connector_atomic_get_property(connector, state, property, val); 2328 2329 return 0; 2330 } 2331 2332 static int 2333 intel_sdvo_connector_atomic_set_property(struct drm_connector *connector, 2334 struct drm_connector_state *state, 2335 struct drm_property *property, 2336 u64 val) 2337 { 2338 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2339 struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state(state); 2340 2341 if (property == intel_sdvo_connector->tv_format) { 2342 state->tv.mode = intel_sdvo_connector->tv_format_supported[val]; 2343 2344 if (state->crtc) { 2345 struct drm_crtc_state *crtc_state = 2346 drm_atomic_get_new_crtc_state(state->state, state->crtc); 2347 2348 crtc_state->connectors_changed = true; 2349 } 2350 } else if (property == intel_sdvo_connector->top || 2351 property == intel_sdvo_connector->bottom) 2352 /* Cannot set these independent from each other */ 2353 sdvo_state->tv.overscan_v = intel_sdvo_connector->max_vscan - val; 2354 else if (property == intel_sdvo_connector->left || 2355 property == intel_sdvo_connector->right) 2356 /* Cannot set these independent from each other */ 2357 sdvo_state->tv.overscan_h = intel_sdvo_connector->max_hscan - val; 2358 else if (property == intel_sdvo_connector->hpos) 2359 sdvo_state->tv.hpos = val; 2360 else if (property == intel_sdvo_connector->vpos) 2361 sdvo_state->tv.vpos = val; 2362 else if (property == intel_sdvo_connector->saturation) 2363 state->tv.saturation = val; 2364 else if (property == intel_sdvo_connector->contrast) 2365 state->tv.contrast = val; 2366 else if (property == intel_sdvo_connector->hue) 2367 state->tv.hue = val; 2368 else if (property == intel_sdvo_connector->brightness) 2369 state->tv.brightness = val; 2370 else if (property == intel_sdvo_connector->sharpness) 2371 sdvo_state->tv.sharpness = val; 2372 else if (property == intel_sdvo_connector->flicker_filter) 2373 sdvo_state->tv.flicker_filter = val; 2374 else if (property == intel_sdvo_connector->flicker_filter_2d) 2375 sdvo_state->tv.flicker_filter_2d = val; 2376 else if (property == intel_sdvo_connector->flicker_filter_adaptive) 2377 sdvo_state->tv.flicker_filter_adaptive = val; 2378 else if (property == intel_sdvo_connector->tv_chroma_filter) 2379 sdvo_state->tv.chroma_filter = val; 2380 else if (property == intel_sdvo_connector->tv_luma_filter) 2381 sdvo_state->tv.luma_filter = val; 2382 else if (property == intel_sdvo_connector->dot_crawl) 2383 sdvo_state->tv.dot_crawl = val; 2384 else 2385 return intel_digital_connector_atomic_set_property(connector, state, property, val); 2386 2387 return 0; 2388 } 2389 2390 static int 2391 intel_sdvo_connector_register(struct drm_connector *connector) 2392 { 2393 struct intel_sdvo *sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2394 int ret; 2395 2396 ret = intel_connector_register(connector); 2397 if (ret) 2398 return ret; 2399 2400 return sysfs_create_link(&connector->kdev->kobj, 2401 &sdvo->ddc.dev.kobj, 2402 sdvo->ddc.dev.kobj.name); 2403 } 2404 2405 static void 2406 intel_sdvo_connector_unregister(struct drm_connector *connector) 2407 { 2408 struct intel_sdvo *sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2409 2410 sysfs_remove_link(&connector->kdev->kobj, 2411 sdvo->ddc.dev.kobj.name); 2412 intel_connector_unregister(connector); 2413 } 2414 2415 static struct drm_connector_state * 2416 intel_sdvo_connector_duplicate_state(struct drm_connector *connector) 2417 { 2418 struct intel_sdvo_connector_state *state; 2419 2420 state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL); 2421 if (!state) 2422 return NULL; 2423 2424 __drm_atomic_helper_connector_duplicate_state(connector, &state->base.base); 2425 return &state->base.base; 2426 } 2427 2428 static const struct drm_connector_funcs intel_sdvo_connector_funcs = { 2429 .detect = intel_sdvo_detect, 2430 .fill_modes = drm_helper_probe_single_connector_modes, 2431 .atomic_get_property = intel_sdvo_connector_atomic_get_property, 2432 .atomic_set_property = intel_sdvo_connector_atomic_set_property, 2433 .late_register = intel_sdvo_connector_register, 2434 .early_unregister = intel_sdvo_connector_unregister, 2435 .destroy = intel_connector_destroy, 2436 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2437 .atomic_duplicate_state = intel_sdvo_connector_duplicate_state, 2438 }; 2439 2440 static int intel_sdvo_atomic_check(struct drm_connector *conn, 2441 struct drm_atomic_state *state) 2442 { 2443 struct drm_connector_state *new_conn_state = 2444 drm_atomic_get_new_connector_state(state, conn); 2445 struct drm_connector_state *old_conn_state = 2446 drm_atomic_get_old_connector_state(state, conn); 2447 struct intel_sdvo_connector_state *old_state = 2448 to_intel_sdvo_connector_state(old_conn_state); 2449 struct intel_sdvo_connector_state *new_state = 2450 to_intel_sdvo_connector_state(new_conn_state); 2451 2452 if (new_conn_state->crtc && 2453 (memcmp(&old_state->tv, &new_state->tv, sizeof(old_state->tv)) || 2454 memcmp(&old_conn_state->tv, &new_conn_state->tv, sizeof(old_conn_state->tv)))) { 2455 struct drm_crtc_state *crtc_state = 2456 drm_atomic_get_new_crtc_state(state, 2457 new_conn_state->crtc); 2458 2459 crtc_state->connectors_changed = true; 2460 } 2461 2462 return intel_digital_connector_atomic_check(conn, state); 2463 } 2464 2465 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { 2466 .get_modes = intel_sdvo_get_modes, 2467 .mode_valid = intel_sdvo_mode_valid, 2468 .atomic_check = intel_sdvo_atomic_check, 2469 }; 2470 2471 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) 2472 { 2473 struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder)); 2474 2475 i2c_del_adapter(&intel_sdvo->ddc); 2476 intel_encoder_destroy(encoder); 2477 } 2478 2479 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { 2480 .destroy = intel_sdvo_enc_destroy, 2481 }; 2482 2483 static void 2484 intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo) 2485 { 2486 u16 mask = 0; 2487 unsigned int num_bits; 2488 2489 /* 2490 * Make a mask of outputs less than or equal to our own priority in the 2491 * list. 2492 */ 2493 switch (sdvo->controlled_output) { 2494 case SDVO_OUTPUT_LVDS1: 2495 mask |= SDVO_OUTPUT_LVDS1; 2496 /* fall through */ 2497 case SDVO_OUTPUT_LVDS0: 2498 mask |= SDVO_OUTPUT_LVDS0; 2499 /* fall through */ 2500 case SDVO_OUTPUT_TMDS1: 2501 mask |= SDVO_OUTPUT_TMDS1; 2502 /* fall through */ 2503 case SDVO_OUTPUT_TMDS0: 2504 mask |= SDVO_OUTPUT_TMDS0; 2505 /* fall through */ 2506 case SDVO_OUTPUT_RGB1: 2507 mask |= SDVO_OUTPUT_RGB1; 2508 /* fall through */ 2509 case SDVO_OUTPUT_RGB0: 2510 mask |= SDVO_OUTPUT_RGB0; 2511 break; 2512 } 2513 2514 /* Count bits to find what number we are in the priority list. */ 2515 mask &= sdvo->caps.output_flags; 2516 num_bits = hweight16(mask); 2517 /* If more than 3 outputs, default to DDC bus 3 for now. */ 2518 if (num_bits > 3) 2519 num_bits = 3; 2520 2521 /* Corresponds to SDVO_CONTROL_BUS_DDCx */ 2522 sdvo->ddc_bus = 1 << num_bits; 2523 } 2524 2525 /* 2526 * Choose the appropriate DDC bus for control bus switch command for this 2527 * SDVO output based on the controlled output. 2528 * 2529 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS 2530 * outputs, then LVDS outputs. 2531 */ 2532 static void 2533 intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, 2534 struct intel_sdvo *sdvo) 2535 { 2536 struct sdvo_device_mapping *mapping; 2537 2538 if (sdvo->port == PORT_B) 2539 mapping = &dev_priv->vbt.sdvo_mappings[0]; 2540 else 2541 mapping = &dev_priv->vbt.sdvo_mappings[1]; 2542 2543 if (mapping->initialized) 2544 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); 2545 else 2546 intel_sdvo_guess_ddc_bus(sdvo); 2547 } 2548 2549 static void 2550 intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv, 2551 struct intel_sdvo *sdvo) 2552 { 2553 struct sdvo_device_mapping *mapping; 2554 u8 pin; 2555 2556 if (sdvo->port == PORT_B) 2557 mapping = &dev_priv->vbt.sdvo_mappings[0]; 2558 else 2559 mapping = &dev_priv->vbt.sdvo_mappings[1]; 2560 2561 if (mapping->initialized && 2562 intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin)) 2563 pin = mapping->i2c_pin; 2564 else 2565 pin = GMBUS_PIN_DPB; 2566 2567 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin); 2568 2569 /* 2570 * With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow 2571 * our code totally fails once we start using gmbus. Hence fall back to 2572 * bit banging for now. 2573 */ 2574 intel_gmbus_force_bit(sdvo->i2c, true); 2575 } 2576 2577 /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */ 2578 static void 2579 intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo) 2580 { 2581 intel_gmbus_force_bit(sdvo->i2c, false); 2582 } 2583 2584 static bool 2585 intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device) 2586 { 2587 return intel_sdvo_check_supp_encode(intel_sdvo); 2588 } 2589 2590 static u8 2591 intel_sdvo_get_slave_addr(struct drm_i915_private *dev_priv, 2592 struct intel_sdvo *sdvo) 2593 { 2594 struct sdvo_device_mapping *my_mapping, *other_mapping; 2595 2596 if (sdvo->port == PORT_B) { 2597 my_mapping = &dev_priv->vbt.sdvo_mappings[0]; 2598 other_mapping = &dev_priv->vbt.sdvo_mappings[1]; 2599 } else { 2600 my_mapping = &dev_priv->vbt.sdvo_mappings[1]; 2601 other_mapping = &dev_priv->vbt.sdvo_mappings[0]; 2602 } 2603 2604 /* If the BIOS described our SDVO device, take advantage of it. */ 2605 if (my_mapping->slave_addr) 2606 return my_mapping->slave_addr; 2607 2608 /* 2609 * If the BIOS only described a different SDVO device, use the 2610 * address that it isn't using. 2611 */ 2612 if (other_mapping->slave_addr) { 2613 if (other_mapping->slave_addr == 0x70) 2614 return 0x72; 2615 else 2616 return 0x70; 2617 } 2618 2619 /* 2620 * No SDVO device info is found for another DVO port, 2621 * so use mapping assumption we had before BIOS parsing. 2622 */ 2623 if (sdvo->port == PORT_B) 2624 return 0x70; 2625 else 2626 return 0x72; 2627 } 2628 2629 static int 2630 intel_sdvo_connector_init(struct intel_sdvo_connector *connector, 2631 struct intel_sdvo *encoder) 2632 { 2633 struct drm_connector *drm_connector; 2634 int ret; 2635 2636 drm_connector = &connector->base.base; 2637 ret = drm_connector_init(encoder->base.base.dev, 2638 drm_connector, 2639 &intel_sdvo_connector_funcs, 2640 connector->base.base.connector_type); 2641 if (ret < 0) 2642 return ret; 2643 2644 drm_connector_helper_add(drm_connector, 2645 &intel_sdvo_connector_helper_funcs); 2646 2647 connector->base.base.interlace_allowed = 1; 2648 connector->base.base.doublescan_allowed = 0; 2649 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; 2650 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state; 2651 2652 intel_connector_attach_encoder(&connector->base, &encoder->base); 2653 2654 return 0; 2655 } 2656 2657 static void 2658 intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo, 2659 struct intel_sdvo_connector *connector) 2660 { 2661 struct drm_i915_private *dev_priv = to_i915(connector->base.base.dev); 2662 2663 intel_attach_force_audio_property(&connector->base.base); 2664 if (INTEL_GEN(dev_priv) >= 4 && IS_MOBILE(dev_priv)) { 2665 intel_attach_broadcast_rgb_property(&connector->base.base); 2666 } 2667 intel_attach_aspect_ratio_property(&connector->base.base); 2668 } 2669 2670 static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void) 2671 { 2672 struct intel_sdvo_connector *sdvo_connector; 2673 struct intel_sdvo_connector_state *conn_state; 2674 2675 sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL); 2676 if (!sdvo_connector) 2677 return NULL; 2678 2679 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL); 2680 if (!conn_state) { 2681 kfree(sdvo_connector); 2682 return NULL; 2683 } 2684 2685 __drm_atomic_helper_connector_reset(&sdvo_connector->base.base, 2686 &conn_state->base.base); 2687 2688 return sdvo_connector; 2689 } 2690 2691 static bool 2692 intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) 2693 { 2694 struct drm_encoder *encoder = &intel_sdvo->base.base; 2695 struct drm_connector *connector; 2696 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2697 struct intel_connector *intel_connector; 2698 struct intel_sdvo_connector *intel_sdvo_connector; 2699 2700 DRM_DEBUG_KMS("initialising DVI device %d\n", device); 2701 2702 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2703 if (!intel_sdvo_connector) 2704 return false; 2705 2706 if (device == 0) { 2707 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0; 2708 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0; 2709 } else if (device == 1) { 2710 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1; 2711 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1; 2712 } 2713 2714 intel_connector = &intel_sdvo_connector->base; 2715 connector = &intel_connector->base; 2716 if (intel_sdvo_get_hotplug_support(intel_sdvo) & 2717 intel_sdvo_connector->output_flag) { 2718 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag; 2719 /* 2720 * Some SDVO devices have one-shot hotplug interrupts. 2721 * Ensure that they get re-enabled when an interrupt happens. 2722 */ 2723 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 2724 intel_encoder->hotplug = intel_sdvo_hotplug; 2725 intel_sdvo_enable_hotplug(intel_encoder); 2726 } else { 2727 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 2728 } 2729 encoder->encoder_type = DRM_MODE_ENCODER_TMDS; 2730 connector->connector_type = DRM_MODE_CONNECTOR_DVID; 2731 2732 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) { 2733 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; 2734 intel_sdvo_connector->is_hdmi = true; 2735 } 2736 2737 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2738 kfree(intel_sdvo_connector); 2739 return false; 2740 } 2741 2742 if (intel_sdvo_connector->is_hdmi) 2743 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector); 2744 2745 return true; 2746 } 2747 2748 static bool 2749 intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type) 2750 { 2751 struct drm_encoder *encoder = &intel_sdvo->base.base; 2752 struct drm_connector *connector; 2753 struct intel_connector *intel_connector; 2754 struct intel_sdvo_connector *intel_sdvo_connector; 2755 2756 DRM_DEBUG_KMS("initialising TV type %d\n", type); 2757 2758 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2759 if (!intel_sdvo_connector) 2760 return false; 2761 2762 intel_connector = &intel_sdvo_connector->base; 2763 connector = &intel_connector->base; 2764 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; 2765 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; 2766 2767 intel_sdvo->controlled_output |= type; 2768 intel_sdvo_connector->output_flag = type; 2769 2770 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2771 kfree(intel_sdvo_connector); 2772 return false; 2773 } 2774 2775 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) 2776 goto err; 2777 2778 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2779 goto err; 2780 2781 return true; 2782 2783 err: 2784 intel_connector_destroy(connector); 2785 return false; 2786 } 2787 2788 static bool 2789 intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device) 2790 { 2791 struct drm_encoder *encoder = &intel_sdvo->base.base; 2792 struct drm_connector *connector; 2793 struct intel_connector *intel_connector; 2794 struct intel_sdvo_connector *intel_sdvo_connector; 2795 2796 DRM_DEBUG_KMS("initialising analog device %d\n", device); 2797 2798 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2799 if (!intel_sdvo_connector) 2800 return false; 2801 2802 intel_connector = &intel_sdvo_connector->base; 2803 connector = &intel_connector->base; 2804 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 2805 encoder->encoder_type = DRM_MODE_ENCODER_DAC; 2806 connector->connector_type = DRM_MODE_CONNECTOR_VGA; 2807 2808 if (device == 0) { 2809 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0; 2810 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0; 2811 } else if (device == 1) { 2812 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1; 2813 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; 2814 } 2815 2816 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2817 kfree(intel_sdvo_connector); 2818 return false; 2819 } 2820 2821 return true; 2822 } 2823 2824 static bool 2825 intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device) 2826 { 2827 struct drm_encoder *encoder = &intel_sdvo->base.base; 2828 struct drm_connector *connector; 2829 struct intel_connector *intel_connector; 2830 struct intel_sdvo_connector *intel_sdvo_connector; 2831 struct drm_display_mode *mode; 2832 2833 DRM_DEBUG_KMS("initialising LVDS device %d\n", device); 2834 2835 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2836 if (!intel_sdvo_connector) 2837 return false; 2838 2839 intel_connector = &intel_sdvo_connector->base; 2840 connector = &intel_connector->base; 2841 encoder->encoder_type = DRM_MODE_ENCODER_LVDS; 2842 connector->connector_type = DRM_MODE_CONNECTOR_LVDS; 2843 2844 if (device == 0) { 2845 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0; 2846 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0; 2847 } else if (device == 1) { 2848 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1; 2849 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; 2850 } 2851 2852 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2853 kfree(intel_sdvo_connector); 2854 return false; 2855 } 2856 2857 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2858 goto err; 2859 2860 intel_sdvo_get_lvds_modes(connector); 2861 2862 list_for_each_entry(mode, &connector->probed_modes, head) { 2863 if (mode->type & DRM_MODE_TYPE_PREFERRED) { 2864 struct drm_display_mode *fixed_mode = 2865 drm_mode_duplicate(connector->dev, mode); 2866 2867 intel_panel_init(&intel_connector->panel, 2868 fixed_mode, NULL); 2869 break; 2870 } 2871 } 2872 2873 if (!intel_connector->panel.fixed_mode) 2874 goto err; 2875 2876 return true; 2877 2878 err: 2879 intel_connector_destroy(connector); 2880 return false; 2881 } 2882 2883 static bool 2884 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, u16 flags) 2885 { 2886 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ 2887 2888 if (flags & SDVO_OUTPUT_TMDS0) 2889 if (!intel_sdvo_dvi_init(intel_sdvo, 0)) 2890 return false; 2891 2892 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK) 2893 if (!intel_sdvo_dvi_init(intel_sdvo, 1)) 2894 return false; 2895 2896 /* TV has no XXX1 function block */ 2897 if (flags & SDVO_OUTPUT_SVID0) 2898 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0)) 2899 return false; 2900 2901 if (flags & SDVO_OUTPUT_CVBS0) 2902 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0)) 2903 return false; 2904 2905 if (flags & SDVO_OUTPUT_YPRPB0) 2906 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0)) 2907 return false; 2908 2909 if (flags & SDVO_OUTPUT_RGB0) 2910 if (!intel_sdvo_analog_init(intel_sdvo, 0)) 2911 return false; 2912 2913 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK) 2914 if (!intel_sdvo_analog_init(intel_sdvo, 1)) 2915 return false; 2916 2917 if (flags & SDVO_OUTPUT_LVDS0) 2918 if (!intel_sdvo_lvds_init(intel_sdvo, 0)) 2919 return false; 2920 2921 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK) 2922 if (!intel_sdvo_lvds_init(intel_sdvo, 1)) 2923 return false; 2924 2925 if ((flags & SDVO_OUTPUT_MASK) == 0) { 2926 unsigned char bytes[2]; 2927 2928 intel_sdvo->controlled_output = 0; 2929 memcpy(bytes, &intel_sdvo->caps.output_flags, 2); 2930 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", 2931 SDVO_NAME(intel_sdvo), 2932 bytes[0], bytes[1]); 2933 return false; 2934 } 2935 intel_sdvo->base.pipe_mask = ~0; 2936 2937 return true; 2938 } 2939 2940 static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo) 2941 { 2942 struct drm_device *dev = intel_sdvo->base.base.dev; 2943 struct drm_connector *connector, *tmp; 2944 2945 list_for_each_entry_safe(connector, tmp, 2946 &dev->mode_config.connector_list, head) { 2947 if (intel_attached_encoder(to_intel_connector(connector)) == &intel_sdvo->base) { 2948 drm_connector_unregister(connector); 2949 intel_connector_destroy(connector); 2950 } 2951 } 2952 } 2953 2954 static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 2955 struct intel_sdvo_connector *intel_sdvo_connector, 2956 int type) 2957 { 2958 struct drm_device *dev = intel_sdvo->base.base.dev; 2959 struct intel_sdvo_tv_format format; 2960 u32 format_map, i; 2961 2962 if (!intel_sdvo_set_target_output(intel_sdvo, type)) 2963 return false; 2964 2965 BUILD_BUG_ON(sizeof(format) != 6); 2966 if (!intel_sdvo_get_value(intel_sdvo, 2967 SDVO_CMD_GET_SUPPORTED_TV_FORMATS, 2968 &format, sizeof(format))) 2969 return false; 2970 2971 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); 2972 2973 if (format_map == 0) 2974 return false; 2975 2976 intel_sdvo_connector->format_supported_num = 0; 2977 for (i = 0 ; i < TV_FORMAT_NUM; i++) 2978 if (format_map & (1 << i)) 2979 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; 2980 2981 2982 intel_sdvo_connector->tv_format = 2983 drm_property_create(dev, DRM_MODE_PROP_ENUM, 2984 "mode", intel_sdvo_connector->format_supported_num); 2985 if (!intel_sdvo_connector->tv_format) 2986 return false; 2987 2988 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) 2989 drm_property_add_enum(intel_sdvo_connector->tv_format, i, 2990 tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); 2991 2992 intel_sdvo_connector->base.base.state->tv.mode = intel_sdvo_connector->tv_format_supported[0]; 2993 drm_object_attach_property(&intel_sdvo_connector->base.base.base, 2994 intel_sdvo_connector->tv_format, 0); 2995 return true; 2996 2997 } 2998 2999 #define _ENHANCEMENT(state_assignment, name, NAME) do { \ 3000 if (enhancements.name) { \ 3001 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ 3002 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ 3003 return false; \ 3004 intel_sdvo_connector->name = \ 3005 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \ 3006 if (!intel_sdvo_connector->name) return false; \ 3007 state_assignment = response; \ 3008 drm_object_attach_property(&connector->base, \ 3009 intel_sdvo_connector->name, 0); \ 3010 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ 3011 data_value[0], data_value[1], response); \ 3012 } \ 3013 } while (0) 3014 3015 #define ENHANCEMENT(state, name, NAME) _ENHANCEMENT((state)->name, name, NAME) 3016 3017 static bool 3018 intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, 3019 struct intel_sdvo_connector *intel_sdvo_connector, 3020 struct intel_sdvo_enhancements_reply enhancements) 3021 { 3022 struct drm_device *dev = intel_sdvo->base.base.dev; 3023 struct drm_connector *connector = &intel_sdvo_connector->base.base; 3024 struct drm_connector_state *conn_state = connector->state; 3025 struct intel_sdvo_connector_state *sdvo_state = 3026 to_intel_sdvo_connector_state(conn_state); 3027 u16 response, data_value[2]; 3028 3029 /* when horizontal overscan is supported, Add the left/right property */ 3030 if (enhancements.overscan_h) { 3031 if (!intel_sdvo_get_value(intel_sdvo, 3032 SDVO_CMD_GET_MAX_OVERSCAN_H, 3033 &data_value, 4)) 3034 return false; 3035 3036 if (!intel_sdvo_get_value(intel_sdvo, 3037 SDVO_CMD_GET_OVERSCAN_H, 3038 &response, 2)) 3039 return false; 3040 3041 sdvo_state->tv.overscan_h = response; 3042 3043 intel_sdvo_connector->max_hscan = data_value[0]; 3044 intel_sdvo_connector->left = 3045 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]); 3046 if (!intel_sdvo_connector->left) 3047 return false; 3048 3049 drm_object_attach_property(&connector->base, 3050 intel_sdvo_connector->left, 0); 3051 3052 intel_sdvo_connector->right = 3053 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]); 3054 if (!intel_sdvo_connector->right) 3055 return false; 3056 3057 drm_object_attach_property(&connector->base, 3058 intel_sdvo_connector->right, 0); 3059 DRM_DEBUG_KMS("h_overscan: max %d, " 3060 "default %d, current %d\n", 3061 data_value[0], data_value[1], response); 3062 } 3063 3064 if (enhancements.overscan_v) { 3065 if (!intel_sdvo_get_value(intel_sdvo, 3066 SDVO_CMD_GET_MAX_OVERSCAN_V, 3067 &data_value, 4)) 3068 return false; 3069 3070 if (!intel_sdvo_get_value(intel_sdvo, 3071 SDVO_CMD_GET_OVERSCAN_V, 3072 &response, 2)) 3073 return false; 3074 3075 sdvo_state->tv.overscan_v = response; 3076 3077 intel_sdvo_connector->max_vscan = data_value[0]; 3078 intel_sdvo_connector->top = 3079 drm_property_create_range(dev, 0, 3080 "top_margin", 0, data_value[0]); 3081 if (!intel_sdvo_connector->top) 3082 return false; 3083 3084 drm_object_attach_property(&connector->base, 3085 intel_sdvo_connector->top, 0); 3086 3087 intel_sdvo_connector->bottom = 3088 drm_property_create_range(dev, 0, 3089 "bottom_margin", 0, data_value[0]); 3090 if (!intel_sdvo_connector->bottom) 3091 return false; 3092 3093 drm_object_attach_property(&connector->base, 3094 intel_sdvo_connector->bottom, 0); 3095 DRM_DEBUG_KMS("v_overscan: max %d, " 3096 "default %d, current %d\n", 3097 data_value[0], data_value[1], response); 3098 } 3099 3100 ENHANCEMENT(&sdvo_state->tv, hpos, HPOS); 3101 ENHANCEMENT(&sdvo_state->tv, vpos, VPOS); 3102 ENHANCEMENT(&conn_state->tv, saturation, SATURATION); 3103 ENHANCEMENT(&conn_state->tv, contrast, CONTRAST); 3104 ENHANCEMENT(&conn_state->tv, hue, HUE); 3105 ENHANCEMENT(&conn_state->tv, brightness, BRIGHTNESS); 3106 ENHANCEMENT(&sdvo_state->tv, sharpness, SHARPNESS); 3107 ENHANCEMENT(&sdvo_state->tv, flicker_filter, FLICKER_FILTER); 3108 ENHANCEMENT(&sdvo_state->tv, flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); 3109 ENHANCEMENT(&sdvo_state->tv, flicker_filter_2d, FLICKER_FILTER_2D); 3110 _ENHANCEMENT(sdvo_state->tv.chroma_filter, tv_chroma_filter, TV_CHROMA_FILTER); 3111 _ENHANCEMENT(sdvo_state->tv.luma_filter, tv_luma_filter, TV_LUMA_FILTER); 3112 3113 if (enhancements.dot_crawl) { 3114 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) 3115 return false; 3116 3117 sdvo_state->tv.dot_crawl = response & 0x1; 3118 intel_sdvo_connector->dot_crawl = 3119 drm_property_create_range(dev, 0, "dot_crawl", 0, 1); 3120 if (!intel_sdvo_connector->dot_crawl) 3121 return false; 3122 3123 drm_object_attach_property(&connector->base, 3124 intel_sdvo_connector->dot_crawl, 0); 3125 DRM_DEBUG_KMS("dot crawl: current %d\n", response); 3126 } 3127 3128 return true; 3129 } 3130 3131 static bool 3132 intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, 3133 struct intel_sdvo_connector *intel_sdvo_connector, 3134 struct intel_sdvo_enhancements_reply enhancements) 3135 { 3136 struct drm_device *dev = intel_sdvo->base.base.dev; 3137 struct drm_connector *connector = &intel_sdvo_connector->base.base; 3138 u16 response, data_value[2]; 3139 3140 ENHANCEMENT(&connector->state->tv, brightness, BRIGHTNESS); 3141 3142 return true; 3143 } 3144 #undef ENHANCEMENT 3145 #undef _ENHANCEMENT 3146 3147 static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 3148 struct intel_sdvo_connector *intel_sdvo_connector) 3149 { 3150 union { 3151 struct intel_sdvo_enhancements_reply reply; 3152 u16 response; 3153 } enhancements; 3154 3155 BUILD_BUG_ON(sizeof(enhancements) != 2); 3156 3157 if (!intel_sdvo_get_value(intel_sdvo, 3158 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, 3159 &enhancements, sizeof(enhancements)) || 3160 enhancements.response == 0) { 3161 DRM_DEBUG_KMS("No enhancement is supported\n"); 3162 return true; 3163 } 3164 3165 if (IS_TV(intel_sdvo_connector)) 3166 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); 3167 else if (IS_LVDS(intel_sdvo_connector)) 3168 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); 3169 else 3170 return true; 3171 } 3172 3173 static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, 3174 struct i2c_msg *msgs, 3175 int num) 3176 { 3177 struct intel_sdvo *sdvo = adapter->algo_data; 3178 3179 if (!__intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) 3180 return -EIO; 3181 3182 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num); 3183 } 3184 3185 static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter) 3186 { 3187 struct intel_sdvo *sdvo = adapter->algo_data; 3188 return sdvo->i2c->algo->functionality(sdvo->i2c); 3189 } 3190 3191 static const struct i2c_algorithm intel_sdvo_ddc_proxy = { 3192 .master_xfer = intel_sdvo_ddc_proxy_xfer, 3193 .functionality = intel_sdvo_ddc_proxy_func 3194 }; 3195 3196 static void proxy_lock_bus(struct i2c_adapter *adapter, 3197 unsigned int flags) 3198 { 3199 struct intel_sdvo *sdvo = adapter->algo_data; 3200 sdvo->i2c->lock_ops->lock_bus(sdvo->i2c, flags); 3201 } 3202 3203 static int proxy_trylock_bus(struct i2c_adapter *adapter, 3204 unsigned int flags) 3205 { 3206 struct intel_sdvo *sdvo = adapter->algo_data; 3207 return sdvo->i2c->lock_ops->trylock_bus(sdvo->i2c, flags); 3208 } 3209 3210 static void proxy_unlock_bus(struct i2c_adapter *adapter, 3211 unsigned int flags) 3212 { 3213 struct intel_sdvo *sdvo = adapter->algo_data; 3214 sdvo->i2c->lock_ops->unlock_bus(sdvo->i2c, flags); 3215 } 3216 3217 static const struct i2c_lock_operations proxy_lock_ops = { 3218 .lock_bus = proxy_lock_bus, 3219 .trylock_bus = proxy_trylock_bus, 3220 .unlock_bus = proxy_unlock_bus, 3221 }; 3222 3223 static bool 3224 intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo, 3225 struct drm_i915_private *dev_priv) 3226 { 3227 struct pci_dev *pdev = dev_priv->drm.pdev; 3228 3229 sdvo->ddc.owner = THIS_MODULE; 3230 sdvo->ddc.class = I2C_CLASS_DDC; 3231 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy"); 3232 sdvo->ddc.dev.parent = &pdev->dev; 3233 sdvo->ddc.algo_data = sdvo; 3234 sdvo->ddc.algo = &intel_sdvo_ddc_proxy; 3235 sdvo->ddc.lock_ops = &proxy_lock_ops; 3236 3237 return i2c_add_adapter(&sdvo->ddc) == 0; 3238 } 3239 3240 static void assert_sdvo_port_valid(const struct drm_i915_private *dev_priv, 3241 enum port port) 3242 { 3243 if (HAS_PCH_SPLIT(dev_priv)) 3244 drm_WARN_ON(&dev_priv->drm, port != PORT_B); 3245 else 3246 drm_WARN_ON(&dev_priv->drm, port != PORT_B && port != PORT_C); 3247 } 3248 3249 bool intel_sdvo_init(struct drm_i915_private *dev_priv, 3250 i915_reg_t sdvo_reg, enum port port) 3251 { 3252 struct intel_encoder *intel_encoder; 3253 struct intel_sdvo *intel_sdvo; 3254 int i; 3255 3256 assert_sdvo_port_valid(dev_priv, port); 3257 3258 intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL); 3259 if (!intel_sdvo) 3260 return false; 3261 3262 intel_sdvo->sdvo_reg = sdvo_reg; 3263 intel_sdvo->port = port; 3264 intel_sdvo->slave_addr = 3265 intel_sdvo_get_slave_addr(dev_priv, intel_sdvo) >> 1; 3266 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo); 3267 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev_priv)) 3268 goto err_i2c_bus; 3269 3270 /* encoder type will be decided later */ 3271 intel_encoder = &intel_sdvo->base; 3272 intel_encoder->type = INTEL_OUTPUT_SDVO; 3273 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER; 3274 intel_encoder->port = port; 3275 drm_encoder_init(&dev_priv->drm, &intel_encoder->base, 3276 &intel_sdvo_enc_funcs, 0, 3277 "SDVO %c", port_name(port)); 3278 3279 /* Read the regs to test if we can talk to the device */ 3280 for (i = 0; i < 0x40; i++) { 3281 u8 byte; 3282 3283 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { 3284 drm_dbg_kms(&dev_priv->drm, 3285 "No SDVO device found on %s\n", 3286 SDVO_NAME(intel_sdvo)); 3287 goto err; 3288 } 3289 } 3290 3291 intel_encoder->compute_config = intel_sdvo_compute_config; 3292 if (HAS_PCH_SPLIT(dev_priv)) { 3293 intel_encoder->disable = pch_disable_sdvo; 3294 intel_encoder->post_disable = pch_post_disable_sdvo; 3295 } else { 3296 intel_encoder->disable = intel_disable_sdvo; 3297 } 3298 intel_encoder->pre_enable = intel_sdvo_pre_enable; 3299 intel_encoder->enable = intel_enable_sdvo; 3300 intel_encoder->get_hw_state = intel_sdvo_get_hw_state; 3301 intel_encoder->get_config = intel_sdvo_get_config; 3302 3303 /* In default case sdvo lvds is false */ 3304 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) 3305 goto err; 3306 3307 if (intel_sdvo_output_setup(intel_sdvo, 3308 intel_sdvo->caps.output_flags) != true) { 3309 drm_dbg_kms(&dev_priv->drm, 3310 "SDVO output failed to setup on %s\n", 3311 SDVO_NAME(intel_sdvo)); 3312 /* Output_setup can leave behind connectors! */ 3313 goto err_output; 3314 } 3315 3316 /* 3317 * Only enable the hotplug irq if we need it, to work around noisy 3318 * hotplug lines. 3319 */ 3320 if (intel_sdvo->hotplug_active) { 3321 if (intel_sdvo->port == PORT_B) 3322 intel_encoder->hpd_pin = HPD_SDVO_B; 3323 else 3324 intel_encoder->hpd_pin = HPD_SDVO_C; 3325 } 3326 3327 /* 3328 * Cloning SDVO with anything is often impossible, since the SDVO 3329 * encoder can request a special input timing mode. And even if that's 3330 * not the case we have evidence that cloning a plain unscaled mode with 3331 * VGA doesn't really work. Furthermore the cloning flags are way too 3332 * simplistic anyway to express such constraints, so just give up on 3333 * cloning for SDVO encoders. 3334 */ 3335 intel_sdvo->base.cloneable = 0; 3336 3337 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo); 3338 3339 /* Set the input timing to the screen. Assume always input 0. */ 3340 if (!intel_sdvo_set_target_input(intel_sdvo)) 3341 goto err_output; 3342 3343 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, 3344 &intel_sdvo->pixel_clock_min, 3345 &intel_sdvo->pixel_clock_max)) 3346 goto err_output; 3347 3348 drm_dbg_kms(&dev_priv->drm, "%s device VID/DID: %02X:%02X.%02X, " 3349 "clock range %dMHz - %dMHz, " 3350 "input 1: %c, input 2: %c, " 3351 "output 1: %c, output 2: %c\n", 3352 SDVO_NAME(intel_sdvo), 3353 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, 3354 intel_sdvo->caps.device_rev_id, 3355 intel_sdvo->pixel_clock_min / 1000, 3356 intel_sdvo->pixel_clock_max / 1000, 3357 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', 3358 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', 3359 /* check currently supported outputs */ 3360 intel_sdvo->caps.output_flags & 3361 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', 3362 intel_sdvo->caps.output_flags & 3363 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); 3364 return true; 3365 3366 err_output: 3367 intel_sdvo_output_cleanup(intel_sdvo); 3368 3369 err: 3370 drm_encoder_cleanup(&intel_encoder->base); 3371 i2c_del_adapter(&intel_sdvo->ddc); 3372 err_i2c_bus: 3373 intel_sdvo_unselect_i2c_bus(intel_sdvo); 3374 kfree(intel_sdvo); 3375 3376 return false; 3377 } 3378