1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 */ 4 #ifndef _ASM_POWERPC_CACHEFLUSH_H 5 #define _ASM_POWERPC_CACHEFLUSH_H 6 7 #include <linux/mm.h> 8 #include <asm/cputable.h> 9 10 #ifdef CONFIG_PPC_BOOK3S_64 11 /* 12 * Book3s has no ptesync after setting a pte, so without this ptesync it's 13 * possible for a kernel virtual mapping access to return a spurious fault 14 * if it's accessed right after the pte is set. The page fault handler does 15 * not expect this type of fault. flush_cache_vmap is not exactly the right 16 * place to put this, but it seems to work well enough. 17 */ 18 static inline void flush_cache_vmap(unsigned long start, unsigned long end) 19 { 20 asm volatile("ptesync" ::: "memory"); 21 } 22 #define flush_cache_vmap flush_cache_vmap 23 #endif /* CONFIG_PPC_BOOK3S_64 */ 24 25 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 26 extern void flush_dcache_page(struct page *page); 27 28 void flush_icache_range(unsigned long start, unsigned long stop); 29 #define flush_icache_range flush_icache_range 30 31 void flush_icache_user_page(struct vm_area_struct *vma, struct page *page, 32 unsigned long addr, int len); 33 #define flush_icache_user_page flush_icache_user_page 34 35 void flush_dcache_icache_page(struct page *page); 36 void __flush_dcache_icache(void *page); 37 38 /** 39 * flush_dcache_range(): Write any modified data cache blocks out to memory and 40 * invalidate them. Does not invalidate the corresponding instruction cache 41 * blocks. 42 * 43 * @start: the start address 44 * @stop: the stop address (exclusive) 45 */ 46 static inline void flush_dcache_range(unsigned long start, unsigned long stop) 47 { 48 unsigned long shift = l1_dcache_shift(); 49 unsigned long bytes = l1_dcache_bytes(); 50 void *addr = (void *)(start & ~(bytes - 1)); 51 unsigned long size = stop - (unsigned long)addr + (bytes - 1); 52 unsigned long i; 53 54 if (IS_ENABLED(CONFIG_PPC64)) 55 mb(); /* sync */ 56 57 for (i = 0; i < size >> shift; i++, addr += bytes) 58 dcbf(addr); 59 mb(); /* sync */ 60 61 } 62 63 /* 64 * Write any modified data cache blocks out to memory. 65 * Does not invalidate the corresponding cache lines (especially for 66 * any corresponding instruction cache). 67 */ 68 static inline void clean_dcache_range(unsigned long start, unsigned long stop) 69 { 70 unsigned long shift = l1_dcache_shift(); 71 unsigned long bytes = l1_dcache_bytes(); 72 void *addr = (void *)(start & ~(bytes - 1)); 73 unsigned long size = stop - (unsigned long)addr + (bytes - 1); 74 unsigned long i; 75 76 for (i = 0; i < size >> shift; i++, addr += bytes) 77 dcbst(addr); 78 mb(); /* sync */ 79 } 80 81 /* 82 * Like above, but invalidate the D-cache. This is used by the 8xx 83 * to invalidate the cache so the PPC core doesn't get stale data 84 * from the CPM (no cache snooping here :-). 85 */ 86 static inline void invalidate_dcache_range(unsigned long start, 87 unsigned long stop) 88 { 89 unsigned long shift = l1_dcache_shift(); 90 unsigned long bytes = l1_dcache_bytes(); 91 void *addr = (void *)(start & ~(bytes - 1)); 92 unsigned long size = stop - (unsigned long)addr + (bytes - 1); 93 unsigned long i; 94 95 for (i = 0; i < size >> shift; i++, addr += bytes) 96 dcbi(addr); 97 mb(); /* sync */ 98 } 99 100 #include <asm-generic/cacheflush.h> 101 102 #endif /* _ASM_POWERPC_CACHEFLUSH_H */ 103