1# SPDX-License-Identifier: GPL-2.0-or-later 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2400-pinctrl.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ASPEED AST2400 Pin Controller 8 9maintainers: 10 - Andrew Jeffery <andrew@aj.id.au> 11 12description: |+ 13 The pin controller node should be the child of a syscon node with the 14 required property: 15 16 - compatible: Should be one of the following: 17 "aspeed,ast2400-scu", "syscon", "simple-mfd" 18 19 Refer to the the bindings described in 20 Documentation/devicetree/bindings/mfd/syscon.yaml 21 22properties: 23 compatible: 24 const: aspeed,ast2400-pinctrl 25 reg: 26 description: | 27 A hint for the memory regions associated with the pin-controller 28 29patternProperties: 30 '^.*$': 31 if: 32 type: object 33 then: 34 patternProperties: 35 "^function|groups$": 36 $ref: "/schemas/types.yaml#/definitions/string" 37 enum: [ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, 38 ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, DDCCLK, DDCDAT, 39 EXTRST, FLACK, FLBUSY, FLWP, GPID, GPID0, GPID2, GPID4, GPID6, GPIE0, 40 GPIE2, GPIE4, GPIE6, I2C10, I2C11, I2C12, I2C13, I2C14, I2C3, I2C4, 41 I2C5, I2C6, I2C7, I2C8, I2C9, LPCPD, LPCPME, LPCRST, LPCSMI, MAC1LINK, 42 MAC2LINK, MDIO1, MDIO2, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, 43 NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, 44 NDTS4, NRI1, NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, OSCCLK, PWM0, 45 PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, RGMII1, RGMII2, RMII1, 46 RMII2, ROM16, ROM8, ROMCS1, ROMCS2, ROMCS3, ROMCS4, RXD1, RXD2, RXD3, 47 RXD4, SALT1, SALT2, SALT3, SALT4, SD1, SD2, SGPMCK, SGPMI, SGPMLD, 48 SGPMO, SGPSCK, SGPSI0, SGPSI1, SGPSLD, SIOONCTRL, SIOPBI, SIOPBO, 49 SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1DEBUG, SPI1PASSTHRU, 50 SPICS1, TIMER3, TIMER4, TIMER5, TIMER6, TIMER7, TIMER8, TXD1, TXD2, 51 TXD3, TXD4, UART6, USB11D1, USB11H2, USB2D1, USB2H1, USBCKI, VGABIOS_ROM, 52 VGAHS, VGAVS, VPI18, VPI24, VPI30, VPO12, VPO24, WDTRST1, WDTRST2] 53 54required: 55 - compatible 56 57additionalProperties: false 58 59examples: 60 - | 61 syscon: scu@1e6e2000 { 62 compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd"; 63 reg = <0x1e6e2000 0x1a8>; 64 65 pinctrl: pinctrl { 66 compatible = "aspeed,g4-pinctrl"; 67 68 pinctrl_i2c3_default: i2c3_default { 69 function = "I2C3"; 70 groups = "I2C3"; 71 }; 72 73 pinctrl_gpioh0_unbiased_default: gpioh0 { 74 pins = "A8"; 75 bias-disable; 76 }; 77 }; 78 }; 79