1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994, 1995 Waldorf GmbH 7 * Copyright (C) 1994 - 2000, 06 Ralf Baechle 8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 9 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. 10 * Author: Maciej W. Rozycki <macro@mips.com> 11 */ 12 #ifndef _ASM_IO_H 13 #define _ASM_IO_H 14 15 #define ARCH_HAS_IOREMAP_WC 16 17 #include <linux/compiler.h> 18 #include <linux/kernel.h> 19 #include <linux/types.h> 20 #include <linux/irqflags.h> 21 22 #include <asm/addrspace.h> 23 #include <asm/barrier.h> 24 #include <asm/bug.h> 25 #include <asm/byteorder.h> 26 #include <asm/cpu.h> 27 #include <asm/cpu-features.h> 28 #include <asm-generic/iomap.h> 29 #include <asm/page.h> 30 #include <asm/pgtable-bits.h> 31 #include <asm/processor.h> 32 #include <asm/string.h> 33 #include <mangle-port.h> 34 35 /* 36 * Raw operations are never swapped in software. OTOH values that raw 37 * operations are working on may or may not have been swapped by the bus 38 * hardware. An example use would be for flash memory that's used for 39 * execute in place. 40 */ 41 # define __raw_ioswabb(a, x) (x) 42 # define __raw_ioswabw(a, x) (x) 43 # define __raw_ioswabl(a, x) (x) 44 # define __raw_ioswabq(a, x) (x) 45 # define ____raw_ioswabq(a, x) (x) 46 47 # define __relaxed_ioswabb ioswabb 48 # define __relaxed_ioswabw ioswabw 49 # define __relaxed_ioswabl ioswabl 50 # define __relaxed_ioswabq ioswabq 51 52 /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */ 53 54 /* 55 * On MIPS I/O ports are memory mapped, so we access them using normal 56 * load/store instructions. mips_io_port_base is the virtual address to 57 * which all ports are being mapped. For sake of efficiency some code 58 * assumes that this is an address that can be loaded with a single lui 59 * instruction, so the lower 16 bits must be zero. Should be true on 60 * any sane architecture; generic code does not use this assumption. 61 */ 62 extern unsigned long mips_io_port_base; 63 64 static inline void set_io_port_base(unsigned long base) 65 { 66 mips_io_port_base = base; 67 } 68 69 /* 70 * Provide the necessary definitions for generic iomap. We make use of 71 * mips_io_port_base for iomap(), but we don't reserve any low addresses for 72 * use with I/O ports. 73 */ 74 75 #define HAVE_ARCH_PIO_SIZE 76 #define PIO_OFFSET mips_io_port_base 77 #define PIO_MASK IO_SPACE_LIMIT 78 #define PIO_RESERVED 0x0UL 79 80 /* 81 * Enforce in-order execution of data I/O. In the MIPS architecture 82 * these are equivalent to corresponding platform-specific memory 83 * barriers defined in <asm/barrier.h>. API pinched from PowerPC, 84 * with sync additionally defined. 85 */ 86 #define iobarrier_rw() mb() 87 #define iobarrier_r() rmb() 88 #define iobarrier_w() wmb() 89 #define iobarrier_sync() iob() 90 91 /* 92 * virt_to_phys - map virtual addresses to physical 93 * @address: address to remap 94 * 95 * The returned physical address is the physical (CPU) mapping for 96 * the memory address given. It is only valid to use this function on 97 * addresses directly mapped or allocated via kmalloc. 98 * 99 * This function does not give bus mappings for DMA transfers. In 100 * almost all conceivable cases a device driver should not be using 101 * this function 102 */ 103 static inline unsigned long virt_to_phys(volatile const void *address) 104 { 105 return __pa(address); 106 } 107 108 /* 109 * phys_to_virt - map physical address to virtual 110 * @address: address to remap 111 * 112 * The returned virtual address is a current CPU mapping for 113 * the memory address given. It is only valid to use this function on 114 * addresses that have a kernel mapping 115 * 116 * This function does not handle bus mappings for DMA transfers. In 117 * almost all conceivable cases a device driver should not be using 118 * this function 119 */ 120 static inline void * phys_to_virt(unsigned long address) 121 { 122 return (void *)(address + PAGE_OFFSET - PHYS_OFFSET); 123 } 124 125 /* 126 * ISA I/O bus memory addresses are 1:1 with the physical address. 127 */ 128 static inline unsigned long isa_virt_to_bus(volatile void *address) 129 { 130 return virt_to_phys(address); 131 } 132 133 static inline void *isa_bus_to_virt(unsigned long address) 134 { 135 return phys_to_virt(address); 136 } 137 138 /* 139 * However PCI ones are not necessarily 1:1 and therefore these interfaces 140 * are forbidden in portable PCI drivers. 141 * 142 * Allow them for x86 for legacy drivers, though. 143 */ 144 #define virt_to_bus virt_to_phys 145 #define bus_to_virt phys_to_virt 146 147 /* 148 * Change "struct page" to physical address. 149 */ 150 #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT) 151 152 void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size, 153 unsigned long prot_val); 154 void iounmap(const volatile void __iomem *addr); 155 156 /* 157 * ioremap - map bus memory into CPU space 158 * @offset: bus address of the memory 159 * @size: size of the resource to map 160 * 161 * ioremap performs a platform specific sequence of operations to 162 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 163 * writew/writel functions and the other mmio helpers. The returned 164 * address is not guaranteed to be usable directly as a virtual 165 * address. 166 */ 167 #define ioremap(offset, size) \ 168 ioremap_prot((offset), (size), _CACHE_UNCACHED) 169 #define ioremap_uc ioremap 170 171 /* 172 * ioremap_cache - map bus memory into CPU space 173 * @offset: bus address of the memory 174 * @size: size of the resource to map 175 * 176 * ioremap_cache performs a platform specific sequence of operations to 177 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 178 * writew/writel functions and the other mmio helpers. The returned 179 * address is not guaranteed to be usable directly as a virtual 180 * address. 181 * 182 * This version of ioremap ensures that the memory is marked cachable by 183 * the CPU. Also enables full write-combining. Useful for some 184 * memory-like regions on I/O busses. 185 */ 186 #define ioremap_cache(offset, size) \ 187 ioremap_prot((offset), (size), _page_cachable_default) 188 189 /* 190 * ioremap_wc - map bus memory into CPU space 191 * @offset: bus address of the memory 192 * @size: size of the resource to map 193 * 194 * ioremap_wc performs a platform specific sequence of operations to 195 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 196 * writew/writel functions and the other mmio helpers. The returned 197 * address is not guaranteed to be usable directly as a virtual 198 * address. 199 * 200 * This version of ioremap ensures that the memory is marked uncachable 201 * but accelerated by means of write-combining feature. It is specifically 202 * useful for PCIe prefetchable windows, which may vastly improve a 203 * communications performance. If it was determined on boot stage, what 204 * CPU CCA doesn't support UCA, the method shall fall-back to the 205 * _CACHE_UNCACHED option (see cpu_probe() method). 206 */ 207 #define ioremap_wc(offset, size) \ 208 ioremap_prot((offset), (size), boot_cpu_data.writecombine) 209 210 #if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_CPU_LOONGSON64) 211 #define war_io_reorder_wmb() wmb() 212 #else 213 #define war_io_reorder_wmb() barrier() 214 #endif 215 216 #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, barrier, relax, irq) \ 217 \ 218 static inline void pfx##write##bwlq(type val, \ 219 volatile void __iomem *mem) \ 220 { \ 221 volatile type *__mem; \ 222 type __val; \ 223 \ 224 if (barrier) \ 225 iobarrier_rw(); \ 226 else \ 227 war_io_reorder_wmb(); \ 228 \ 229 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ 230 \ 231 __val = pfx##ioswab##bwlq(__mem, val); \ 232 \ 233 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \ 234 *__mem = __val; \ 235 else if (cpu_has_64bits) { \ 236 unsigned long __flags; \ 237 type __tmp; \ 238 \ 239 if (irq) \ 240 local_irq_save(__flags); \ 241 __asm__ __volatile__( \ 242 ".set push" "\t\t# __writeq""\n\t" \ 243 ".set arch=r4000" "\n\t" \ 244 "dsll32 %L0, %L0, 0" "\n\t" \ 245 "dsrl32 %L0, %L0, 0" "\n\t" \ 246 "dsll32 %M0, %M0, 0" "\n\t" \ 247 "or %L0, %L0, %M0" "\n\t" \ 248 "sd %L0, %2" "\n\t" \ 249 ".set pop" "\n" \ 250 : "=r" (__tmp) \ 251 : "0" (__val), "m" (*__mem)); \ 252 if (irq) \ 253 local_irq_restore(__flags); \ 254 } else \ 255 BUG(); \ 256 } \ 257 \ 258 static inline type pfx##read##bwlq(const volatile void __iomem *mem) \ 259 { \ 260 volatile type *__mem; \ 261 type __val; \ 262 \ 263 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ 264 \ 265 if (barrier) \ 266 iobarrier_rw(); \ 267 \ 268 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \ 269 __val = *__mem; \ 270 else if (cpu_has_64bits) { \ 271 unsigned long __flags; \ 272 \ 273 if (irq) \ 274 local_irq_save(__flags); \ 275 __asm__ __volatile__( \ 276 ".set push" "\t\t# __readq" "\n\t" \ 277 ".set arch=r4000" "\n\t" \ 278 "ld %L0, %1" "\n\t" \ 279 "dsra32 %M0, %L0, 0" "\n\t" \ 280 "sll %L0, %L0, 0" "\n\t" \ 281 ".set pop" "\n" \ 282 : "=r" (__val) \ 283 : "m" (*__mem)); \ 284 if (irq) \ 285 local_irq_restore(__flags); \ 286 } else { \ 287 __val = 0; \ 288 BUG(); \ 289 } \ 290 \ 291 /* prevent prefetching of coherent DMA data prematurely */ \ 292 if (!relax) \ 293 rmb(); \ 294 return pfx##ioswab##bwlq(__mem, __val); \ 295 } 296 297 #define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, barrier, relax, p) \ 298 \ 299 static inline void pfx##out##bwlq##p(type val, unsigned long port) \ 300 { \ 301 volatile type *__addr; \ 302 type __val; \ 303 \ 304 if (barrier) \ 305 iobarrier_rw(); \ 306 else \ 307 war_io_reorder_wmb(); \ 308 \ 309 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ 310 \ 311 __val = pfx##ioswab##bwlq(__addr, val); \ 312 \ 313 /* Really, we want this to be atomic */ \ 314 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \ 315 \ 316 *__addr = __val; \ 317 } \ 318 \ 319 static inline type pfx##in##bwlq##p(unsigned long port) \ 320 { \ 321 volatile type *__addr; \ 322 type __val; \ 323 \ 324 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ 325 \ 326 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \ 327 \ 328 if (barrier) \ 329 iobarrier_rw(); \ 330 \ 331 __val = *__addr; \ 332 \ 333 /* prevent prefetching of coherent DMA data prematurely */ \ 334 if (!relax) \ 335 rmb(); \ 336 return pfx##ioswab##bwlq(__addr, __val); \ 337 } 338 339 #define __BUILD_MEMORY_PFX(bus, bwlq, type, relax) \ 340 \ 341 __BUILD_MEMORY_SINGLE(bus, bwlq, type, 1, relax, 1) 342 343 #define BUILDIO_MEM(bwlq, type) \ 344 \ 345 __BUILD_MEMORY_PFX(__raw_, bwlq, type, 0) \ 346 __BUILD_MEMORY_PFX(__relaxed_, bwlq, type, 1) \ 347 __BUILD_MEMORY_PFX(__mem_, bwlq, type, 0) \ 348 __BUILD_MEMORY_PFX(, bwlq, type, 0) 349 350 BUILDIO_MEM(b, u8) 351 BUILDIO_MEM(w, u16) 352 BUILDIO_MEM(l, u32) 353 #ifdef CONFIG_64BIT 354 BUILDIO_MEM(q, u64) 355 #else 356 __BUILD_MEMORY_PFX(__raw_, q, u64, 0) 357 __BUILD_MEMORY_PFX(__mem_, q, u64, 0) 358 #endif 359 360 #define __BUILD_IOPORT_PFX(bus, bwlq, type) \ 361 __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0,) \ 362 __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0, _p) 363 364 #define BUILDIO_IOPORT(bwlq, type) \ 365 __BUILD_IOPORT_PFX(, bwlq, type) \ 366 __BUILD_IOPORT_PFX(__mem_, bwlq, type) 367 368 BUILDIO_IOPORT(b, u8) 369 BUILDIO_IOPORT(w, u16) 370 BUILDIO_IOPORT(l, u32) 371 #ifdef CONFIG_64BIT 372 BUILDIO_IOPORT(q, u64) 373 #endif 374 375 #define __BUILDIO(bwlq, type) \ 376 \ 377 __BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 1, 0, 0) 378 379 __BUILDIO(q, u64) 380 381 #define readb_relaxed __relaxed_readb 382 #define readw_relaxed __relaxed_readw 383 #define readl_relaxed __relaxed_readl 384 #ifdef CONFIG_64BIT 385 #define readq_relaxed __relaxed_readq 386 #endif 387 388 #define writeb_relaxed __relaxed_writeb 389 #define writew_relaxed __relaxed_writew 390 #define writel_relaxed __relaxed_writel 391 #ifdef CONFIG_64BIT 392 #define writeq_relaxed __relaxed_writeq 393 #endif 394 395 #define readb_be(addr) \ 396 __raw_readb((__force unsigned *)(addr)) 397 #define readw_be(addr) \ 398 be16_to_cpu(__raw_readw((__force unsigned *)(addr))) 399 #define readl_be(addr) \ 400 be32_to_cpu(__raw_readl((__force unsigned *)(addr))) 401 #define readq_be(addr) \ 402 be64_to_cpu(__raw_readq((__force unsigned *)(addr))) 403 404 #define writeb_be(val, addr) \ 405 __raw_writeb((val), (__force unsigned *)(addr)) 406 #define writew_be(val, addr) \ 407 __raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr)) 408 #define writel_be(val, addr) \ 409 __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr)) 410 #define writeq_be(val, addr) \ 411 __raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr)) 412 413 /* 414 * Some code tests for these symbols 415 */ 416 #ifdef CONFIG_64BIT 417 #define readq readq 418 #define writeq writeq 419 #endif 420 421 #define __BUILD_MEMORY_STRING(bwlq, type) \ 422 \ 423 static inline void writes##bwlq(volatile void __iomem *mem, \ 424 const void *addr, unsigned int count) \ 425 { \ 426 const volatile type *__addr = addr; \ 427 \ 428 while (count--) { \ 429 __mem_write##bwlq(*__addr, mem); \ 430 __addr++; \ 431 } \ 432 } \ 433 \ 434 static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \ 435 unsigned int count) \ 436 { \ 437 volatile type *__addr = addr; \ 438 \ 439 while (count--) { \ 440 *__addr = __mem_read##bwlq(mem); \ 441 __addr++; \ 442 } \ 443 } 444 445 #define __BUILD_IOPORT_STRING(bwlq, type) \ 446 \ 447 static inline void outs##bwlq(unsigned long port, const void *addr, \ 448 unsigned int count) \ 449 { \ 450 const volatile type *__addr = addr; \ 451 \ 452 while (count--) { \ 453 __mem_out##bwlq(*__addr, port); \ 454 __addr++; \ 455 } \ 456 } \ 457 \ 458 static inline void ins##bwlq(unsigned long port, void *addr, \ 459 unsigned int count) \ 460 { \ 461 volatile type *__addr = addr; \ 462 \ 463 while (count--) { \ 464 *__addr = __mem_in##bwlq(port); \ 465 __addr++; \ 466 } \ 467 } 468 469 #define BUILDSTRING(bwlq, type) \ 470 \ 471 __BUILD_MEMORY_STRING(bwlq, type) \ 472 __BUILD_IOPORT_STRING(bwlq, type) 473 474 BUILDSTRING(b, u8) 475 BUILDSTRING(w, u16) 476 BUILDSTRING(l, u32) 477 #ifdef CONFIG_64BIT 478 BUILDSTRING(q, u64) 479 #endif 480 481 static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) 482 { 483 memset((void __force *) addr, val, count); 484 } 485 static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count) 486 { 487 memcpy(dst, (void __force *) src, count); 488 } 489 static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count) 490 { 491 memcpy((void __force *) dst, src, count); 492 } 493 494 /* 495 * The caches on some architectures aren't dma-coherent and have need to 496 * handle this in software. There are three types of operations that 497 * can be applied to dma buffers. 498 * 499 * - dma_cache_wback_inv(start, size) makes caches and coherent by 500 * writing the content of the caches back to memory, if necessary. 501 * The function also invalidates the affected part of the caches as 502 * necessary before DMA transfers from outside to memory. 503 * - dma_cache_wback(start, size) makes caches and coherent by 504 * writing the content of the caches back to memory, if necessary. 505 * The function also invalidates the affected part of the caches as 506 * necessary before DMA transfers from outside to memory. 507 * - dma_cache_inv(start, size) invalidates the affected parts of the 508 * caches. Dirty lines of the caches may be written back or simply 509 * be discarded. This operation is necessary before dma operations 510 * to the memory. 511 * 512 * This API used to be exported; it now is for arch code internal use only. 513 */ 514 #ifdef CONFIG_DMA_NONCOHERENT 515 516 extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size); 517 extern void (*_dma_cache_wback)(unsigned long start, unsigned long size); 518 extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); 519 520 #define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start, size) 521 #define dma_cache_wback(start, size) _dma_cache_wback(start, size) 522 #define dma_cache_inv(start, size) _dma_cache_inv(start, size) 523 524 #else /* Sane hardware */ 525 526 #define dma_cache_wback_inv(start,size) \ 527 do { (void) (start); (void) (size); } while (0) 528 #define dma_cache_wback(start,size) \ 529 do { (void) (start); (void) (size); } while (0) 530 #define dma_cache_inv(start,size) \ 531 do { (void) (start); (void) (size); } while (0) 532 533 #endif /* CONFIG_DMA_NONCOHERENT */ 534 535 /* 536 * Read a 32-bit register that requires a 64-bit read cycle on the bus. 537 * Avoid interrupt mucking, just adjust the address for 4-byte access. 538 * Assume the addresses are 8-byte aligned. 539 */ 540 #ifdef __MIPSEB__ 541 #define __CSR_32_ADJUST 4 542 #else 543 #define __CSR_32_ADJUST 0 544 #endif 545 546 #define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v)) 547 #define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST)) 548 549 /* 550 * Convert a physical pointer to a virtual kernel pointer for /dev/mem 551 * access 552 */ 553 #define xlate_dev_mem_ptr(p) __va(p) 554 555 /* 556 * Convert a virtual cached pointer to an uncached pointer 557 */ 558 #define xlate_dev_kmem_ptr(p) p 559 560 void __ioread64_copy(void *to, const void __iomem *from, size_t count); 561 562 #endif /* _ASM_IO_H */ 563