1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: RDMA Controller HW interface 37 */ 38 39 #define dev_fmt(fmt) "QPLIB: " fmt 40 41 #include <linux/interrupt.h> 42 #include <linux/spinlock.h> 43 #include <linux/pci.h> 44 #include <linux/prefetch.h> 45 #include <linux/delay.h> 46 47 #include "roce_hsi.h" 48 #include "qplib_res.h" 49 #include "qplib_rcfw.h" 50 #include "qplib_sp.h" 51 #include "qplib_fp.h" 52 53 static void bnxt_qplib_service_creq(unsigned long data); 54 55 /* Hardware communication channel */ 56 static int __wait_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie) 57 { 58 struct bnxt_qplib_cmdq_ctx *cmdq; 59 u16 cbit; 60 int rc; 61 62 cmdq = &rcfw->cmdq; 63 cbit = cookie % rcfw->cmdq_depth; 64 rc = wait_event_timeout(cmdq->waitq, 65 !test_bit(cbit, cmdq->cmdq_bitmap), 66 msecs_to_jiffies(RCFW_CMD_WAIT_TIME_MS)); 67 return rc ? 0 : -ETIMEDOUT; 68 }; 69 70 static int __block_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie) 71 { 72 u32 count = RCFW_BLOCKED_CMD_WAIT_COUNT; 73 struct bnxt_qplib_cmdq_ctx *cmdq; 74 u16 cbit; 75 76 cmdq = &rcfw->cmdq; 77 cbit = cookie % rcfw->cmdq_depth; 78 if (!test_bit(cbit, cmdq->cmdq_bitmap)) 79 goto done; 80 do { 81 mdelay(1); /* 1m sec */ 82 bnxt_qplib_service_creq((unsigned long)rcfw); 83 } while (test_bit(cbit, cmdq->cmdq_bitmap) && --count); 84 done: 85 return count ? 0 : -ETIMEDOUT; 86 }; 87 88 static int __send_message(struct bnxt_qplib_rcfw *rcfw, struct cmdq_base *req, 89 struct creq_base *resp, void *sb, u8 is_block) 90 { 91 struct bnxt_qplib_cmdq_ctx *cmdq = &rcfw->cmdq; 92 struct bnxt_qplib_cmdqe *cmdqe, **hwq_ptr; 93 struct bnxt_qplib_hwq *hwq = &cmdq->hwq; 94 struct bnxt_qplib_crsqe *crsqe; 95 u32 cmdq_depth = rcfw->cmdq_depth; 96 u32 sw_prod, cmdq_prod; 97 struct pci_dev *pdev; 98 unsigned long flags; 99 u32 size, opcode; 100 u16 cookie, cbit; 101 u8 *preq; 102 103 pdev = rcfw->pdev; 104 105 opcode = req->opcode; 106 if (!test_bit(FIRMWARE_INITIALIZED_FLAG, &cmdq->flags) && 107 (opcode != CMDQ_BASE_OPCODE_QUERY_FUNC && 108 opcode != CMDQ_BASE_OPCODE_INITIALIZE_FW && 109 opcode != CMDQ_BASE_OPCODE_QUERY_VERSION)) { 110 dev_err(&pdev->dev, 111 "RCFW not initialized, reject opcode 0x%x\n", opcode); 112 return -EINVAL; 113 } 114 115 if (test_bit(FIRMWARE_INITIALIZED_FLAG, &cmdq->flags) && 116 opcode == CMDQ_BASE_OPCODE_INITIALIZE_FW) { 117 dev_err(&pdev->dev, "RCFW already initialized!\n"); 118 return -EINVAL; 119 } 120 121 if (test_bit(FIRMWARE_TIMED_OUT, &cmdq->flags)) 122 return -ETIMEDOUT; 123 124 /* Cmdq are in 16-byte units, each request can consume 1 or more 125 * cmdqe 126 */ 127 spin_lock_irqsave(&hwq->lock, flags); 128 if (req->cmd_size >= HWQ_FREE_SLOTS(hwq)) { 129 dev_err(&pdev->dev, "RCFW: CMDQ is full!\n"); 130 spin_unlock_irqrestore(&hwq->lock, flags); 131 return -EAGAIN; 132 } 133 134 135 cookie = cmdq->seq_num & RCFW_MAX_COOKIE_VALUE; 136 cbit = cookie % rcfw->cmdq_depth; 137 if (is_block) 138 cookie |= RCFW_CMD_IS_BLOCKING; 139 140 set_bit(cbit, cmdq->cmdq_bitmap); 141 req->cookie = cpu_to_le16(cookie); 142 crsqe = &rcfw->crsqe_tbl[cbit]; 143 if (crsqe->resp) { 144 spin_unlock_irqrestore(&hwq->lock, flags); 145 return -EBUSY; 146 } 147 148 size = req->cmd_size; 149 /* change the cmd_size to the number of 16byte cmdq unit. 150 * req->cmd_size is modified here 151 */ 152 bnxt_qplib_set_cmd_slots(req); 153 154 memset(resp, 0, sizeof(*resp)); 155 crsqe->resp = (struct creq_qp_event *)resp; 156 crsqe->resp->cookie = req->cookie; 157 crsqe->req_size = req->cmd_size; 158 if (req->resp_size && sb) { 159 struct bnxt_qplib_rcfw_sbuf *sbuf = sb; 160 161 req->resp_addr = cpu_to_le64(sbuf->dma_addr); 162 req->resp_size = (sbuf->size + BNXT_QPLIB_CMDQE_UNITS - 1) / 163 BNXT_QPLIB_CMDQE_UNITS; 164 } 165 166 hwq_ptr = (struct bnxt_qplib_cmdqe **)hwq->pbl_ptr; 167 preq = (u8 *)req; 168 do { 169 /* Locate the next cmdq slot */ 170 sw_prod = HWQ_CMP(hwq->prod, hwq); 171 cmdqe = &hwq_ptr[get_cmdq_pg(sw_prod, cmdq_depth)] 172 [get_cmdq_idx(sw_prod, cmdq_depth)]; 173 if (!cmdqe) { 174 dev_err(&pdev->dev, 175 "RCFW request failed with no cmdqe!\n"); 176 goto done; 177 } 178 /* Copy a segment of the req cmd to the cmdq */ 179 memset(cmdqe, 0, sizeof(*cmdqe)); 180 memcpy(cmdqe, preq, min_t(u32, size, sizeof(*cmdqe))); 181 preq += min_t(u32, size, sizeof(*cmdqe)); 182 size -= min_t(u32, size, sizeof(*cmdqe)); 183 hwq->prod++; 184 } while (size > 0); 185 cmdq->seq_num++; 186 187 cmdq_prod = hwq->prod; 188 if (test_bit(FIRMWARE_FIRST_FLAG, &cmdq->flags)) { 189 /* The very first doorbell write 190 * is required to set this flag 191 * which prompts the FW to reset 192 * its internal pointers 193 */ 194 cmdq_prod |= BIT(FIRMWARE_FIRST_FLAG); 195 clear_bit(FIRMWARE_FIRST_FLAG, &cmdq->flags); 196 } 197 198 /* ring CMDQ DB */ 199 wmb(); 200 writel(cmdq_prod, cmdq->cmdq_mbox.prod); 201 writel(RCFW_CMDQ_TRIG_VAL, cmdq->cmdq_mbox.db); 202 done: 203 spin_unlock_irqrestore(&hwq->lock, flags); 204 /* Return the CREQ response pointer */ 205 return 0; 206 } 207 208 int bnxt_qplib_rcfw_send_message(struct bnxt_qplib_rcfw *rcfw, 209 struct cmdq_base *req, 210 struct creq_base *resp, 211 void *sb, u8 is_block) 212 { 213 struct creq_qp_event *evnt = (struct creq_qp_event *)resp; 214 u16 cookie; 215 u8 opcode, retry_cnt = 0xFF; 216 int rc = 0; 217 218 do { 219 opcode = req->opcode; 220 rc = __send_message(rcfw, req, resp, sb, is_block); 221 cookie = le16_to_cpu(req->cookie) & RCFW_MAX_COOKIE_VALUE; 222 if (!rc) 223 break; 224 225 if (!retry_cnt || (rc != -EAGAIN && rc != -EBUSY)) { 226 /* send failed */ 227 dev_err(&rcfw->pdev->dev, "cmdq[%#x]=%#x send failed\n", 228 cookie, opcode); 229 return rc; 230 } 231 is_block ? mdelay(1) : usleep_range(500, 1000); 232 233 } while (retry_cnt--); 234 235 if (is_block) 236 rc = __block_for_resp(rcfw, cookie); 237 else 238 rc = __wait_for_resp(rcfw, cookie); 239 if (rc) { 240 /* timed out */ 241 dev_err(&rcfw->pdev->dev, "cmdq[%#x]=%#x timedout (%d)msec\n", 242 cookie, opcode, RCFW_CMD_WAIT_TIME_MS); 243 set_bit(FIRMWARE_TIMED_OUT, &rcfw->cmdq.flags); 244 return rc; 245 } 246 247 if (evnt->status) { 248 /* failed with status */ 249 dev_err(&rcfw->pdev->dev, "cmdq[%#x]=%#x status %#x\n", 250 cookie, opcode, evnt->status); 251 rc = -EFAULT; 252 } 253 254 return rc; 255 } 256 /* Completions */ 257 static int bnxt_qplib_process_func_event(struct bnxt_qplib_rcfw *rcfw, 258 struct creq_func_event *func_event) 259 { 260 int rc; 261 262 switch (func_event->event) { 263 case CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR: 264 break; 265 case CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR: 266 break; 267 case CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR: 268 break; 269 case CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR: 270 break; 271 case CREQ_FUNC_EVENT_EVENT_CQ_ERROR: 272 break; 273 case CREQ_FUNC_EVENT_EVENT_TQM_ERROR: 274 break; 275 case CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR: 276 break; 277 case CREQ_FUNC_EVENT_EVENT_CFCS_ERROR: 278 /* SRQ ctx error, call srq_handler?? 279 * But there's no SRQ handle! 280 */ 281 break; 282 case CREQ_FUNC_EVENT_EVENT_CFCC_ERROR: 283 break; 284 case CREQ_FUNC_EVENT_EVENT_CFCM_ERROR: 285 break; 286 case CREQ_FUNC_EVENT_EVENT_TIM_ERROR: 287 break; 288 case CREQ_FUNC_EVENT_EVENT_VF_COMM_REQUEST: 289 break; 290 case CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED: 291 break; 292 default: 293 return -EINVAL; 294 } 295 296 rc = rcfw->creq.aeq_handler(rcfw, (void *)func_event, NULL); 297 return rc; 298 } 299 300 static int bnxt_qplib_process_qp_event(struct bnxt_qplib_rcfw *rcfw, 301 struct creq_qp_event *qp_event) 302 { 303 struct creq_qp_error_notification *err_event; 304 struct bnxt_qplib_hwq *hwq = &rcfw->cmdq.hwq; 305 struct bnxt_qplib_crsqe *crsqe; 306 struct bnxt_qplib_qp *qp; 307 u16 cbit, blocked = 0; 308 struct pci_dev *pdev; 309 unsigned long flags; 310 __le16 mcookie; 311 u16 cookie; 312 int rc = 0; 313 u32 qp_id; 314 315 pdev = rcfw->pdev; 316 switch (qp_event->event) { 317 case CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION: 318 err_event = (struct creq_qp_error_notification *)qp_event; 319 qp_id = le32_to_cpu(err_event->xid); 320 qp = rcfw->qp_tbl[qp_id].qp_handle; 321 dev_dbg(&pdev->dev, "Received QP error notification\n"); 322 dev_dbg(&pdev->dev, 323 "qpid 0x%x, req_err=0x%x, resp_err=0x%x\n", 324 qp_id, err_event->req_err_state_reason, 325 err_event->res_err_state_reason); 326 if (!qp) 327 break; 328 bnxt_qplib_mark_qp_error(qp); 329 rc = rcfw->creq.aeq_handler(rcfw, qp_event, qp); 330 break; 331 default: 332 /* 333 * Command Response 334 * cmdq->lock needs to be acquired to synchronie 335 * the command send and completion reaping. This function 336 * is always called with creq->lock held. Using 337 * the nested variant of spin_lock. 338 * 339 */ 340 341 spin_lock_irqsave_nested(&hwq->lock, flags, 342 SINGLE_DEPTH_NESTING); 343 cookie = le16_to_cpu(qp_event->cookie); 344 mcookie = qp_event->cookie; 345 blocked = cookie & RCFW_CMD_IS_BLOCKING; 346 cookie &= RCFW_MAX_COOKIE_VALUE; 347 cbit = cookie % rcfw->cmdq_depth; 348 crsqe = &rcfw->crsqe_tbl[cbit]; 349 if (crsqe->resp && 350 crsqe->resp->cookie == mcookie) { 351 memcpy(crsqe->resp, qp_event, sizeof(*qp_event)); 352 crsqe->resp = NULL; 353 } else { 354 if (crsqe->resp && crsqe->resp->cookie) 355 dev_err(&pdev->dev, 356 "CMD %s cookie sent=%#x, recd=%#x\n", 357 crsqe->resp ? "mismatch" : "collision", 358 crsqe->resp ? crsqe->resp->cookie : 0, 359 mcookie); 360 } 361 if (!test_and_clear_bit(cbit, rcfw->cmdq.cmdq_bitmap)) 362 dev_warn(&pdev->dev, 363 "CMD bit %d was not requested\n", cbit); 364 hwq->cons += crsqe->req_size; 365 crsqe->req_size = 0; 366 367 if (!blocked) 368 wake_up(&rcfw->cmdq.waitq); 369 spin_unlock_irqrestore(&hwq->lock, flags); 370 } 371 return rc; 372 } 373 374 /* SP - CREQ Completion handlers */ 375 static void bnxt_qplib_service_creq(unsigned long data) 376 { 377 struct bnxt_qplib_rcfw *rcfw = (struct bnxt_qplib_rcfw *)data; 378 struct bnxt_qplib_creq_ctx *creq = &rcfw->creq; 379 u32 type, budget = CREQ_ENTRY_POLL_BUDGET; 380 struct bnxt_qplib_hwq *hwq = &creq->hwq; 381 struct creq_base *creqe, **hwq_ptr; 382 u32 sw_cons, raw_cons; 383 unsigned long flags; 384 385 /* Service the CREQ until budget is over */ 386 spin_lock_irqsave(&hwq->lock, flags); 387 raw_cons = hwq->cons; 388 while (budget > 0) { 389 sw_cons = HWQ_CMP(raw_cons, hwq); 390 hwq_ptr = (struct creq_base **)hwq->pbl_ptr; 391 creqe = &hwq_ptr[get_creq_pg(sw_cons)][get_creq_idx(sw_cons)]; 392 if (!CREQ_CMP_VALID(creqe, raw_cons, hwq->max_elements)) 393 break; 394 /* The valid test of the entry must be done first before 395 * reading any further. 396 */ 397 dma_rmb(); 398 399 type = creqe->type & CREQ_BASE_TYPE_MASK; 400 switch (type) { 401 case CREQ_BASE_TYPE_QP_EVENT: 402 bnxt_qplib_process_qp_event 403 (rcfw, (struct creq_qp_event *)creqe); 404 creq->stats.creq_qp_event_processed++; 405 break; 406 case CREQ_BASE_TYPE_FUNC_EVENT: 407 if (!bnxt_qplib_process_func_event 408 (rcfw, (struct creq_func_event *)creqe)) 409 creq->stats.creq_func_event_processed++; 410 else 411 dev_warn(&rcfw->pdev->dev, 412 "aeqe:%#x Not handled\n", type); 413 break; 414 default: 415 if (type != ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT) 416 dev_warn(&rcfw->pdev->dev, 417 "creqe with event 0x%x not handled\n", 418 type); 419 break; 420 } 421 raw_cons++; 422 budget--; 423 } 424 425 if (hwq->cons != raw_cons) { 426 hwq->cons = raw_cons; 427 bnxt_qplib_ring_nq_db(&creq->creq_db.dbinfo, 428 rcfw->res->cctx, true); 429 } 430 spin_unlock_irqrestore(&hwq->lock, flags); 431 } 432 433 static irqreturn_t bnxt_qplib_creq_irq(int irq, void *dev_instance) 434 { 435 struct bnxt_qplib_rcfw *rcfw = dev_instance; 436 struct bnxt_qplib_creq_ctx *creq; 437 struct creq_base **creq_ptr; 438 struct bnxt_qplib_hwq *hwq; 439 u32 sw_cons; 440 441 creq = &rcfw->creq; 442 hwq = &creq->hwq; 443 /* Prefetch the CREQ element */ 444 sw_cons = HWQ_CMP(hwq->cons, hwq); 445 creq_ptr = (struct creq_base **)creq->hwq.pbl_ptr; 446 prefetch(&creq_ptr[get_creq_pg(sw_cons)][get_creq_idx(sw_cons)]); 447 448 tasklet_schedule(&creq->creq_tasklet); 449 450 return IRQ_HANDLED; 451 } 452 453 /* RCFW */ 454 int bnxt_qplib_deinit_rcfw(struct bnxt_qplib_rcfw *rcfw) 455 { 456 struct cmdq_deinitialize_fw req; 457 struct creq_deinitialize_fw_resp resp; 458 u16 cmd_flags = 0; 459 int rc; 460 461 RCFW_CMD_PREP(req, DEINITIALIZE_FW, cmd_flags); 462 rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, (void *)&resp, 463 NULL, 0); 464 if (rc) 465 return rc; 466 467 clear_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->cmdq.flags); 468 return 0; 469 } 470 471 static int __get_pbl_pg_idx(struct bnxt_qplib_pbl *pbl) 472 { 473 return (pbl->pg_size == ROCE_PG_SIZE_4K ? 474 CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_4K : 475 pbl->pg_size == ROCE_PG_SIZE_8K ? 476 CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8K : 477 pbl->pg_size == ROCE_PG_SIZE_64K ? 478 CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_64K : 479 pbl->pg_size == ROCE_PG_SIZE_2M ? 480 CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_2M : 481 pbl->pg_size == ROCE_PG_SIZE_8M ? 482 CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8M : 483 pbl->pg_size == ROCE_PG_SIZE_1G ? 484 CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G : 485 CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_4K); 486 } 487 488 int bnxt_qplib_init_rcfw(struct bnxt_qplib_rcfw *rcfw, 489 struct bnxt_qplib_ctx *ctx, int is_virtfn) 490 { 491 struct cmdq_initialize_fw req; 492 struct creq_initialize_fw_resp resp; 493 u16 cmd_flags = 0, level; 494 int rc; 495 496 RCFW_CMD_PREP(req, INITIALIZE_FW, cmd_flags); 497 /* Supply (log-base-2-of-host-page-size - base-page-shift) 498 * to bono to adjust the doorbell page sizes. 499 */ 500 req.log2_dbr_pg_size = cpu_to_le16(PAGE_SHIFT - 501 RCFW_DBR_BASE_PAGE_SHIFT); 502 /* 503 * Gen P5 devices doesn't require this allocation 504 * as the L2 driver does the same for RoCE also. 505 * Also, VFs need not setup the HW context area, PF 506 * shall setup this area for VF. Skipping the 507 * HW programming 508 */ 509 if (is_virtfn) 510 goto skip_ctx_setup; 511 if (bnxt_qplib_is_chip_gen_p5(rcfw->res->cctx)) 512 goto config_vf_res; 513 514 level = ctx->qpc_tbl.level; 515 req.qpc_pg_size_qpc_lvl = (level << CMDQ_INITIALIZE_FW_QPC_LVL_SFT) | 516 __get_pbl_pg_idx(&ctx->qpc_tbl.pbl[level]); 517 level = ctx->mrw_tbl.level; 518 req.mrw_pg_size_mrw_lvl = (level << CMDQ_INITIALIZE_FW_MRW_LVL_SFT) | 519 __get_pbl_pg_idx(&ctx->mrw_tbl.pbl[level]); 520 level = ctx->srqc_tbl.level; 521 req.srq_pg_size_srq_lvl = (level << CMDQ_INITIALIZE_FW_SRQ_LVL_SFT) | 522 __get_pbl_pg_idx(&ctx->srqc_tbl.pbl[level]); 523 level = ctx->cq_tbl.level; 524 req.cq_pg_size_cq_lvl = (level << CMDQ_INITIALIZE_FW_CQ_LVL_SFT) | 525 __get_pbl_pg_idx(&ctx->cq_tbl.pbl[level]); 526 level = ctx->srqc_tbl.level; 527 req.srq_pg_size_srq_lvl = (level << CMDQ_INITIALIZE_FW_SRQ_LVL_SFT) | 528 __get_pbl_pg_idx(&ctx->srqc_tbl.pbl[level]); 529 level = ctx->cq_tbl.level; 530 req.cq_pg_size_cq_lvl = (level << CMDQ_INITIALIZE_FW_CQ_LVL_SFT) | 531 __get_pbl_pg_idx(&ctx->cq_tbl.pbl[level]); 532 level = ctx->tim_tbl.level; 533 req.tim_pg_size_tim_lvl = (level << CMDQ_INITIALIZE_FW_TIM_LVL_SFT) | 534 __get_pbl_pg_idx(&ctx->tim_tbl.pbl[level]); 535 level = ctx->tqm_ctx.pde.level; 536 req.tqm_pg_size_tqm_lvl = 537 (level << CMDQ_INITIALIZE_FW_TQM_LVL_SFT) | 538 __get_pbl_pg_idx(&ctx->tqm_ctx.pde.pbl[level]); 539 540 req.qpc_page_dir = 541 cpu_to_le64(ctx->qpc_tbl.pbl[PBL_LVL_0].pg_map_arr[0]); 542 req.mrw_page_dir = 543 cpu_to_le64(ctx->mrw_tbl.pbl[PBL_LVL_0].pg_map_arr[0]); 544 req.srq_page_dir = 545 cpu_to_le64(ctx->srqc_tbl.pbl[PBL_LVL_0].pg_map_arr[0]); 546 req.cq_page_dir = 547 cpu_to_le64(ctx->cq_tbl.pbl[PBL_LVL_0].pg_map_arr[0]); 548 req.tim_page_dir = 549 cpu_to_le64(ctx->tim_tbl.pbl[PBL_LVL_0].pg_map_arr[0]); 550 req.tqm_page_dir = 551 cpu_to_le64(ctx->tqm_ctx.pde.pbl[PBL_LVL_0].pg_map_arr[0]); 552 553 req.number_of_qp = cpu_to_le32(ctx->qpc_tbl.max_elements); 554 req.number_of_mrw = cpu_to_le32(ctx->mrw_tbl.max_elements); 555 req.number_of_srq = cpu_to_le32(ctx->srqc_tbl.max_elements); 556 req.number_of_cq = cpu_to_le32(ctx->cq_tbl.max_elements); 557 558 config_vf_res: 559 req.max_qp_per_vf = cpu_to_le32(ctx->vf_res.max_qp_per_vf); 560 req.max_mrw_per_vf = cpu_to_le32(ctx->vf_res.max_mrw_per_vf); 561 req.max_srq_per_vf = cpu_to_le32(ctx->vf_res.max_srq_per_vf); 562 req.max_cq_per_vf = cpu_to_le32(ctx->vf_res.max_cq_per_vf); 563 req.max_gid_per_vf = cpu_to_le32(ctx->vf_res.max_gid_per_vf); 564 565 skip_ctx_setup: 566 req.stat_ctx_id = cpu_to_le32(ctx->stats.fw_id); 567 rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, (void *)&resp, 568 NULL, 0); 569 if (rc) 570 return rc; 571 set_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->cmdq.flags); 572 return 0; 573 } 574 575 void bnxt_qplib_free_rcfw_channel(struct bnxt_qplib_rcfw *rcfw) 576 { 577 kfree(rcfw->cmdq.cmdq_bitmap); 578 kfree(rcfw->qp_tbl); 579 kfree(rcfw->crsqe_tbl); 580 bnxt_qplib_free_hwq(rcfw->res, &rcfw->cmdq.hwq); 581 bnxt_qplib_free_hwq(rcfw->res, &rcfw->creq.hwq); 582 rcfw->pdev = NULL; 583 } 584 585 int bnxt_qplib_alloc_rcfw_channel(struct bnxt_qplib_res *res, 586 struct bnxt_qplib_rcfw *rcfw, 587 struct bnxt_qplib_ctx *ctx, 588 int qp_tbl_sz) 589 { 590 struct bnxt_qplib_hwq_attr hwq_attr = {}; 591 struct bnxt_qplib_sg_info sginfo = {}; 592 struct bnxt_qplib_cmdq_ctx *cmdq; 593 struct bnxt_qplib_creq_ctx *creq; 594 u32 bmap_size = 0; 595 596 rcfw->pdev = res->pdev; 597 cmdq = &rcfw->cmdq; 598 creq = &rcfw->creq; 599 rcfw->res = res; 600 601 sginfo.pgsize = PAGE_SIZE; 602 sginfo.pgshft = PAGE_SHIFT; 603 604 hwq_attr.sginfo = &sginfo; 605 hwq_attr.res = rcfw->res; 606 hwq_attr.depth = BNXT_QPLIB_CREQE_MAX_CNT; 607 hwq_attr.stride = BNXT_QPLIB_CREQE_UNITS; 608 hwq_attr.type = bnxt_qplib_get_hwq_type(res); 609 610 if (bnxt_qplib_alloc_init_hwq(&creq->hwq, &hwq_attr)) { 611 dev_err(&rcfw->pdev->dev, 612 "HW channel CREQ allocation failed\n"); 613 goto fail; 614 } 615 if (ctx->hwrm_intf_ver < HWRM_VERSION_RCFW_CMDQ_DEPTH_CHECK) 616 rcfw->cmdq_depth = BNXT_QPLIB_CMDQE_MAX_CNT_256; 617 else 618 rcfw->cmdq_depth = BNXT_QPLIB_CMDQE_MAX_CNT_8192; 619 620 sginfo.pgsize = bnxt_qplib_cmdqe_page_size(rcfw->cmdq_depth); 621 hwq_attr.depth = rcfw->cmdq_depth; 622 hwq_attr.stride = BNXT_QPLIB_CMDQE_UNITS; 623 hwq_attr.type = HWQ_TYPE_CTX; 624 if (bnxt_qplib_alloc_init_hwq(&cmdq->hwq, &hwq_attr)) { 625 dev_err(&rcfw->pdev->dev, 626 "HW channel CMDQ allocation failed\n"); 627 goto fail; 628 } 629 630 rcfw->crsqe_tbl = kcalloc(cmdq->hwq.max_elements, 631 sizeof(*rcfw->crsqe_tbl), GFP_KERNEL); 632 if (!rcfw->crsqe_tbl) 633 goto fail; 634 635 bmap_size = BITS_TO_LONGS(rcfw->cmdq_depth) * sizeof(unsigned long); 636 cmdq->cmdq_bitmap = kzalloc(bmap_size, GFP_KERNEL); 637 if (!cmdq->cmdq_bitmap) 638 goto fail; 639 640 cmdq->bmap_size = bmap_size; 641 642 rcfw->qp_tbl_size = qp_tbl_sz; 643 rcfw->qp_tbl = kcalloc(qp_tbl_sz, sizeof(struct bnxt_qplib_qp_node), 644 GFP_KERNEL); 645 if (!rcfw->qp_tbl) 646 goto fail; 647 648 return 0; 649 650 fail: 651 bnxt_qplib_free_rcfw_channel(rcfw); 652 return -ENOMEM; 653 } 654 655 void bnxt_qplib_rcfw_stop_irq(struct bnxt_qplib_rcfw *rcfw, bool kill) 656 { 657 struct bnxt_qplib_creq_ctx *creq; 658 659 creq = &rcfw->creq; 660 tasklet_disable(&creq->creq_tasklet); 661 /* Mask h/w interrupts */ 662 bnxt_qplib_ring_nq_db(&creq->creq_db.dbinfo, rcfw->res->cctx, false); 663 /* Sync with last running IRQ-handler */ 664 synchronize_irq(creq->msix_vec); 665 if (kill) 666 tasklet_kill(&creq->creq_tasklet); 667 668 if (creq->requested) { 669 free_irq(creq->msix_vec, rcfw); 670 creq->requested = false; 671 } 672 } 673 674 void bnxt_qplib_disable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw) 675 { 676 struct bnxt_qplib_creq_ctx *creq; 677 struct bnxt_qplib_cmdq_ctx *cmdq; 678 unsigned long indx; 679 680 creq = &rcfw->creq; 681 cmdq = &rcfw->cmdq; 682 /* Make sure the HW channel is stopped! */ 683 bnxt_qplib_rcfw_stop_irq(rcfw, true); 684 685 iounmap(cmdq->cmdq_mbox.reg.bar_reg); 686 iounmap(creq->creq_db.reg.bar_reg); 687 688 indx = find_first_bit(cmdq->cmdq_bitmap, cmdq->bmap_size); 689 if (indx != cmdq->bmap_size) 690 dev_err(&rcfw->pdev->dev, 691 "disabling RCFW with pending cmd-bit %lx\n", indx); 692 693 cmdq->cmdq_mbox.reg.bar_reg = NULL; 694 creq->creq_db.reg.bar_reg = NULL; 695 creq->aeq_handler = NULL; 696 creq->msix_vec = 0; 697 } 698 699 int bnxt_qplib_rcfw_start_irq(struct bnxt_qplib_rcfw *rcfw, int msix_vector, 700 bool need_init) 701 { 702 struct bnxt_qplib_creq_ctx *creq; 703 int rc; 704 705 creq = &rcfw->creq; 706 707 if (creq->requested) 708 return -EFAULT; 709 710 creq->msix_vec = msix_vector; 711 if (need_init) 712 tasklet_init(&creq->creq_tasklet, 713 bnxt_qplib_service_creq, (unsigned long)rcfw); 714 else 715 tasklet_enable(&creq->creq_tasklet); 716 rc = request_irq(creq->msix_vec, bnxt_qplib_creq_irq, 0, 717 "bnxt_qplib_creq", rcfw); 718 if (rc) 719 return rc; 720 creq->requested = true; 721 722 bnxt_qplib_ring_nq_db(&creq->creq_db.dbinfo, rcfw->res->cctx, true); 723 724 return 0; 725 } 726 727 static int bnxt_qplib_map_cmdq_mbox(struct bnxt_qplib_rcfw *rcfw, bool is_vf) 728 { 729 struct bnxt_qplib_cmdq_mbox *mbox; 730 resource_size_t bar_reg; 731 struct pci_dev *pdev; 732 u16 prod_offt; 733 int rc = 0; 734 735 pdev = rcfw->pdev; 736 mbox = &rcfw->cmdq.cmdq_mbox; 737 738 mbox->reg.bar_id = RCFW_COMM_PCI_BAR_REGION; 739 mbox->reg.len = RCFW_COMM_SIZE; 740 mbox->reg.bar_base = pci_resource_start(pdev, mbox->reg.bar_id); 741 if (!mbox->reg.bar_base) { 742 dev_err(&pdev->dev, 743 "QPLIB: CMDQ BAR region %d resc start is 0!\n", 744 mbox->reg.bar_id); 745 return -ENOMEM; 746 } 747 748 bar_reg = mbox->reg.bar_base + RCFW_COMM_BASE_OFFSET; 749 mbox->reg.len = RCFW_COMM_SIZE; 750 mbox->reg.bar_reg = ioremap(bar_reg, mbox->reg.len); 751 if (!mbox->reg.bar_reg) { 752 dev_err(&pdev->dev, 753 "QPLIB: CMDQ BAR region %d mapping failed\n", 754 mbox->reg.bar_id); 755 return -ENOMEM; 756 } 757 758 prod_offt = is_vf ? RCFW_VF_COMM_PROD_OFFSET : 759 RCFW_PF_COMM_PROD_OFFSET; 760 mbox->prod = (void __iomem *)(mbox->reg.bar_reg + prod_offt); 761 mbox->db = (void __iomem *)(mbox->reg.bar_reg + RCFW_COMM_TRIG_OFFSET); 762 return rc; 763 } 764 765 static int bnxt_qplib_map_creq_db(struct bnxt_qplib_rcfw *rcfw, u32 reg_offt) 766 { 767 struct bnxt_qplib_creq_db *creq_db; 768 resource_size_t bar_reg; 769 struct pci_dev *pdev; 770 771 pdev = rcfw->pdev; 772 creq_db = &rcfw->creq.creq_db; 773 774 creq_db->reg.bar_id = RCFW_COMM_CONS_PCI_BAR_REGION; 775 creq_db->reg.bar_base = pci_resource_start(pdev, creq_db->reg.bar_id); 776 if (!creq_db->reg.bar_id) 777 dev_err(&pdev->dev, 778 "QPLIB: CREQ BAR region %d resc start is 0!", 779 creq_db->reg.bar_id); 780 781 bar_reg = creq_db->reg.bar_base + reg_offt; 782 /* Unconditionally map 8 bytes to support 57500 series */ 783 creq_db->reg.len = 8; 784 creq_db->reg.bar_reg = ioremap(bar_reg, creq_db->reg.len); 785 if (!creq_db->reg.bar_reg) { 786 dev_err(&pdev->dev, 787 "QPLIB: CREQ BAR region %d mapping failed", 788 creq_db->reg.bar_id); 789 return -ENOMEM; 790 } 791 creq_db->dbinfo.db = creq_db->reg.bar_reg; 792 creq_db->dbinfo.hwq = &rcfw->creq.hwq; 793 creq_db->dbinfo.xid = rcfw->creq.ring_id; 794 return 0; 795 } 796 797 static void bnxt_qplib_start_rcfw(struct bnxt_qplib_rcfw *rcfw) 798 { 799 struct bnxt_qplib_cmdq_ctx *cmdq; 800 struct bnxt_qplib_creq_ctx *creq; 801 struct bnxt_qplib_cmdq_mbox *mbox; 802 struct cmdq_init init = {0}; 803 804 cmdq = &rcfw->cmdq; 805 creq = &rcfw->creq; 806 mbox = &cmdq->cmdq_mbox; 807 808 init.cmdq_pbl = cpu_to_le64(cmdq->hwq.pbl[PBL_LVL_0].pg_map_arr[0]); 809 init.cmdq_size_cmdq_lvl = 810 cpu_to_le16(((rcfw->cmdq_depth << 811 CMDQ_INIT_CMDQ_SIZE_SFT) & 812 CMDQ_INIT_CMDQ_SIZE_MASK) | 813 ((cmdq->hwq.level << 814 CMDQ_INIT_CMDQ_LVL_SFT) & 815 CMDQ_INIT_CMDQ_LVL_MASK)); 816 init.creq_ring_id = cpu_to_le16(creq->ring_id); 817 /* Write to the Bono mailbox register */ 818 __iowrite32_copy(mbox->reg.bar_reg, &init, sizeof(init) / 4); 819 } 820 821 int bnxt_qplib_enable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw, 822 int msix_vector, 823 int cp_bar_reg_off, int virt_fn, 824 aeq_handler_t aeq_handler) 825 { 826 struct bnxt_qplib_cmdq_ctx *cmdq; 827 struct bnxt_qplib_creq_ctx *creq; 828 int rc; 829 830 cmdq = &rcfw->cmdq; 831 creq = &rcfw->creq; 832 833 /* Clear to defaults */ 834 835 cmdq->seq_num = 0; 836 set_bit(FIRMWARE_FIRST_FLAG, &cmdq->flags); 837 init_waitqueue_head(&cmdq->waitq); 838 839 creq->stats.creq_qp_event_processed = 0; 840 creq->stats.creq_func_event_processed = 0; 841 creq->aeq_handler = aeq_handler; 842 843 rc = bnxt_qplib_map_cmdq_mbox(rcfw, virt_fn); 844 if (rc) 845 return rc; 846 847 rc = bnxt_qplib_map_creq_db(rcfw, cp_bar_reg_off); 848 if (rc) 849 return rc; 850 851 rc = bnxt_qplib_rcfw_start_irq(rcfw, msix_vector, true); 852 if (rc) { 853 dev_err(&rcfw->pdev->dev, 854 "Failed to request IRQ for CREQ rc = 0x%x\n", rc); 855 bnxt_qplib_disable_rcfw_channel(rcfw); 856 return rc; 857 } 858 859 bnxt_qplib_start_rcfw(rcfw); 860 861 return 0; 862 } 863 864 struct bnxt_qplib_rcfw_sbuf *bnxt_qplib_rcfw_alloc_sbuf( 865 struct bnxt_qplib_rcfw *rcfw, 866 u32 size) 867 { 868 struct bnxt_qplib_rcfw_sbuf *sbuf; 869 870 sbuf = kzalloc(sizeof(*sbuf), GFP_ATOMIC); 871 if (!sbuf) 872 return NULL; 873 874 sbuf->size = size; 875 sbuf->sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf->size, 876 &sbuf->dma_addr, GFP_ATOMIC); 877 if (!sbuf->sb) 878 goto bail; 879 880 return sbuf; 881 bail: 882 kfree(sbuf); 883 return NULL; 884 } 885 886 void bnxt_qplib_rcfw_free_sbuf(struct bnxt_qplib_rcfw *rcfw, 887 struct bnxt_qplib_rcfw_sbuf *sbuf) 888 { 889 if (sbuf->sb) 890 dma_free_coherent(&rcfw->pdev->dev, sbuf->size, 891 sbuf->sb, sbuf->dma_addr); 892 kfree(sbuf); 893 } 894