1/*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Mars.C <mars.cheng@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11 * GNU General Public License for more details.
12 */
13
14#include <dt-bindings/clock/mt6797-clk.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16#include <dt-bindings/interrupt-controller/arm-gic.h>
17#include <dt-bindings/pinctrl/mt6797-pinfunc.h>
18
19/ {
20	compatible = "mediatek,mt6797";
21	interrupt-parent = <&sysirq>;
22	#address-cells = <2>;
23	#size-cells = <2>;
24
25	psci {
26		compatible = "arm,psci-0.2";
27		method = "smc";
28	};
29
30	cpus {
31		#address-cells = <1>;
32		#size-cells = <0>;
33
34		cpu0: cpu@0 {
35			device_type = "cpu";
36			compatible = "arm,cortex-a53";
37			enable-method = "psci";
38			reg = <0x000>;
39		};
40
41		cpu1: cpu@1 {
42			device_type = "cpu";
43			compatible = "arm,cortex-a53";
44			enable-method = "psci";
45			reg = <0x001>;
46		};
47
48		cpu2: cpu@2 {
49			device_type = "cpu";
50			compatible = "arm,cortex-a53";
51			enable-method = "psci";
52			reg = <0x002>;
53		};
54
55		cpu3: cpu@3 {
56			device_type = "cpu";
57			compatible = "arm,cortex-a53";
58			enable-method = "psci";
59			reg = <0x003>;
60		};
61
62		cpu4: cpu@100 {
63			device_type = "cpu";
64			compatible = "arm,cortex-a53";
65			enable-method = "psci";
66			reg = <0x100>;
67		};
68
69		cpu5: cpu@101 {
70			device_type = "cpu";
71			compatible = "arm,cortex-a53";
72			enable-method = "psci";
73			reg = <0x101>;
74		};
75
76		cpu6: cpu@102 {
77			device_type = "cpu";
78			compatible = "arm,cortex-a53";
79			enable-method = "psci";
80			reg = <0x102>;
81		};
82
83		cpu7: cpu@103 {
84			device_type = "cpu";
85			compatible = "arm,cortex-a53";
86			enable-method = "psci";
87			reg = <0x103>;
88		};
89
90		cpu8: cpu@200 {
91			device_type = "cpu";
92			compatible = "arm,cortex-a72";
93			enable-method = "psci";
94			reg = <0x200>;
95		};
96
97		cpu9: cpu@201 {
98			device_type = "cpu";
99			compatible = "arm,cortex-a72";
100			enable-method = "psci";
101			reg = <0x201>;
102		};
103	};
104
105	clk26m: oscillator@0 {
106		compatible = "fixed-clock";
107		#clock-cells = <0>;
108		clock-frequency = <26000000>;
109		clock-output-names = "clk26m";
110	};
111
112	timer {
113		compatible = "arm,armv8-timer";
114		interrupt-parent = <&gic>;
115		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
116			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
117			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
118			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
119	};
120
121	topckgen: topckgen@10000000 {
122		compatible = "mediatek,mt6797-topckgen";
123		reg = <0 0x10000000 0 0x1000>;
124		#clock-cells = <1>;
125	};
126
127	infrasys: infracfg_ao@10001000 {
128		compatible = "mediatek,mt6797-infracfg", "syscon";
129		reg = <0 0x10001000 0 0x1000>;
130		#clock-cells = <1>;
131	};
132
133	pio: pinctrl@10005000 {
134		compatible = "mediatek,mt6797-pinctrl";
135		reg = <0 0x10005000 0 0x1000>,
136		      <0 0x10002000 0 0x400>,
137		      <0 0x10002400 0 0x400>,
138		      <0 0x10002800 0 0x400>,
139		      <0 0x10002C00 0 0x400>;
140		reg-names = "gpio", "iocfgl", "iocfgb",
141			    "iocfgr", "iocfgt";
142		gpio-controller;
143		#gpio-cells = <2>;
144
145		uart0_pins_a: uart0 {
146			pins0 {
147				pinmux = <MT6797_GPIO234__FUNC_UTXD0>,
148					 <MT6797_GPIO235__FUNC_URXD0>;
149			};
150		};
151
152		uart1_pins_a: uart1 {
153			pins1 {
154				pinmux = <MT6797_GPIO232__FUNC_URXD1>,
155					 <MT6797_GPIO233__FUNC_UTXD1>;
156			};
157		};
158	};
159
160	scpsys: power-controller@10006000 {
161		compatible = "mediatek,mt6797-scpsys";
162		#power-domain-cells = <1>;
163		reg = <0 0x10006000 0 0x1000>;
164		clocks = <&topckgen CLK_TOP_MUX_MFG>,
165			 <&topckgen CLK_TOP_MUX_MM>,
166			 <&topckgen CLK_TOP_MUX_VDEC>;
167		clock-names = "mfg", "mm", "vdec";
168		infracfg = <&infrasys>;
169	};
170
171	watchdog: watchdog@10007000 {
172		compatible = "mediatek,mt6797-wdt", "mediatek,mt6589-wdt";
173		reg = <0 0x10007000 0 0x100>;
174	};
175
176	apmixedsys: apmixed@1000c000 {
177		compatible = "mediatek,mt6797-apmixedsys";
178		reg = <0 0x1000c000 0 0x1000>;
179		#clock-cells = <1>;
180	};
181
182	sysirq: intpol-controller@10200620 {
183		compatible = "mediatek,mt6797-sysirq",
184			     "mediatek,mt6577-sysirq";
185		interrupt-controller;
186		#interrupt-cells = <3>;
187		interrupt-parent = <&gic>;
188		reg = <0 0x10220620 0 0x20>,
189		      <0 0x10220690 0 0x10>;
190	};
191
192	uart0: serial@11002000 {
193		compatible = "mediatek,mt6797-uart",
194			     "mediatek,mt6577-uart";
195		reg = <0 0x11002000 0 0x400>;
196		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
197		clocks = <&infrasys CLK_INFRA_UART0>,
198			 <&infrasys CLK_INFRA_AP_DMA>;
199		clock-names = "baud", "bus";
200		status = "disabled";
201	};
202
203	uart1: serial@11003000 {
204		compatible = "mediatek,mt6797-uart",
205			     "mediatek,mt6577-uart";
206		reg = <0 0x11003000 0 0x400>;
207		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
208		clocks = <&infrasys CLK_INFRA_UART1>,
209			 <&infrasys CLK_INFRA_AP_DMA>;
210		clock-names = "baud", "bus";
211		status = "disabled";
212	};
213
214	uart2: serial@11004000 {
215		compatible = "mediatek,mt6797-uart",
216			     "mediatek,mt6577-uart";
217		reg = <0 0x11004000 0 0x400>;
218		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
219		clocks = <&infrasys CLK_INFRA_UART2>,
220			 <&infrasys CLK_INFRA_AP_DMA>;
221		clock-names = "baud", "bus";
222		status = "disabled";
223	};
224
225	uart3: serial@11005000 {
226		compatible = "mediatek,mt6797-uart",
227			     "mediatek,mt6577-uart";
228		reg = <0 0x11005000 0 0x400>;
229		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
230		clocks = <&infrasys CLK_INFRA_UART3>,
231			 <&infrasys CLK_INFRA_AP_DMA>;
232		clock-names = "baud", "bus";
233		status = "disabled";
234	};
235
236	mmsys: mmsys_config@14000000 {
237		compatible = "mediatek,mt6797-mmsys", "syscon";
238		reg = <0 0x14000000 0 0x1000>;
239		#clock-cells = <1>;
240	};
241
242	imgsys: imgsys_config@15000000  {
243		compatible = "mediatek,mt6797-imgsys", "syscon";
244		reg = <0 0x15000000 0 0x1000>;
245		#clock-cells = <1>;
246	};
247
248	vdecsys: vdec_gcon@16000000 {
249		compatible = "mediatek,mt6797-vdecsys", "syscon";
250		reg = <0 0x16000000 0 0x10000>;
251		#clock-cells = <1>;
252	};
253
254	vencsys: venc_gcon@17000000 {
255		compatible = "mediatek,mt6797-vencsys", "syscon";
256		reg = <0 0x17000000 0 0x1000>;
257		#clock-cells = <1>;
258	};
259
260	gic: interrupt-controller@19000000 {
261		compatible = "arm,gic-v3";
262		#interrupt-cells = <3>;
263		interrupt-parent = <&gic>;
264		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
265		interrupt-controller;
266		reg = <0 0x19000000 0 0x10000>,    /* GICD */
267		      <0 0x19200000 0 0x200000>,   /* GICR */
268		      <0 0x10240000 0 0x2000>;     /* GICC */
269	};
270};
271