1 // SPDX-License-Identifier: GPL-2.0 2 /* Atheros AR71xx built-in ethernet mac driver 3 * 4 * Copyright (C) 2019 Oleksij Rempel <o.rempel@pengutronix.de> 5 * 6 * List of authors contributed to this driver before mainlining: 7 * Alexander Couzens <lynxis@fe80.eu> 8 * Christian Lamparter <chunkeey@gmail.com> 9 * Chuanhong Guo <gch981213@gmail.com> 10 * Daniel F. Dickinson <cshored@thecshore.com> 11 * David Bauer <mail@david-bauer.net> 12 * Felix Fietkau <nbd@nbd.name> 13 * Gabor Juhos <juhosg@freemail.hu> 14 * Hauke Mehrtens <hauke@hauke-m.de> 15 * Johann Neuhauser <johann@it-neuhauser.de> 16 * John Crispin <john@phrozen.org> 17 * Jo-Philipp Wich <jo@mein.io> 18 * Koen Vandeputte <koen.vandeputte@ncentric.com> 19 * Lucian Cristian <lucian.cristian@gmail.com> 20 * Matt Merhar <mattmerhar@protonmail.com> 21 * Milan Krstic <milan.krstic@gmail.com> 22 * Petr Štetiar <ynezz@true.cz> 23 * Rosen Penev <rosenp@gmail.com> 24 * Stephen Walker <stephendwalker+github@gmail.com> 25 * Vittorio Gambaletta <openwrt@vittgam.net> 26 * Weijie Gao <hackpascal@gmail.com> 27 * Imre Kaloz <kaloz@openwrt.org> 28 */ 29 30 #include <linux/if_vlan.h> 31 #include <linux/mfd/syscon.h> 32 #include <linux/of_mdio.h> 33 #include <linux/of_net.h> 34 #include <linux/of_platform.h> 35 #include <linux/phylink.h> 36 #include <linux/regmap.h> 37 #include <linux/reset.h> 38 #include <linux/clk.h> 39 #include <linux/io.h> 40 41 /* For our NAPI weight bigger does *NOT* mean better - it means more 42 * D-cache misses and lots more wasted cycles than we'll ever 43 * possibly gain from saving instructions. 44 */ 45 #define AG71XX_NAPI_WEIGHT 32 46 #define AG71XX_OOM_REFILL (1 + HZ / 10) 47 48 #define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE) 49 #define AG71XX_INT_TX (AG71XX_INT_TX_PS) 50 #define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF) 51 52 #define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX) 53 #define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL) 54 55 #define AG71XX_TX_MTU_LEN 1540 56 57 #define AG71XX_TX_RING_SPLIT 512 58 #define AG71XX_TX_RING_DS_PER_PKT DIV_ROUND_UP(AG71XX_TX_MTU_LEN, \ 59 AG71XX_TX_RING_SPLIT) 60 #define AG71XX_TX_RING_SIZE_DEFAULT 128 61 #define AG71XX_RX_RING_SIZE_DEFAULT 256 62 63 #define AG71XX_MDIO_RETRY 1000 64 #define AG71XX_MDIO_DELAY 5 65 #define AG71XX_MDIO_MAX_CLK 5000000 66 67 /* Register offsets */ 68 #define AG71XX_REG_MAC_CFG1 0x0000 69 #define MAC_CFG1_TXE BIT(0) /* Tx Enable */ 70 #define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */ 71 #define MAC_CFG1_RXE BIT(2) /* Rx Enable */ 72 #define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */ 73 #define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */ 74 #define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */ 75 #define MAC_CFG1_SR BIT(31) /* Soft Reset */ 76 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \ 77 MAC_CFG1_SRX | MAC_CFG1_STX) 78 79 #define AG71XX_REG_MAC_CFG2 0x0004 80 #define MAC_CFG2_FDX BIT(0) 81 #define MAC_CFG2_PAD_CRC_EN BIT(2) 82 #define MAC_CFG2_LEN_CHECK BIT(4) 83 #define MAC_CFG2_IF_1000 BIT(9) 84 #define MAC_CFG2_IF_10_100 BIT(8) 85 86 #define AG71XX_REG_MAC_MFL 0x0010 87 88 #define AG71XX_REG_MII_CFG 0x0020 89 #define MII_CFG_CLK_DIV_4 0 90 #define MII_CFG_CLK_DIV_6 2 91 #define MII_CFG_CLK_DIV_8 3 92 #define MII_CFG_CLK_DIV_10 4 93 #define MII_CFG_CLK_DIV_14 5 94 #define MII_CFG_CLK_DIV_20 6 95 #define MII_CFG_CLK_DIV_28 7 96 #define MII_CFG_CLK_DIV_34 8 97 #define MII_CFG_CLK_DIV_42 9 98 #define MII_CFG_CLK_DIV_50 10 99 #define MII_CFG_CLK_DIV_58 11 100 #define MII_CFG_CLK_DIV_66 12 101 #define MII_CFG_CLK_DIV_74 13 102 #define MII_CFG_CLK_DIV_82 14 103 #define MII_CFG_CLK_DIV_98 15 104 #define MII_CFG_RESET BIT(31) 105 106 #define AG71XX_REG_MII_CMD 0x0024 107 #define MII_CMD_READ BIT(0) 108 109 #define AG71XX_REG_MII_ADDR 0x0028 110 #define MII_ADDR_SHIFT 8 111 112 #define AG71XX_REG_MII_CTRL 0x002c 113 #define AG71XX_REG_MII_STATUS 0x0030 114 #define AG71XX_REG_MII_IND 0x0034 115 #define MII_IND_BUSY BIT(0) 116 #define MII_IND_INVALID BIT(2) 117 118 #define AG71XX_REG_MAC_IFCTL 0x0038 119 #define MAC_IFCTL_SPEED BIT(16) 120 121 #define AG71XX_REG_MAC_ADDR1 0x0040 122 #define AG71XX_REG_MAC_ADDR2 0x0044 123 #define AG71XX_REG_FIFO_CFG0 0x0048 124 #define FIFO_CFG0_WTM BIT(0) /* Watermark Module */ 125 #define FIFO_CFG0_RXS BIT(1) /* Rx System Module */ 126 #define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */ 127 #define FIFO_CFG0_TXS BIT(3) /* Tx System Module */ 128 #define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */ 129 #define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \ 130 | FIFO_CFG0_TXS | FIFO_CFG0_TXF) 131 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT) 132 133 #define FIFO_CFG0_ENABLE_SHIFT 8 134 135 #define AG71XX_REG_FIFO_CFG1 0x004c 136 #define AG71XX_REG_FIFO_CFG2 0x0050 137 #define AG71XX_REG_FIFO_CFG3 0x0054 138 #define AG71XX_REG_FIFO_CFG4 0x0058 139 #define FIFO_CFG4_DE BIT(0) /* Drop Event */ 140 #define FIFO_CFG4_DV BIT(1) /* RX_DV Event */ 141 #define FIFO_CFG4_FC BIT(2) /* False Carrier */ 142 #define FIFO_CFG4_CE BIT(3) /* Code Error */ 143 #define FIFO_CFG4_CR BIT(4) /* CRC error */ 144 #define FIFO_CFG4_LM BIT(5) /* Length Mismatch */ 145 #define FIFO_CFG4_LO BIT(6) /* Length out of range */ 146 #define FIFO_CFG4_OK BIT(7) /* Packet is OK */ 147 #define FIFO_CFG4_MC BIT(8) /* Multicast Packet */ 148 #define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */ 149 #define FIFO_CFG4_DR BIT(10) /* Dribble */ 150 #define FIFO_CFG4_LE BIT(11) /* Long Event */ 151 #define FIFO_CFG4_CF BIT(12) /* Control Frame */ 152 #define FIFO_CFG4_PF BIT(13) /* Pause Frame */ 153 #define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */ 154 #define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */ 155 #define FIFO_CFG4_FT BIT(16) /* Frame Truncated */ 156 #define FIFO_CFG4_UC BIT(17) /* Unicast Packet */ 157 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \ 158 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \ 159 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \ 160 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \ 161 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \ 162 FIFO_CFG4_VT) 163 164 #define AG71XX_REG_FIFO_CFG5 0x005c 165 #define FIFO_CFG5_DE BIT(0) /* Drop Event */ 166 #define FIFO_CFG5_DV BIT(1) /* RX_DV Event */ 167 #define FIFO_CFG5_FC BIT(2) /* False Carrier */ 168 #define FIFO_CFG5_CE BIT(3) /* Code Error */ 169 #define FIFO_CFG5_LM BIT(4) /* Length Mismatch */ 170 #define FIFO_CFG5_LO BIT(5) /* Length Out of Range */ 171 #define FIFO_CFG5_OK BIT(6) /* Packet is OK */ 172 #define FIFO_CFG5_MC BIT(7) /* Multicast Packet */ 173 #define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */ 174 #define FIFO_CFG5_DR BIT(9) /* Dribble */ 175 #define FIFO_CFG5_CF BIT(10) /* Control Frame */ 176 #define FIFO_CFG5_PF BIT(11) /* Pause Frame */ 177 #define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */ 178 #define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */ 179 #define FIFO_CFG5_LE BIT(14) /* Long Event */ 180 #define FIFO_CFG5_FT BIT(15) /* Frame Truncated */ 181 #define FIFO_CFG5_16 BIT(16) /* unknown */ 182 #define FIFO_CFG5_17 BIT(17) /* unknown */ 183 #define FIFO_CFG5_SF BIT(18) /* Short Frame */ 184 #define FIFO_CFG5_BM BIT(19) /* Byte Mode */ 185 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \ 186 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \ 187 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \ 188 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \ 189 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \ 190 FIFO_CFG5_17 | FIFO_CFG5_SF) 191 192 #define AG71XX_REG_TX_CTRL 0x0180 193 #define TX_CTRL_TXE BIT(0) /* Tx Enable */ 194 195 #define AG71XX_REG_TX_DESC 0x0184 196 #define AG71XX_REG_TX_STATUS 0x0188 197 #define TX_STATUS_PS BIT(0) /* Packet Sent */ 198 #define TX_STATUS_UR BIT(1) /* Tx Underrun */ 199 #define TX_STATUS_BE BIT(3) /* Bus Error */ 200 201 #define AG71XX_REG_RX_CTRL 0x018c 202 #define RX_CTRL_RXE BIT(0) /* Rx Enable */ 203 204 #define AG71XX_DMA_RETRY 10 205 #define AG71XX_DMA_DELAY 1 206 207 #define AG71XX_REG_RX_DESC 0x0190 208 #define AG71XX_REG_RX_STATUS 0x0194 209 #define RX_STATUS_PR BIT(0) /* Packet Received */ 210 #define RX_STATUS_OF BIT(2) /* Rx Overflow */ 211 #define RX_STATUS_BE BIT(3) /* Bus Error */ 212 213 #define AG71XX_REG_INT_ENABLE 0x0198 214 #define AG71XX_REG_INT_STATUS 0x019c 215 #define AG71XX_INT_TX_PS BIT(0) 216 #define AG71XX_INT_TX_UR BIT(1) 217 #define AG71XX_INT_TX_BE BIT(3) 218 #define AG71XX_INT_RX_PR BIT(4) 219 #define AG71XX_INT_RX_OF BIT(6) 220 #define AG71XX_INT_RX_BE BIT(7) 221 222 #define AG71XX_REG_FIFO_DEPTH 0x01a8 223 #define AG71XX_REG_RX_SM 0x01b0 224 #define AG71XX_REG_TX_SM 0x01b4 225 226 #define ETH_SWITCH_HEADER_LEN 2 227 228 #define AG71XX_DEFAULT_MSG_ENABLE \ 229 (NETIF_MSG_DRV \ 230 | NETIF_MSG_PROBE \ 231 | NETIF_MSG_LINK \ 232 | NETIF_MSG_TIMER \ 233 | NETIF_MSG_IFDOWN \ 234 | NETIF_MSG_IFUP \ 235 | NETIF_MSG_RX_ERR \ 236 | NETIF_MSG_TX_ERR) 237 238 #define DESC_EMPTY BIT(31) 239 #define DESC_MORE BIT(24) 240 #define DESC_PKTLEN_M 0xfff 241 struct ag71xx_desc { 242 u32 data; 243 u32 ctrl; 244 u32 next; 245 u32 pad; 246 } __aligned(4); 247 248 #define AG71XX_DESC_SIZE roundup(sizeof(struct ag71xx_desc), \ 249 L1_CACHE_BYTES) 250 251 struct ag71xx_buf { 252 union { 253 struct { 254 struct sk_buff *skb; 255 unsigned int len; 256 } tx; 257 struct { 258 dma_addr_t dma_addr; 259 void *rx_buf; 260 } rx; 261 }; 262 }; 263 264 struct ag71xx_ring { 265 /* "Hot" fields in the data path. */ 266 unsigned int curr; 267 unsigned int dirty; 268 269 /* "Cold" fields - not used in the data path. */ 270 struct ag71xx_buf *buf; 271 u16 order; 272 u16 desc_split; 273 dma_addr_t descs_dma; 274 u8 *descs_cpu; 275 }; 276 277 enum ag71xx_type { 278 AR7100, 279 AR7240, 280 AR9130, 281 AR9330, 282 AR9340, 283 QCA9530, 284 QCA9550, 285 }; 286 287 struct ag71xx_dcfg { 288 u32 max_frame_len; 289 const u32 *fifodata; 290 u16 desc_pktlen_mask; 291 bool tx_hang_workaround; 292 enum ag71xx_type type; 293 }; 294 295 struct ag71xx { 296 /* Critical data related to the per-packet data path are clustered 297 * early in this structure to help improve the D-cache footprint. 298 */ 299 struct ag71xx_ring rx_ring ____cacheline_aligned; 300 struct ag71xx_ring tx_ring ____cacheline_aligned; 301 302 u16 rx_buf_size; 303 u8 rx_buf_offset; 304 305 struct net_device *ndev; 306 struct platform_device *pdev; 307 struct napi_struct napi; 308 u32 msg_enable; 309 const struct ag71xx_dcfg *dcfg; 310 311 /* From this point onwards we're not looking at per-packet fields. */ 312 void __iomem *mac_base; 313 314 struct ag71xx_desc *stop_desc; 315 dma_addr_t stop_desc_dma; 316 317 phy_interface_t phy_if_mode; 318 struct phylink *phylink; 319 struct phylink_config phylink_config; 320 321 struct delayed_work restart_work; 322 struct timer_list oom_timer; 323 324 struct reset_control *mac_reset; 325 326 u32 fifodata[3]; 327 int mac_idx; 328 329 struct reset_control *mdio_reset; 330 struct mii_bus *mii_bus; 331 struct clk *clk_mdio; 332 struct clk *clk_eth; 333 }; 334 335 static int ag71xx_desc_empty(struct ag71xx_desc *desc) 336 { 337 return (desc->ctrl & DESC_EMPTY) != 0; 338 } 339 340 static struct ag71xx_desc *ag71xx_ring_desc(struct ag71xx_ring *ring, int idx) 341 { 342 return (struct ag71xx_desc *)&ring->descs_cpu[idx * AG71XX_DESC_SIZE]; 343 } 344 345 static int ag71xx_ring_size_order(int size) 346 { 347 return fls(size - 1); 348 } 349 350 static bool ag71xx_is(struct ag71xx *ag, enum ag71xx_type type) 351 { 352 return ag->dcfg->type == type; 353 } 354 355 static void ag71xx_wr(struct ag71xx *ag, unsigned int reg, u32 value) 356 { 357 iowrite32(value, ag->mac_base + reg); 358 /* flush write */ 359 (void)ioread32(ag->mac_base + reg); 360 } 361 362 static u32 ag71xx_rr(struct ag71xx *ag, unsigned int reg) 363 { 364 return ioread32(ag->mac_base + reg); 365 } 366 367 static void ag71xx_sb(struct ag71xx *ag, unsigned int reg, u32 mask) 368 { 369 void __iomem *r; 370 371 r = ag->mac_base + reg; 372 iowrite32(ioread32(r) | mask, r); 373 /* flush write */ 374 (void)ioread32(r); 375 } 376 377 static void ag71xx_cb(struct ag71xx *ag, unsigned int reg, u32 mask) 378 { 379 void __iomem *r; 380 381 r = ag->mac_base + reg; 382 iowrite32(ioread32(r) & ~mask, r); 383 /* flush write */ 384 (void)ioread32(r); 385 } 386 387 static void ag71xx_int_enable(struct ag71xx *ag, u32 ints) 388 { 389 ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints); 390 } 391 392 static void ag71xx_int_disable(struct ag71xx *ag, u32 ints) 393 { 394 ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints); 395 } 396 397 static int ag71xx_mdio_wait_busy(struct ag71xx *ag) 398 { 399 struct net_device *ndev = ag->ndev; 400 int i; 401 402 for (i = 0; i < AG71XX_MDIO_RETRY; i++) { 403 u32 busy; 404 405 udelay(AG71XX_MDIO_DELAY); 406 407 busy = ag71xx_rr(ag, AG71XX_REG_MII_IND); 408 if (!busy) 409 return 0; 410 411 udelay(AG71XX_MDIO_DELAY); 412 } 413 414 netif_err(ag, link, ndev, "MDIO operation timed out\n"); 415 416 return -ETIMEDOUT; 417 } 418 419 static int ag71xx_mdio_mii_read(struct mii_bus *bus, int addr, int reg) 420 { 421 struct ag71xx *ag = bus->priv; 422 int err, val; 423 424 err = ag71xx_mdio_wait_busy(ag); 425 if (err) 426 return err; 427 428 ag71xx_wr(ag, AG71XX_REG_MII_ADDR, 429 ((addr & 0x1f) << MII_ADDR_SHIFT) | (reg & 0xff)); 430 /* enable read mode */ 431 ag71xx_wr(ag, AG71XX_REG_MII_CMD, MII_CMD_READ); 432 433 err = ag71xx_mdio_wait_busy(ag); 434 if (err) 435 return err; 436 437 val = ag71xx_rr(ag, AG71XX_REG_MII_STATUS); 438 /* disable read mode */ 439 ag71xx_wr(ag, AG71XX_REG_MII_CMD, 0); 440 441 netif_dbg(ag, link, ag->ndev, "mii_read: addr=%04x, reg=%04x, value=%04x\n", 442 addr, reg, val); 443 444 return val; 445 } 446 447 static int ag71xx_mdio_mii_write(struct mii_bus *bus, int addr, int reg, 448 u16 val) 449 { 450 struct ag71xx *ag = bus->priv; 451 452 netif_dbg(ag, link, ag->ndev, "mii_write: addr=%04x, reg=%04x, value=%04x\n", 453 addr, reg, val); 454 455 ag71xx_wr(ag, AG71XX_REG_MII_ADDR, 456 ((addr & 0x1f) << MII_ADDR_SHIFT) | (reg & 0xff)); 457 ag71xx_wr(ag, AG71XX_REG_MII_CTRL, val); 458 459 return ag71xx_mdio_wait_busy(ag); 460 } 461 462 static const u32 ar71xx_mdio_div_table[] = { 463 4, 4, 6, 8, 10, 14, 20, 28, 464 }; 465 466 static const u32 ar7240_mdio_div_table[] = { 467 2, 2, 4, 6, 8, 12, 18, 26, 32, 40, 48, 56, 62, 70, 78, 96, 468 }; 469 470 static const u32 ar933x_mdio_div_table[] = { 471 4, 4, 6, 8, 10, 14, 20, 28, 34, 42, 50, 58, 66, 74, 82, 98, 472 }; 473 474 static int ag71xx_mdio_get_divider(struct ag71xx *ag, u32 *div) 475 { 476 unsigned long ref_clock; 477 const u32 *table; 478 int ndivs, i; 479 480 ref_clock = clk_get_rate(ag->clk_mdio); 481 if (!ref_clock) 482 return -EINVAL; 483 484 if (ag71xx_is(ag, AR9330) || ag71xx_is(ag, AR9340)) { 485 table = ar933x_mdio_div_table; 486 ndivs = ARRAY_SIZE(ar933x_mdio_div_table); 487 } else if (ag71xx_is(ag, AR7240)) { 488 table = ar7240_mdio_div_table; 489 ndivs = ARRAY_SIZE(ar7240_mdio_div_table); 490 } else { 491 table = ar71xx_mdio_div_table; 492 ndivs = ARRAY_SIZE(ar71xx_mdio_div_table); 493 } 494 495 for (i = 0; i < ndivs; i++) { 496 unsigned long t; 497 498 t = ref_clock / table[i]; 499 if (t <= AG71XX_MDIO_MAX_CLK) { 500 *div = i; 501 return 0; 502 } 503 } 504 505 return -ENOENT; 506 } 507 508 static int ag71xx_mdio_reset(struct mii_bus *bus) 509 { 510 struct ag71xx *ag = bus->priv; 511 int err; 512 u32 t; 513 514 err = ag71xx_mdio_get_divider(ag, &t); 515 if (err) 516 return err; 517 518 ag71xx_wr(ag, AG71XX_REG_MII_CFG, t | MII_CFG_RESET); 519 usleep_range(100, 200); 520 521 ag71xx_wr(ag, AG71XX_REG_MII_CFG, t); 522 usleep_range(100, 200); 523 524 return 0; 525 } 526 527 static int ag71xx_mdio_probe(struct ag71xx *ag) 528 { 529 struct device *dev = &ag->pdev->dev; 530 struct net_device *ndev = ag->ndev; 531 static struct mii_bus *mii_bus; 532 struct device_node *np, *mnp; 533 int err; 534 535 np = dev->of_node; 536 ag->mii_bus = NULL; 537 538 ag->clk_mdio = devm_clk_get(dev, "mdio"); 539 if (IS_ERR(ag->clk_mdio)) { 540 netif_err(ag, probe, ndev, "Failed to get mdio clk.\n"); 541 return PTR_ERR(ag->clk_mdio); 542 } 543 544 err = clk_prepare_enable(ag->clk_mdio); 545 if (err) { 546 netif_err(ag, probe, ndev, "Failed to enable mdio clk.\n"); 547 return err; 548 } 549 550 mii_bus = devm_mdiobus_alloc(dev); 551 if (!mii_bus) { 552 err = -ENOMEM; 553 goto mdio_err_put_clk; 554 } 555 556 ag->mdio_reset = of_reset_control_get_exclusive(np, "mdio"); 557 if (IS_ERR(ag->mdio_reset)) { 558 netif_err(ag, probe, ndev, "Failed to get reset mdio.\n"); 559 return PTR_ERR(ag->mdio_reset); 560 } 561 562 mii_bus->name = "ag71xx_mdio"; 563 mii_bus->read = ag71xx_mdio_mii_read; 564 mii_bus->write = ag71xx_mdio_mii_write; 565 mii_bus->reset = ag71xx_mdio_reset; 566 mii_bus->priv = ag; 567 mii_bus->parent = dev; 568 snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%s.%d", np->name, ag->mac_idx); 569 570 if (!IS_ERR(ag->mdio_reset)) { 571 reset_control_assert(ag->mdio_reset); 572 msleep(100); 573 reset_control_deassert(ag->mdio_reset); 574 msleep(200); 575 } 576 577 mnp = of_get_child_by_name(np, "mdio"); 578 err = of_mdiobus_register(mii_bus, mnp); 579 of_node_put(mnp); 580 if (err) 581 goto mdio_err_put_clk; 582 583 ag->mii_bus = mii_bus; 584 585 return 0; 586 587 mdio_err_put_clk: 588 clk_disable_unprepare(ag->clk_mdio); 589 return err; 590 } 591 592 static void ag71xx_mdio_remove(struct ag71xx *ag) 593 { 594 if (ag->mii_bus) 595 mdiobus_unregister(ag->mii_bus); 596 clk_disable_unprepare(ag->clk_mdio); 597 } 598 599 static void ag71xx_hw_stop(struct ag71xx *ag) 600 { 601 /* disable all interrupts and stop the rx/tx engine */ 602 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0); 603 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0); 604 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0); 605 } 606 607 static bool ag71xx_check_dma_stuck(struct ag71xx *ag) 608 { 609 unsigned long timestamp; 610 u32 rx_sm, tx_sm, rx_fd; 611 612 timestamp = netdev_get_tx_queue(ag->ndev, 0)->trans_start; 613 if (likely(time_before(jiffies, timestamp + HZ / 10))) 614 return false; 615 616 if (!netif_carrier_ok(ag->ndev)) 617 return false; 618 619 rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM); 620 if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6) 621 return true; 622 623 tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM); 624 rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH); 625 if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) && 626 ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0) 627 return true; 628 629 return false; 630 } 631 632 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush) 633 { 634 struct ag71xx_ring *ring = &ag->tx_ring; 635 int sent = 0, bytes_compl = 0, n = 0; 636 struct net_device *ndev = ag->ndev; 637 int ring_mask, ring_size; 638 bool dma_stuck = false; 639 640 ring_mask = BIT(ring->order) - 1; 641 ring_size = BIT(ring->order); 642 643 netif_dbg(ag, tx_queued, ndev, "processing TX ring\n"); 644 645 while (ring->dirty + n != ring->curr) { 646 struct ag71xx_desc *desc; 647 struct sk_buff *skb; 648 unsigned int i; 649 650 i = (ring->dirty + n) & ring_mask; 651 desc = ag71xx_ring_desc(ring, i); 652 skb = ring->buf[i].tx.skb; 653 654 if (!flush && !ag71xx_desc_empty(desc)) { 655 if (ag->dcfg->tx_hang_workaround && 656 ag71xx_check_dma_stuck(ag)) { 657 schedule_delayed_work(&ag->restart_work, 658 HZ / 2); 659 dma_stuck = true; 660 } 661 break; 662 } 663 664 if (flush) 665 desc->ctrl |= DESC_EMPTY; 666 667 n++; 668 if (!skb) 669 continue; 670 671 dev_kfree_skb_any(skb); 672 ring->buf[i].tx.skb = NULL; 673 674 bytes_compl += ring->buf[i].tx.len; 675 676 sent++; 677 ring->dirty += n; 678 679 while (n > 0) { 680 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS); 681 n--; 682 } 683 } 684 685 netif_dbg(ag, tx_done, ndev, "%d packets sent out\n", sent); 686 687 if (!sent) 688 return 0; 689 690 ag->ndev->stats.tx_bytes += bytes_compl; 691 ag->ndev->stats.tx_packets += sent; 692 693 netdev_completed_queue(ag->ndev, sent, bytes_compl); 694 if ((ring->curr - ring->dirty) < (ring_size * 3) / 4) 695 netif_wake_queue(ag->ndev); 696 697 if (!dma_stuck) 698 cancel_delayed_work(&ag->restart_work); 699 700 return sent; 701 } 702 703 static void ag71xx_dma_wait_stop(struct ag71xx *ag) 704 { 705 struct net_device *ndev = ag->ndev; 706 int i; 707 708 for (i = 0; i < AG71XX_DMA_RETRY; i++) { 709 u32 rx, tx; 710 711 mdelay(AG71XX_DMA_DELAY); 712 713 rx = ag71xx_rr(ag, AG71XX_REG_RX_CTRL) & RX_CTRL_RXE; 714 tx = ag71xx_rr(ag, AG71XX_REG_TX_CTRL) & TX_CTRL_TXE; 715 if (!rx && !tx) 716 return; 717 } 718 719 netif_err(ag, hw, ndev, "DMA stop operation timed out\n"); 720 } 721 722 static void ag71xx_dma_reset(struct ag71xx *ag) 723 { 724 struct net_device *ndev = ag->ndev; 725 u32 val; 726 int i; 727 728 /* stop RX and TX */ 729 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0); 730 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0); 731 732 /* give the hardware some time to really stop all rx/tx activity 733 * clearing the descriptors too early causes random memory corruption 734 */ 735 ag71xx_dma_wait_stop(ag); 736 737 /* clear descriptor addresses */ 738 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma); 739 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma); 740 741 /* clear pending RX/TX interrupts */ 742 for (i = 0; i < 256; i++) { 743 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR); 744 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS); 745 } 746 747 /* clear pending errors */ 748 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF); 749 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR); 750 751 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS); 752 if (val) 753 netif_err(ag, hw, ndev, "unable to clear DMA Rx status: %08x\n", 754 val); 755 756 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS); 757 758 /* mask out reserved bits */ 759 val &= ~0xff000000; 760 761 if (val) 762 netif_err(ag, hw, ndev, "unable to clear DMA Tx status: %08x\n", 763 val); 764 } 765 766 static void ag71xx_hw_setup(struct ag71xx *ag) 767 { 768 u32 init = MAC_CFG1_INIT; 769 770 /* setup MAC configuration registers */ 771 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, init); 772 773 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2, 774 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK); 775 776 /* setup max frame length to zero */ 777 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0); 778 779 /* setup FIFO configuration registers */ 780 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT); 781 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, ag->fifodata[0]); 782 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, ag->fifodata[1]); 783 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT); 784 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT); 785 } 786 787 static unsigned int ag71xx_max_frame_len(unsigned int mtu) 788 { 789 return ETH_SWITCH_HEADER_LEN + ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN; 790 } 791 792 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac) 793 { 794 u32 t; 795 796 t = (((u32)mac[5]) << 24) | (((u32)mac[4]) << 16) 797 | (((u32)mac[3]) << 8) | ((u32)mac[2]); 798 799 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t); 800 801 t = (((u32)mac[1]) << 24) | (((u32)mac[0]) << 16); 802 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t); 803 } 804 805 static void ag71xx_fast_reset(struct ag71xx *ag) 806 { 807 struct net_device *dev = ag->ndev; 808 u32 rx_ds; 809 u32 mii_reg; 810 811 ag71xx_hw_stop(ag); 812 813 mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG); 814 rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC); 815 816 ag71xx_tx_packets(ag, true); 817 818 reset_control_assert(ag->mac_reset); 819 usleep_range(10, 20); 820 reset_control_deassert(ag->mac_reset); 821 usleep_range(10, 20); 822 823 ag71xx_dma_reset(ag); 824 ag71xx_hw_setup(ag); 825 ag->tx_ring.curr = 0; 826 ag->tx_ring.dirty = 0; 827 netdev_reset_queue(ag->ndev); 828 829 /* setup max frame length */ 830 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 831 ag71xx_max_frame_len(ag->ndev->mtu)); 832 833 ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds); 834 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma); 835 ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg); 836 837 ag71xx_hw_set_macaddr(ag, dev->dev_addr); 838 } 839 840 static void ag71xx_hw_start(struct ag71xx *ag) 841 { 842 /* start RX engine */ 843 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE); 844 845 /* enable interrupts */ 846 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT); 847 848 netif_wake_queue(ag->ndev); 849 } 850 851 static void ag71xx_mac_config(struct phylink_config *config, unsigned int mode, 852 const struct phylink_link_state *state) 853 { 854 struct ag71xx *ag = netdev_priv(to_net_dev(config->dev)); 855 856 if (phylink_autoneg_inband(mode)) 857 return; 858 859 if (!ag71xx_is(ag, AR7100) && !ag71xx_is(ag, AR9130)) 860 ag71xx_fast_reset(ag); 861 862 if (ag->tx_ring.desc_split) { 863 ag->fifodata[2] &= 0xffff; 864 ag->fifodata[2] |= ((2048 - ag->tx_ring.desc_split) / 4) << 16; 865 } 866 867 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, ag->fifodata[2]); 868 } 869 870 static void ag71xx_mac_validate(struct phylink_config *config, 871 unsigned long *supported, 872 struct phylink_link_state *state) 873 { 874 struct ag71xx *ag = netdev_priv(to_net_dev(config->dev)); 875 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 876 877 switch (state->interface) { 878 case PHY_INTERFACE_MODE_NA: 879 break; 880 case PHY_INTERFACE_MODE_MII: 881 if ((ag71xx_is(ag, AR9330) && ag->mac_idx == 0) || 882 ag71xx_is(ag, AR9340) || 883 ag71xx_is(ag, QCA9530) || 884 (ag71xx_is(ag, QCA9550) && ag->mac_idx == 1)) 885 break; 886 goto unsupported; 887 case PHY_INTERFACE_MODE_GMII: 888 if ((ag71xx_is(ag, AR9330) && ag->mac_idx == 1) || 889 (ag71xx_is(ag, AR9340) && ag->mac_idx == 1) || 890 (ag71xx_is(ag, QCA9530) && ag->mac_idx == 1)) 891 break; 892 goto unsupported; 893 case PHY_INTERFACE_MODE_SGMII: 894 if (ag71xx_is(ag, QCA9550) && ag->mac_idx == 0) 895 break; 896 goto unsupported; 897 case PHY_INTERFACE_MODE_RMII: 898 if (ag71xx_is(ag, AR9340) && ag->mac_idx == 0) 899 break; 900 goto unsupported; 901 case PHY_INTERFACE_MODE_RGMII: 902 if ((ag71xx_is(ag, AR9340) && ag->mac_idx == 0) || 903 (ag71xx_is(ag, QCA9550) && ag->mac_idx == 1)) 904 break; 905 goto unsupported; 906 default: 907 goto unsupported; 908 } 909 910 phylink_set(mask, MII); 911 912 phylink_set(mask, Autoneg); 913 phylink_set(mask, 10baseT_Half); 914 phylink_set(mask, 10baseT_Full); 915 phylink_set(mask, 100baseT_Half); 916 phylink_set(mask, 100baseT_Full); 917 918 if (state->interface == PHY_INTERFACE_MODE_NA || 919 state->interface == PHY_INTERFACE_MODE_SGMII || 920 state->interface == PHY_INTERFACE_MODE_RGMII || 921 state->interface == PHY_INTERFACE_MODE_GMII) { 922 phylink_set(mask, 1000baseT_Full); 923 phylink_set(mask, 1000baseX_Full); 924 } 925 926 bitmap_and(supported, supported, mask, 927 __ETHTOOL_LINK_MODE_MASK_NBITS); 928 bitmap_and(state->advertising, state->advertising, mask, 929 __ETHTOOL_LINK_MODE_MASK_NBITS); 930 931 return; 932 unsupported: 933 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 934 } 935 936 static void ag71xx_mac_pcs_get_state(struct phylink_config *config, 937 struct phylink_link_state *state) 938 { 939 state->link = 0; 940 } 941 942 static void ag71xx_mac_an_restart(struct phylink_config *config) 943 { 944 /* Not Supported */ 945 } 946 947 static void ag71xx_mac_link_down(struct phylink_config *config, 948 unsigned int mode, phy_interface_t interface) 949 { 950 struct ag71xx *ag = netdev_priv(to_net_dev(config->dev)); 951 952 ag71xx_hw_stop(ag); 953 } 954 955 static void ag71xx_mac_link_up(struct phylink_config *config, 956 struct phy_device *phy, 957 unsigned int mode, phy_interface_t interface, 958 int speed, int duplex, 959 bool tx_pause, bool rx_pause) 960 { 961 struct ag71xx *ag = netdev_priv(to_net_dev(config->dev)); 962 u32 cfg2; 963 u32 ifctl; 964 u32 fifo5; 965 966 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2); 967 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX); 968 cfg2 |= duplex ? MAC_CFG2_FDX : 0; 969 970 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL); 971 ifctl &= ~(MAC_IFCTL_SPEED); 972 973 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5); 974 fifo5 &= ~FIFO_CFG5_BM; 975 976 switch (speed) { 977 case SPEED_1000: 978 cfg2 |= MAC_CFG2_IF_1000; 979 fifo5 |= FIFO_CFG5_BM; 980 break; 981 case SPEED_100: 982 cfg2 |= MAC_CFG2_IF_10_100; 983 ifctl |= MAC_IFCTL_SPEED; 984 break; 985 case SPEED_10: 986 cfg2 |= MAC_CFG2_IF_10_100; 987 break; 988 default: 989 return; 990 } 991 992 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2); 993 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5); 994 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl); 995 996 ag71xx_hw_start(ag); 997 } 998 999 static const struct phylink_mac_ops ag71xx_phylink_mac_ops = { 1000 .validate = ag71xx_mac_validate, 1001 .mac_pcs_get_state = ag71xx_mac_pcs_get_state, 1002 .mac_an_restart = ag71xx_mac_an_restart, 1003 .mac_config = ag71xx_mac_config, 1004 .mac_link_down = ag71xx_mac_link_down, 1005 .mac_link_up = ag71xx_mac_link_up, 1006 }; 1007 1008 static int ag71xx_phylink_setup(struct ag71xx *ag) 1009 { 1010 struct phylink *phylink; 1011 1012 ag->phylink_config.dev = &ag->ndev->dev; 1013 ag->phylink_config.type = PHYLINK_NETDEV; 1014 1015 phylink = phylink_create(&ag->phylink_config, ag->pdev->dev.fwnode, 1016 ag->phy_if_mode, &ag71xx_phylink_mac_ops); 1017 if (IS_ERR(phylink)) 1018 return PTR_ERR(phylink); 1019 1020 ag->phylink = phylink; 1021 return 0; 1022 } 1023 1024 static void ag71xx_ring_tx_clean(struct ag71xx *ag) 1025 { 1026 struct ag71xx_ring *ring = &ag->tx_ring; 1027 int ring_mask = BIT(ring->order) - 1; 1028 u32 bytes_compl = 0, pkts_compl = 0; 1029 struct net_device *ndev = ag->ndev; 1030 1031 while (ring->curr != ring->dirty) { 1032 struct ag71xx_desc *desc; 1033 u32 i = ring->dirty & ring_mask; 1034 1035 desc = ag71xx_ring_desc(ring, i); 1036 if (!ag71xx_desc_empty(desc)) { 1037 desc->ctrl = 0; 1038 ndev->stats.tx_errors++; 1039 } 1040 1041 if (ring->buf[i].tx.skb) { 1042 bytes_compl += ring->buf[i].tx.len; 1043 pkts_compl++; 1044 dev_kfree_skb_any(ring->buf[i].tx.skb); 1045 } 1046 ring->buf[i].tx.skb = NULL; 1047 ring->dirty++; 1048 } 1049 1050 /* flush descriptors */ 1051 wmb(); 1052 1053 netdev_completed_queue(ndev, pkts_compl, bytes_compl); 1054 } 1055 1056 static void ag71xx_ring_tx_init(struct ag71xx *ag) 1057 { 1058 struct ag71xx_ring *ring = &ag->tx_ring; 1059 int ring_size = BIT(ring->order); 1060 int ring_mask = ring_size - 1; 1061 int i; 1062 1063 for (i = 0; i < ring_size; i++) { 1064 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); 1065 1066 desc->next = (u32)(ring->descs_dma + 1067 AG71XX_DESC_SIZE * ((i + 1) & ring_mask)); 1068 1069 desc->ctrl = DESC_EMPTY; 1070 ring->buf[i].tx.skb = NULL; 1071 } 1072 1073 /* flush descriptors */ 1074 wmb(); 1075 1076 ring->curr = 0; 1077 ring->dirty = 0; 1078 netdev_reset_queue(ag->ndev); 1079 } 1080 1081 static void ag71xx_ring_rx_clean(struct ag71xx *ag) 1082 { 1083 struct ag71xx_ring *ring = &ag->rx_ring; 1084 int ring_size = BIT(ring->order); 1085 int i; 1086 1087 if (!ring->buf) 1088 return; 1089 1090 for (i = 0; i < ring_size; i++) 1091 if (ring->buf[i].rx.rx_buf) { 1092 dma_unmap_single(&ag->pdev->dev, 1093 ring->buf[i].rx.dma_addr, 1094 ag->rx_buf_size, DMA_FROM_DEVICE); 1095 skb_free_frag(ring->buf[i].rx.rx_buf); 1096 } 1097 } 1098 1099 static int ag71xx_buffer_size(struct ag71xx *ag) 1100 { 1101 return ag->rx_buf_size + 1102 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 1103 } 1104 1105 static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf, 1106 int offset, 1107 void *(*alloc)(unsigned int size)) 1108 { 1109 struct ag71xx_ring *ring = &ag->rx_ring; 1110 struct ag71xx_desc *desc; 1111 void *data; 1112 1113 desc = ag71xx_ring_desc(ring, buf - &ring->buf[0]); 1114 1115 data = alloc(ag71xx_buffer_size(ag)); 1116 if (!data) 1117 return false; 1118 1119 buf->rx.rx_buf = data; 1120 buf->rx.dma_addr = dma_map_single(&ag->pdev->dev, data, ag->rx_buf_size, 1121 DMA_FROM_DEVICE); 1122 desc->data = (u32)buf->rx.dma_addr + offset; 1123 return true; 1124 } 1125 1126 static int ag71xx_ring_rx_init(struct ag71xx *ag) 1127 { 1128 struct ag71xx_ring *ring = &ag->rx_ring; 1129 struct net_device *ndev = ag->ndev; 1130 int ring_mask = BIT(ring->order) - 1; 1131 int ring_size = BIT(ring->order); 1132 unsigned int i; 1133 int ret; 1134 1135 ret = 0; 1136 for (i = 0; i < ring_size; i++) { 1137 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); 1138 1139 desc->next = (u32)(ring->descs_dma + 1140 AG71XX_DESC_SIZE * ((i + 1) & ring_mask)); 1141 1142 netif_dbg(ag, rx_status, ndev, "RX desc at %p, next is %08x\n", 1143 desc, desc->next); 1144 } 1145 1146 for (i = 0; i < ring_size; i++) { 1147 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); 1148 1149 if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], ag->rx_buf_offset, 1150 netdev_alloc_frag)) { 1151 ret = -ENOMEM; 1152 break; 1153 } 1154 1155 desc->ctrl = DESC_EMPTY; 1156 } 1157 1158 /* flush descriptors */ 1159 wmb(); 1160 1161 ring->curr = 0; 1162 ring->dirty = 0; 1163 1164 return ret; 1165 } 1166 1167 static int ag71xx_ring_rx_refill(struct ag71xx *ag) 1168 { 1169 struct ag71xx_ring *ring = &ag->rx_ring; 1170 int ring_mask = BIT(ring->order) - 1; 1171 int offset = ag->rx_buf_offset; 1172 unsigned int count; 1173 1174 count = 0; 1175 for (; ring->curr - ring->dirty > 0; ring->dirty++) { 1176 struct ag71xx_desc *desc; 1177 unsigned int i; 1178 1179 i = ring->dirty & ring_mask; 1180 desc = ag71xx_ring_desc(ring, i); 1181 1182 if (!ring->buf[i].rx.rx_buf && 1183 !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset, 1184 napi_alloc_frag)) 1185 break; 1186 1187 desc->ctrl = DESC_EMPTY; 1188 count++; 1189 } 1190 1191 /* flush descriptors */ 1192 wmb(); 1193 1194 netif_dbg(ag, rx_status, ag->ndev, "%u rx descriptors refilled\n", 1195 count); 1196 1197 return count; 1198 } 1199 1200 static int ag71xx_rings_init(struct ag71xx *ag) 1201 { 1202 struct ag71xx_ring *tx = &ag->tx_ring; 1203 struct ag71xx_ring *rx = &ag->rx_ring; 1204 int ring_size, tx_size; 1205 1206 ring_size = BIT(tx->order) + BIT(rx->order); 1207 tx_size = BIT(tx->order); 1208 1209 tx->buf = kcalloc(ring_size, sizeof(*tx->buf), GFP_KERNEL); 1210 if (!tx->buf) 1211 return -ENOMEM; 1212 1213 tx->descs_cpu = dma_alloc_coherent(&ag->pdev->dev, 1214 ring_size * AG71XX_DESC_SIZE, 1215 &tx->descs_dma, GFP_KERNEL); 1216 if (!tx->descs_cpu) { 1217 kfree(tx->buf); 1218 tx->buf = NULL; 1219 return -ENOMEM; 1220 } 1221 1222 rx->buf = &tx->buf[tx_size]; 1223 rx->descs_cpu = ((void *)tx->descs_cpu) + tx_size * AG71XX_DESC_SIZE; 1224 rx->descs_dma = tx->descs_dma + tx_size * AG71XX_DESC_SIZE; 1225 1226 ag71xx_ring_tx_init(ag); 1227 return ag71xx_ring_rx_init(ag); 1228 } 1229 1230 static void ag71xx_rings_free(struct ag71xx *ag) 1231 { 1232 struct ag71xx_ring *tx = &ag->tx_ring; 1233 struct ag71xx_ring *rx = &ag->rx_ring; 1234 int ring_size; 1235 1236 ring_size = BIT(tx->order) + BIT(rx->order); 1237 1238 if (tx->descs_cpu) 1239 dma_free_coherent(&ag->pdev->dev, ring_size * AG71XX_DESC_SIZE, 1240 tx->descs_cpu, tx->descs_dma); 1241 1242 kfree(tx->buf); 1243 1244 tx->descs_cpu = NULL; 1245 rx->descs_cpu = NULL; 1246 tx->buf = NULL; 1247 rx->buf = NULL; 1248 } 1249 1250 static void ag71xx_rings_cleanup(struct ag71xx *ag) 1251 { 1252 ag71xx_ring_rx_clean(ag); 1253 ag71xx_ring_tx_clean(ag); 1254 ag71xx_rings_free(ag); 1255 1256 netdev_reset_queue(ag->ndev); 1257 } 1258 1259 static void ag71xx_hw_init(struct ag71xx *ag) 1260 { 1261 ag71xx_hw_stop(ag); 1262 1263 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR); 1264 usleep_range(20, 30); 1265 1266 reset_control_assert(ag->mac_reset); 1267 msleep(100); 1268 reset_control_deassert(ag->mac_reset); 1269 msleep(200); 1270 1271 ag71xx_hw_setup(ag); 1272 1273 ag71xx_dma_reset(ag); 1274 } 1275 1276 static int ag71xx_hw_enable(struct ag71xx *ag) 1277 { 1278 int ret; 1279 1280 ret = ag71xx_rings_init(ag); 1281 if (ret) 1282 return ret; 1283 1284 napi_enable(&ag->napi); 1285 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma); 1286 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma); 1287 netif_start_queue(ag->ndev); 1288 1289 return 0; 1290 } 1291 1292 static void ag71xx_hw_disable(struct ag71xx *ag) 1293 { 1294 netif_stop_queue(ag->ndev); 1295 1296 ag71xx_hw_stop(ag); 1297 ag71xx_dma_reset(ag); 1298 1299 napi_disable(&ag->napi); 1300 del_timer_sync(&ag->oom_timer); 1301 1302 ag71xx_rings_cleanup(ag); 1303 } 1304 1305 static int ag71xx_open(struct net_device *ndev) 1306 { 1307 struct ag71xx *ag = netdev_priv(ndev); 1308 unsigned int max_frame_len; 1309 int ret; 1310 1311 ret = phylink_of_phy_connect(ag->phylink, ag->pdev->dev.of_node, 0); 1312 if (ret) { 1313 netif_err(ag, link, ndev, "phylink_of_phy_connect filed with err: %i\n", 1314 ret); 1315 goto err; 1316 } 1317 1318 max_frame_len = ag71xx_max_frame_len(ndev->mtu); 1319 ag->rx_buf_size = 1320 SKB_DATA_ALIGN(max_frame_len + NET_SKB_PAD + NET_IP_ALIGN); 1321 1322 /* setup max frame length */ 1323 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len); 1324 ag71xx_hw_set_macaddr(ag, ndev->dev_addr); 1325 1326 ret = ag71xx_hw_enable(ag); 1327 if (ret) 1328 goto err; 1329 1330 phylink_start(ag->phylink); 1331 1332 return 0; 1333 1334 err: 1335 ag71xx_rings_cleanup(ag); 1336 return ret; 1337 } 1338 1339 static int ag71xx_stop(struct net_device *ndev) 1340 { 1341 struct ag71xx *ag = netdev_priv(ndev); 1342 1343 phylink_stop(ag->phylink); 1344 phylink_disconnect_phy(ag->phylink); 1345 ag71xx_hw_disable(ag); 1346 1347 return 0; 1348 } 1349 1350 static int ag71xx_fill_dma_desc(struct ag71xx_ring *ring, u32 addr, int len) 1351 { 1352 int i, ring_mask, ndesc, split; 1353 struct ag71xx_desc *desc; 1354 1355 ring_mask = BIT(ring->order) - 1; 1356 ndesc = 0; 1357 split = ring->desc_split; 1358 1359 if (!split) 1360 split = len; 1361 1362 while (len > 0) { 1363 unsigned int cur_len = len; 1364 1365 i = (ring->curr + ndesc) & ring_mask; 1366 desc = ag71xx_ring_desc(ring, i); 1367 1368 if (!ag71xx_desc_empty(desc)) 1369 return -1; 1370 1371 if (cur_len > split) { 1372 cur_len = split; 1373 1374 /* TX will hang if DMA transfers <= 4 bytes, 1375 * make sure next segment is more than 4 bytes long. 1376 */ 1377 if (len <= split + 4) 1378 cur_len -= 4; 1379 } 1380 1381 desc->data = addr; 1382 addr += cur_len; 1383 len -= cur_len; 1384 1385 if (len > 0) 1386 cur_len |= DESC_MORE; 1387 1388 /* prevent early tx attempt of this descriptor */ 1389 if (!ndesc) 1390 cur_len |= DESC_EMPTY; 1391 1392 desc->ctrl = cur_len; 1393 ndesc++; 1394 } 1395 1396 return ndesc; 1397 } 1398 1399 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb, 1400 struct net_device *ndev) 1401 { 1402 int i, n, ring_min, ring_mask, ring_size; 1403 struct ag71xx *ag = netdev_priv(ndev); 1404 struct ag71xx_ring *ring; 1405 struct ag71xx_desc *desc; 1406 dma_addr_t dma_addr; 1407 1408 ring = &ag->tx_ring; 1409 ring_mask = BIT(ring->order) - 1; 1410 ring_size = BIT(ring->order); 1411 1412 if (skb->len <= 4) { 1413 netif_dbg(ag, tx_err, ndev, "packet len is too small\n"); 1414 goto err_drop; 1415 } 1416 1417 dma_addr = dma_map_single(&ag->pdev->dev, skb->data, skb->len, 1418 DMA_TO_DEVICE); 1419 1420 i = ring->curr & ring_mask; 1421 desc = ag71xx_ring_desc(ring, i); 1422 1423 /* setup descriptor fields */ 1424 n = ag71xx_fill_dma_desc(ring, (u32)dma_addr, 1425 skb->len & ag->dcfg->desc_pktlen_mask); 1426 if (n < 0) 1427 goto err_drop_unmap; 1428 1429 i = (ring->curr + n - 1) & ring_mask; 1430 ring->buf[i].tx.len = skb->len; 1431 ring->buf[i].tx.skb = skb; 1432 1433 netdev_sent_queue(ndev, skb->len); 1434 1435 skb_tx_timestamp(skb); 1436 1437 desc->ctrl &= ~DESC_EMPTY; 1438 ring->curr += n; 1439 1440 /* flush descriptor */ 1441 wmb(); 1442 1443 ring_min = 2; 1444 if (ring->desc_split) 1445 ring_min *= AG71XX_TX_RING_DS_PER_PKT; 1446 1447 if (ring->curr - ring->dirty >= ring_size - ring_min) { 1448 netif_dbg(ag, tx_err, ndev, "tx queue full\n"); 1449 netif_stop_queue(ndev); 1450 } 1451 1452 netif_dbg(ag, tx_queued, ndev, "packet injected into TX queue\n"); 1453 1454 /* enable TX engine */ 1455 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE); 1456 1457 return NETDEV_TX_OK; 1458 1459 err_drop_unmap: 1460 dma_unmap_single(&ag->pdev->dev, dma_addr, skb->len, DMA_TO_DEVICE); 1461 1462 err_drop: 1463 ndev->stats.tx_dropped++; 1464 1465 dev_kfree_skb(skb); 1466 return NETDEV_TX_OK; 1467 } 1468 1469 static void ag71xx_oom_timer_handler(struct timer_list *t) 1470 { 1471 struct ag71xx *ag = from_timer(ag, t, oom_timer); 1472 1473 napi_schedule(&ag->napi); 1474 } 1475 1476 static void ag71xx_tx_timeout(struct net_device *ndev, unsigned int txqueue) 1477 { 1478 struct ag71xx *ag = netdev_priv(ndev); 1479 1480 netif_err(ag, tx_err, ndev, "tx timeout\n"); 1481 1482 schedule_delayed_work(&ag->restart_work, 1); 1483 } 1484 1485 static void ag71xx_restart_work_func(struct work_struct *work) 1486 { 1487 struct ag71xx *ag = container_of(work, struct ag71xx, 1488 restart_work.work); 1489 1490 rtnl_lock(); 1491 ag71xx_hw_disable(ag); 1492 ag71xx_hw_enable(ag); 1493 1494 phylink_stop(ag->phylink); 1495 phylink_start(ag->phylink); 1496 1497 rtnl_unlock(); 1498 } 1499 1500 static int ag71xx_rx_packets(struct ag71xx *ag, int limit) 1501 { 1502 struct net_device *ndev = ag->ndev; 1503 int ring_mask, ring_size, done = 0; 1504 unsigned int pktlen_mask, offset; 1505 struct sk_buff *next, *skb; 1506 struct ag71xx_ring *ring; 1507 struct list_head rx_list; 1508 1509 ring = &ag->rx_ring; 1510 pktlen_mask = ag->dcfg->desc_pktlen_mask; 1511 offset = ag->rx_buf_offset; 1512 ring_mask = BIT(ring->order) - 1; 1513 ring_size = BIT(ring->order); 1514 1515 netif_dbg(ag, rx_status, ndev, "rx packets, limit=%d, curr=%u, dirty=%u\n", 1516 limit, ring->curr, ring->dirty); 1517 1518 INIT_LIST_HEAD(&rx_list); 1519 1520 while (done < limit) { 1521 unsigned int i = ring->curr & ring_mask; 1522 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); 1523 int pktlen; 1524 int err = 0; 1525 1526 if (ag71xx_desc_empty(desc)) 1527 break; 1528 1529 if ((ring->dirty + ring_size) == ring->curr) { 1530 WARN_ONCE(1, "RX out of ring"); 1531 break; 1532 } 1533 1534 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR); 1535 1536 pktlen = desc->ctrl & pktlen_mask; 1537 pktlen -= ETH_FCS_LEN; 1538 1539 dma_unmap_single(&ag->pdev->dev, ring->buf[i].rx.dma_addr, 1540 ag->rx_buf_size, DMA_FROM_DEVICE); 1541 1542 ndev->stats.rx_packets++; 1543 ndev->stats.rx_bytes += pktlen; 1544 1545 skb = build_skb(ring->buf[i].rx.rx_buf, ag71xx_buffer_size(ag)); 1546 if (!skb) { 1547 skb_free_frag(ring->buf[i].rx.rx_buf); 1548 goto next; 1549 } 1550 1551 skb_reserve(skb, offset); 1552 skb_put(skb, pktlen); 1553 1554 if (err) { 1555 ndev->stats.rx_dropped++; 1556 kfree_skb(skb); 1557 } else { 1558 skb->dev = ndev; 1559 skb->ip_summed = CHECKSUM_NONE; 1560 list_add_tail(&skb->list, &rx_list); 1561 } 1562 1563 next: 1564 ring->buf[i].rx.rx_buf = NULL; 1565 done++; 1566 1567 ring->curr++; 1568 } 1569 1570 ag71xx_ring_rx_refill(ag); 1571 1572 list_for_each_entry_safe(skb, next, &rx_list, list) 1573 skb->protocol = eth_type_trans(skb, ndev); 1574 netif_receive_skb_list(&rx_list); 1575 1576 netif_dbg(ag, rx_status, ndev, "rx finish, curr=%u, dirty=%u, done=%d\n", 1577 ring->curr, ring->dirty, done); 1578 1579 return done; 1580 } 1581 1582 static int ag71xx_poll(struct napi_struct *napi, int limit) 1583 { 1584 struct ag71xx *ag = container_of(napi, struct ag71xx, napi); 1585 struct ag71xx_ring *rx_ring = &ag->rx_ring; 1586 int rx_ring_size = BIT(rx_ring->order); 1587 struct net_device *ndev = ag->ndev; 1588 int tx_done, rx_done; 1589 u32 status; 1590 1591 tx_done = ag71xx_tx_packets(ag, false); 1592 1593 netif_dbg(ag, rx_status, ndev, "processing RX ring\n"); 1594 rx_done = ag71xx_rx_packets(ag, limit); 1595 1596 if (!rx_ring->buf[rx_ring->dirty % rx_ring_size].rx.rx_buf) 1597 goto oom; 1598 1599 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS); 1600 if (unlikely(status & RX_STATUS_OF)) { 1601 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF); 1602 ndev->stats.rx_fifo_errors++; 1603 1604 /* restart RX */ 1605 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE); 1606 } 1607 1608 if (rx_done < limit) { 1609 if (status & RX_STATUS_PR) 1610 goto more; 1611 1612 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS); 1613 if (status & TX_STATUS_PS) 1614 goto more; 1615 1616 netif_dbg(ag, rx_status, ndev, "disable polling mode, rx=%d, tx=%d,limit=%d\n", 1617 rx_done, tx_done, limit); 1618 1619 napi_complete(napi); 1620 1621 /* enable interrupts */ 1622 ag71xx_int_enable(ag, AG71XX_INT_POLL); 1623 return rx_done; 1624 } 1625 1626 more: 1627 netif_dbg(ag, rx_status, ndev, "stay in polling mode, rx=%d, tx=%d, limit=%d\n", 1628 rx_done, tx_done, limit); 1629 return limit; 1630 1631 oom: 1632 netif_err(ag, rx_err, ndev, "out of memory\n"); 1633 1634 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL); 1635 napi_complete(napi); 1636 return 0; 1637 } 1638 1639 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id) 1640 { 1641 struct net_device *ndev = dev_id; 1642 struct ag71xx *ag; 1643 u32 status; 1644 1645 ag = netdev_priv(ndev); 1646 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS); 1647 1648 if (unlikely(!status)) 1649 return IRQ_NONE; 1650 1651 if (unlikely(status & AG71XX_INT_ERR)) { 1652 if (status & AG71XX_INT_TX_BE) { 1653 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE); 1654 netif_err(ag, intr, ndev, "TX BUS error\n"); 1655 } 1656 if (status & AG71XX_INT_RX_BE) { 1657 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE); 1658 netif_err(ag, intr, ndev, "RX BUS error\n"); 1659 } 1660 } 1661 1662 if (likely(status & AG71XX_INT_POLL)) { 1663 ag71xx_int_disable(ag, AG71XX_INT_POLL); 1664 netif_dbg(ag, intr, ndev, "enable polling mode\n"); 1665 napi_schedule(&ag->napi); 1666 } 1667 1668 return IRQ_HANDLED; 1669 } 1670 1671 static int ag71xx_change_mtu(struct net_device *ndev, int new_mtu) 1672 { 1673 struct ag71xx *ag = netdev_priv(ndev); 1674 1675 ndev->mtu = new_mtu; 1676 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 1677 ag71xx_max_frame_len(ndev->mtu)); 1678 1679 return 0; 1680 } 1681 1682 static const struct net_device_ops ag71xx_netdev_ops = { 1683 .ndo_open = ag71xx_open, 1684 .ndo_stop = ag71xx_stop, 1685 .ndo_start_xmit = ag71xx_hard_start_xmit, 1686 .ndo_do_ioctl = phy_do_ioctl, 1687 .ndo_tx_timeout = ag71xx_tx_timeout, 1688 .ndo_change_mtu = ag71xx_change_mtu, 1689 .ndo_set_mac_address = eth_mac_addr, 1690 .ndo_validate_addr = eth_validate_addr, 1691 }; 1692 1693 static const u32 ar71xx_addr_ar7100[] = { 1694 0x19000000, 0x1a000000, 1695 }; 1696 1697 static int ag71xx_probe(struct platform_device *pdev) 1698 { 1699 struct device_node *np = pdev->dev.of_node; 1700 const struct ag71xx_dcfg *dcfg; 1701 struct net_device *ndev; 1702 struct resource *res; 1703 const void *mac_addr; 1704 int tx_size, err, i; 1705 struct ag71xx *ag; 1706 1707 if (!np) 1708 return -ENODEV; 1709 1710 ndev = devm_alloc_etherdev(&pdev->dev, sizeof(*ag)); 1711 if (!ndev) 1712 return -ENOMEM; 1713 1714 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1715 if (!res) 1716 return -EINVAL; 1717 1718 dcfg = of_device_get_match_data(&pdev->dev); 1719 if (!dcfg) 1720 return -EINVAL; 1721 1722 ag = netdev_priv(ndev); 1723 ag->mac_idx = -1; 1724 for (i = 0; i < ARRAY_SIZE(ar71xx_addr_ar7100); i++) { 1725 if (ar71xx_addr_ar7100[i] == res->start) 1726 ag->mac_idx = i; 1727 } 1728 1729 if (ag->mac_idx < 0) { 1730 netif_err(ag, probe, ndev, "unknown mac idx\n"); 1731 return -EINVAL; 1732 } 1733 1734 ag->clk_eth = devm_clk_get(&pdev->dev, "eth"); 1735 if (IS_ERR(ag->clk_eth)) { 1736 netif_err(ag, probe, ndev, "Failed to get eth clk.\n"); 1737 return PTR_ERR(ag->clk_eth); 1738 } 1739 1740 SET_NETDEV_DEV(ndev, &pdev->dev); 1741 1742 ag->pdev = pdev; 1743 ag->ndev = ndev; 1744 ag->dcfg = dcfg; 1745 ag->msg_enable = netif_msg_init(-1, AG71XX_DEFAULT_MSG_ENABLE); 1746 memcpy(ag->fifodata, dcfg->fifodata, sizeof(ag->fifodata)); 1747 1748 ag->mac_reset = devm_reset_control_get(&pdev->dev, "mac"); 1749 if (IS_ERR(ag->mac_reset)) { 1750 netif_err(ag, probe, ndev, "missing mac reset\n"); 1751 err = PTR_ERR(ag->mac_reset); 1752 goto err_free; 1753 } 1754 1755 ag->mac_base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); 1756 if (!ag->mac_base) { 1757 err = -ENOMEM; 1758 goto err_free; 1759 } 1760 1761 ndev->irq = platform_get_irq(pdev, 0); 1762 err = devm_request_irq(&pdev->dev, ndev->irq, ag71xx_interrupt, 1763 0x0, dev_name(&pdev->dev), ndev); 1764 if (err) { 1765 netif_err(ag, probe, ndev, "unable to request IRQ %d\n", 1766 ndev->irq); 1767 goto err_free; 1768 } 1769 1770 ndev->netdev_ops = &ag71xx_netdev_ops; 1771 1772 INIT_DELAYED_WORK(&ag->restart_work, ag71xx_restart_work_func); 1773 timer_setup(&ag->oom_timer, ag71xx_oom_timer_handler, 0); 1774 1775 tx_size = AG71XX_TX_RING_SIZE_DEFAULT; 1776 ag->rx_ring.order = ag71xx_ring_size_order(AG71XX_RX_RING_SIZE_DEFAULT); 1777 1778 ndev->min_mtu = 68; 1779 ndev->max_mtu = dcfg->max_frame_len - ag71xx_max_frame_len(0); 1780 1781 ag->rx_buf_offset = NET_SKB_PAD; 1782 if (!ag71xx_is(ag, AR7100) && !ag71xx_is(ag, AR9130)) 1783 ag->rx_buf_offset += NET_IP_ALIGN; 1784 1785 if (ag71xx_is(ag, AR7100)) { 1786 ag->tx_ring.desc_split = AG71XX_TX_RING_SPLIT; 1787 tx_size *= AG71XX_TX_RING_DS_PER_PKT; 1788 } 1789 ag->tx_ring.order = ag71xx_ring_size_order(tx_size); 1790 1791 ag->stop_desc = dmam_alloc_coherent(&pdev->dev, 1792 sizeof(struct ag71xx_desc), 1793 &ag->stop_desc_dma, GFP_KERNEL); 1794 if (!ag->stop_desc) { 1795 err = -ENOMEM; 1796 goto err_free; 1797 } 1798 1799 ag->stop_desc->data = 0; 1800 ag->stop_desc->ctrl = 0; 1801 ag->stop_desc->next = (u32)ag->stop_desc_dma; 1802 1803 mac_addr = of_get_mac_address(np); 1804 if (!IS_ERR(mac_addr)) 1805 memcpy(ndev->dev_addr, mac_addr, ETH_ALEN); 1806 if (IS_ERR(mac_addr) || !is_valid_ether_addr(ndev->dev_addr)) { 1807 netif_err(ag, probe, ndev, "invalid MAC address, using random address\n"); 1808 eth_random_addr(ndev->dev_addr); 1809 } 1810 1811 err = of_get_phy_mode(np, &ag->phy_if_mode); 1812 if (err) { 1813 netif_err(ag, probe, ndev, "missing phy-mode property in DT\n"); 1814 goto err_free; 1815 } 1816 1817 netif_napi_add(ndev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT); 1818 1819 err = clk_prepare_enable(ag->clk_eth); 1820 if (err) { 1821 netif_err(ag, probe, ndev, "Failed to enable eth clk.\n"); 1822 goto err_free; 1823 } 1824 1825 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, 0); 1826 1827 ag71xx_hw_init(ag); 1828 1829 err = ag71xx_mdio_probe(ag); 1830 if (err) 1831 goto err_put_clk; 1832 1833 platform_set_drvdata(pdev, ndev); 1834 1835 err = ag71xx_phylink_setup(ag); 1836 if (err) { 1837 netif_err(ag, probe, ndev, "failed to setup phylink (%d)\n", err); 1838 goto err_mdio_remove; 1839 } 1840 1841 err = register_netdev(ndev); 1842 if (err) { 1843 netif_err(ag, probe, ndev, "unable to register net device\n"); 1844 platform_set_drvdata(pdev, NULL); 1845 goto err_mdio_remove; 1846 } 1847 1848 netif_info(ag, probe, ndev, "Atheros AG71xx at 0x%08lx, irq %d, mode:%s\n", 1849 (unsigned long)ag->mac_base, ndev->irq, 1850 phy_modes(ag->phy_if_mode)); 1851 1852 return 0; 1853 1854 err_mdio_remove: 1855 ag71xx_mdio_remove(ag); 1856 err_put_clk: 1857 clk_disable_unprepare(ag->clk_eth); 1858 err_free: 1859 free_netdev(ndev); 1860 return err; 1861 } 1862 1863 static int ag71xx_remove(struct platform_device *pdev) 1864 { 1865 struct net_device *ndev = platform_get_drvdata(pdev); 1866 struct ag71xx *ag; 1867 1868 if (!ndev) 1869 return 0; 1870 1871 ag = netdev_priv(ndev); 1872 unregister_netdev(ndev); 1873 ag71xx_mdio_remove(ag); 1874 clk_disable_unprepare(ag->clk_eth); 1875 platform_set_drvdata(pdev, NULL); 1876 1877 return 0; 1878 } 1879 1880 static const u32 ar71xx_fifo_ar7100[] = { 1881 0x0fff0000, 0x00001fff, 0x00780fff, 1882 }; 1883 1884 static const u32 ar71xx_fifo_ar9130[] = { 1885 0x0fff0000, 0x00001fff, 0x008001ff, 1886 }; 1887 1888 static const u32 ar71xx_fifo_ar9330[] = { 1889 0x0010ffff, 0x015500aa, 0x01f00140, 1890 }; 1891 1892 static const struct ag71xx_dcfg ag71xx_dcfg_ar7100 = { 1893 .type = AR7100, 1894 .fifodata = ar71xx_fifo_ar7100, 1895 .max_frame_len = 1540, 1896 .desc_pktlen_mask = SZ_4K - 1, 1897 .tx_hang_workaround = false, 1898 }; 1899 1900 static const struct ag71xx_dcfg ag71xx_dcfg_ar7240 = { 1901 .type = AR7240, 1902 .fifodata = ar71xx_fifo_ar7100, 1903 .max_frame_len = 1540, 1904 .desc_pktlen_mask = SZ_4K - 1, 1905 .tx_hang_workaround = true, 1906 }; 1907 1908 static const struct ag71xx_dcfg ag71xx_dcfg_ar9130 = { 1909 .type = AR9130, 1910 .fifodata = ar71xx_fifo_ar9130, 1911 .max_frame_len = 1540, 1912 .desc_pktlen_mask = SZ_4K - 1, 1913 .tx_hang_workaround = false, 1914 }; 1915 1916 static const struct ag71xx_dcfg ag71xx_dcfg_ar9330 = { 1917 .type = AR9330, 1918 .fifodata = ar71xx_fifo_ar9330, 1919 .max_frame_len = 1540, 1920 .desc_pktlen_mask = SZ_4K - 1, 1921 .tx_hang_workaround = true, 1922 }; 1923 1924 static const struct ag71xx_dcfg ag71xx_dcfg_ar9340 = { 1925 .type = AR9340, 1926 .fifodata = ar71xx_fifo_ar9330, 1927 .max_frame_len = SZ_16K - 1, 1928 .desc_pktlen_mask = SZ_16K - 1, 1929 .tx_hang_workaround = true, 1930 }; 1931 1932 static const struct ag71xx_dcfg ag71xx_dcfg_qca9530 = { 1933 .type = QCA9530, 1934 .fifodata = ar71xx_fifo_ar9330, 1935 .max_frame_len = SZ_16K - 1, 1936 .desc_pktlen_mask = SZ_16K - 1, 1937 .tx_hang_workaround = true, 1938 }; 1939 1940 static const struct ag71xx_dcfg ag71xx_dcfg_qca9550 = { 1941 .type = QCA9550, 1942 .fifodata = ar71xx_fifo_ar9330, 1943 .max_frame_len = 1540, 1944 .desc_pktlen_mask = SZ_16K - 1, 1945 .tx_hang_workaround = true, 1946 }; 1947 1948 static const struct of_device_id ag71xx_match[] = { 1949 { .compatible = "qca,ar7100-eth", .data = &ag71xx_dcfg_ar7100 }, 1950 { .compatible = "qca,ar7240-eth", .data = &ag71xx_dcfg_ar7240 }, 1951 { .compatible = "qca,ar7241-eth", .data = &ag71xx_dcfg_ar7240 }, 1952 { .compatible = "qca,ar7242-eth", .data = &ag71xx_dcfg_ar7240 }, 1953 { .compatible = "qca,ar9130-eth", .data = &ag71xx_dcfg_ar9130 }, 1954 { .compatible = "qca,ar9330-eth", .data = &ag71xx_dcfg_ar9330 }, 1955 { .compatible = "qca,ar9340-eth", .data = &ag71xx_dcfg_ar9340 }, 1956 { .compatible = "qca,qca9530-eth", .data = &ag71xx_dcfg_qca9530 }, 1957 { .compatible = "qca,qca9550-eth", .data = &ag71xx_dcfg_qca9550 }, 1958 { .compatible = "qca,qca9560-eth", .data = &ag71xx_dcfg_qca9550 }, 1959 {} 1960 }; 1961 1962 static struct platform_driver ag71xx_driver = { 1963 .probe = ag71xx_probe, 1964 .remove = ag71xx_remove, 1965 .driver = { 1966 .name = "ag71xx", 1967 .of_match_table = ag71xx_match, 1968 } 1969 }; 1970 1971 module_platform_driver(ag71xx_driver); 1972 MODULE_LICENSE("GPL v2"); 1973