1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2008,2010 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 * Chris Wilson <chris@chris-wilson.co.uk> 28 */ 29 30 #include <linux/export.h> 31 #include <linux/i2c-algo-bit.h> 32 #include <linux/i2c.h> 33 34 #include <drm/drm_hdcp.h> 35 36 #include "i915_drv.h" 37 #include "intel_display_types.h" 38 #include "intel_gmbus.h" 39 40 struct gmbus_pin { 41 const char *name; 42 enum i915_gpio gpio; 43 }; 44 45 /* Map gmbus pin pairs to names and registers. */ 46 static const struct gmbus_pin gmbus_pins[] = { 47 [GMBUS_PIN_SSC] = { "ssc", GPIOB }, 48 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 49 [GMBUS_PIN_PANEL] = { "panel", GPIOC }, 50 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 51 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 52 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 53 }; 54 55 static const struct gmbus_pin gmbus_pins_bdw[] = { 56 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 57 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 58 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 59 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 60 }; 61 62 static const struct gmbus_pin gmbus_pins_skl[] = { 63 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 64 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 65 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 66 }; 67 68 static const struct gmbus_pin gmbus_pins_bxt[] = { 69 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 70 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 71 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 72 }; 73 74 static const struct gmbus_pin gmbus_pins_cnp[] = { 75 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 76 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 77 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 78 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 79 }; 80 81 static const struct gmbus_pin gmbus_pins_icp[] = { 82 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 83 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 84 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 85 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 86 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, 87 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, 88 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, 89 [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION }, 90 [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO }, 91 }; 92 93 /* pin is expected to be valid */ 94 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv, 95 unsigned int pin) 96 { 97 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 98 return &gmbus_pins_icp[pin]; 99 else if (HAS_PCH_CNP(dev_priv)) 100 return &gmbus_pins_cnp[pin]; 101 else if (IS_GEN9_LP(dev_priv)) 102 return &gmbus_pins_bxt[pin]; 103 else if (IS_GEN9_BC(dev_priv)) 104 return &gmbus_pins_skl[pin]; 105 else if (IS_BROADWELL(dev_priv)) 106 return &gmbus_pins_bdw[pin]; 107 else 108 return &gmbus_pins[pin]; 109 } 110 111 bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, 112 unsigned int pin) 113 { 114 unsigned int size; 115 116 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 117 size = ARRAY_SIZE(gmbus_pins_icp); 118 else if (HAS_PCH_CNP(dev_priv)) 119 size = ARRAY_SIZE(gmbus_pins_cnp); 120 else if (IS_GEN9_LP(dev_priv)) 121 size = ARRAY_SIZE(gmbus_pins_bxt); 122 else if (IS_GEN9_BC(dev_priv)) 123 size = ARRAY_SIZE(gmbus_pins_skl); 124 else if (IS_BROADWELL(dev_priv)) 125 size = ARRAY_SIZE(gmbus_pins_bdw); 126 else 127 size = ARRAY_SIZE(gmbus_pins); 128 129 return pin < size && get_gmbus_pin(dev_priv, pin)->name; 130 } 131 132 /* Intel GPIO access functions */ 133 134 #define I2C_RISEFALL_TIME 10 135 136 static inline struct intel_gmbus * 137 to_intel_gmbus(struct i2c_adapter *i2c) 138 { 139 return container_of(i2c, struct intel_gmbus, adapter); 140 } 141 142 void 143 intel_gmbus_reset(struct drm_i915_private *dev_priv) 144 { 145 intel_de_write(dev_priv, GMBUS0, 0); 146 intel_de_write(dev_priv, GMBUS4, 0); 147 } 148 149 static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv, 150 bool enable) 151 { 152 u32 val; 153 154 /* When using bit bashing for I2C, this bit needs to be set to 1 */ 155 val = intel_de_read(dev_priv, DSPCLK_GATE_D); 156 if (!enable) 157 val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; 158 else 159 val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; 160 intel_de_write(dev_priv, DSPCLK_GATE_D, val); 161 } 162 163 static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv, 164 bool enable) 165 { 166 u32 val; 167 168 val = intel_de_read(dev_priv, SOUTH_DSPCLK_GATE_D); 169 if (!enable) 170 val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; 171 else 172 val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; 173 intel_de_write(dev_priv, SOUTH_DSPCLK_GATE_D, val); 174 } 175 176 static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv, 177 bool enable) 178 { 179 u32 val; 180 181 val = intel_de_read(dev_priv, GEN9_CLKGATE_DIS_4); 182 if (!enable) 183 val |= BXT_GMBUS_GATING_DIS; 184 else 185 val &= ~BXT_GMBUS_GATING_DIS; 186 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_4, val); 187 } 188 189 static u32 get_reserved(struct intel_gmbus *bus) 190 { 191 struct drm_i915_private *i915 = bus->dev_priv; 192 struct intel_uncore *uncore = &i915->uncore; 193 u32 reserved = 0; 194 195 /* On most chips, these bits must be preserved in software. */ 196 if (!IS_I830(i915) && !IS_I845G(i915)) 197 reserved = intel_uncore_read_notrace(uncore, bus->gpio_reg) & 198 (GPIO_DATA_PULLUP_DISABLE | 199 GPIO_CLOCK_PULLUP_DISABLE); 200 201 return reserved; 202 } 203 204 static int get_clock(void *data) 205 { 206 struct intel_gmbus *bus = data; 207 struct intel_uncore *uncore = &bus->dev_priv->uncore; 208 u32 reserved = get_reserved(bus); 209 210 intel_uncore_write_notrace(uncore, 211 bus->gpio_reg, 212 reserved | GPIO_CLOCK_DIR_MASK); 213 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved); 214 215 return (intel_uncore_read_notrace(uncore, bus->gpio_reg) & 216 GPIO_CLOCK_VAL_IN) != 0; 217 } 218 219 static int get_data(void *data) 220 { 221 struct intel_gmbus *bus = data; 222 struct intel_uncore *uncore = &bus->dev_priv->uncore; 223 u32 reserved = get_reserved(bus); 224 225 intel_uncore_write_notrace(uncore, 226 bus->gpio_reg, 227 reserved | GPIO_DATA_DIR_MASK); 228 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved); 229 230 return (intel_uncore_read_notrace(uncore, bus->gpio_reg) & 231 GPIO_DATA_VAL_IN) != 0; 232 } 233 234 static void set_clock(void *data, int state_high) 235 { 236 struct intel_gmbus *bus = data; 237 struct intel_uncore *uncore = &bus->dev_priv->uncore; 238 u32 reserved = get_reserved(bus); 239 u32 clock_bits; 240 241 if (state_high) 242 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; 243 else 244 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | 245 GPIO_CLOCK_VAL_MASK; 246 247 intel_uncore_write_notrace(uncore, 248 bus->gpio_reg, 249 reserved | clock_bits); 250 intel_uncore_posting_read(uncore, bus->gpio_reg); 251 } 252 253 static void set_data(void *data, int state_high) 254 { 255 struct intel_gmbus *bus = data; 256 struct intel_uncore *uncore = &bus->dev_priv->uncore; 257 u32 reserved = get_reserved(bus); 258 u32 data_bits; 259 260 if (state_high) 261 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; 262 else 263 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | 264 GPIO_DATA_VAL_MASK; 265 266 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved | data_bits); 267 intel_uncore_posting_read(uncore, bus->gpio_reg); 268 } 269 270 static int 271 intel_gpio_pre_xfer(struct i2c_adapter *adapter) 272 { 273 struct intel_gmbus *bus = container_of(adapter, 274 struct intel_gmbus, 275 adapter); 276 struct drm_i915_private *dev_priv = bus->dev_priv; 277 278 intel_gmbus_reset(dev_priv); 279 280 if (IS_PINEVIEW(dev_priv)) 281 pnv_gmbus_clock_gating(dev_priv, false); 282 283 set_data(bus, 1); 284 set_clock(bus, 1); 285 udelay(I2C_RISEFALL_TIME); 286 return 0; 287 } 288 289 static void 290 intel_gpio_post_xfer(struct i2c_adapter *adapter) 291 { 292 struct intel_gmbus *bus = container_of(adapter, 293 struct intel_gmbus, 294 adapter); 295 struct drm_i915_private *dev_priv = bus->dev_priv; 296 297 set_data(bus, 1); 298 set_clock(bus, 1); 299 300 if (IS_PINEVIEW(dev_priv)) 301 pnv_gmbus_clock_gating(dev_priv, true); 302 } 303 304 static void 305 intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin) 306 { 307 struct drm_i915_private *dev_priv = bus->dev_priv; 308 struct i2c_algo_bit_data *algo; 309 310 algo = &bus->bit_algo; 311 312 bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio); 313 bus->adapter.algo_data = algo; 314 algo->setsda = set_data; 315 algo->setscl = set_clock; 316 algo->getsda = get_data; 317 algo->getscl = get_clock; 318 algo->pre_xfer = intel_gpio_pre_xfer; 319 algo->post_xfer = intel_gpio_post_xfer; 320 algo->udelay = I2C_RISEFALL_TIME; 321 algo->timeout = usecs_to_jiffies(2200); 322 algo->data = bus; 323 } 324 325 static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en) 326 { 327 DEFINE_WAIT(wait); 328 u32 gmbus2; 329 int ret; 330 331 /* Important: The hw handles only the first bit, so set only one! Since 332 * we also need to check for NAKs besides the hw ready/idle signal, we 333 * need to wake up periodically and check that ourselves. 334 */ 335 if (!HAS_GMBUS_IRQ(dev_priv)) 336 irq_en = 0; 337 338 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); 339 intel_de_write_fw(dev_priv, GMBUS4, irq_en); 340 341 status |= GMBUS_SATOER; 342 ret = wait_for_us((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status, 343 2); 344 if (ret) 345 ret = wait_for((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status, 346 50); 347 348 intel_de_write_fw(dev_priv, GMBUS4, 0); 349 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); 350 351 if (gmbus2 & GMBUS_SATOER) 352 return -ENXIO; 353 354 return ret; 355 } 356 357 static int 358 gmbus_wait_idle(struct drm_i915_private *dev_priv) 359 { 360 DEFINE_WAIT(wait); 361 u32 irq_enable; 362 int ret; 363 364 /* Important: The hw handles only the first bit, so set only one! */ 365 irq_enable = 0; 366 if (HAS_GMBUS_IRQ(dev_priv)) 367 irq_enable = GMBUS_IDLE_EN; 368 369 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); 370 intel_de_write_fw(dev_priv, GMBUS4, irq_enable); 371 372 ret = intel_wait_for_register_fw(&dev_priv->uncore, 373 GMBUS2, GMBUS_ACTIVE, 0, 374 10); 375 376 intel_de_write_fw(dev_priv, GMBUS4, 0); 377 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); 378 379 return ret; 380 } 381 382 static inline 383 unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv) 384 { 385 return INTEL_GEN(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX : 386 GMBUS_BYTE_COUNT_MAX; 387 } 388 389 static int 390 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, 391 unsigned short addr, u8 *buf, unsigned int len, 392 u32 gmbus0_reg, u32 gmbus1_index) 393 { 394 unsigned int size = len; 395 bool burst_read = len > gmbus_max_xfer_size(dev_priv); 396 bool extra_byte_added = false; 397 398 if (burst_read) { 399 /* 400 * As per HW Spec, for 512Bytes need to read extra Byte and 401 * Ignore the extra byte read. 402 */ 403 if (len == 512) { 404 extra_byte_added = true; 405 len++; 406 } 407 size = len % 256 + 256; 408 intel_de_write_fw(dev_priv, GMBUS0, 409 gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE); 410 } 411 412 intel_de_write_fw(dev_priv, GMBUS1, 413 gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY); 414 while (len) { 415 int ret; 416 u32 val, loop = 0; 417 418 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 419 if (ret) 420 return ret; 421 422 val = intel_de_read_fw(dev_priv, GMBUS3); 423 do { 424 if (extra_byte_added && len == 1) 425 break; 426 427 *buf++ = val & 0xff; 428 val >>= 8; 429 } while (--len && ++loop < 4); 430 431 if (burst_read && len == size - 4) 432 /* Reset the override bit */ 433 intel_de_write_fw(dev_priv, GMBUS0, gmbus0_reg); 434 } 435 436 return 0; 437 } 438 439 /* 440 * HW spec says that 512Bytes in Burst read need special treatment. 441 * But it doesn't talk about other multiple of 256Bytes. And couldn't locate 442 * an I2C slave, which supports such a lengthy burst read too for experiments. 443 * 444 * So until things get clarified on HW support, to avoid the burst read length 445 * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes. 446 */ 447 #define INTEL_GMBUS_BURST_READ_MAX_LEN 767U 448 449 static int 450 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, 451 u32 gmbus0_reg, u32 gmbus1_index) 452 { 453 u8 *buf = msg->buf; 454 unsigned int rx_size = msg->len; 455 unsigned int len; 456 int ret; 457 458 do { 459 if (HAS_GMBUS_BURST_READ(dev_priv)) 460 len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN); 461 else 462 len = min(rx_size, gmbus_max_xfer_size(dev_priv)); 463 464 ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, buf, len, 465 gmbus0_reg, gmbus1_index); 466 if (ret) 467 return ret; 468 469 rx_size -= len; 470 buf += len; 471 } while (rx_size != 0); 472 473 return 0; 474 } 475 476 static int 477 gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, 478 unsigned short addr, u8 *buf, unsigned int len, 479 u32 gmbus1_index) 480 { 481 unsigned int chunk_size = len; 482 u32 val, loop; 483 484 val = loop = 0; 485 while (len && loop < 4) { 486 val |= *buf++ << (8 * loop++); 487 len -= 1; 488 } 489 490 intel_de_write_fw(dev_priv, GMBUS3, val); 491 intel_de_write_fw(dev_priv, GMBUS1, 492 gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); 493 while (len) { 494 int ret; 495 496 val = loop = 0; 497 do { 498 val |= *buf++ << (8 * loop); 499 } while (--len && ++loop < 4); 500 501 intel_de_write_fw(dev_priv, GMBUS3, val); 502 503 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 504 if (ret) 505 return ret; 506 } 507 508 return 0; 509 } 510 511 static int 512 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg, 513 u32 gmbus1_index) 514 { 515 u8 *buf = msg->buf; 516 unsigned int tx_size = msg->len; 517 unsigned int len; 518 int ret; 519 520 do { 521 len = min(tx_size, gmbus_max_xfer_size(dev_priv)); 522 523 ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len, 524 gmbus1_index); 525 if (ret) 526 return ret; 527 528 buf += len; 529 tx_size -= len; 530 } while (tx_size != 0); 531 532 return 0; 533 } 534 535 /* 536 * The gmbus controller can combine a 1 or 2 byte write with another read/write 537 * that immediately follows it by using an "INDEX" cycle. 538 */ 539 static bool 540 gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num) 541 { 542 return (i + 1 < num && 543 msgs[i].addr == msgs[i + 1].addr && 544 !(msgs[i].flags & I2C_M_RD) && 545 (msgs[i].len == 1 || msgs[i].len == 2) && 546 msgs[i + 1].len > 0); 547 } 548 549 static int 550 gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs, 551 u32 gmbus0_reg) 552 { 553 u32 gmbus1_index = 0; 554 u32 gmbus5 = 0; 555 int ret; 556 557 if (msgs[0].len == 2) 558 gmbus5 = GMBUS_2BYTE_INDEX_EN | 559 msgs[0].buf[1] | (msgs[0].buf[0] << 8); 560 if (msgs[0].len == 1) 561 gmbus1_index = GMBUS_CYCLE_INDEX | 562 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); 563 564 /* GMBUS5 holds 16-bit index */ 565 if (gmbus5) 566 intel_de_write_fw(dev_priv, GMBUS5, gmbus5); 567 568 if (msgs[1].flags & I2C_M_RD) 569 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg, 570 gmbus1_index); 571 else 572 ret = gmbus_xfer_write(dev_priv, &msgs[1], gmbus1_index); 573 574 /* Clear GMBUS5 after each index transfer */ 575 if (gmbus5) 576 intel_de_write_fw(dev_priv, GMBUS5, 0); 577 578 return ret; 579 } 580 581 static int 582 do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, 583 u32 gmbus0_source) 584 { 585 struct intel_gmbus *bus = container_of(adapter, 586 struct intel_gmbus, 587 adapter); 588 struct drm_i915_private *dev_priv = bus->dev_priv; 589 int i = 0, inc, try = 0; 590 int ret = 0; 591 592 /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */ 593 if (IS_GEN9_LP(dev_priv)) 594 bxt_gmbus_clock_gating(dev_priv, false); 595 else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv)) 596 pch_gmbus_clock_gating(dev_priv, false); 597 598 retry: 599 intel_de_write_fw(dev_priv, GMBUS0, gmbus0_source | bus->reg0); 600 601 for (; i < num; i += inc) { 602 inc = 1; 603 if (gmbus_is_index_xfer(msgs, i, num)) { 604 ret = gmbus_index_xfer(dev_priv, &msgs[i], 605 gmbus0_source | bus->reg0); 606 inc = 2; /* an index transmission is two msgs */ 607 } else if (msgs[i].flags & I2C_M_RD) { 608 ret = gmbus_xfer_read(dev_priv, &msgs[i], 609 gmbus0_source | bus->reg0, 0); 610 } else { 611 ret = gmbus_xfer_write(dev_priv, &msgs[i], 0); 612 } 613 614 if (!ret) 615 ret = gmbus_wait(dev_priv, 616 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN); 617 if (ret == -ETIMEDOUT) 618 goto timeout; 619 else if (ret) 620 goto clear_err; 621 } 622 623 /* Generate a STOP condition on the bus. Note that gmbus can't generata 624 * a STOP on the very first cycle. To simplify the code we 625 * unconditionally generate the STOP condition with an additional gmbus 626 * cycle. */ 627 intel_de_write_fw(dev_priv, GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); 628 629 /* Mark the GMBUS interface as disabled after waiting for idle. 630 * We will re-enable it at the start of the next xfer, 631 * till then let it sleep. 632 */ 633 if (gmbus_wait_idle(dev_priv)) { 634 drm_dbg_kms(&dev_priv->drm, 635 "GMBUS [%s] timed out waiting for idle\n", 636 adapter->name); 637 ret = -ETIMEDOUT; 638 } 639 intel_de_write_fw(dev_priv, GMBUS0, 0); 640 ret = ret ?: i; 641 goto out; 642 643 clear_err: 644 /* 645 * Wait for bus to IDLE before clearing NAK. 646 * If we clear the NAK while bus is still active, then it will stay 647 * active and the next transaction may fail. 648 * 649 * If no ACK is received during the address phase of a transaction, the 650 * adapter must report -ENXIO. It is not clear what to return if no ACK 651 * is received at other times. But we have to be careful to not return 652 * spurious -ENXIO because that will prevent i2c and drm edid functions 653 * from retrying. So return -ENXIO only when gmbus properly quiescents - 654 * timing out seems to happen when there _is_ a ddc chip present, but 655 * it's slow responding and only answers on the 2nd retry. 656 */ 657 ret = -ENXIO; 658 if (gmbus_wait_idle(dev_priv)) { 659 drm_dbg_kms(&dev_priv->drm, 660 "GMBUS [%s] timed out after NAK\n", 661 adapter->name); 662 ret = -ETIMEDOUT; 663 } 664 665 /* Toggle the Software Clear Interrupt bit. This has the effect 666 * of resetting the GMBUS controller and so clearing the 667 * BUS_ERROR raised by the slave's NAK. 668 */ 669 intel_de_write_fw(dev_priv, GMBUS1, GMBUS_SW_CLR_INT); 670 intel_de_write_fw(dev_priv, GMBUS1, 0); 671 intel_de_write_fw(dev_priv, GMBUS0, 0); 672 673 drm_dbg_kms(&dev_priv->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n", 674 adapter->name, msgs[i].addr, 675 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); 676 677 /* 678 * Passive adapters sometimes NAK the first probe. Retry the first 679 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm 680 * has retries internally. See also the retry loop in 681 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO. 682 */ 683 if (ret == -ENXIO && i == 0 && try++ == 0) { 684 drm_dbg_kms(&dev_priv->drm, 685 "GMBUS [%s] NAK on first message, retry\n", 686 adapter->name); 687 goto retry; 688 } 689 690 goto out; 691 692 timeout: 693 drm_dbg_kms(&dev_priv->drm, 694 "GMBUS [%s] timed out, falling back to bit banging on pin %d\n", 695 bus->adapter.name, bus->reg0 & 0xff); 696 intel_de_write_fw(dev_priv, GMBUS0, 0); 697 698 /* 699 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging 700 * instead. Use EAGAIN to have i2c core retry. 701 */ 702 ret = -EAGAIN; 703 704 out: 705 /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */ 706 if (IS_GEN9_LP(dev_priv)) 707 bxt_gmbus_clock_gating(dev_priv, true); 708 else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv)) 709 pch_gmbus_clock_gating(dev_priv, true); 710 711 return ret; 712 } 713 714 static int 715 gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) 716 { 717 struct intel_gmbus *bus = 718 container_of(adapter, struct intel_gmbus, adapter); 719 struct drm_i915_private *dev_priv = bus->dev_priv; 720 intel_wakeref_t wakeref; 721 int ret; 722 723 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 724 725 if (bus->force_bit) { 726 ret = i2c_bit_algo.master_xfer(adapter, msgs, num); 727 if (ret < 0) 728 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY; 729 } else { 730 ret = do_gmbus_xfer(adapter, msgs, num, 0); 731 if (ret == -EAGAIN) 732 bus->force_bit |= GMBUS_FORCE_BIT_RETRY; 733 } 734 735 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 736 737 return ret; 738 } 739 740 int intel_gmbus_output_aksv(struct i2c_adapter *adapter) 741 { 742 struct intel_gmbus *bus = 743 container_of(adapter, struct intel_gmbus, adapter); 744 struct drm_i915_private *dev_priv = bus->dev_priv; 745 u8 cmd = DRM_HDCP_DDC_AKSV; 746 u8 buf[DRM_HDCP_KSV_LEN] = { 0 }; 747 struct i2c_msg msgs[] = { 748 { 749 .addr = DRM_HDCP_DDC_ADDR, 750 .flags = 0, 751 .len = sizeof(cmd), 752 .buf = &cmd, 753 }, 754 { 755 .addr = DRM_HDCP_DDC_ADDR, 756 .flags = 0, 757 .len = sizeof(buf), 758 .buf = buf, 759 } 760 }; 761 intel_wakeref_t wakeref; 762 int ret; 763 764 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 765 mutex_lock(&dev_priv->gmbus_mutex); 766 767 /* 768 * In order to output Aksv to the receiver, use an indexed write to 769 * pass the i2c command, and tell GMBUS to use the HW-provided value 770 * instead of sourcing GMBUS3 for the data. 771 */ 772 ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT); 773 774 mutex_unlock(&dev_priv->gmbus_mutex); 775 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 776 777 return ret; 778 } 779 780 static u32 gmbus_func(struct i2c_adapter *adapter) 781 { 782 return i2c_bit_algo.functionality(adapter) & 783 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 784 /* I2C_FUNC_10BIT_ADDR | */ 785 I2C_FUNC_SMBUS_READ_BLOCK_DATA | 786 I2C_FUNC_SMBUS_BLOCK_PROC_CALL); 787 } 788 789 static const struct i2c_algorithm gmbus_algorithm = { 790 .master_xfer = gmbus_xfer, 791 .functionality = gmbus_func 792 }; 793 794 static void gmbus_lock_bus(struct i2c_adapter *adapter, 795 unsigned int flags) 796 { 797 struct intel_gmbus *bus = to_intel_gmbus(adapter); 798 struct drm_i915_private *dev_priv = bus->dev_priv; 799 800 mutex_lock(&dev_priv->gmbus_mutex); 801 } 802 803 static int gmbus_trylock_bus(struct i2c_adapter *adapter, 804 unsigned int flags) 805 { 806 struct intel_gmbus *bus = to_intel_gmbus(adapter); 807 struct drm_i915_private *dev_priv = bus->dev_priv; 808 809 return mutex_trylock(&dev_priv->gmbus_mutex); 810 } 811 812 static void gmbus_unlock_bus(struct i2c_adapter *adapter, 813 unsigned int flags) 814 { 815 struct intel_gmbus *bus = to_intel_gmbus(adapter); 816 struct drm_i915_private *dev_priv = bus->dev_priv; 817 818 mutex_unlock(&dev_priv->gmbus_mutex); 819 } 820 821 static const struct i2c_lock_operations gmbus_lock_ops = { 822 .lock_bus = gmbus_lock_bus, 823 .trylock_bus = gmbus_trylock_bus, 824 .unlock_bus = gmbus_unlock_bus, 825 }; 826 827 /** 828 * intel_gmbus_setup - instantiate all Intel i2c GMBuses 829 * @dev_priv: i915 device private 830 */ 831 int intel_gmbus_setup(struct drm_i915_private *dev_priv) 832 { 833 struct pci_dev *pdev = dev_priv->drm.pdev; 834 struct intel_gmbus *bus; 835 unsigned int pin; 836 int ret; 837 838 if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv)) 839 return 0; 840 841 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 842 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; 843 else if (!HAS_GMCH(dev_priv)) 844 /* 845 * Broxton uses the same PCH offsets for South Display Engine, 846 * even though it doesn't have a PCH. 847 */ 848 dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE; 849 850 mutex_init(&dev_priv->gmbus_mutex); 851 init_waitqueue_head(&dev_priv->gmbus_wait_queue); 852 853 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { 854 if (!intel_gmbus_is_valid_pin(dev_priv, pin)) 855 continue; 856 857 bus = &dev_priv->gmbus[pin]; 858 859 bus->adapter.owner = THIS_MODULE; 860 bus->adapter.class = I2C_CLASS_DDC; 861 snprintf(bus->adapter.name, 862 sizeof(bus->adapter.name), 863 "i915 gmbus %s", 864 get_gmbus_pin(dev_priv, pin)->name); 865 866 bus->adapter.dev.parent = &pdev->dev; 867 bus->dev_priv = dev_priv; 868 869 bus->adapter.algo = &gmbus_algorithm; 870 bus->adapter.lock_ops = &gmbus_lock_ops; 871 872 /* 873 * We wish to retry with bit banging 874 * after a timed out GMBUS attempt. 875 */ 876 bus->adapter.retries = 1; 877 878 /* By default use a conservative clock rate */ 879 bus->reg0 = pin | GMBUS_RATE_100KHZ; 880 881 /* gmbus seems to be broken on i830 */ 882 if (IS_I830(dev_priv)) 883 bus->force_bit = 1; 884 885 intel_gpio_setup(bus, pin); 886 887 ret = i2c_add_adapter(&bus->adapter); 888 if (ret) 889 goto err; 890 } 891 892 intel_gmbus_reset(dev_priv); 893 894 return 0; 895 896 err: 897 while (pin--) { 898 if (!intel_gmbus_is_valid_pin(dev_priv, pin)) 899 continue; 900 901 bus = &dev_priv->gmbus[pin]; 902 i2c_del_adapter(&bus->adapter); 903 } 904 return ret; 905 } 906 907 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, 908 unsigned int pin) 909 { 910 if (drm_WARN_ON(&dev_priv->drm, 911 !intel_gmbus_is_valid_pin(dev_priv, pin))) 912 return NULL; 913 914 return &dev_priv->gmbus[pin].adapter; 915 } 916 917 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed) 918 { 919 struct intel_gmbus *bus = to_intel_gmbus(adapter); 920 921 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed; 922 } 923 924 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) 925 { 926 struct intel_gmbus *bus = to_intel_gmbus(adapter); 927 struct drm_i915_private *dev_priv = bus->dev_priv; 928 929 mutex_lock(&dev_priv->gmbus_mutex); 930 931 bus->force_bit += force_bit ? 1 : -1; 932 drm_dbg_kms(&dev_priv->drm, 933 "%sabling bit-banging on %s. force bit now %d\n", 934 force_bit ? "en" : "dis", adapter->name, 935 bus->force_bit); 936 937 mutex_unlock(&dev_priv->gmbus_mutex); 938 } 939 940 bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 941 { 942 struct intel_gmbus *bus = to_intel_gmbus(adapter); 943 944 return bus->force_bit; 945 } 946 947 void intel_gmbus_teardown(struct drm_i915_private *dev_priv) 948 { 949 struct intel_gmbus *bus; 950 unsigned int pin; 951 952 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { 953 if (!intel_gmbus_is_valid_pin(dev_priv, pin)) 954 continue; 955 956 bus = &dev_priv->gmbus[pin]; 957 i2c_del_adapter(&bus->adapter); 958 } 959 } 960