1 // SPDX-License-Identifier: GPL-2.0 2 // (C) 2017-2018 Synopsys, Inc. (www.synopsys.com) 3 4 /* 5 * Synopsys DesignWare AXI DMA Controller driver. 6 * 7 * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> 8 */ 9 10 #include <linux/bitops.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/dmaengine.h> 14 #include <linux/dmapool.h> 15 #include <linux/err.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/platform_device.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/property.h> 24 #include <linux/types.h> 25 26 #include "dw-axi-dmac.h" 27 #include "../dmaengine.h" 28 #include "../virt-dma.h" 29 30 /* 31 * The set of bus widths supported by the DMA controller. DW AXI DMAC supports 32 * master data bus width up to 512 bits (for both AXI master interfaces), but 33 * it depends on IP block configurarion. 34 */ 35 #define AXI_DMA_BUSWIDTHS \ 36 (DMA_SLAVE_BUSWIDTH_1_BYTE | \ 37 DMA_SLAVE_BUSWIDTH_2_BYTES | \ 38 DMA_SLAVE_BUSWIDTH_4_BYTES | \ 39 DMA_SLAVE_BUSWIDTH_8_BYTES | \ 40 DMA_SLAVE_BUSWIDTH_16_BYTES | \ 41 DMA_SLAVE_BUSWIDTH_32_BYTES | \ 42 DMA_SLAVE_BUSWIDTH_64_BYTES) 43 44 static inline void 45 axi_dma_iowrite32(struct axi_dma_chip *chip, u32 reg, u32 val) 46 { 47 iowrite32(val, chip->regs + reg); 48 } 49 50 static inline u32 axi_dma_ioread32(struct axi_dma_chip *chip, u32 reg) 51 { 52 return ioread32(chip->regs + reg); 53 } 54 55 static inline void 56 axi_chan_iowrite32(struct axi_dma_chan *chan, u32 reg, u32 val) 57 { 58 iowrite32(val, chan->chan_regs + reg); 59 } 60 61 static inline u32 axi_chan_ioread32(struct axi_dma_chan *chan, u32 reg) 62 { 63 return ioread32(chan->chan_regs + reg); 64 } 65 66 static inline void 67 axi_chan_iowrite64(struct axi_dma_chan *chan, u32 reg, u64 val) 68 { 69 /* 70 * We split one 64 bit write for two 32 bit write as some HW doesn't 71 * support 64 bit access. 72 */ 73 iowrite32(lower_32_bits(val), chan->chan_regs + reg); 74 iowrite32(upper_32_bits(val), chan->chan_regs + reg + 4); 75 } 76 77 static inline void axi_dma_disable(struct axi_dma_chip *chip) 78 { 79 u32 val; 80 81 val = axi_dma_ioread32(chip, DMAC_CFG); 82 val &= ~DMAC_EN_MASK; 83 axi_dma_iowrite32(chip, DMAC_CFG, val); 84 } 85 86 static inline void axi_dma_enable(struct axi_dma_chip *chip) 87 { 88 u32 val; 89 90 val = axi_dma_ioread32(chip, DMAC_CFG); 91 val |= DMAC_EN_MASK; 92 axi_dma_iowrite32(chip, DMAC_CFG, val); 93 } 94 95 static inline void axi_dma_irq_disable(struct axi_dma_chip *chip) 96 { 97 u32 val; 98 99 val = axi_dma_ioread32(chip, DMAC_CFG); 100 val &= ~INT_EN_MASK; 101 axi_dma_iowrite32(chip, DMAC_CFG, val); 102 } 103 104 static inline void axi_dma_irq_enable(struct axi_dma_chip *chip) 105 { 106 u32 val; 107 108 val = axi_dma_ioread32(chip, DMAC_CFG); 109 val |= INT_EN_MASK; 110 axi_dma_iowrite32(chip, DMAC_CFG, val); 111 } 112 113 static inline void axi_chan_irq_disable(struct axi_dma_chan *chan, u32 irq_mask) 114 { 115 u32 val; 116 117 if (likely(irq_mask == DWAXIDMAC_IRQ_ALL)) { 118 axi_chan_iowrite32(chan, CH_INTSTATUS_ENA, DWAXIDMAC_IRQ_NONE); 119 } else { 120 val = axi_chan_ioread32(chan, CH_INTSTATUS_ENA); 121 val &= ~irq_mask; 122 axi_chan_iowrite32(chan, CH_INTSTATUS_ENA, val); 123 } 124 } 125 126 static inline void axi_chan_irq_set(struct axi_dma_chan *chan, u32 irq_mask) 127 { 128 axi_chan_iowrite32(chan, CH_INTSTATUS_ENA, irq_mask); 129 } 130 131 static inline void axi_chan_irq_sig_set(struct axi_dma_chan *chan, u32 irq_mask) 132 { 133 axi_chan_iowrite32(chan, CH_INTSIGNAL_ENA, irq_mask); 134 } 135 136 static inline void axi_chan_irq_clear(struct axi_dma_chan *chan, u32 irq_mask) 137 { 138 axi_chan_iowrite32(chan, CH_INTCLEAR, irq_mask); 139 } 140 141 static inline u32 axi_chan_irq_read(struct axi_dma_chan *chan) 142 { 143 return axi_chan_ioread32(chan, CH_INTSTATUS); 144 } 145 146 static inline void axi_chan_disable(struct axi_dma_chan *chan) 147 { 148 u32 val; 149 150 val = axi_dma_ioread32(chan->chip, DMAC_CHEN); 151 val &= ~(BIT(chan->id) << DMAC_CHAN_EN_SHIFT); 152 val |= BIT(chan->id) << DMAC_CHAN_EN_WE_SHIFT; 153 axi_dma_iowrite32(chan->chip, DMAC_CHEN, val); 154 } 155 156 static inline void axi_chan_enable(struct axi_dma_chan *chan) 157 { 158 u32 val; 159 160 val = axi_dma_ioread32(chan->chip, DMAC_CHEN); 161 val |= BIT(chan->id) << DMAC_CHAN_EN_SHIFT | 162 BIT(chan->id) << DMAC_CHAN_EN_WE_SHIFT; 163 axi_dma_iowrite32(chan->chip, DMAC_CHEN, val); 164 } 165 166 static inline bool axi_chan_is_hw_enable(struct axi_dma_chan *chan) 167 { 168 u32 val; 169 170 val = axi_dma_ioread32(chan->chip, DMAC_CHEN); 171 172 return !!(val & (BIT(chan->id) << DMAC_CHAN_EN_SHIFT)); 173 } 174 175 static void axi_dma_hw_init(struct axi_dma_chip *chip) 176 { 177 u32 i; 178 179 for (i = 0; i < chip->dw->hdata->nr_channels; i++) { 180 axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL); 181 axi_chan_disable(&chip->dw->chan[i]); 182 } 183 } 184 185 static u32 axi_chan_get_xfer_width(struct axi_dma_chan *chan, dma_addr_t src, 186 dma_addr_t dst, size_t len) 187 { 188 u32 max_width = chan->chip->dw->hdata->m_data_width; 189 190 return __ffs(src | dst | len | BIT(max_width)); 191 } 192 193 static inline const char *axi_chan_name(struct axi_dma_chan *chan) 194 { 195 return dma_chan_name(&chan->vc.chan); 196 } 197 198 static struct axi_dma_desc *axi_desc_get(struct axi_dma_chan *chan) 199 { 200 struct dw_axi_dma *dw = chan->chip->dw; 201 struct axi_dma_desc *desc; 202 dma_addr_t phys; 203 204 desc = dma_pool_zalloc(dw->desc_pool, GFP_NOWAIT, &phys); 205 if (unlikely(!desc)) { 206 dev_err(chan2dev(chan), "%s: not enough descriptors available\n", 207 axi_chan_name(chan)); 208 return NULL; 209 } 210 211 atomic_inc(&chan->descs_allocated); 212 INIT_LIST_HEAD(&desc->xfer_list); 213 desc->vd.tx.phys = phys; 214 desc->chan = chan; 215 216 return desc; 217 } 218 219 static void axi_desc_put(struct axi_dma_desc *desc) 220 { 221 struct axi_dma_chan *chan = desc->chan; 222 struct dw_axi_dma *dw = chan->chip->dw; 223 struct axi_dma_desc *child, *_next; 224 unsigned int descs_put = 0; 225 226 list_for_each_entry_safe(child, _next, &desc->xfer_list, xfer_list) { 227 list_del(&child->xfer_list); 228 dma_pool_free(dw->desc_pool, child, child->vd.tx.phys); 229 descs_put++; 230 } 231 232 dma_pool_free(dw->desc_pool, desc, desc->vd.tx.phys); 233 descs_put++; 234 235 atomic_sub(descs_put, &chan->descs_allocated); 236 dev_vdbg(chan2dev(chan), "%s: %d descs put, %d still allocated\n", 237 axi_chan_name(chan), descs_put, 238 atomic_read(&chan->descs_allocated)); 239 } 240 241 static void vchan_desc_put(struct virt_dma_desc *vdesc) 242 { 243 axi_desc_put(vd_to_axi_desc(vdesc)); 244 } 245 246 static enum dma_status 247 dma_chan_tx_status(struct dma_chan *dchan, dma_cookie_t cookie, 248 struct dma_tx_state *txstate) 249 { 250 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 251 enum dma_status ret; 252 253 ret = dma_cookie_status(dchan, cookie, txstate); 254 255 if (chan->is_paused && ret == DMA_IN_PROGRESS) 256 ret = DMA_PAUSED; 257 258 return ret; 259 } 260 261 static void write_desc_llp(struct axi_dma_desc *desc, dma_addr_t adr) 262 { 263 desc->lli.llp = cpu_to_le64(adr); 264 } 265 266 static void write_chan_llp(struct axi_dma_chan *chan, dma_addr_t adr) 267 { 268 axi_chan_iowrite64(chan, CH_LLP, adr); 269 } 270 271 /* Called in chan locked context */ 272 static void axi_chan_block_xfer_start(struct axi_dma_chan *chan, 273 struct axi_dma_desc *first) 274 { 275 u32 priority = chan->chip->dw->hdata->priority[chan->id]; 276 u32 reg, irq_mask; 277 u8 lms = 0; /* Select AXI0 master for LLI fetching */ 278 279 if (unlikely(axi_chan_is_hw_enable(chan))) { 280 dev_err(chan2dev(chan), "%s is non-idle!\n", 281 axi_chan_name(chan)); 282 283 return; 284 } 285 286 axi_dma_enable(chan->chip); 287 288 reg = (DWAXIDMAC_MBLK_TYPE_LL << CH_CFG_L_DST_MULTBLK_TYPE_POS | 289 DWAXIDMAC_MBLK_TYPE_LL << CH_CFG_L_SRC_MULTBLK_TYPE_POS); 290 axi_chan_iowrite32(chan, CH_CFG_L, reg); 291 292 reg = (DWAXIDMAC_TT_FC_MEM_TO_MEM_DMAC << CH_CFG_H_TT_FC_POS | 293 priority << CH_CFG_H_PRIORITY_POS | 294 DWAXIDMAC_HS_SEL_HW << CH_CFG_H_HS_SEL_DST_POS | 295 DWAXIDMAC_HS_SEL_HW << CH_CFG_H_HS_SEL_SRC_POS); 296 axi_chan_iowrite32(chan, CH_CFG_H, reg); 297 298 write_chan_llp(chan, first->vd.tx.phys | lms); 299 300 irq_mask = DWAXIDMAC_IRQ_DMA_TRF | DWAXIDMAC_IRQ_ALL_ERR; 301 axi_chan_irq_sig_set(chan, irq_mask); 302 303 /* Generate 'suspend' status but don't generate interrupt */ 304 irq_mask |= DWAXIDMAC_IRQ_SUSPENDED; 305 axi_chan_irq_set(chan, irq_mask); 306 307 axi_chan_enable(chan); 308 } 309 310 static void axi_chan_start_first_queued(struct axi_dma_chan *chan) 311 { 312 struct axi_dma_desc *desc; 313 struct virt_dma_desc *vd; 314 315 vd = vchan_next_desc(&chan->vc); 316 if (!vd) 317 return; 318 319 desc = vd_to_axi_desc(vd); 320 dev_vdbg(chan2dev(chan), "%s: started %u\n", axi_chan_name(chan), 321 vd->tx.cookie); 322 axi_chan_block_xfer_start(chan, desc); 323 } 324 325 static void dma_chan_issue_pending(struct dma_chan *dchan) 326 { 327 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 328 unsigned long flags; 329 330 spin_lock_irqsave(&chan->vc.lock, flags); 331 if (vchan_issue_pending(&chan->vc)) 332 axi_chan_start_first_queued(chan); 333 spin_unlock_irqrestore(&chan->vc.lock, flags); 334 } 335 336 static int dma_chan_alloc_chan_resources(struct dma_chan *dchan) 337 { 338 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 339 340 /* ASSERT: channel is idle */ 341 if (axi_chan_is_hw_enable(chan)) { 342 dev_err(chan2dev(chan), "%s is non-idle!\n", 343 axi_chan_name(chan)); 344 return -EBUSY; 345 } 346 347 dev_vdbg(dchan2dev(dchan), "%s: allocating\n", axi_chan_name(chan)); 348 349 pm_runtime_get(chan->chip->dev); 350 351 return 0; 352 } 353 354 static void dma_chan_free_chan_resources(struct dma_chan *dchan) 355 { 356 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 357 358 /* ASSERT: channel is idle */ 359 if (axi_chan_is_hw_enable(chan)) 360 dev_err(dchan2dev(dchan), "%s is non-idle!\n", 361 axi_chan_name(chan)); 362 363 axi_chan_disable(chan); 364 axi_chan_irq_disable(chan, DWAXIDMAC_IRQ_ALL); 365 366 vchan_free_chan_resources(&chan->vc); 367 368 dev_vdbg(dchan2dev(dchan), 369 "%s: free resources, descriptor still allocated: %u\n", 370 axi_chan_name(chan), atomic_read(&chan->descs_allocated)); 371 372 pm_runtime_put(chan->chip->dev); 373 } 374 375 /* 376 * If DW_axi_dmac sees CHx_CTL.ShadowReg_Or_LLI_Last bit of the fetched LLI 377 * as 1, it understands that the current block is the final block in the 378 * transfer and completes the DMA transfer operation at the end of current 379 * block transfer. 380 */ 381 static void set_desc_last(struct axi_dma_desc *desc) 382 { 383 u32 val; 384 385 val = le32_to_cpu(desc->lli.ctl_hi); 386 val |= CH_CTL_H_LLI_LAST; 387 desc->lli.ctl_hi = cpu_to_le32(val); 388 } 389 390 static void write_desc_sar(struct axi_dma_desc *desc, dma_addr_t adr) 391 { 392 desc->lli.sar = cpu_to_le64(adr); 393 } 394 395 static void write_desc_dar(struct axi_dma_desc *desc, dma_addr_t adr) 396 { 397 desc->lli.dar = cpu_to_le64(adr); 398 } 399 400 static void set_desc_src_master(struct axi_dma_desc *desc) 401 { 402 u32 val; 403 404 /* Select AXI0 for source master */ 405 val = le32_to_cpu(desc->lli.ctl_lo); 406 val &= ~CH_CTL_L_SRC_MAST; 407 desc->lli.ctl_lo = cpu_to_le32(val); 408 } 409 410 static void set_desc_dest_master(struct axi_dma_desc *desc) 411 { 412 u32 val; 413 414 /* Select AXI1 for source master if available */ 415 val = le32_to_cpu(desc->lli.ctl_lo); 416 if (desc->chan->chip->dw->hdata->nr_masters > 1) 417 val |= CH_CTL_L_DST_MAST; 418 else 419 val &= ~CH_CTL_L_DST_MAST; 420 421 desc->lli.ctl_lo = cpu_to_le32(val); 422 } 423 424 static struct dma_async_tx_descriptor * 425 dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t dst_adr, 426 dma_addr_t src_adr, size_t len, unsigned long flags) 427 { 428 struct axi_dma_desc *first = NULL, *desc = NULL, *prev = NULL; 429 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 430 size_t block_ts, max_block_ts, xfer_len; 431 u32 xfer_width, reg; 432 u8 lms = 0; /* Select AXI0 master for LLI fetching */ 433 434 dev_dbg(chan2dev(chan), "%s: memcpy: src: %pad dst: %pad length: %zd flags: %#lx", 435 axi_chan_name(chan), &src_adr, &dst_adr, len, flags); 436 437 max_block_ts = chan->chip->dw->hdata->block_size[chan->id]; 438 439 while (len) { 440 xfer_len = len; 441 442 /* 443 * Take care for the alignment. 444 * Actually source and destination widths can be different, but 445 * make them same to be simpler. 446 */ 447 xfer_width = axi_chan_get_xfer_width(chan, src_adr, dst_adr, xfer_len); 448 449 /* 450 * block_ts indicates the total number of data of width 451 * to be transferred in a DMA block transfer. 452 * BLOCK_TS register should be set to block_ts - 1 453 */ 454 block_ts = xfer_len >> xfer_width; 455 if (block_ts > max_block_ts) { 456 block_ts = max_block_ts; 457 xfer_len = max_block_ts << xfer_width; 458 } 459 460 desc = axi_desc_get(chan); 461 if (unlikely(!desc)) 462 goto err_desc_get; 463 464 write_desc_sar(desc, src_adr); 465 write_desc_dar(desc, dst_adr); 466 desc->lli.block_ts_lo = cpu_to_le32(block_ts - 1); 467 468 reg = CH_CTL_H_LLI_VALID; 469 if (chan->chip->dw->hdata->restrict_axi_burst_len) { 470 u32 burst_len = chan->chip->dw->hdata->axi_rw_burst_len; 471 472 reg |= (CH_CTL_H_ARLEN_EN | 473 burst_len << CH_CTL_H_ARLEN_POS | 474 CH_CTL_H_AWLEN_EN | 475 burst_len << CH_CTL_H_AWLEN_POS); 476 } 477 desc->lli.ctl_hi = cpu_to_le32(reg); 478 479 reg = (DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_DST_MSIZE_POS | 480 DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_SRC_MSIZE_POS | 481 xfer_width << CH_CTL_L_DST_WIDTH_POS | 482 xfer_width << CH_CTL_L_SRC_WIDTH_POS | 483 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS | 484 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS); 485 desc->lli.ctl_lo = cpu_to_le32(reg); 486 487 set_desc_src_master(desc); 488 set_desc_dest_master(desc); 489 490 /* Manage transfer list (xfer_list) */ 491 if (!first) { 492 first = desc; 493 } else { 494 list_add_tail(&desc->xfer_list, &first->xfer_list); 495 write_desc_llp(prev, desc->vd.tx.phys | lms); 496 } 497 prev = desc; 498 499 /* update the length and addresses for the next loop cycle */ 500 len -= xfer_len; 501 dst_adr += xfer_len; 502 src_adr += xfer_len; 503 } 504 505 /* Total len of src/dest sg == 0, so no descriptor were allocated */ 506 if (unlikely(!first)) 507 return NULL; 508 509 /* Set end-of-link to the last link descriptor of list */ 510 set_desc_last(desc); 511 512 return vchan_tx_prep(&chan->vc, &first->vd, flags); 513 514 err_desc_get: 515 if (first) 516 axi_desc_put(first); 517 return NULL; 518 } 519 520 static void axi_chan_dump_lli(struct axi_dma_chan *chan, 521 struct axi_dma_desc *desc) 522 { 523 dev_err(dchan2dev(&chan->vc.chan), 524 "SAR: 0x%llx DAR: 0x%llx LLP: 0x%llx BTS 0x%x CTL: 0x%x:%08x", 525 le64_to_cpu(desc->lli.sar), 526 le64_to_cpu(desc->lli.dar), 527 le64_to_cpu(desc->lli.llp), 528 le32_to_cpu(desc->lli.block_ts_lo), 529 le32_to_cpu(desc->lli.ctl_hi), 530 le32_to_cpu(desc->lli.ctl_lo)); 531 } 532 533 static void axi_chan_list_dump_lli(struct axi_dma_chan *chan, 534 struct axi_dma_desc *desc_head) 535 { 536 struct axi_dma_desc *desc; 537 538 axi_chan_dump_lli(chan, desc_head); 539 list_for_each_entry(desc, &desc_head->xfer_list, xfer_list) 540 axi_chan_dump_lli(chan, desc); 541 } 542 543 static noinline void axi_chan_handle_err(struct axi_dma_chan *chan, u32 status) 544 { 545 struct virt_dma_desc *vd; 546 unsigned long flags; 547 548 spin_lock_irqsave(&chan->vc.lock, flags); 549 550 axi_chan_disable(chan); 551 552 /* The bad descriptor currently is in the head of vc list */ 553 vd = vchan_next_desc(&chan->vc); 554 /* Remove the completed descriptor from issued list */ 555 list_del(&vd->node); 556 557 /* WARN about bad descriptor */ 558 dev_err(chan2dev(chan), 559 "Bad descriptor submitted for %s, cookie: %d, irq: 0x%08x\n", 560 axi_chan_name(chan), vd->tx.cookie, status); 561 axi_chan_list_dump_lli(chan, vd_to_axi_desc(vd)); 562 563 vchan_cookie_complete(vd); 564 565 /* Try to restart the controller */ 566 axi_chan_start_first_queued(chan); 567 568 spin_unlock_irqrestore(&chan->vc.lock, flags); 569 } 570 571 static void axi_chan_block_xfer_complete(struct axi_dma_chan *chan) 572 { 573 struct virt_dma_desc *vd; 574 unsigned long flags; 575 576 spin_lock_irqsave(&chan->vc.lock, flags); 577 if (unlikely(axi_chan_is_hw_enable(chan))) { 578 dev_err(chan2dev(chan), "BUG: %s caught DWAXIDMAC_IRQ_DMA_TRF, but channel not idle!\n", 579 axi_chan_name(chan)); 580 axi_chan_disable(chan); 581 } 582 583 /* The completed descriptor currently is in the head of vc list */ 584 vd = vchan_next_desc(&chan->vc); 585 /* Remove the completed descriptor from issued list before completing */ 586 list_del(&vd->node); 587 vchan_cookie_complete(vd); 588 589 /* Submit queued descriptors after processing the completed ones */ 590 axi_chan_start_first_queued(chan); 591 592 spin_unlock_irqrestore(&chan->vc.lock, flags); 593 } 594 595 static irqreturn_t dw_axi_dma_interrupt(int irq, void *dev_id) 596 { 597 struct axi_dma_chip *chip = dev_id; 598 struct dw_axi_dma *dw = chip->dw; 599 struct axi_dma_chan *chan; 600 601 u32 status, i; 602 603 /* Disable DMAC inerrupts. We'll enable them after processing chanels */ 604 axi_dma_irq_disable(chip); 605 606 /* Poll, clear and process every chanel interrupt status */ 607 for (i = 0; i < dw->hdata->nr_channels; i++) { 608 chan = &dw->chan[i]; 609 status = axi_chan_irq_read(chan); 610 axi_chan_irq_clear(chan, status); 611 612 dev_vdbg(chip->dev, "%s %u IRQ status: 0x%08x\n", 613 axi_chan_name(chan), i, status); 614 615 if (status & DWAXIDMAC_IRQ_ALL_ERR) 616 axi_chan_handle_err(chan, status); 617 else if (status & DWAXIDMAC_IRQ_DMA_TRF) 618 axi_chan_block_xfer_complete(chan); 619 } 620 621 /* Re-enable interrupts */ 622 axi_dma_irq_enable(chip); 623 624 return IRQ_HANDLED; 625 } 626 627 static int dma_chan_terminate_all(struct dma_chan *dchan) 628 { 629 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 630 unsigned long flags; 631 LIST_HEAD(head); 632 633 spin_lock_irqsave(&chan->vc.lock, flags); 634 635 axi_chan_disable(chan); 636 637 vchan_get_all_descriptors(&chan->vc, &head); 638 639 spin_unlock_irqrestore(&chan->vc.lock, flags); 640 641 vchan_dma_desc_free_list(&chan->vc, &head); 642 643 dev_vdbg(dchan2dev(dchan), "terminated: %s\n", axi_chan_name(chan)); 644 645 return 0; 646 } 647 648 static int dma_chan_pause(struct dma_chan *dchan) 649 { 650 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 651 unsigned long flags; 652 unsigned int timeout = 20; /* timeout iterations */ 653 u32 val; 654 655 spin_lock_irqsave(&chan->vc.lock, flags); 656 657 val = axi_dma_ioread32(chan->chip, DMAC_CHEN); 658 val |= BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT | 659 BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT; 660 axi_dma_iowrite32(chan->chip, DMAC_CHEN, val); 661 662 do { 663 if (axi_chan_irq_read(chan) & DWAXIDMAC_IRQ_SUSPENDED) 664 break; 665 666 udelay(2); 667 } while (--timeout); 668 669 axi_chan_irq_clear(chan, DWAXIDMAC_IRQ_SUSPENDED); 670 671 chan->is_paused = true; 672 673 spin_unlock_irqrestore(&chan->vc.lock, flags); 674 675 return timeout ? 0 : -EAGAIN; 676 } 677 678 /* Called in chan locked context */ 679 static inline void axi_chan_resume(struct axi_dma_chan *chan) 680 { 681 u32 val; 682 683 val = axi_dma_ioread32(chan->chip, DMAC_CHEN); 684 val &= ~(BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT); 685 val |= (BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT); 686 axi_dma_iowrite32(chan->chip, DMAC_CHEN, val); 687 688 chan->is_paused = false; 689 } 690 691 static int dma_chan_resume(struct dma_chan *dchan) 692 { 693 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 694 unsigned long flags; 695 696 spin_lock_irqsave(&chan->vc.lock, flags); 697 698 if (chan->is_paused) 699 axi_chan_resume(chan); 700 701 spin_unlock_irqrestore(&chan->vc.lock, flags); 702 703 return 0; 704 } 705 706 static int axi_dma_suspend(struct axi_dma_chip *chip) 707 { 708 axi_dma_irq_disable(chip); 709 axi_dma_disable(chip); 710 711 clk_disable_unprepare(chip->core_clk); 712 clk_disable_unprepare(chip->cfgr_clk); 713 714 return 0; 715 } 716 717 static int axi_dma_resume(struct axi_dma_chip *chip) 718 { 719 int ret; 720 721 ret = clk_prepare_enable(chip->cfgr_clk); 722 if (ret < 0) 723 return ret; 724 725 ret = clk_prepare_enable(chip->core_clk); 726 if (ret < 0) 727 return ret; 728 729 axi_dma_enable(chip); 730 axi_dma_irq_enable(chip); 731 732 return 0; 733 } 734 735 static int __maybe_unused axi_dma_runtime_suspend(struct device *dev) 736 { 737 struct axi_dma_chip *chip = dev_get_drvdata(dev); 738 739 return axi_dma_suspend(chip); 740 } 741 742 static int __maybe_unused axi_dma_runtime_resume(struct device *dev) 743 { 744 struct axi_dma_chip *chip = dev_get_drvdata(dev); 745 746 return axi_dma_resume(chip); 747 } 748 749 static int parse_device_properties(struct axi_dma_chip *chip) 750 { 751 struct device *dev = chip->dev; 752 u32 tmp, carr[DMAC_MAX_CHANNELS]; 753 int ret; 754 755 ret = device_property_read_u32(dev, "dma-channels", &tmp); 756 if (ret) 757 return ret; 758 if (tmp == 0 || tmp > DMAC_MAX_CHANNELS) 759 return -EINVAL; 760 761 chip->dw->hdata->nr_channels = tmp; 762 763 ret = device_property_read_u32(dev, "snps,dma-masters", &tmp); 764 if (ret) 765 return ret; 766 if (tmp == 0 || tmp > DMAC_MAX_MASTERS) 767 return -EINVAL; 768 769 chip->dw->hdata->nr_masters = tmp; 770 771 ret = device_property_read_u32(dev, "snps,data-width", &tmp); 772 if (ret) 773 return ret; 774 if (tmp > DWAXIDMAC_TRANS_WIDTH_MAX) 775 return -EINVAL; 776 777 chip->dw->hdata->m_data_width = tmp; 778 779 ret = device_property_read_u32_array(dev, "snps,block-size", carr, 780 chip->dw->hdata->nr_channels); 781 if (ret) 782 return ret; 783 for (tmp = 0; tmp < chip->dw->hdata->nr_channels; tmp++) { 784 if (carr[tmp] == 0 || carr[tmp] > DMAC_MAX_BLK_SIZE) 785 return -EINVAL; 786 787 chip->dw->hdata->block_size[tmp] = carr[tmp]; 788 } 789 790 ret = device_property_read_u32_array(dev, "snps,priority", carr, 791 chip->dw->hdata->nr_channels); 792 if (ret) 793 return ret; 794 /* Priority value must be programmed within [0:nr_channels-1] range */ 795 for (tmp = 0; tmp < chip->dw->hdata->nr_channels; tmp++) { 796 if (carr[tmp] >= chip->dw->hdata->nr_channels) 797 return -EINVAL; 798 799 chip->dw->hdata->priority[tmp] = carr[tmp]; 800 } 801 802 /* axi-max-burst-len is optional property */ 803 ret = device_property_read_u32(dev, "snps,axi-max-burst-len", &tmp); 804 if (!ret) { 805 if (tmp > DWAXIDMAC_ARWLEN_MAX + 1) 806 return -EINVAL; 807 if (tmp < DWAXIDMAC_ARWLEN_MIN + 1) 808 return -EINVAL; 809 810 chip->dw->hdata->restrict_axi_burst_len = true; 811 chip->dw->hdata->axi_rw_burst_len = tmp - 1; 812 } 813 814 return 0; 815 } 816 817 static int dw_probe(struct platform_device *pdev) 818 { 819 struct axi_dma_chip *chip; 820 struct resource *mem; 821 struct dw_axi_dma *dw; 822 struct dw_axi_dma_hcfg *hdata; 823 u32 i; 824 int ret; 825 826 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 827 if (!chip) 828 return -ENOMEM; 829 830 dw = devm_kzalloc(&pdev->dev, sizeof(*dw), GFP_KERNEL); 831 if (!dw) 832 return -ENOMEM; 833 834 hdata = devm_kzalloc(&pdev->dev, sizeof(*hdata), GFP_KERNEL); 835 if (!hdata) 836 return -ENOMEM; 837 838 chip->dw = dw; 839 chip->dev = &pdev->dev; 840 chip->dw->hdata = hdata; 841 842 chip->irq = platform_get_irq(pdev, 0); 843 if (chip->irq < 0) 844 return chip->irq; 845 846 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 847 chip->regs = devm_ioremap_resource(chip->dev, mem); 848 if (IS_ERR(chip->regs)) 849 return PTR_ERR(chip->regs); 850 851 chip->core_clk = devm_clk_get(chip->dev, "core-clk"); 852 if (IS_ERR(chip->core_clk)) 853 return PTR_ERR(chip->core_clk); 854 855 chip->cfgr_clk = devm_clk_get(chip->dev, "cfgr-clk"); 856 if (IS_ERR(chip->cfgr_clk)) 857 return PTR_ERR(chip->cfgr_clk); 858 859 ret = parse_device_properties(chip); 860 if (ret) 861 return ret; 862 863 dw->chan = devm_kcalloc(chip->dev, hdata->nr_channels, 864 sizeof(*dw->chan), GFP_KERNEL); 865 if (!dw->chan) 866 return -ENOMEM; 867 868 ret = devm_request_irq(chip->dev, chip->irq, dw_axi_dma_interrupt, 869 IRQF_SHARED, KBUILD_MODNAME, chip); 870 if (ret) 871 return ret; 872 873 /* Lli address must be aligned to a 64-byte boundary */ 874 dw->desc_pool = dmam_pool_create(KBUILD_MODNAME, chip->dev, 875 sizeof(struct axi_dma_desc), 64, 0); 876 if (!dw->desc_pool) { 877 dev_err(chip->dev, "No memory for descriptors dma pool\n"); 878 return -ENOMEM; 879 } 880 881 INIT_LIST_HEAD(&dw->dma.channels); 882 for (i = 0; i < hdata->nr_channels; i++) { 883 struct axi_dma_chan *chan = &dw->chan[i]; 884 885 chan->chip = chip; 886 chan->id = i; 887 chan->chan_regs = chip->regs + COMMON_REG_LEN + i * CHAN_REG_LEN; 888 atomic_set(&chan->descs_allocated, 0); 889 890 chan->vc.desc_free = vchan_desc_put; 891 vchan_init(&chan->vc, &dw->dma); 892 } 893 894 /* Set capabilities */ 895 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); 896 897 /* DMA capabilities */ 898 dw->dma.chancnt = hdata->nr_channels; 899 dw->dma.src_addr_widths = AXI_DMA_BUSWIDTHS; 900 dw->dma.dst_addr_widths = AXI_DMA_BUSWIDTHS; 901 dw->dma.directions = BIT(DMA_MEM_TO_MEM); 902 dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; 903 904 dw->dma.dev = chip->dev; 905 dw->dma.device_tx_status = dma_chan_tx_status; 906 dw->dma.device_issue_pending = dma_chan_issue_pending; 907 dw->dma.device_terminate_all = dma_chan_terminate_all; 908 dw->dma.device_pause = dma_chan_pause; 909 dw->dma.device_resume = dma_chan_resume; 910 911 dw->dma.device_alloc_chan_resources = dma_chan_alloc_chan_resources; 912 dw->dma.device_free_chan_resources = dma_chan_free_chan_resources; 913 914 dw->dma.device_prep_dma_memcpy = dma_chan_prep_dma_memcpy; 915 916 platform_set_drvdata(pdev, chip); 917 918 pm_runtime_enable(chip->dev); 919 920 /* 921 * We can't just call pm_runtime_get here instead of 922 * pm_runtime_get_noresume + axi_dma_resume because we need 923 * driver to work also without Runtime PM. 924 */ 925 pm_runtime_get_noresume(chip->dev); 926 ret = axi_dma_resume(chip); 927 if (ret < 0) 928 goto err_pm_disable; 929 930 axi_dma_hw_init(chip); 931 932 pm_runtime_put(chip->dev); 933 934 ret = dmaenginem_async_device_register(&dw->dma); 935 if (ret) 936 goto err_pm_disable; 937 938 dev_info(chip->dev, "DesignWare AXI DMA Controller, %d channels\n", 939 dw->hdata->nr_channels); 940 941 return 0; 942 943 err_pm_disable: 944 pm_runtime_disable(chip->dev); 945 946 return ret; 947 } 948 949 static int dw_remove(struct platform_device *pdev) 950 { 951 struct axi_dma_chip *chip = platform_get_drvdata(pdev); 952 struct dw_axi_dma *dw = chip->dw; 953 struct axi_dma_chan *chan, *_chan; 954 u32 i; 955 956 /* Enable clk before accessing to registers */ 957 clk_prepare_enable(chip->cfgr_clk); 958 clk_prepare_enable(chip->core_clk); 959 axi_dma_irq_disable(chip); 960 for (i = 0; i < dw->hdata->nr_channels; i++) { 961 axi_chan_disable(&chip->dw->chan[i]); 962 axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL); 963 } 964 axi_dma_disable(chip); 965 966 pm_runtime_disable(chip->dev); 967 axi_dma_suspend(chip); 968 969 devm_free_irq(chip->dev, chip->irq, chip); 970 971 list_for_each_entry_safe(chan, _chan, &dw->dma.channels, 972 vc.chan.device_node) { 973 list_del(&chan->vc.chan.device_node); 974 tasklet_kill(&chan->vc.task); 975 } 976 977 return 0; 978 } 979 980 static const struct dev_pm_ops dw_axi_dma_pm_ops = { 981 SET_RUNTIME_PM_OPS(axi_dma_runtime_suspend, axi_dma_runtime_resume, NULL) 982 }; 983 984 static const struct of_device_id dw_dma_of_id_table[] = { 985 { .compatible = "snps,axi-dma-1.01a" }, 986 {} 987 }; 988 MODULE_DEVICE_TABLE(of, dw_dma_of_id_table); 989 990 static struct platform_driver dw_driver = { 991 .probe = dw_probe, 992 .remove = dw_remove, 993 .driver = { 994 .name = KBUILD_MODNAME, 995 .of_match_table = of_match_ptr(dw_dma_of_id_table), 996 .pm = &dw_axi_dma_pm_ops, 997 }, 998 }; 999 module_platform_driver(dw_driver); 1000 1001 MODULE_LICENSE("GPL v2"); 1002 MODULE_DESCRIPTION("Synopsys DesignWare AXI DMA Controller platform driver"); 1003 MODULE_AUTHOR("Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>"); 1004