1=============================================================================
2Freescale Frame Manager Device Bindings
3
4CONTENTS
5  - FMan Node
6  - FMan Port Node
7  - FMan MURAM Node
8  - FMan dTSEC/XGEC/mEMAC Node
9  - FMan IEEE 1588 Node
10  - FMan MDIO Node
11  - Example
12
13=============================================================================
14FMan Node
15
16DESCRIPTION
17
18Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
19etc.) the FMan node will have child nodes for each of them.
20
21PROPERTIES
22
23- compatible
24		Usage: required
25		Value type: <stringlist>
26		Definition: Must include "fsl,fman"
27		FMan version can be determined via FM_IP_REV_1 register in the
28		FMan block. The offset is 0xc4 from the beginning of the
29		Frame Processing Manager memory map (0xc3000 from the
30		beginning of the FMan node).
31
32- cell-index
33		Usage: required
34		Value type: <u32>
35		Definition: Specifies the index of the FMan unit.
36
37		The cell-index value may be used by the SoC, to identify the
38		FMan unit in the SoC memory map. In the table below,
39		there's a description of the cell-index use in each SoC:
40
41		- P1023:
42		register[bit]			FMan unit	cell-index
43		============================================================
44		DEVDISR[1]			1		0
45
46		- P2041, P3041, P4080 P5020, P5040:
47		register[bit]			FMan unit	cell-index
48		============================================================
49		DCFG_DEVDISR2[6]		1		0
50		DCFG_DEVDISR2[14]		2		1
51			(Second FM available only in P4080 and P5040)
52
53		- B4860, T1040, T2080, T4240:
54		register[bit]			FMan unit	cell-index
55		============================================================
56		DCFG_CCSR_DEVDISR2[24]		1		0
57		DCFG_CCSR_DEVDISR2[25]		2		1
58			(Second FM available only in T4240)
59
60		DEVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in
61		the specific SoC "Device Configuration/Pin Control" Memory
62		Map.
63
64- reg
65		Usage: required
66		Value type: <prop-encoded-array>
67		Definition: A standard property. Specifies the offset of the
68		following configuration registers:
69		- BMI configuration registers.
70		- QMI configuration registers.
71		- DMA configuration registers.
72		- FPM configuration registers.
73		- FMan controller configuration registers.
74
75- ranges
76		Usage: required
77		Value type: <prop-encoded-array>
78		Definition: A standard property.
79
80- clocks
81		Usage: required
82		Value type: <prop-encoded-array>
83		Definition: phandle for the fman input clock.
84
85- clock-names
86		usage: required
87		Value type: <stringlist>
88		Definition: "fmanclk" for the fman input clock.
89
90- interrupts
91		Usage: required
92		Value type: <prop-encoded-array>
93		Definition: A pair of IRQs are specified in this property.
94		The first element is associated with the event interrupts and
95		the second element is associated with the error interrupts.
96
97- fsl,qman-channel-range
98		Usage: required
99		Value type: <prop-encoded-array>
100		Definition: Specifies the range of the available dedicated
101		channels in the FMan. The first cell specifies the beginning
102		of the range and the second cell specifies the number of
103		channels.
104		Further information available at:
105		"Work Queue (WQ) Channel Assignments in the QMan" section
106		in DPAA Reference Manual.
107
108- fsl,qman
109- fsl,bman
110		Usage: required
111		Definition: See soc/fsl/qman.txt and soc/fsl/bman.txt
112
113=============================================================================
114FMan MURAM Node
115
116DESCRIPTION
117
118FMan Internal memory - shared between all the FMan modules.
119It contains data structures that are common and written to or read by
120the modules.
121FMan internal memory is split into the following parts:
122	Packet buffering (Tx/Rx FIFOs)
123	Frames internal context
124
125PROPERTIES
126
127- compatible
128		Usage: required
129		Value type: <stringlist>
130		Definition: Must include "fsl,fman-muram"
131
132- ranges
133		Usage: required
134		Value type: <prop-encoded-array>
135		Definition: A standard property.
136		Specifies the multi-user memory offset and the size within
137		the FMan.
138
139EXAMPLE
140
141muram@0 {
142	compatible = "fsl,fman-muram";
143	ranges = <0 0x000000 0x28000>;
144};
145
146=============================================================================
147FMan Port Node
148
149DESCRIPTION
150
151The Frame Manager (FMan) supports several types of hardware ports:
152	Ethernet receiver (RX)
153	Ethernet transmitter (TX)
154	Offline/Host command (O/H)
155
156PROPERTIES
157
158- compatible
159		Usage: required
160		Value type: <stringlist>
161		Definition: A standard property.
162		Must include one of the following:
163			- "fsl,fman-v2-port-oh" for FManV2 OH ports
164			- "fsl,fman-v2-port-rx" for FManV2 RX ports
165			- "fsl,fman-v2-port-tx" for FManV2 TX ports
166			- "fsl,fman-v3-port-oh" for FManV3 OH ports
167			- "fsl,fman-v3-port-rx" for FManV3 RX ports
168			- "fsl,fman-v3-port-tx" for FManV3 TX ports
169
170- cell-index
171		Usage: required
172		Value type: <u32>
173		Definition: Specifies the hardware port id.
174		Each hardware port on the FMan has its own hardware PortID.
175		Super set of all hardware Port IDs available at FMan Reference
176		Manual under "FMan Hardware Ports in Freescale Devices" table.
177
178		Each hardware port is assigned a 4KB, port-specific page in
179		the FMan hardware port memory region (which is part of the
180		FMan memory map). The first 4 KB in the FMan hardware ports
181		memory region is used for what are called common registers.
182		The subsequent 63 4KB pages are allocated to the hardware
183		ports.
184		The page of a specific port is determined by the cell-index.
185
186- reg
187		Usage: required
188		Value type: <prop-encoded-array>
189		Definition: There is one reg region describing the port
190		configuration registers.
191
192- fsl,fman-10g-port
193		Usage: optional
194		Value type: boolean
195		Definition: The default port rate is 1G.
196		If this property exists, the port is s 10G port.
197
198- fsl,fman-best-effort-port
199		Usage: optional
200		Value type: boolean
201		Definition: Can be defined only if 10G-support is set.
202		This property marks a best-effort 10G port (10G port that
203		may not be capable of line rate).
204
205EXAMPLE
206
207port@a8000 {
208	cell-index = <0x28>;
209	compatible = "fsl,fman-v2-port-tx";
210	reg = <0xa8000 0x1000>;
211};
212
213port@88000 {
214	cell-index = <0x8>;
215	compatible = "fsl,fman-v2-port-rx";
216	reg = <0x88000 0x1000>;
217};
218
219port@81000 {
220	cell-index = <0x1>;
221	compatible = "fsl,fman-v2-port-oh";
222	reg = <0x81000 0x1000>;
223};
224
225=============================================================================
226FMan dTSEC/XGEC/mEMAC Node
227
228DESCRIPTION
229
230mEMAC/dTSEC/XGEC are the Ethernet network interfaces
231
232PROPERTIES
233
234- compatible
235		Usage: required
236		Value type: <stringlist>
237		Definition: A standard property.
238		Must include one of the following:
239		- "fsl,fman-dtsec" for dTSEC MAC
240		- "fsl,fman-xgec" for XGEC MAC
241		- "fsl,fman-memac" for mEMAC MAC
242
243- cell-index
244		Usage: required
245		Value type: <u32>
246		Definition: Specifies the MAC id.
247
248		The cell-index value may be used by the FMan or the SoC, to
249		identify the MAC unit in the FMan (or SoC) memory map.
250		In the tables below there's a description of the cell-index
251		use, there are two tables, one describes the use of cell-index
252		by the FMan, the second describes the use by the SoC:
253
254		1. FMan Registers
255
256		FManV2:
257		register[bit]		MAC		cell-index
258		============================================================
259		FM_EPI[16]		XGEC		8
260		FM_EPI[16+n]		dTSECn		n-1
261		FM_NPI[11+n]		dTSECn		n-1
262			n = 1,..,5
263
264		FManV3:
265		register[bit]		MAC		cell-index
266		============================================================
267		FM_EPI[16+n]		mEMACn		n-1
268		FM_EPI[25]		mEMAC10		9
269
270		FM_NPI[11+n]		mEMACn		n-1
271		FM_NPI[10]		mEMAC10		9
272		FM_NPI[11]		mEMAC9		8
273			n = 1,..8
274
275		FM_EPI and FM_NPI are located in the FMan memory map.
276
277		2. SoC registers:
278
279		- P2041, P3041, P4080 P5020, P5040:
280		register[bit]		FMan		MAC		cell
281					Unit				index
282		============================================================
283		DCFG_DEVDISR2[7]	1		XGEC		8
284		DCFG_DEVDISR2[7+n]	1		dTSECn		n-1
285		DCFG_DEVDISR2[15]	2		XGEC		8
286		DCFG_DEVDISR2[15+n]	2		dTSECn		n-1
287			n = 1,..5
288
289		- T1040, T2080, T4240, B4860:
290		register[bit]			FMan	MAC		cell
291						Unit			index
292		============================================================
293		DCFG_CCSR_DEVDISR2[n-1]		1	mEMACn		n-1
294		DCFG_CCSR_DEVDISR2[11+n]	2	mEMACn		n-1
295			n = 1,..6,9,10
296
297		EVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in
298		the specific SoC "Device Configuration/Pin Control" Memory
299		Map.
300
301- reg
302		Usage: required
303		Value type: <prop-encoded-array>
304		Definition: A standard property.
305
306- fsl,fman-ports
307		Usage: required
308		Value type: <prop-encoded-array>
309		Definition: An array of two phandles - the first references is
310		the FMan RX port and the second is the TX port used by this
311		MAC.
312
313- ptp-timer
314		Usage required
315		Value type: <phandle>
316		Definition: A phandle for 1EEE1588 timer.
317
318- pcsphy-handle
319		Usage required for "fsl,fman-memac" MACs
320		Value type: <phandle>
321		Definition: A phandle for pcsphy.
322
323- tbi-handle
324		Usage required for "fsl,fman-dtsec" MACs
325		Value type: <phandle>
326		Definition: A phandle for tbiphy.
327
328EXAMPLE
329
330fman1_tx28: port@a8000 {
331	cell-index = <0x28>;
332	compatible = "fsl,fman-v2-port-tx";
333	reg = <0xa8000 0x1000>;
334};
335
336fman1_rx8: port@88000 {
337	cell-index = <0x8>;
338	compatible = "fsl,fman-v2-port-rx";
339	reg = <0x88000 0x1000>;
340};
341
342ptp-timer: ptp_timer@fe000 {
343	compatible = "fsl,fman-ptp-timer";
344	reg = <0xfe000 0x1000>;
345};
346
347ethernet@e0000 {
348	compatible = "fsl,fman-dtsec";
349	cell-index = <0>;
350	reg = <0xe0000 0x1000>;
351	fsl,fman-ports = <&fman1_rx8 &fman1_tx28>;
352	ptp-timer = <&ptp-timer>;
353	tbi-handle = <&tbi0>;
354};
355
356============================================================================
357FMan IEEE 1588 Node
358
359Refer to Documentation/devicetree/bindings/ptp/ptp-qoriq.txt
360
361=============================================================================
362FMan MDIO Node
363
364DESCRIPTION
365
366The MDIO is a bus to which the PHY devices are connected.
367
368PROPERTIES
369
370- compatible
371		Usage: required
372		Value type: <stringlist>
373		Definition: A standard property.
374		Must include "fsl,fman-mdio" for 1 Gb/s MDIO from FMan v2.
375		Must include "fsl,fman-xmdio" for 10 Gb/s MDIO from FMan v2.
376		Must include "fsl,fman-memac-mdio" for 1/10 Gb/s MDIO from
377		FMan v3.
378
379- reg
380		Usage: required
381		Value type: <prop-encoded-array>
382		Definition: A standard property.
383
384- bus-frequency
385		Usage: optional
386		Value type: <u32>
387		Definition: Specifies the external MDIO bus clock speed to
388		be used, if different from the standard 2.5 MHz.
389		This may be due to the standard speed being unsupported (e.g.
390		due to a hardware problem), or to advertise that all relevant
391		components in the system support a faster speed.
392
393- interrupts
394		Usage: required for external MDIO
395		Value type: <prop-encoded-array>
396		Definition: Event interrupt of external MDIO controller.
397
398- fsl,fman-internal-mdio
399		Usage: required for internal MDIO
400		Value type: boolean
401		Definition: Fman has internal MDIO for internal PCS(Physical
402		Coding Sublayer) PHYs and external MDIO for external PHYs.
403		The settings and programming routines for internal/external
404		MDIO are different. Must be included for internal MDIO.
405
406- fsl,erratum-a011043
407		Usage: optional
408		Value type: <boolean>
409		Definition: Indicates the presence of the A011043 erratum
410		describing that the MDIO_CFG[MDIO_RD_ER] bit may be falsely
411		set when reading internal PCS registers. MDIO reads to
412		internal PCS registers may result in having the
413		MDIO_CFG[MDIO_RD_ER] bit set, even when there is no error and
414		read data (MDIO_DATA[MDIO_DATA]) is correct.
415		Software may get false read error when reading internal
416		PCS registers through MDIO. As a workaround, all internal
417		MDIO accesses should ignore the MDIO_CFG[MDIO_RD_ER] bit.
418
419For internal PHY device on internal mdio bus, a PHY node should be created.
420See the definition of the PHY node in booting-without-of.txt for an
421example of how to define a PHY (Internal PHY has no interrupt line).
422- For "fsl,fman-mdio" compatible internal mdio bus, the PHY is TBI PHY.
423- For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY,
424  PCS PHY addr must be '0'.
425
426EXAMPLE
427
428Example for FMan v2 external MDIO:
429
430mdio@f1000 {
431	compatible = "fsl,fman-xmdio";
432	reg = <0xf1000 0x1000>;
433	interrupts = <101 2 0 0>;
434};
435
436Example for FMan v2 internal MDIO:
437
438mdio@e3120 {
439	compatible = "fsl,fman-mdio";
440	reg = <0xe3120 0xee0>;
441	fsl,fman-internal-mdio;
442
443	tbi1: tbi-phy@8 {
444		reg = <0x8>;
445		device_type = "tbi-phy";
446	};
447};
448
449Example for FMan v3 internal MDIO:
450
451mdio@f1000 {
452	compatible = "fsl,fman-memac-mdio";
453	reg = <0xf1000 0x1000>;
454	fsl,fman-internal-mdio;
455
456	pcsphy6: ethernet-phy@0 {
457		reg = <0x0>;
458	};
459};
460
461=============================================================================
462Example
463
464fman@400000 {
465	#address-cells = <1>;
466	#size-cells = <1>;
467	cell-index = <1>;
468	compatible = "fsl,fman"
469	ranges = <0 0x400000 0x100000>;
470	reg = <0x400000 0x100000>;
471	clocks = <&fman_clk>;
472	clock-names = "fmanclk";
473	interrupts = <
474		96 2 0 0
475		16 2 1 1>;
476	fsl,qman-channel-range = <0x40 0xc>;
477
478	muram@0 {
479		compatible = "fsl,fman-muram";
480		reg = <0x0 0x28000>;
481	};
482
483	port@81000 {
484		cell-index = <1>;
485		compatible = "fsl,fman-v2-port-oh";
486		reg = <0x81000 0x1000>;
487	};
488
489	port@82000 {
490		cell-index = <2>;
491		compatible = "fsl,fman-v2-port-oh";
492		reg = <0x82000 0x1000>;
493	};
494
495	port@83000 {
496		cell-index = <3>;
497		compatible = "fsl,fman-v2-port-oh";
498		reg = <0x83000 0x1000>;
499	};
500
501	port@84000 {
502		cell-index = <4>;
503		compatible = "fsl,fman-v2-port-oh";
504		reg = <0x84000 0x1000>;
505	};
506
507	port@85000 {
508		cell-index = <5>;
509		compatible = "fsl,fman-v2-port-oh";
510		reg = <0x85000 0x1000>;
511	};
512
513	port@86000 {
514		cell-index = <6>;
515		compatible = "fsl,fman-v2-port-oh";
516		reg = <0x86000 0x1000>;
517	};
518
519	fman1_rx_0x8: port@88000 {
520		cell-index = <0x8>;
521		compatible = "fsl,fman-v2-port-rx";
522		reg = <0x88000 0x1000>;
523	};
524
525	fman1_rx_0x9: port@89000 {
526		cell-index = <0x9>;
527		compatible = "fsl,fman-v2-port-rx";
528		reg = <0x89000 0x1000>;
529	};
530
531	fman1_rx_0xa: port@8a000 {
532		cell-index = <0xa>;
533		compatible = "fsl,fman-v2-port-rx";
534		reg = <0x8a000 0x1000>;
535	};
536
537	fman1_rx_0xb: port@8b000 {
538		cell-index = <0xb>;
539		compatible = "fsl,fman-v2-port-rx";
540		reg = <0x8b000 0x1000>;
541	};
542
543	fman1_rx_0xc: port@8c000 {
544		cell-index = <0xc>;
545		compatible = "fsl,fman-v2-port-rx";
546		reg = <0x8c000 0x1000>;
547	};
548
549	fman1_rx_0x10: port@90000 {
550		cell-index = <0x10>;
551		compatible = "fsl,fman-v2-port-rx";
552		reg = <0x90000 0x1000>;
553	};
554
555	fman1_tx_0x28: port@a8000 {
556		cell-index = <0x28>;
557		compatible = "fsl,fman-v2-port-tx";
558		reg = <0xa8000 0x1000>;
559	};
560
561	fman1_tx_0x29: port@a9000 {
562		cell-index = <0x29>;
563		compatible = "fsl,fman-v2-port-tx";
564		reg = <0xa9000 0x1000>;
565	};
566
567	fman1_tx_0x2a: port@aa000 {
568		cell-index = <0x2a>;
569		compatible = "fsl,fman-v2-port-tx";
570		reg = <0xaa000 0x1000>;
571	};
572
573	fman1_tx_0x2b: port@ab000 {
574		cell-index = <0x2b>;
575		compatible = "fsl,fman-v2-port-tx";
576		reg = <0xab000 0x1000>;
577	};
578
579	fman1_tx_0x2c: port@ac0000 {
580		cell-index = <0x2c>;
581		compatible = "fsl,fman-v2-port-tx";
582		reg = <0xac000 0x1000>;
583	};
584
585	fman1_tx_0x30: port@b0000 {
586		cell-index = <0x30>;
587		compatible = "fsl,fman-v2-port-tx";
588		reg = <0xb0000 0x1000>;
589	};
590
591	ethernet@e0000 {
592		compatible = "fsl,fman-dtsec";
593		cell-index = <0>;
594		reg = <0xe0000 0x1000>;
595		fsl,fman-ports = <&fman1_rx_0x8 &fman1_tx_0x28>;
596		tbi-handle = <&tbi5>;
597	};
598
599	ethernet@e2000 {
600		compatible = "fsl,fman-dtsec";
601		cell-index = <1>;
602		reg = <0xe2000 0x1000>;
603		fsl,fman-ports = <&fman1_rx_0x9 &fman1_tx_0x29>;
604		tbi-handle = <&tbi6>;
605	};
606
607	ethernet@e4000 {
608		compatible = "fsl,fman-dtsec";
609		cell-index = <2>;
610		reg = <0xe4000 0x1000>;
611		fsl,fman-ports = <&fman1_rx_0xa &fman1_tx_0x2a>;
612		tbi-handle = <&tbi7>;
613	};
614
615	ethernet@e6000 {
616		compatible = "fsl,fman-dtsec";
617		cell-index = <3>;
618		reg = <0xe6000 0x1000>;
619		fsl,fman-ports = <&fman1_rx_0xb &fman1_tx_0x2b>;
620		tbi-handle = <&tbi8>;
621	};
622
623	ethernet@e8000 {
624		compatible = "fsl,fman-dtsec";
625		cell-index = <4>;
626		reg = <0xf0000 0x1000>;
627		fsl,fman-ports = <&fman1_rx_0xc &fman1_tx_0x2c>;
628		tbi-handle = <&tbi9>;
629
630	ethernet@f0000 {
631		cell-index = <8>;
632		compatible = "fsl,fman-xgec";
633		reg = <0xf0000 0x1000>;
634		fsl,fman-ports = <&fman1_rx_0x10 &fman1_tx_0x30>;
635	};
636
637	ptp-timer@fe000 {
638		compatible = "fsl,fman-ptp-timer";
639		reg = <0xfe000 0x1000>;
640	};
641
642	mdio@f1000 {
643		compatible = "fsl,fman-xmdio";
644		reg = <0xf1000 0x1000>;
645		interrupts = <101 2 0 0>;
646	};
647};
648