1=========================== 2 drm/i915 Intel GFX Driver 3=========================== 4 5The drm/i915 driver supports all (with the exception of some very early 6models) integrated GFX chipsets with both Intel display and rendering 7blocks. This excludes a set of SoC platforms with an SGX rendering unit, 8those have basic support through the gma500 drm driver. 9 10Core Driver Infrastructure 11========================== 12 13This section covers core driver infrastructure used by both the display 14and the GEM parts of the driver. 15 16Runtime Power Management 17------------------------ 18 19.. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c 20 :doc: runtime pm 21 22.. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c 23 :internal: 24 25.. kernel-doc:: drivers/gpu/drm/i915/intel_uncore.c 26 :internal: 27 28Interrupt Handling 29------------------ 30 31.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c 32 :doc: interrupt handling 33 34.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c 35 :functions: intel_irq_init intel_irq_init_hw intel_hpd_init 36 37.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c 38 :functions: intel_runtime_pm_disable_interrupts 39 40.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c 41 :functions: intel_runtime_pm_enable_interrupts 42 43Intel GVT-g Guest Support(vGPU) 44------------------------------- 45 46.. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c 47 :doc: Intel GVT-g guest support 48 49.. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c 50 :internal: 51 52Intel GVT-g Host Support(vGPU device model) 53------------------------------------------- 54 55.. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c 56 :doc: Intel GVT-g host support 57 58.. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c 59 :internal: 60 61Workarounds 62----------- 63 64.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_workarounds.c 65 :doc: Hardware workarounds 66 67Display Hardware Handling 68========================= 69 70This section covers everything related to the display hardware including 71the mode setting infrastructure, plane, sprite and cursor handling and 72display, output probing and related topics. 73 74Mode Setting Infrastructure 75--------------------------- 76 77The i915 driver is thus far the only DRM driver which doesn't use the 78common DRM helper code to implement mode setting sequences. Thus it has 79its own tailor-made infrastructure for executing a display configuration 80change. 81 82Frontbuffer Tracking 83-------------------- 84 85.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c 86 :doc: frontbuffer tracking 87 88.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.h 89 :internal: 90 91.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c 92 :internal: 93 94Display FIFO Underrun Reporting 95------------------------------- 96 97.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c 98 :doc: fifo underrun handling 99 100.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c 101 :internal: 102 103Plane Configuration 104------------------- 105 106This section covers plane configuration and composition with the primary 107plane, sprites, cursors and overlays. This includes the infrastructure 108to do atomic vsync'ed updates of all this state and also tightly coupled 109topics like watermark setup and computation, framebuffer compression and 110panel self refresh. 111 112Atomic Plane Helpers 113-------------------- 114 115.. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic_plane.c 116 :doc: atomic plane helpers 117 118.. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic_plane.c 119 :internal: 120 121Output Probing 122-------------- 123 124This section covers output probing and related infrastructure like the 125hotplug interrupt storm detection and mitigation code. Note that the 126i915 driver still uses most of the common DRM helper code for output 127probing, so those sections fully apply. 128 129Hotplug 130------- 131 132.. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c 133 :doc: Hotplug 134 135.. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c 136 :internal: 137 138High Definition Audio 139--------------------- 140 141.. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c 142 :doc: High Definition Audio over HDMI and Display Port 143 144.. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c 145 :internal: 146 147.. kernel-doc:: include/drm/i915_component.h 148 :internal: 149 150Intel HDMI LPE Audio Support 151---------------------------- 152 153.. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c 154 :doc: LPE Audio integration for HDMI or DP playback 155 156.. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c 157 :internal: 158 159Panel Self Refresh PSR (PSR/SRD) 160-------------------------------- 161 162.. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c 163 :doc: Panel Self Refresh (PSR/SRD) 164 165.. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c 166 :internal: 167 168Frame Buffer Compression (FBC) 169------------------------------ 170 171.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c 172 :doc: Frame Buffer Compression (FBC) 173 174.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c 175 :internal: 176 177Display Refresh Rate Switching (DRRS) 178------------------------------------- 179 180.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c 181 :doc: Display Refresh Rate Switching (DRRS) 182 183.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c 184 :functions: intel_dp_set_drrs_state 185 186.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c 187 :functions: intel_edp_drrs_enable 188 189.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c 190 :functions: intel_edp_drrs_disable 191 192.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c 193 :functions: intel_edp_drrs_invalidate 194 195.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c 196 :functions: intel_edp_drrs_flush 197 198.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c 199 :functions: intel_dp_drrs_init 200 201DPIO 202---- 203 204.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpio_phy.c 205 :doc: DPIO 206 207CSR firmware support for DMC 208---------------------------- 209 210.. kernel-doc:: drivers/gpu/drm/i915/display/intel_csr.c 211 :doc: csr support for dmc 212 213.. kernel-doc:: drivers/gpu/drm/i915/display/intel_csr.c 214 :internal: 215 216Video BIOS Table (VBT) 217---------------------- 218 219.. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c 220 :doc: Video BIOS Table (VBT) 221 222.. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c 223 :internal: 224 225.. kernel-doc:: drivers/gpu/drm/i915/display/intel_vbt_defs.h 226 :internal: 227 228Display clocks 229-------------- 230 231.. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c 232 :doc: CDCLK / RAWCLK 233 234.. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c 235 :internal: 236 237Display PLLs 238------------ 239 240.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c 241 :doc: Display PLLs 242 243.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c 244 :internal: 245 246.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.h 247 :internal: 248 249Display State Buffer 250-------------------- 251 252.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c 253 :doc: DSB 254 255.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c 256 :internal: 257 258Memory Management and Command Submission 259======================================== 260 261This sections covers all things related to the GEM implementation in the 262i915 driver. 263 264Intel GPU Basics 265---------------- 266 267An Intel GPU has multiple engines. There are several engine types. 268 269- RCS engine is for rendering 3D and performing compute, this is named 270 `I915_EXEC_RENDER` in user space. 271- BCS is a blitting (copy) engine, this is named `I915_EXEC_BLT` in user 272 space. 273- VCS is a video encode and decode engine, this is named `I915_EXEC_BSD` 274 in user space 275- VECS is video enhancement engine, this is named `I915_EXEC_VEBOX` in user 276 space. 277- The enumeration `I915_EXEC_DEFAULT` does not refer to specific engine; 278 instead it is to be used by user space to specify a default rendering 279 engine (for 3D) that may or may not be the same as RCS. 280 281The Intel GPU family is a family of integrated GPU's using Unified 282Memory Access. For having the GPU "do work", user space will feed the 283GPU batch buffers via one of the ioctls `DRM_IOCTL_I915_GEM_EXECBUFFER2` 284or `DRM_IOCTL_I915_GEM_EXECBUFFER2_WR`. Most such batchbuffers will 285instruct the GPU to perform work (for example rendering) and that work 286needs memory from which to read and memory to which to write. All memory 287is encapsulated within GEM buffer objects (usually created with the ioctl 288`DRM_IOCTL_I915_GEM_CREATE`). An ioctl providing a batchbuffer for the GPU 289to create will also list all GEM buffer objects that the batchbuffer reads 290and/or writes. For implementation details of memory management see 291`GEM BO Management Implementation Details`_. 292 293The i915 driver allows user space to create a context via the ioctl 294`DRM_IOCTL_I915_GEM_CONTEXT_CREATE` which is identified by a 32-bit 295integer. Such a context should be viewed by user-space as -loosely- 296analogous to the idea of a CPU process of an operating system. The i915 297driver guarantees that commands issued to a fixed context are to be 298executed so that writes of a previously issued command are seen by 299reads of following commands. Actions issued between different contexts 300(even if from the same file descriptor) are NOT given that guarantee 301and the only way to synchronize across contexts (even from the same 302file descriptor) is through the use of fences. At least as far back as 303Gen4, also have that a context carries with it a GPU HW context; 304the HW context is essentially (most of atleast) the state of a GPU. 305In addition to the ordering guarantees, the kernel will restore GPU 306state via HW context when commands are issued to a context, this saves 307user space the need to restore (most of atleast) the GPU state at the 308start of each batchbuffer. The non-deprecated ioctls to submit batchbuffer 309work can pass that ID (in the lower bits of drm_i915_gem_execbuffer2::rsvd1) 310to identify what context to use with the command. 311 312The GPU has its own memory management and address space. The kernel 313driver maintains the memory translation table for the GPU. For older 314GPUs (i.e. those before Gen8), there is a single global such translation 315table, a global Graphics Translation Table (GTT). For newer generation 316GPUs each context has its own translation table, called Per-Process 317Graphics Translation Table (PPGTT). Of important note, is that although 318PPGTT is named per-process it is actually per context. When user space 319submits a batchbuffer, the kernel walks the list of GEM buffer objects 320used by the batchbuffer and guarantees that not only is the memory of 321each such GEM buffer object resident but it is also present in the 322(PP)GTT. If the GEM buffer object is not yet placed in the (PP)GTT, 323then it is given an address. Two consequences of this are: the kernel 324needs to edit the batchbuffer submitted to write the correct value of 325the GPU address when a GEM BO is assigned a GPU address and the kernel 326might evict a different GEM BO from the (PP)GTT to make address room 327for another GEM BO. Consequently, the ioctls submitting a batchbuffer 328for execution also include a list of all locations within buffers that 329refer to GPU-addresses so that the kernel can edit the buffer correctly. 330This process is dubbed relocation. 331 332Locking Guidelines 333------------------ 334 335.. note:: 336 This is a description of how the locking should be after 337 refactoring is done. Does not necessarily reflect what the locking 338 looks like while WIP. 339 340#. All locking rules and interface contracts with cross-driver interfaces 341 (dma-buf, dma_fence) need to be followed. 342 343#. No struct_mutex anywhere in the code 344 345#. dma_resv will be the outermost lock (when needed) and ww_acquire_ctx 346 is to be hoisted at highest level and passed down within i915_gem_ctx 347 in the call chain 348 349#. While holding lru/memory manager (buddy, drm_mm, whatever) locks 350 system memory allocations are not allowed 351 352 * Enforce this by priming lockdep (with fs_reclaim). If we 353 allocate memory while holding these looks we get a rehash 354 of the shrinker vs. struct_mutex saga, and that would be 355 real bad. 356 357#. Do not nest different lru/memory manager locks within each other. 358 Take them in turn to update memory allocations, relying on the object’s 359 dma_resv ww_mutex to serialize against other operations. 360 361#. The suggestion for lru/memory managers locks is that they are small 362 enough to be spinlocks. 363 364#. All features need to come with exhaustive kernel selftests and/or 365 IGT tests when appropriate 366 367#. All LMEM uAPI paths need to be fully restartable (_interruptible() 368 for all locks/waits/sleeps) 369 370 * Error handling validation through signal injection. 371 Still the best strategy we have for validating GEM uAPI 372 corner cases. 373 Must be excessively used in the IGT, and we need to check 374 that we really have full path coverage of all error cases. 375 376 * -EDEADLK handling with ww_mutex 377 378GEM BO Management Implementation Details 379---------------------------------------- 380 381.. kernel-doc:: drivers/gpu/drm/i915/i915_vma_types.h 382 :doc: Virtual Memory Address 383 384Buffer Object Eviction 385---------------------- 386 387This section documents the interface functions for evicting buffer 388objects to make space available in the virtual gpu address spaces. Note 389that this is mostly orthogonal to shrinking buffer objects caches, which 390has the goal to make main memory (shared with the gpu through the 391unified memory architecture) available. 392 393.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_evict.c 394 :internal: 395 396Buffer Object Memory Shrinking 397------------------------------ 398 399This section documents the interface function for shrinking memory usage 400of buffer object caches. Shrinking is used to make main memory 401available. Note that this is mostly orthogonal to evicting buffer 402objects, which has the goal to make space in gpu virtual address spaces. 403 404.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_shrinker.c 405 :internal: 406 407Batchbuffer Parsing 408------------------- 409 410.. kernel-doc:: drivers/gpu/drm/i915/i915_cmd_parser.c 411 :doc: batch buffer command parser 412 413.. kernel-doc:: drivers/gpu/drm/i915/i915_cmd_parser.c 414 :internal: 415 416User Batchbuffer Execution 417-------------------------- 418 419.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 420 :doc: User command execution 421 422Logical Rings, Logical Ring Contexts and Execlists 423-------------------------------------------------- 424 425.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_lrc.c 426 :doc: Logical Rings, Logical Ring Contexts and Execlists 427 428Global GTT views 429---------------- 430 431.. kernel-doc:: drivers/gpu/drm/i915/i915_vma_types.h 432 :doc: Global GTT views 433 434.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_gtt.c 435 :internal: 436 437GTT Fences and Swizzling 438------------------------ 439 440.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c 441 :internal: 442 443Global GTT Fence Handling 444~~~~~~~~~~~~~~~~~~~~~~~~~ 445 446.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c 447 :doc: fence register handling 448 449Hardware Tiling and Swizzling Details 450~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 451 452.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c 453 :doc: tiling swizzling details 454 455Object Tiling IOCTLs 456-------------------- 457 458.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c 459 :internal: 460 461.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c 462 :doc: buffer object tiling 463 464Microcontrollers 465================ 466 467Starting from gen9, three microcontrollers are available on the HW: the 468graphics microcontroller (GuC), the HEVC/H.265 microcontroller (HuC) and the 469display microcontroller (DMC). The driver is responsible for loading the 470firmwares on the microcontrollers; the GuC and HuC firmwares are transferred 471to WOPCM using the DMA engine, while the DMC firmware is written through MMIO. 472 473WOPCM 474----- 475 476WOPCM Layout 477~~~~~~~~~~~~ 478 479.. kernel-doc:: drivers/gpu/drm/i915/intel_wopcm.c 480 :doc: WOPCM Layout 481 482GuC 483--- 484 485.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c 486 :doc: GuC 487 488GuC Firmware Layout 489~~~~~~~~~~~~~~~~~~~ 490 491.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h 492 :doc: Firmware Layout 493 494GuC Memory Management 495~~~~~~~~~~~~~~~~~~~~~ 496 497.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c 498 :doc: GuC Memory Management 499.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c 500 :functions: intel_guc_allocate_vma 501 502 503GuC-specific firmware loader 504~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 505 506.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c 507 :internal: 508 509GuC-based command submission 510~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 511 512.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 513 :doc: GuC-based command submission 514 515HuC 516--- 517.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c 518 :doc: HuC 519.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c 520 :functions: intel_huc_auth 521 522HuC Memory Management 523~~~~~~~~~~~~~~~~~~~~~ 524 525.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c 526 :doc: HuC Memory Management 527 528HuC Firmware Layout 529~~~~~~~~~~~~~~~~~~~ 530The HuC FW layout is the same as the GuC one, see `GuC Firmware Layout`_ 531 532DMC 533--- 534See `CSR firmware support for DMC`_ 535 536Tracing 537======= 538 539This sections covers all things related to the tracepoints implemented 540in the i915 driver. 541 542i915_ppgtt_create and i915_ppgtt_release 543---------------------------------------- 544 545.. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h 546 :doc: i915_ppgtt_create and i915_ppgtt_release tracepoints 547 548i915_context_create and i915_context_free 549----------------------------------------- 550 551.. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h 552 :doc: i915_context_create and i915_context_free tracepoints 553 554Perf 555==== 556 557Overview 558-------- 559.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 560 :doc: i915 Perf Overview 561 562Comparison with Core Perf 563------------------------- 564.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 565 :doc: i915 Perf History and Comparison with Core Perf 566 567i915 Driver Entry Points 568------------------------ 569 570This section covers the entrypoints exported outside of i915_perf.c to 571integrate with drm/i915 and to handle the `DRM_I915_PERF_OPEN` ioctl. 572 573.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 574 :functions: i915_perf_init 575.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 576 :functions: i915_perf_fini 577.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 578 :functions: i915_perf_register 579.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 580 :functions: i915_perf_unregister 581.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 582 :functions: i915_perf_open_ioctl 583.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 584 :functions: i915_perf_release 585.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 586 :functions: i915_perf_add_config_ioctl 587.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 588 :functions: i915_perf_remove_config_ioctl 589 590i915 Perf Stream 591---------------- 592 593This section covers the stream-semantics-agnostic structures and functions 594for representing an i915 perf stream FD and associated file operations. 595 596.. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h 597 :functions: i915_perf_stream 598.. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h 599 :functions: i915_perf_stream_ops 600 601.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 602 :functions: read_properties_unlocked 603.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 604 :functions: i915_perf_open_ioctl_locked 605.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 606 :functions: i915_perf_destroy_locked 607.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 608 :functions: i915_perf_read 609.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 610 :functions: i915_perf_ioctl 611.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 612 :functions: i915_perf_enable_locked 613.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 614 :functions: i915_perf_disable_locked 615.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 616 :functions: i915_perf_poll 617.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 618 :functions: i915_perf_poll_locked 619 620i915 Perf Observation Architecture Stream 621----------------------------------------- 622 623.. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h 624 :functions: i915_oa_ops 625 626.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 627 :functions: i915_oa_stream_init 628.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 629 :functions: i915_oa_read 630.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 631 :functions: i915_oa_stream_enable 632.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 633 :functions: i915_oa_stream_disable 634.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 635 :functions: i915_oa_wait_unlocked 636.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 637 :functions: i915_oa_poll_wait 638 639All i915 Perf Internals 640----------------------- 641 642This section simply includes all currently documented i915 perf internals, in 643no particular order, but may include some more minor utilities or platform 644specific details than found in the more high-level sections. 645 646.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 647 :internal: 648 649Style 650===== 651 652The drm/i915 driver codebase has some style rules in addition to (and, in some 653cases, deviating from) the kernel coding style. 654 655Register macro definition style 656------------------------------- 657 658The style guide for ``i915_reg.h``. 659 660.. kernel-doc:: drivers/gpu/drm/i915/i915_reg.h 661 :doc: The i915 register macro definition style guide 662