1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #include <linux/kthread.h> 25 #include <linux/wait.h> 26 #include <linux/sched.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_trace.h" 30 31 static void amdgpu_job_timedout(struct drm_sched_job *s_job) 32 { 33 struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched); 34 struct amdgpu_job *job = to_amdgpu_job(s_job); 35 struct amdgpu_task_info ti; 36 37 memset(&ti, 0, sizeof(struct amdgpu_task_info)); 38 39 if (amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) { 40 DRM_ERROR("ring %s timeout, but soft recovered\n", 41 s_job->sched->name); 42 return; 43 } 44 45 amdgpu_vm_get_task_info(ring->adev, job->pasid, &ti); 46 DRM_ERROR("ring %s timeout, signaled seq=%u, emitted seq=%u\n", 47 job->base.sched->name, atomic_read(&ring->fence_drv.last_seq), 48 ring->fence_drv.sync_seq); 49 DRM_ERROR("Process information: process %s pid %d thread %s pid %d\n", 50 ti.process_name, ti.tgid, ti.task_name, ti.pid); 51 52 if (amdgpu_device_should_recover_gpu(ring->adev)) 53 amdgpu_device_gpu_recover(ring->adev, job); 54 else 55 drm_sched_suspend_timeout(&ring->sched); 56 } 57 58 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, 59 struct amdgpu_job **job, struct amdgpu_vm *vm) 60 { 61 size_t size = sizeof(struct amdgpu_job); 62 63 if (num_ibs == 0) 64 return -EINVAL; 65 66 size += sizeof(struct amdgpu_ib) * num_ibs; 67 68 *job = kzalloc(size, GFP_KERNEL); 69 if (!*job) 70 return -ENOMEM; 71 72 /* 73 * Initialize the scheduler to at least some ring so that we always 74 * have a pointer to adev. 75 */ 76 (*job)->base.sched = &adev->rings[0]->sched; 77 (*job)->vm = vm; 78 (*job)->ibs = (void *)&(*job)[1]; 79 (*job)->num_ibs = num_ibs; 80 81 amdgpu_sync_create(&(*job)->sync); 82 amdgpu_sync_create(&(*job)->sched_sync); 83 (*job)->vram_lost_counter = atomic_read(&adev->vram_lost_counter); 84 (*job)->vm_pd_addr = AMDGPU_BO_INVALID_OFFSET; 85 86 return 0; 87 } 88 89 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, 90 struct amdgpu_job **job) 91 { 92 int r; 93 94 r = amdgpu_job_alloc(adev, 1, job, NULL); 95 if (r) 96 return r; 97 98 r = amdgpu_ib_get(adev, NULL, size, &(*job)->ibs[0]); 99 if (r) 100 kfree(*job); 101 102 return r; 103 } 104 105 void amdgpu_job_free_resources(struct amdgpu_job *job) 106 { 107 struct amdgpu_ring *ring = to_amdgpu_ring(job->base.sched); 108 struct dma_fence *f; 109 unsigned i; 110 111 /* use sched fence if available */ 112 f = job->base.s_fence ? &job->base.s_fence->finished : job->fence; 113 114 for (i = 0; i < job->num_ibs; ++i) 115 amdgpu_ib_free(ring->adev, &job->ibs[i], f); 116 } 117 118 static void amdgpu_job_free_cb(struct drm_sched_job *s_job) 119 { 120 struct amdgpu_job *job = to_amdgpu_job(s_job); 121 122 drm_sched_job_cleanup(s_job); 123 124 dma_fence_put(job->fence); 125 amdgpu_sync_free(&job->sync); 126 amdgpu_sync_free(&job->sched_sync); 127 kfree(job); 128 } 129 130 void amdgpu_job_free(struct amdgpu_job *job) 131 { 132 amdgpu_job_free_resources(job); 133 134 dma_fence_put(job->fence); 135 amdgpu_sync_free(&job->sync); 136 amdgpu_sync_free(&job->sched_sync); 137 kfree(job); 138 } 139 140 int amdgpu_job_submit(struct amdgpu_job *job, struct drm_sched_entity *entity, 141 void *owner, struct dma_fence **f) 142 { 143 enum drm_sched_priority priority; 144 int r; 145 146 if (!f) 147 return -EINVAL; 148 149 r = drm_sched_job_init(&job->base, entity, owner); 150 if (r) 151 return r; 152 153 *f = dma_fence_get(&job->base.s_fence->finished); 154 amdgpu_job_free_resources(job); 155 priority = job->base.s_priority; 156 drm_sched_entity_push_job(&job->base, entity); 157 158 return 0; 159 } 160 161 int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring, 162 struct dma_fence **fence) 163 { 164 int r; 165 166 job->base.sched = &ring->sched; 167 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, NULL, fence); 168 job->fence = dma_fence_get(*fence); 169 if (r) 170 return r; 171 172 amdgpu_job_free(job); 173 return 0; 174 } 175 176 static struct dma_fence *amdgpu_job_dependency(struct drm_sched_job *sched_job, 177 struct drm_sched_entity *s_entity) 178 { 179 struct amdgpu_ring *ring = to_amdgpu_ring(s_entity->rq->sched); 180 struct amdgpu_job *job = to_amdgpu_job(sched_job); 181 struct amdgpu_vm *vm = job->vm; 182 struct dma_fence *fence; 183 bool explicit = false; 184 int r; 185 186 fence = amdgpu_sync_get_fence(&job->sync, &explicit); 187 if (fence && explicit) { 188 if (drm_sched_dependency_optimized(fence, s_entity)) { 189 r = amdgpu_sync_fence(&job->sched_sync, fence, false); 190 if (r) 191 DRM_ERROR("Error adding fence (%d)\n", r); 192 } 193 } 194 195 while (fence == NULL && vm && !job->vmid) { 196 r = amdgpu_vmid_grab(vm, ring, &job->sync, 197 &job->base.s_fence->finished, 198 job); 199 if (r) 200 DRM_ERROR("Error getting VM ID (%d)\n", r); 201 202 fence = amdgpu_sync_get_fence(&job->sync, NULL); 203 } 204 205 return fence; 206 } 207 208 static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job) 209 { 210 struct amdgpu_ring *ring = to_amdgpu_ring(sched_job->sched); 211 struct dma_fence *fence = NULL, *finished; 212 struct amdgpu_job *job; 213 int r = 0; 214 215 job = to_amdgpu_job(sched_job); 216 finished = &job->base.s_fence->finished; 217 218 BUG_ON(amdgpu_sync_peek_fence(&job->sync, NULL)); 219 220 trace_amdgpu_sched_run_job(job); 221 222 if (job->vram_lost_counter != atomic_read(&ring->adev->vram_lost_counter)) 223 dma_fence_set_error(finished, -ECANCELED);/* skip IB as well if VRAM lost */ 224 225 if (finished->error < 0) { 226 DRM_INFO("Skip scheduling IBs!\n"); 227 } else { 228 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job, 229 &fence); 230 if (r) 231 DRM_ERROR("Error scheduling IBs (%d)\n", r); 232 } 233 /* if gpu reset, hw fence will be replaced here */ 234 dma_fence_put(job->fence); 235 job->fence = dma_fence_get(fence); 236 237 amdgpu_job_free_resources(job); 238 239 fence = r ? ERR_PTR(r) : fence; 240 return fence; 241 } 242 243 #define to_drm_sched_job(sched_job) \ 244 container_of((sched_job), struct drm_sched_job, queue_node) 245 246 void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched) 247 { 248 struct drm_sched_job *s_job; 249 struct drm_sched_entity *s_entity = NULL; 250 int i; 251 252 /* Signal all jobs not yet scheduled */ 253 for (i = DRM_SCHED_PRIORITY_MAX - 1; i >= DRM_SCHED_PRIORITY_MIN; i--) { 254 struct drm_sched_rq *rq = &sched->sched_rq[i]; 255 256 if (!rq) 257 continue; 258 259 spin_lock(&rq->lock); 260 list_for_each_entry(s_entity, &rq->entities, list) { 261 while ((s_job = to_drm_sched_job(spsc_queue_pop(&s_entity->job_queue)))) { 262 struct drm_sched_fence *s_fence = s_job->s_fence; 263 264 dma_fence_signal(&s_fence->scheduled); 265 dma_fence_set_error(&s_fence->finished, -EHWPOISON); 266 dma_fence_signal(&s_fence->finished); 267 } 268 } 269 spin_unlock(&rq->lock); 270 } 271 272 /* Signal all jobs already scheduled to HW */ 273 list_for_each_entry(s_job, &sched->ring_mirror_list, node) { 274 struct drm_sched_fence *s_fence = s_job->s_fence; 275 276 dma_fence_set_error(&s_fence->finished, -EHWPOISON); 277 dma_fence_signal(&s_fence->finished); 278 } 279 } 280 281 const struct drm_sched_backend_ops amdgpu_sched_ops = { 282 .dependency = amdgpu_job_dependency, 283 .run_job = amdgpu_job_run, 284 .timedout_job = amdgpu_job_timedout, 285 .free_job = amdgpu_job_free_cb 286 }; 287