1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2010 Google, Inc. 4 */ 5 6 #include <linux/delay.h> 7 #include <linux/dma-mapping.h> 8 #include <linux/err.h> 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/iopoll.h> 12 #include <linux/platform_device.h> 13 #include <linux/clk.h> 14 #include <linux/io.h> 15 #include <linux/of.h> 16 #include <linux/of_device.h> 17 #include <linux/pinctrl/consumer.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/reset.h> 20 #include <linux/mmc/card.h> 21 #include <linux/mmc/host.h> 22 #include <linux/mmc/mmc.h> 23 #include <linux/mmc/slot-gpio.h> 24 #include <linux/gpio/consumer.h> 25 #include <linux/ktime.h> 26 27 #include "sdhci-pltfm.h" 28 #include "cqhci.h" 29 30 /* Tegra SDHOST controller vendor register definitions */ 31 #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100 32 #define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000 33 #define SDHCI_CLOCK_CTRL_TAP_SHIFT 16 34 #define SDHCI_CLOCK_CTRL_TRIM_MASK 0x1f000000 35 #define SDHCI_CLOCK_CTRL_TRIM_SHIFT 24 36 #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5) 37 #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3) 38 #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2) 39 40 #define SDHCI_TEGRA_VENDOR_SYS_SW_CTRL 0x104 41 #define SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE BIT(31) 42 43 #define SDHCI_TEGRA_VENDOR_CAP_OVERRIDES 0x10c 44 #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK 0x00003f00 45 #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT 8 46 47 #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 48 #define SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT BIT(0) 49 #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 50 #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 51 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 52 #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 53 54 #define SDHCI_TEGRA_VENDOR_DLLCAL_CFG 0x1b0 55 #define SDHCI_TEGRA_DLLCAL_CALIBRATE BIT(31) 56 57 #define SDHCI_TEGRA_VENDOR_DLLCAL_STA 0x1bc 58 #define SDHCI_TEGRA_DLLCAL_STA_ACTIVE BIT(31) 59 60 #define SDHCI_VNDR_TUN_CTRL0_0 0x1c0 61 #define SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP 0x20000 62 #define SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_MASK 0x03fc0000 63 #define SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_SHIFT 18 64 #define SDHCI_VNDR_TUN_CTRL0_MUL_M_MASK 0x00001fc0 65 #define SDHCI_VNDR_TUN_CTRL0_MUL_M_SHIFT 6 66 #define SDHCI_VNDR_TUN_CTRL0_TUN_ITER_MASK 0x000e000 67 #define SDHCI_VNDR_TUN_CTRL0_TUN_ITER_SHIFT 13 68 #define TRIES_128 2 69 #define TRIES_256 4 70 #define SDHCI_VNDR_TUN_CTRL0_TUN_WORD_SEL_MASK 0x7 71 72 #define SDHCI_TEGRA_VNDR_TUN_CTRL1_0 0x1c4 73 #define SDHCI_TEGRA_VNDR_TUN_STATUS0 0x1C8 74 #define SDHCI_TEGRA_VNDR_TUN_STATUS1 0x1CC 75 #define SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK 0xFF 76 #define SDHCI_TEGRA_VNDR_TUN_STATUS1_END_TAP_SHIFT 0x8 77 #define TUNING_WORD_BIT_SIZE 32 78 79 #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4 80 #define SDHCI_AUTO_CAL_START BIT(31) 81 #define SDHCI_AUTO_CAL_ENABLE BIT(29) 82 #define SDHCI_AUTO_CAL_PDPU_OFFSET_MASK 0x0000ffff 83 84 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL 0x1e0 85 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK 0x0000000f 86 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL 0x7 87 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD BIT(31) 88 #define SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK 0x07FFF000 89 90 #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec 91 #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) 92 93 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) 94 #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) 95 #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) 96 #define NVQUIRK_ENABLE_SDR50 BIT(3) 97 #define NVQUIRK_ENABLE_SDR104 BIT(4) 98 #define NVQUIRK_ENABLE_DDR50 BIT(5) 99 #define NVQUIRK_HAS_PADCALIB BIT(6) 100 #define NVQUIRK_NEEDS_PAD_CONTROL BIT(7) 101 #define NVQUIRK_DIS_CARD_CLK_CONFIG_TAP BIT(8) 102 #define NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING BIT(9) 103 104 /* SDMMC CQE Base Address for Tegra Host Ver 4.1 and Higher */ 105 #define SDHCI_TEGRA_CQE_BASE_ADDR 0xF000 106 107 struct sdhci_tegra_soc_data { 108 const struct sdhci_pltfm_data *pdata; 109 u64 dma_mask; 110 u32 nvquirks; 111 u8 min_tap_delay; 112 u8 max_tap_delay; 113 }; 114 115 /* Magic pull up and pull down pad calibration offsets */ 116 struct sdhci_tegra_autocal_offsets { 117 u32 pull_up_3v3; 118 u32 pull_down_3v3; 119 u32 pull_up_3v3_timeout; 120 u32 pull_down_3v3_timeout; 121 u32 pull_up_1v8; 122 u32 pull_down_1v8; 123 u32 pull_up_1v8_timeout; 124 u32 pull_down_1v8_timeout; 125 u32 pull_up_sdr104; 126 u32 pull_down_sdr104; 127 u32 pull_up_hs400; 128 u32 pull_down_hs400; 129 }; 130 131 struct sdhci_tegra { 132 const struct sdhci_tegra_soc_data *soc_data; 133 struct gpio_desc *power_gpio; 134 bool ddr_signaling; 135 bool pad_calib_required; 136 bool pad_control_available; 137 138 struct reset_control *rst; 139 struct pinctrl *pinctrl_sdmmc; 140 struct pinctrl_state *pinctrl_state_3v3; 141 struct pinctrl_state *pinctrl_state_1v8; 142 struct pinctrl_state *pinctrl_state_3v3_drv; 143 struct pinctrl_state *pinctrl_state_1v8_drv; 144 145 struct sdhci_tegra_autocal_offsets autocal_offsets; 146 ktime_t last_calib; 147 148 u32 default_tap; 149 u32 default_trim; 150 u32 dqs_trim; 151 bool enable_hwcq; 152 unsigned long curr_clk_rate; 153 u8 tuned_tap_delay; 154 }; 155 156 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) 157 { 158 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 159 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 160 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 161 162 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && 163 (reg == SDHCI_HOST_VERSION))) { 164 /* Erratum: Version register is invalid in HW. */ 165 return SDHCI_SPEC_200; 166 } 167 168 return readw(host->ioaddr + reg); 169 } 170 171 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 172 { 173 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 174 175 switch (reg) { 176 case SDHCI_TRANSFER_MODE: 177 /* 178 * Postpone this write, we must do it together with a 179 * command write that is down below. 180 */ 181 pltfm_host->xfer_mode_shadow = val; 182 return; 183 case SDHCI_COMMAND: 184 writel((val << 16) | pltfm_host->xfer_mode_shadow, 185 host->ioaddr + SDHCI_TRANSFER_MODE); 186 return; 187 } 188 189 writew(val, host->ioaddr + reg); 190 } 191 192 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 193 { 194 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 195 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 196 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 197 198 /* Seems like we're getting spurious timeout and crc errors, so 199 * disable signalling of them. In case of real errors software 200 * timers should take care of eventually detecting them. 201 */ 202 if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) 203 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); 204 205 writel(val, host->ioaddr + reg); 206 207 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && 208 (reg == SDHCI_INT_ENABLE))) { 209 /* Erratum: Must enable block gap interrupt detection */ 210 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 211 if (val & SDHCI_INT_CARD_INT) 212 gap_ctrl |= 0x8; 213 else 214 gap_ctrl &= ~0x8; 215 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 216 } 217 } 218 219 static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable) 220 { 221 bool status; 222 u32 reg; 223 224 reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 225 status = !!(reg & SDHCI_CLOCK_CARD_EN); 226 227 if (status == enable) 228 return status; 229 230 if (enable) 231 reg |= SDHCI_CLOCK_CARD_EN; 232 else 233 reg &= ~SDHCI_CLOCK_CARD_EN; 234 235 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); 236 237 return status; 238 } 239 240 static void tegra210_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 241 { 242 bool is_tuning_cmd = 0; 243 bool clk_enabled; 244 u8 cmd; 245 246 if (reg == SDHCI_COMMAND) { 247 cmd = SDHCI_GET_CMD(val); 248 is_tuning_cmd = cmd == MMC_SEND_TUNING_BLOCK || 249 cmd == MMC_SEND_TUNING_BLOCK_HS200; 250 } 251 252 if (is_tuning_cmd) 253 clk_enabled = tegra_sdhci_configure_card_clk(host, 0); 254 255 writew(val, host->ioaddr + reg); 256 257 if (is_tuning_cmd) { 258 udelay(1); 259 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 260 tegra_sdhci_configure_card_clk(host, clk_enabled); 261 } 262 } 263 264 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host) 265 { 266 /* 267 * Write-enable shall be assumed if GPIO is missing in a board's 268 * device-tree because SDHCI's WRITE_PROTECT bit doesn't work on 269 * Tegra. 270 */ 271 return mmc_gpio_get_ro(host->mmc); 272 } 273 274 static bool tegra_sdhci_is_pad_and_regulator_valid(struct sdhci_host *host) 275 { 276 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 277 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 278 int has_1v8, has_3v3; 279 280 /* 281 * The SoCs which have NVQUIRK_NEEDS_PAD_CONTROL require software pad 282 * voltage configuration in order to perform voltage switching. This 283 * means that valid pinctrl info is required on SDHCI instances capable 284 * of performing voltage switching. Whether or not an SDHCI instance is 285 * capable of voltage switching is determined based on the regulator. 286 */ 287 288 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) 289 return true; 290 291 if (IS_ERR(host->mmc->supply.vqmmc)) 292 return false; 293 294 has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 295 1700000, 1950000); 296 297 has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, 298 2700000, 3600000); 299 300 if (has_1v8 == 1 && has_3v3 == 1) 301 return tegra_host->pad_control_available; 302 303 /* Fixed voltage, no pad control required. */ 304 return true; 305 } 306 307 static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) 308 { 309 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 310 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 311 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 312 bool card_clk_enabled = false; 313 u32 reg; 314 315 /* 316 * Touching the tap values is a bit tricky on some SoC generations. 317 * The quirk enables a workaround for a glitch that sometimes occurs if 318 * the tap values are changed. 319 */ 320 321 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP) 322 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 323 324 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 325 reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK; 326 reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT; 327 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 328 329 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP && 330 card_clk_enabled) { 331 udelay(1); 332 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 333 tegra_sdhci_configure_card_clk(host, card_clk_enabled); 334 } 335 } 336 337 static void tegra_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc, 338 struct mmc_ios *ios) 339 { 340 struct sdhci_host *host = mmc_priv(mmc); 341 u32 val; 342 343 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); 344 345 if (ios->enhanced_strobe) 346 val |= SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE; 347 else 348 val &= ~SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE; 349 350 sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); 351 352 } 353 354 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) 355 { 356 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 357 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 358 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 359 u32 misc_ctrl, clk_ctrl, pad_ctrl; 360 361 sdhci_reset(host, mask); 362 363 if (!(mask & SDHCI_RESET_ALL)) 364 return; 365 366 tegra_sdhci_set_tap(host, tegra_host->default_tap); 367 368 misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 369 clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 370 371 misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 | 372 SDHCI_MISC_CTRL_ENABLE_SDR50 | 373 SDHCI_MISC_CTRL_ENABLE_DDR50 | 374 SDHCI_MISC_CTRL_ENABLE_SDR104); 375 376 clk_ctrl &= ~(SDHCI_CLOCK_CTRL_TRIM_MASK | 377 SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE); 378 379 if (tegra_sdhci_is_pad_and_regulator_valid(host)) { 380 /* Erratum: Enable SDHCI spec v3.00 support */ 381 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) 382 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; 383 /* Advertise UHS modes as supported by host */ 384 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) 385 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50; 386 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 387 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50; 388 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) 389 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104; 390 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) 391 clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE; 392 } 393 394 clk_ctrl |= tegra_host->default_trim << SDHCI_CLOCK_CTRL_TRIM_SHIFT; 395 396 sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); 397 sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 398 399 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) { 400 pad_ctrl = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 401 pad_ctrl &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK; 402 pad_ctrl |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL; 403 sdhci_writel(host, pad_ctrl, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 404 405 tegra_host->pad_calib_required = true; 406 } 407 408 tegra_host->ddr_signaling = false; 409 } 410 411 static void tegra_sdhci_configure_cal_pad(struct sdhci_host *host, bool enable) 412 { 413 u32 val; 414 415 /* 416 * Enable or disable the additional I/O pad used by the drive strength 417 * calibration process. 418 */ 419 val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 420 421 if (enable) 422 val |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 423 else 424 val &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; 425 426 sdhci_writel(host, val, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 427 428 if (enable) 429 usleep_range(1, 2); 430 } 431 432 static void tegra_sdhci_set_pad_autocal_offset(struct sdhci_host *host, 433 u16 pdpu) 434 { 435 u32 reg; 436 437 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 438 reg &= ~SDHCI_AUTO_CAL_PDPU_OFFSET_MASK; 439 reg |= pdpu; 440 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 441 } 442 443 static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage, 444 bool state_drvupdn) 445 { 446 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 447 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 448 struct sdhci_tegra_autocal_offsets *offsets = 449 &tegra_host->autocal_offsets; 450 struct pinctrl_state *pinctrl_drvupdn = NULL; 451 int ret = 0; 452 u8 drvup = 0, drvdn = 0; 453 u32 reg; 454 455 if (!state_drvupdn) { 456 /* PADS Drive Strength */ 457 if (voltage == MMC_SIGNAL_VOLTAGE_180) { 458 if (tegra_host->pinctrl_state_1v8_drv) { 459 pinctrl_drvupdn = 460 tegra_host->pinctrl_state_1v8_drv; 461 } else { 462 drvup = offsets->pull_up_1v8_timeout; 463 drvdn = offsets->pull_down_1v8_timeout; 464 } 465 } else { 466 if (tegra_host->pinctrl_state_3v3_drv) { 467 pinctrl_drvupdn = 468 tegra_host->pinctrl_state_3v3_drv; 469 } else { 470 drvup = offsets->pull_up_3v3_timeout; 471 drvdn = offsets->pull_down_3v3_timeout; 472 } 473 } 474 475 if (pinctrl_drvupdn != NULL) { 476 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 477 pinctrl_drvupdn); 478 if (ret < 0) 479 dev_err(mmc_dev(host->mmc), 480 "failed pads drvupdn, ret: %d\n", ret); 481 } else if ((drvup) || (drvdn)) { 482 reg = sdhci_readl(host, 483 SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 484 reg &= ~SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK; 485 reg |= (drvup << 20) | (drvdn << 12); 486 sdhci_writel(host, reg, 487 SDHCI_TEGRA_SDMEM_COMP_PADCTRL); 488 } 489 490 } else { 491 /* Dual Voltage PADS Voltage selection */ 492 if (!tegra_host->pad_control_available) 493 return 0; 494 495 if (voltage == MMC_SIGNAL_VOLTAGE_180) { 496 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 497 tegra_host->pinctrl_state_1v8); 498 if (ret < 0) 499 dev_err(mmc_dev(host->mmc), 500 "setting 1.8V failed, ret: %d\n", ret); 501 } else { 502 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, 503 tegra_host->pinctrl_state_3v3); 504 if (ret < 0) 505 dev_err(mmc_dev(host->mmc), 506 "setting 3.3V failed, ret: %d\n", ret); 507 } 508 } 509 510 return ret; 511 } 512 513 static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) 514 { 515 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 516 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 517 struct sdhci_tegra_autocal_offsets offsets = 518 tegra_host->autocal_offsets; 519 struct mmc_ios *ios = &host->mmc->ios; 520 bool card_clk_enabled; 521 u16 pdpu; 522 u32 reg; 523 int ret; 524 525 switch (ios->timing) { 526 case MMC_TIMING_UHS_SDR104: 527 pdpu = offsets.pull_down_sdr104 << 8 | offsets.pull_up_sdr104; 528 break; 529 case MMC_TIMING_MMC_HS400: 530 pdpu = offsets.pull_down_hs400 << 8 | offsets.pull_up_hs400; 531 break; 532 default: 533 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 534 pdpu = offsets.pull_down_1v8 << 8 | offsets.pull_up_1v8; 535 else 536 pdpu = offsets.pull_down_3v3 << 8 | offsets.pull_up_3v3; 537 } 538 539 /* Set initial offset before auto-calibration */ 540 tegra_sdhci_set_pad_autocal_offset(host, pdpu); 541 542 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); 543 544 tegra_sdhci_configure_cal_pad(host, true); 545 546 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 547 reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START; 548 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 549 550 usleep_range(1, 2); 551 /* 10 ms timeout */ 552 ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS, 553 reg, !(reg & SDHCI_TEGRA_AUTO_CAL_ACTIVE), 554 1000, 10000); 555 556 tegra_sdhci_configure_cal_pad(host, false); 557 558 tegra_sdhci_configure_card_clk(host, card_clk_enabled); 559 560 if (ret) { 561 dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); 562 563 /* Disable automatic cal and use fixed Drive Strengths */ 564 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 565 reg &= ~SDHCI_AUTO_CAL_ENABLE; 566 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); 567 568 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, false); 569 if (ret < 0) 570 dev_err(mmc_dev(host->mmc), 571 "Setting drive strengths failed: %d\n", ret); 572 } 573 } 574 575 static void tegra_sdhci_parse_pad_autocal_dt(struct sdhci_host *host) 576 { 577 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 578 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 579 struct sdhci_tegra_autocal_offsets *autocal = 580 &tegra_host->autocal_offsets; 581 int err; 582 583 err = device_property_read_u32(host->mmc->parent, 584 "nvidia,pad-autocal-pull-up-offset-3v3", 585 &autocal->pull_up_3v3); 586 if (err) 587 autocal->pull_up_3v3 = 0; 588 589 err = device_property_read_u32(host->mmc->parent, 590 "nvidia,pad-autocal-pull-down-offset-3v3", 591 &autocal->pull_down_3v3); 592 if (err) 593 autocal->pull_down_3v3 = 0; 594 595 err = device_property_read_u32(host->mmc->parent, 596 "nvidia,pad-autocal-pull-up-offset-1v8", 597 &autocal->pull_up_1v8); 598 if (err) 599 autocal->pull_up_1v8 = 0; 600 601 err = device_property_read_u32(host->mmc->parent, 602 "nvidia,pad-autocal-pull-down-offset-1v8", 603 &autocal->pull_down_1v8); 604 if (err) 605 autocal->pull_down_1v8 = 0; 606 607 err = device_property_read_u32(host->mmc->parent, 608 "nvidia,pad-autocal-pull-up-offset-3v3-timeout", 609 &autocal->pull_up_3v3_timeout); 610 if (err) { 611 if (!IS_ERR(tegra_host->pinctrl_state_3v3) && 612 (tegra_host->pinctrl_state_3v3_drv == NULL)) 613 pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n", 614 mmc_hostname(host->mmc)); 615 autocal->pull_up_3v3_timeout = 0; 616 } 617 618 err = device_property_read_u32(host->mmc->parent, 619 "nvidia,pad-autocal-pull-down-offset-3v3-timeout", 620 &autocal->pull_down_3v3_timeout); 621 if (err) { 622 if (!IS_ERR(tegra_host->pinctrl_state_3v3) && 623 (tegra_host->pinctrl_state_3v3_drv == NULL)) 624 pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n", 625 mmc_hostname(host->mmc)); 626 autocal->pull_down_3v3_timeout = 0; 627 } 628 629 err = device_property_read_u32(host->mmc->parent, 630 "nvidia,pad-autocal-pull-up-offset-1v8-timeout", 631 &autocal->pull_up_1v8_timeout); 632 if (err) { 633 if (!IS_ERR(tegra_host->pinctrl_state_1v8) && 634 (tegra_host->pinctrl_state_1v8_drv == NULL)) 635 pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n", 636 mmc_hostname(host->mmc)); 637 autocal->pull_up_1v8_timeout = 0; 638 } 639 640 err = device_property_read_u32(host->mmc->parent, 641 "nvidia,pad-autocal-pull-down-offset-1v8-timeout", 642 &autocal->pull_down_1v8_timeout); 643 if (err) { 644 if (!IS_ERR(tegra_host->pinctrl_state_1v8) && 645 (tegra_host->pinctrl_state_1v8_drv == NULL)) 646 pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n", 647 mmc_hostname(host->mmc)); 648 autocal->pull_down_1v8_timeout = 0; 649 } 650 651 err = device_property_read_u32(host->mmc->parent, 652 "nvidia,pad-autocal-pull-up-offset-sdr104", 653 &autocal->pull_up_sdr104); 654 if (err) 655 autocal->pull_up_sdr104 = autocal->pull_up_1v8; 656 657 err = device_property_read_u32(host->mmc->parent, 658 "nvidia,pad-autocal-pull-down-offset-sdr104", 659 &autocal->pull_down_sdr104); 660 if (err) 661 autocal->pull_down_sdr104 = autocal->pull_down_1v8; 662 663 err = device_property_read_u32(host->mmc->parent, 664 "nvidia,pad-autocal-pull-up-offset-hs400", 665 &autocal->pull_up_hs400); 666 if (err) 667 autocal->pull_up_hs400 = autocal->pull_up_1v8; 668 669 err = device_property_read_u32(host->mmc->parent, 670 "nvidia,pad-autocal-pull-down-offset-hs400", 671 &autocal->pull_down_hs400); 672 if (err) 673 autocal->pull_down_hs400 = autocal->pull_down_1v8; 674 } 675 676 static void tegra_sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 677 { 678 struct sdhci_host *host = mmc_priv(mmc); 679 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 680 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 681 ktime_t since_calib = ktime_sub(ktime_get(), tegra_host->last_calib); 682 683 /* 100 ms calibration interval is specified in the TRM */ 684 if (ktime_to_ms(since_calib) > 100) { 685 tegra_sdhci_pad_autocalib(host); 686 tegra_host->last_calib = ktime_get(); 687 } 688 689 sdhci_request(mmc, mrq); 690 } 691 692 static void tegra_sdhci_parse_tap_and_trim(struct sdhci_host *host) 693 { 694 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 695 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 696 int err; 697 698 err = device_property_read_u32(host->mmc->parent, "nvidia,default-tap", 699 &tegra_host->default_tap); 700 if (err) 701 tegra_host->default_tap = 0; 702 703 err = device_property_read_u32(host->mmc->parent, "nvidia,default-trim", 704 &tegra_host->default_trim); 705 if (err) 706 tegra_host->default_trim = 0; 707 708 err = device_property_read_u32(host->mmc->parent, "nvidia,dqs-trim", 709 &tegra_host->dqs_trim); 710 if (err) 711 tegra_host->dqs_trim = 0x11; 712 } 713 714 static void tegra_sdhci_parse_dt(struct sdhci_host *host) 715 { 716 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 717 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 718 719 if (device_property_read_bool(host->mmc->parent, "supports-cqe")) 720 tegra_host->enable_hwcq = true; 721 else 722 tegra_host->enable_hwcq = false; 723 724 tegra_sdhci_parse_pad_autocal_dt(host); 725 tegra_sdhci_parse_tap_and_trim(host); 726 } 727 728 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 729 { 730 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 731 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 732 unsigned long host_clk; 733 734 if (!clock) 735 return sdhci_set_clock(host, clock); 736 737 /* 738 * In DDR50/52 modes the Tegra SDHCI controllers require the SDHCI 739 * divider to be configured to divided the host clock by two. The SDHCI 740 * clock divider is calculated as part of sdhci_set_clock() by 741 * sdhci_calc_clk(). The divider is calculated from host->max_clk and 742 * the requested clock rate. 743 * 744 * By setting the host->max_clk to clock * 2 the divider calculation 745 * will always result in the correct value for DDR50/52 modes, 746 * regardless of clock rate rounding, which may happen if the value 747 * from clk_get_rate() is used. 748 */ 749 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; 750 clk_set_rate(pltfm_host->clk, host_clk); 751 tegra_host->curr_clk_rate = host_clk; 752 if (tegra_host->ddr_signaling) 753 host->max_clk = host_clk; 754 else 755 host->max_clk = clk_get_rate(pltfm_host->clk); 756 757 sdhci_set_clock(host, clock); 758 759 if (tegra_host->pad_calib_required) { 760 tegra_sdhci_pad_autocalib(host); 761 tegra_host->pad_calib_required = false; 762 } 763 } 764 765 static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host) 766 { 767 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 768 769 return clk_round_rate(pltfm_host->clk, UINT_MAX); 770 } 771 772 static void tegra_sdhci_set_dqs_trim(struct sdhci_host *host, u8 trim) 773 { 774 u32 val; 775 776 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES); 777 val &= ~SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK; 778 val |= trim << SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT; 779 sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES); 780 } 781 782 static void tegra_sdhci_hs400_dll_cal(struct sdhci_host *host) 783 { 784 u32 reg; 785 int err; 786 787 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); 788 reg |= SDHCI_TEGRA_DLLCAL_CALIBRATE; 789 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); 790 791 /* 1 ms sleep, 5 ms timeout */ 792 err = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_VENDOR_DLLCAL_STA, 793 reg, !(reg & SDHCI_TEGRA_DLLCAL_STA_ACTIVE), 794 1000, 5000); 795 if (err) 796 dev_err(mmc_dev(host->mmc), 797 "HS400 delay line calibration timed out\n"); 798 } 799 800 static void tegra_sdhci_tap_correction(struct sdhci_host *host, u8 thd_up, 801 u8 thd_low, u8 fixed_tap) 802 { 803 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 804 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 805 u32 val, tun_status; 806 u8 word, bit, edge1, tap, window; 807 bool tap_result; 808 bool start_fail = false; 809 bool start_pass = false; 810 bool end_pass = false; 811 bool first_fail = false; 812 bool first_pass = false; 813 u8 start_pass_tap = 0; 814 u8 end_pass_tap = 0; 815 u8 first_fail_tap = 0; 816 u8 first_pass_tap = 0; 817 u8 total_tuning_words = host->tuning_loop_count / TUNING_WORD_BIT_SIZE; 818 819 /* 820 * Read auto-tuned results and extract good valid passing window by 821 * filtering out un-wanted bubble/partial/merged windows. 822 */ 823 for (word = 0; word < total_tuning_words; word++) { 824 val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0); 825 val &= ~SDHCI_VNDR_TUN_CTRL0_TUN_WORD_SEL_MASK; 826 val |= word; 827 sdhci_writel(host, val, SDHCI_VNDR_TUN_CTRL0_0); 828 tun_status = sdhci_readl(host, SDHCI_TEGRA_VNDR_TUN_STATUS0); 829 bit = 0; 830 while (bit < TUNING_WORD_BIT_SIZE) { 831 tap = word * TUNING_WORD_BIT_SIZE + bit; 832 tap_result = tun_status & (1 << bit); 833 if (!tap_result && !start_fail) { 834 start_fail = true; 835 if (!first_fail) { 836 first_fail_tap = tap; 837 first_fail = true; 838 } 839 840 } else if (tap_result && start_fail && !start_pass) { 841 start_pass_tap = tap; 842 start_pass = true; 843 if (!first_pass) { 844 first_pass_tap = tap; 845 first_pass = true; 846 } 847 848 } else if (!tap_result && start_fail && start_pass && 849 !end_pass) { 850 end_pass_tap = tap - 1; 851 end_pass = true; 852 } else if (tap_result && start_pass && start_fail && 853 end_pass) { 854 window = end_pass_tap - start_pass_tap; 855 /* discard merged window and bubble window */ 856 if (window >= thd_up || window < thd_low) { 857 start_pass_tap = tap; 858 end_pass = false; 859 } else { 860 /* set tap at middle of valid window */ 861 tap = start_pass_tap + window / 2; 862 tegra_host->tuned_tap_delay = tap; 863 return; 864 } 865 } 866 867 bit++; 868 } 869 } 870 871 if (!first_fail) { 872 WARN(1, "no edge detected, continue with hw tuned delay.\n"); 873 } else if (first_pass) { 874 /* set tap location at fixed tap relative to the first edge */ 875 edge1 = first_fail_tap + (first_pass_tap - first_fail_tap) / 2; 876 if (edge1 - 1 > fixed_tap) 877 tegra_host->tuned_tap_delay = edge1 - fixed_tap; 878 else 879 tegra_host->tuned_tap_delay = edge1 + fixed_tap; 880 } 881 } 882 883 static void tegra_sdhci_post_tuning(struct sdhci_host *host) 884 { 885 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 886 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 887 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 888 u32 avg_tap_dly, val, min_tap_dly, max_tap_dly; 889 u8 fixed_tap, start_tap, end_tap, window_width; 890 u8 thdupper, thdlower; 891 u8 num_iter; 892 u32 clk_rate_mhz, period_ps, bestcase, worstcase; 893 894 /* retain HW tuned tap to use incase if no correction is needed */ 895 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 896 tegra_host->tuned_tap_delay = (val & SDHCI_CLOCK_CTRL_TAP_MASK) >> 897 SDHCI_CLOCK_CTRL_TAP_SHIFT; 898 if (soc_data->min_tap_delay && soc_data->max_tap_delay) { 899 min_tap_dly = soc_data->min_tap_delay; 900 max_tap_dly = soc_data->max_tap_delay; 901 clk_rate_mhz = tegra_host->curr_clk_rate / USEC_PER_SEC; 902 period_ps = USEC_PER_SEC / clk_rate_mhz; 903 bestcase = period_ps / min_tap_dly; 904 worstcase = period_ps / max_tap_dly; 905 /* 906 * Upper and Lower bound thresholds used to detect merged and 907 * bubble windows 908 */ 909 thdupper = (2 * worstcase + bestcase) / 2; 910 thdlower = worstcase / 4; 911 /* 912 * fixed tap is used when HW tuning result contains single edge 913 * and tap is set at fixed tap delay relative to the first edge 914 */ 915 avg_tap_dly = (period_ps * 2) / (min_tap_dly + max_tap_dly); 916 fixed_tap = avg_tap_dly / 2; 917 918 val = sdhci_readl(host, SDHCI_TEGRA_VNDR_TUN_STATUS1); 919 start_tap = val & SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK; 920 end_tap = (val >> SDHCI_TEGRA_VNDR_TUN_STATUS1_END_TAP_SHIFT) & 921 SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK; 922 window_width = end_tap - start_tap; 923 num_iter = host->tuning_loop_count; 924 /* 925 * partial window includes edges of the tuning range. 926 * merged window includes more taps so window width is higher 927 * than upper threshold. 928 */ 929 if (start_tap == 0 || (end_tap == (num_iter - 1)) || 930 (end_tap == num_iter - 2) || window_width >= thdupper) { 931 pr_debug("%s: Apply tuning correction\n", 932 mmc_hostname(host->mmc)); 933 tegra_sdhci_tap_correction(host, thdupper, thdlower, 934 fixed_tap); 935 } 936 } 937 938 tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay); 939 } 940 941 static int tegra_sdhci_execute_hw_tuning(struct mmc_host *mmc, u32 opcode) 942 { 943 struct sdhci_host *host = mmc_priv(mmc); 944 int err; 945 946 err = sdhci_execute_tuning(mmc, opcode); 947 if (!err && !host->tuning_err) 948 tegra_sdhci_post_tuning(host); 949 950 return err; 951 } 952 953 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, 954 unsigned timing) 955 { 956 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 957 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 958 bool set_default_tap = false; 959 bool set_dqs_trim = false; 960 bool do_hs400_dll_cal = false; 961 u8 iter = TRIES_256; 962 u32 val; 963 964 tegra_host->ddr_signaling = false; 965 switch (timing) { 966 case MMC_TIMING_UHS_SDR50: 967 break; 968 case MMC_TIMING_UHS_SDR104: 969 case MMC_TIMING_MMC_HS200: 970 /* Don't set default tap on tunable modes. */ 971 iter = TRIES_128; 972 break; 973 case MMC_TIMING_MMC_HS400: 974 set_dqs_trim = true; 975 do_hs400_dll_cal = true; 976 iter = TRIES_128; 977 break; 978 case MMC_TIMING_MMC_DDR52: 979 case MMC_TIMING_UHS_DDR50: 980 tegra_host->ddr_signaling = true; 981 set_default_tap = true; 982 break; 983 default: 984 set_default_tap = true; 985 break; 986 } 987 988 val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0); 989 val &= ~(SDHCI_VNDR_TUN_CTRL0_TUN_ITER_MASK | 990 SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_MASK | 991 SDHCI_VNDR_TUN_CTRL0_MUL_M_MASK); 992 val |= (iter << SDHCI_VNDR_TUN_CTRL0_TUN_ITER_SHIFT | 993 0 << SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_SHIFT | 994 1 << SDHCI_VNDR_TUN_CTRL0_MUL_M_SHIFT); 995 sdhci_writel(host, val, SDHCI_VNDR_TUN_CTRL0_0); 996 sdhci_writel(host, 0, SDHCI_TEGRA_VNDR_TUN_CTRL1_0); 997 998 host->tuning_loop_count = (iter == TRIES_128) ? 128 : 256; 999 1000 sdhci_set_uhs_signaling(host, timing); 1001 1002 tegra_sdhci_pad_autocalib(host); 1003 1004 if (tegra_host->tuned_tap_delay && !set_default_tap) 1005 tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay); 1006 else 1007 tegra_sdhci_set_tap(host, tegra_host->default_tap); 1008 1009 if (set_dqs_trim) 1010 tegra_sdhci_set_dqs_trim(host, tegra_host->dqs_trim); 1011 1012 if (do_hs400_dll_cal) 1013 tegra_sdhci_hs400_dll_cal(host); 1014 } 1015 1016 static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 1017 { 1018 unsigned int min, max; 1019 1020 /* 1021 * Start search for minimum tap value at 10, as smaller values are 1022 * may wrongly be reported as working but fail at higher speeds, 1023 * according to the TRM. 1024 */ 1025 min = 10; 1026 while (min < 255) { 1027 tegra_sdhci_set_tap(host, min); 1028 if (!mmc_send_tuning(host->mmc, opcode, NULL)) 1029 break; 1030 min++; 1031 } 1032 1033 /* Find the maximum tap value that still passes. */ 1034 max = min + 1; 1035 while (max < 255) { 1036 tegra_sdhci_set_tap(host, max); 1037 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1038 max--; 1039 break; 1040 } 1041 max++; 1042 } 1043 1044 /* The TRM states the ideal tap value is at 75% in the passing range. */ 1045 tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4)); 1046 1047 return mmc_send_tuning(host->mmc, opcode, NULL); 1048 } 1049 1050 static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc, 1051 struct mmc_ios *ios) 1052 { 1053 struct sdhci_host *host = mmc_priv(mmc); 1054 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1055 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1056 int ret = 0; 1057 1058 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 1059 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true); 1060 if (ret < 0) 1061 return ret; 1062 ret = sdhci_start_signal_voltage_switch(mmc, ios); 1063 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { 1064 ret = sdhci_start_signal_voltage_switch(mmc, ios); 1065 if (ret < 0) 1066 return ret; 1067 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true); 1068 } 1069 1070 if (tegra_host->pad_calib_required) 1071 tegra_sdhci_pad_autocalib(host); 1072 1073 return ret; 1074 } 1075 1076 static int tegra_sdhci_init_pinctrl_info(struct device *dev, 1077 struct sdhci_tegra *tegra_host) 1078 { 1079 tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev); 1080 if (IS_ERR(tegra_host->pinctrl_sdmmc)) { 1081 dev_dbg(dev, "No pinctrl info, err: %ld\n", 1082 PTR_ERR(tegra_host->pinctrl_sdmmc)); 1083 return -1; 1084 } 1085 1086 tegra_host->pinctrl_state_1v8_drv = pinctrl_lookup_state( 1087 tegra_host->pinctrl_sdmmc, "sdmmc-1v8-drv"); 1088 if (IS_ERR(tegra_host->pinctrl_state_1v8_drv)) { 1089 if (PTR_ERR(tegra_host->pinctrl_state_1v8_drv) == -ENODEV) 1090 tegra_host->pinctrl_state_1v8_drv = NULL; 1091 } 1092 1093 tegra_host->pinctrl_state_3v3_drv = pinctrl_lookup_state( 1094 tegra_host->pinctrl_sdmmc, "sdmmc-3v3-drv"); 1095 if (IS_ERR(tegra_host->pinctrl_state_3v3_drv)) { 1096 if (PTR_ERR(tegra_host->pinctrl_state_3v3_drv) == -ENODEV) 1097 tegra_host->pinctrl_state_3v3_drv = NULL; 1098 } 1099 1100 tegra_host->pinctrl_state_3v3 = 1101 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3"); 1102 if (IS_ERR(tegra_host->pinctrl_state_3v3)) { 1103 dev_warn(dev, "Missing 3.3V pad state, err: %ld\n", 1104 PTR_ERR(tegra_host->pinctrl_state_3v3)); 1105 return -1; 1106 } 1107 1108 tegra_host->pinctrl_state_1v8 = 1109 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8"); 1110 if (IS_ERR(tegra_host->pinctrl_state_1v8)) { 1111 dev_warn(dev, "Missing 1.8V pad state, err: %ld\n", 1112 PTR_ERR(tegra_host->pinctrl_state_1v8)); 1113 return -1; 1114 } 1115 1116 tegra_host->pad_control_available = true; 1117 1118 return 0; 1119 } 1120 1121 static void tegra_sdhci_voltage_switch(struct sdhci_host *host) 1122 { 1123 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1124 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1125 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 1126 1127 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 1128 tegra_host->pad_calib_required = true; 1129 } 1130 1131 static void tegra_cqhci_writel(struct cqhci_host *cq_host, u32 val, int reg) 1132 { 1133 struct mmc_host *mmc = cq_host->mmc; 1134 u8 ctrl; 1135 ktime_t timeout; 1136 bool timed_out; 1137 1138 /* 1139 * During CQE resume/unhalt, CQHCI driver unhalts CQE prior to 1140 * cqhci_host_ops enable where SDHCI DMA and BLOCK_SIZE registers need 1141 * to be re-configured. 1142 * Tegra CQHCI/SDHCI prevents write access to block size register when 1143 * CQE is unhalted. So handling CQE resume sequence here to configure 1144 * SDHCI block registers prior to exiting CQE halt state. 1145 */ 1146 if (reg == CQHCI_CTL && !(val & CQHCI_HALT) && 1147 cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_HALT) { 1148 sdhci_cqe_enable(mmc); 1149 writel(val, cq_host->mmio + reg); 1150 timeout = ktime_add_us(ktime_get(), 50); 1151 while (1) { 1152 timed_out = ktime_compare(ktime_get(), timeout) > 0; 1153 ctrl = cqhci_readl(cq_host, CQHCI_CTL); 1154 if (!(ctrl & CQHCI_HALT) || timed_out) 1155 break; 1156 } 1157 /* 1158 * CQE usually resumes very quick, but incase if Tegra CQE 1159 * doesn't resume retry unhalt. 1160 */ 1161 if (timed_out) 1162 writel(val, cq_host->mmio + reg); 1163 } else { 1164 writel(val, cq_host->mmio + reg); 1165 } 1166 } 1167 1168 static void sdhci_tegra_update_dcmd_desc(struct mmc_host *mmc, 1169 struct mmc_request *mrq, u64 *data) 1170 { 1171 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(mmc_priv(mmc)); 1172 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1173 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 1174 1175 if (soc_data->nvquirks & NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING && 1176 mrq->cmd->flags & MMC_RSP_R1B) 1177 *data |= CQHCI_CMD_TIMING(1); 1178 } 1179 1180 static void sdhci_tegra_cqe_enable(struct mmc_host *mmc) 1181 { 1182 struct cqhci_host *cq_host = mmc->cqe_private; 1183 u32 val; 1184 1185 /* 1186 * Tegra CQHCI/SDMMC design prevents write access to sdhci block size 1187 * register when CQE is enabled and unhalted. 1188 * CQHCI driver enables CQE prior to activation, so disable CQE before 1189 * programming block size in sdhci controller and enable it back. 1190 */ 1191 if (!cq_host->activated) { 1192 val = cqhci_readl(cq_host, CQHCI_CFG); 1193 if (val & CQHCI_ENABLE) 1194 cqhci_writel(cq_host, (val & ~CQHCI_ENABLE), 1195 CQHCI_CFG); 1196 sdhci_cqe_enable(mmc); 1197 if (val & CQHCI_ENABLE) 1198 cqhci_writel(cq_host, val, CQHCI_CFG); 1199 } 1200 1201 /* 1202 * CMD CRC errors are seen sometimes with some eMMC devices when status 1203 * command is sent during transfer of last data block which is the 1204 * default case as send status command block counter (CBC) is 1. 1205 * Recommended fix to set CBC to 0 allowing send status command only 1206 * when data lines are idle. 1207 */ 1208 val = cqhci_readl(cq_host, CQHCI_SSC1); 1209 val &= ~CQHCI_SSC1_CBC_MASK; 1210 cqhci_writel(cq_host, val, CQHCI_SSC1); 1211 } 1212 1213 static void sdhci_tegra_dumpregs(struct mmc_host *mmc) 1214 { 1215 sdhci_dumpregs(mmc_priv(mmc)); 1216 } 1217 1218 static u32 sdhci_tegra_cqhci_irq(struct sdhci_host *host, u32 intmask) 1219 { 1220 int cmd_error = 0; 1221 int data_error = 0; 1222 1223 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 1224 return intmask; 1225 1226 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 1227 1228 return 0; 1229 } 1230 1231 static void tegra_sdhci_set_timeout(struct sdhci_host *host, 1232 struct mmc_command *cmd) 1233 { 1234 u32 val; 1235 1236 /* 1237 * HW busy detection timeout is based on programmed data timeout 1238 * counter and maximum supported timeout is 11s which may not be 1239 * enough for long operations like cache flush, sleep awake, erase. 1240 * 1241 * ERASE_TIMEOUT_LIMIT bit of VENDOR_MISC_CTRL register allows 1242 * host controller to wait for busy state until the card is busy 1243 * without HW timeout. 1244 * 1245 * So, use infinite busy wait mode for operations that may take 1246 * more than maximum HW busy timeout of 11s otherwise use finite 1247 * busy wait mode. 1248 */ 1249 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 1250 if (cmd && cmd->busy_timeout >= 11 * HZ) 1251 val |= SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT; 1252 else 1253 val &= ~SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT; 1254 sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_MISC_CTRL); 1255 1256 __sdhci_set_timeout(host, cmd); 1257 } 1258 1259 static const struct cqhci_host_ops sdhci_tegra_cqhci_ops = { 1260 .write_l = tegra_cqhci_writel, 1261 .enable = sdhci_tegra_cqe_enable, 1262 .disable = sdhci_cqe_disable, 1263 .dumpregs = sdhci_tegra_dumpregs, 1264 .update_dcmd_desc = sdhci_tegra_update_dcmd_desc, 1265 }; 1266 1267 static int tegra_sdhci_set_dma_mask(struct sdhci_host *host) 1268 { 1269 struct sdhci_pltfm_host *platform = sdhci_priv(host); 1270 struct sdhci_tegra *tegra = sdhci_pltfm_priv(platform); 1271 const struct sdhci_tegra_soc_data *soc = tegra->soc_data; 1272 struct device *dev = mmc_dev(host->mmc); 1273 1274 if (soc->dma_mask) 1275 return dma_set_mask_and_coherent(dev, soc->dma_mask); 1276 1277 return 0; 1278 } 1279 1280 static const struct sdhci_ops tegra_sdhci_ops = { 1281 .get_ro = tegra_sdhci_get_ro, 1282 .read_w = tegra_sdhci_readw, 1283 .write_l = tegra_sdhci_writel, 1284 .set_clock = tegra_sdhci_set_clock, 1285 .set_dma_mask = tegra_sdhci_set_dma_mask, 1286 .set_bus_width = sdhci_set_bus_width, 1287 .reset = tegra_sdhci_reset, 1288 .platform_execute_tuning = tegra_sdhci_execute_tuning, 1289 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 1290 .voltage_switch = tegra_sdhci_voltage_switch, 1291 .get_max_clock = tegra_sdhci_get_max_clock, 1292 }; 1293 1294 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { 1295 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1296 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1297 SDHCI_QUIRK_NO_HISPD_BIT | 1298 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1299 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1300 .ops = &tegra_sdhci_ops, 1301 }; 1302 1303 static const struct sdhci_tegra_soc_data soc_data_tegra20 = { 1304 .pdata = &sdhci_tegra20_pdata, 1305 .dma_mask = DMA_BIT_MASK(32), 1306 .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | 1307 NVQUIRK_ENABLE_BLOCK_GAP_DET, 1308 }; 1309 1310 static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { 1311 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1312 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 1313 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1314 SDHCI_QUIRK_NO_HISPD_BIT | 1315 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1316 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1317 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1318 SDHCI_QUIRK2_BROKEN_HS200 | 1319 /* 1320 * Auto-CMD23 leads to "Got command interrupt 0x00010000 even 1321 * though no command operation was in progress." 1322 * 1323 * The exact reason is unknown, as the same hardware seems 1324 * to support Auto CMD23 on a downstream 3.1 kernel. 1325 */ 1326 SDHCI_QUIRK2_ACMD23_BROKEN, 1327 .ops = &tegra_sdhci_ops, 1328 }; 1329 1330 static const struct sdhci_tegra_soc_data soc_data_tegra30 = { 1331 .pdata = &sdhci_tegra30_pdata, 1332 .dma_mask = DMA_BIT_MASK(32), 1333 .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | 1334 NVQUIRK_ENABLE_SDR50 | 1335 NVQUIRK_ENABLE_SDR104 | 1336 NVQUIRK_HAS_PADCALIB, 1337 }; 1338 1339 static const struct sdhci_ops tegra114_sdhci_ops = { 1340 .get_ro = tegra_sdhci_get_ro, 1341 .read_w = tegra_sdhci_readw, 1342 .write_w = tegra_sdhci_writew, 1343 .write_l = tegra_sdhci_writel, 1344 .set_clock = tegra_sdhci_set_clock, 1345 .set_dma_mask = tegra_sdhci_set_dma_mask, 1346 .set_bus_width = sdhci_set_bus_width, 1347 .reset = tegra_sdhci_reset, 1348 .platform_execute_tuning = tegra_sdhci_execute_tuning, 1349 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 1350 .voltage_switch = tegra_sdhci_voltage_switch, 1351 .get_max_clock = tegra_sdhci_get_max_clock, 1352 }; 1353 1354 static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { 1355 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1356 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 1357 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1358 SDHCI_QUIRK_NO_HISPD_BIT | 1359 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1360 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1361 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1362 .ops = &tegra114_sdhci_ops, 1363 }; 1364 1365 static const struct sdhci_tegra_soc_data soc_data_tegra114 = { 1366 .pdata = &sdhci_tegra114_pdata, 1367 .dma_mask = DMA_BIT_MASK(32), 1368 }; 1369 1370 static const struct sdhci_pltfm_data sdhci_tegra124_pdata = { 1371 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1372 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 1373 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1374 SDHCI_QUIRK_NO_HISPD_BIT | 1375 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1376 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1377 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1378 .ops = &tegra114_sdhci_ops, 1379 }; 1380 1381 static const struct sdhci_tegra_soc_data soc_data_tegra124 = { 1382 .pdata = &sdhci_tegra124_pdata, 1383 .dma_mask = DMA_BIT_MASK(34), 1384 }; 1385 1386 static const struct sdhci_ops tegra210_sdhci_ops = { 1387 .get_ro = tegra_sdhci_get_ro, 1388 .read_w = tegra_sdhci_readw, 1389 .write_w = tegra210_sdhci_writew, 1390 .write_l = tegra_sdhci_writel, 1391 .set_clock = tegra_sdhci_set_clock, 1392 .set_dma_mask = tegra_sdhci_set_dma_mask, 1393 .set_bus_width = sdhci_set_bus_width, 1394 .reset = tegra_sdhci_reset, 1395 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 1396 .voltage_switch = tegra_sdhci_voltage_switch, 1397 .get_max_clock = tegra_sdhci_get_max_clock, 1398 .set_timeout = tegra_sdhci_set_timeout, 1399 }; 1400 1401 static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { 1402 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1403 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 1404 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1405 SDHCI_QUIRK_NO_HISPD_BIT | 1406 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1407 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1408 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1409 .ops = &tegra210_sdhci_ops, 1410 }; 1411 1412 static const struct sdhci_tegra_soc_data soc_data_tegra210 = { 1413 .pdata = &sdhci_tegra210_pdata, 1414 .dma_mask = DMA_BIT_MASK(34), 1415 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 1416 NVQUIRK_HAS_PADCALIB | 1417 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | 1418 NVQUIRK_ENABLE_SDR50 | 1419 NVQUIRK_ENABLE_SDR104, 1420 .min_tap_delay = 106, 1421 .max_tap_delay = 185, 1422 }; 1423 1424 static const struct sdhci_ops tegra186_sdhci_ops = { 1425 .get_ro = tegra_sdhci_get_ro, 1426 .read_w = tegra_sdhci_readw, 1427 .write_l = tegra_sdhci_writel, 1428 .set_clock = tegra_sdhci_set_clock, 1429 .set_dma_mask = tegra_sdhci_set_dma_mask, 1430 .set_bus_width = sdhci_set_bus_width, 1431 .reset = tegra_sdhci_reset, 1432 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 1433 .voltage_switch = tegra_sdhci_voltage_switch, 1434 .get_max_clock = tegra_sdhci_get_max_clock, 1435 .irq = sdhci_tegra_cqhci_irq, 1436 .set_timeout = tegra_sdhci_set_timeout, 1437 }; 1438 1439 static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { 1440 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 1441 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 1442 SDHCI_QUIRK_SINGLE_POWER_WRITE | 1443 SDHCI_QUIRK_NO_HISPD_BIT | 1444 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 1445 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1446 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1447 .ops = &tegra186_sdhci_ops, 1448 }; 1449 1450 static const struct sdhci_tegra_soc_data soc_data_tegra186 = { 1451 .pdata = &sdhci_tegra186_pdata, 1452 .dma_mask = DMA_BIT_MASK(40), 1453 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 1454 NVQUIRK_HAS_PADCALIB | 1455 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | 1456 NVQUIRK_ENABLE_SDR50 | 1457 NVQUIRK_ENABLE_SDR104 | 1458 NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING, 1459 .min_tap_delay = 84, 1460 .max_tap_delay = 136, 1461 }; 1462 1463 static const struct sdhci_tegra_soc_data soc_data_tegra194 = { 1464 .pdata = &sdhci_tegra186_pdata, 1465 .dma_mask = DMA_BIT_MASK(39), 1466 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | 1467 NVQUIRK_HAS_PADCALIB | 1468 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | 1469 NVQUIRK_ENABLE_SDR50 | 1470 NVQUIRK_ENABLE_SDR104, 1471 .min_tap_delay = 96, 1472 .max_tap_delay = 139, 1473 }; 1474 1475 static const struct of_device_id sdhci_tegra_dt_match[] = { 1476 { .compatible = "nvidia,tegra194-sdhci", .data = &soc_data_tegra194 }, 1477 { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 }, 1478 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, 1479 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 }, 1480 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, 1481 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, 1482 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, 1483 {} 1484 }; 1485 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match); 1486 1487 static int sdhci_tegra_add_host(struct sdhci_host *host) 1488 { 1489 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1490 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1491 struct cqhci_host *cq_host; 1492 bool dma64; 1493 int ret; 1494 1495 if (!tegra_host->enable_hwcq) 1496 return sdhci_add_host(host); 1497 1498 sdhci_enable_v4_mode(host); 1499 1500 ret = sdhci_setup_host(host); 1501 if (ret) 1502 return ret; 1503 1504 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 1505 1506 cq_host = devm_kzalloc(host->mmc->parent, 1507 sizeof(*cq_host), GFP_KERNEL); 1508 if (!cq_host) { 1509 ret = -ENOMEM; 1510 goto cleanup; 1511 } 1512 1513 cq_host->mmio = host->ioaddr + SDHCI_TEGRA_CQE_BASE_ADDR; 1514 cq_host->ops = &sdhci_tegra_cqhci_ops; 1515 1516 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 1517 if (dma64) 1518 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 1519 1520 ret = cqhci_init(cq_host, host->mmc, dma64); 1521 if (ret) 1522 goto cleanup; 1523 1524 ret = __sdhci_add_host(host); 1525 if (ret) 1526 goto cleanup; 1527 1528 return 0; 1529 1530 cleanup: 1531 sdhci_cleanup_host(host); 1532 return ret; 1533 } 1534 1535 static int sdhci_tegra_probe(struct platform_device *pdev) 1536 { 1537 const struct of_device_id *match; 1538 const struct sdhci_tegra_soc_data *soc_data; 1539 struct sdhci_host *host; 1540 struct sdhci_pltfm_host *pltfm_host; 1541 struct sdhci_tegra *tegra_host; 1542 struct clk *clk; 1543 int rc; 1544 1545 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); 1546 if (!match) 1547 return -EINVAL; 1548 soc_data = match->data; 1549 1550 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host)); 1551 if (IS_ERR(host)) 1552 return PTR_ERR(host); 1553 pltfm_host = sdhci_priv(host); 1554 1555 tegra_host = sdhci_pltfm_priv(pltfm_host); 1556 tegra_host->ddr_signaling = false; 1557 tegra_host->pad_calib_required = false; 1558 tegra_host->pad_control_available = false; 1559 tegra_host->soc_data = soc_data; 1560 1561 if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) { 1562 rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host); 1563 if (rc == 0) 1564 host->mmc_host_ops.start_signal_voltage_switch = 1565 sdhci_tegra_start_signal_voltage_switch; 1566 } 1567 1568 /* Hook to periodically rerun pad calibration */ 1569 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 1570 host->mmc_host_ops.request = tegra_sdhci_request; 1571 1572 host->mmc_host_ops.hs400_enhanced_strobe = 1573 tegra_sdhci_hs400_enhanced_strobe; 1574 1575 if (!host->ops->platform_execute_tuning) 1576 host->mmc_host_ops.execute_tuning = 1577 tegra_sdhci_execute_hw_tuning; 1578 1579 rc = mmc_of_parse(host->mmc); 1580 if (rc) 1581 goto err_parse_dt; 1582 1583 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 1584 host->mmc->caps |= MMC_CAP_1_8V_DDR; 1585 1586 /* HW busy detection is supported, but R1B responses are required. */ 1587 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY; 1588 1589 tegra_sdhci_parse_dt(host); 1590 1591 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", 1592 GPIOD_OUT_HIGH); 1593 if (IS_ERR(tegra_host->power_gpio)) { 1594 rc = PTR_ERR(tegra_host->power_gpio); 1595 goto err_power_req; 1596 } 1597 1598 clk = devm_clk_get(mmc_dev(host->mmc), NULL); 1599 if (IS_ERR(clk)) { 1600 rc = PTR_ERR(clk); 1601 1602 if (rc != -EPROBE_DEFER) 1603 dev_err(&pdev->dev, "failed to get clock: %d\n", rc); 1604 1605 goto err_clk_get; 1606 } 1607 clk_prepare_enable(clk); 1608 pltfm_host->clk = clk; 1609 1610 tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev, 1611 "sdhci"); 1612 if (IS_ERR(tegra_host->rst)) { 1613 rc = PTR_ERR(tegra_host->rst); 1614 dev_err(&pdev->dev, "failed to get reset control: %d\n", rc); 1615 goto err_rst_get; 1616 } 1617 1618 rc = reset_control_assert(tegra_host->rst); 1619 if (rc) 1620 goto err_rst_get; 1621 1622 usleep_range(2000, 4000); 1623 1624 rc = reset_control_deassert(tegra_host->rst); 1625 if (rc) 1626 goto err_rst_get; 1627 1628 usleep_range(2000, 4000); 1629 1630 rc = sdhci_tegra_add_host(host); 1631 if (rc) 1632 goto err_add_host; 1633 1634 return 0; 1635 1636 err_add_host: 1637 reset_control_assert(tegra_host->rst); 1638 err_rst_get: 1639 clk_disable_unprepare(pltfm_host->clk); 1640 err_clk_get: 1641 err_power_req: 1642 err_parse_dt: 1643 sdhci_pltfm_free(pdev); 1644 return rc; 1645 } 1646 1647 static int sdhci_tegra_remove(struct platform_device *pdev) 1648 { 1649 struct sdhci_host *host = platform_get_drvdata(pdev); 1650 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1651 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 1652 1653 sdhci_remove_host(host, 0); 1654 1655 reset_control_assert(tegra_host->rst); 1656 usleep_range(2000, 4000); 1657 clk_disable_unprepare(pltfm_host->clk); 1658 1659 sdhci_pltfm_free(pdev); 1660 1661 return 0; 1662 } 1663 1664 #ifdef CONFIG_PM_SLEEP 1665 static int __maybe_unused sdhci_tegra_suspend(struct device *dev) 1666 { 1667 struct sdhci_host *host = dev_get_drvdata(dev); 1668 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1669 int ret; 1670 1671 if (host->mmc->caps2 & MMC_CAP2_CQE) { 1672 ret = cqhci_suspend(host->mmc); 1673 if (ret) 1674 return ret; 1675 } 1676 1677 ret = sdhci_suspend_host(host); 1678 if (ret) { 1679 cqhci_resume(host->mmc); 1680 return ret; 1681 } 1682 1683 clk_disable_unprepare(pltfm_host->clk); 1684 return 0; 1685 } 1686 1687 static int __maybe_unused sdhci_tegra_resume(struct device *dev) 1688 { 1689 struct sdhci_host *host = dev_get_drvdata(dev); 1690 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1691 int ret; 1692 1693 ret = clk_prepare_enable(pltfm_host->clk); 1694 if (ret) 1695 return ret; 1696 1697 ret = sdhci_resume_host(host); 1698 if (ret) 1699 goto disable_clk; 1700 1701 if (host->mmc->caps2 & MMC_CAP2_CQE) { 1702 ret = cqhci_resume(host->mmc); 1703 if (ret) 1704 goto suspend_host; 1705 } 1706 1707 return 0; 1708 1709 suspend_host: 1710 sdhci_suspend_host(host); 1711 disable_clk: 1712 clk_disable_unprepare(pltfm_host->clk); 1713 return ret; 1714 } 1715 #endif 1716 1717 static SIMPLE_DEV_PM_OPS(sdhci_tegra_dev_pm_ops, sdhci_tegra_suspend, 1718 sdhci_tegra_resume); 1719 1720 static struct platform_driver sdhci_tegra_driver = { 1721 .driver = { 1722 .name = "sdhci-tegra", 1723 .of_match_table = sdhci_tegra_dt_match, 1724 .pm = &sdhci_tegra_dev_pm_ops, 1725 }, 1726 .probe = sdhci_tegra_probe, 1727 .remove = sdhci_tegra_remove, 1728 }; 1729 1730 module_platform_driver(sdhci_tegra_driver); 1731 1732 MODULE_DESCRIPTION("SDHCI driver for Tegra"); 1733 MODULE_AUTHOR("Google, Inc."); 1734 MODULE_LICENSE("GPL v2"); 1735