1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Synopsys DesignWare PCIe host controller driver 4 * 5 * Copyright (C) 2013 Samsung Electronics Co., Ltd. 6 * http://www.samsung.com 7 * 8 * Author: Jingoo Han <jg1.han@samsung.com> 9 */ 10 11 #include <linux/irqchip/chained_irq.h> 12 #include <linux/irqdomain.h> 13 #include <linux/msi.h> 14 #include <linux/of_address.h> 15 #include <linux/of_pci.h> 16 #include <linux/pci_regs.h> 17 #include <linux/platform_device.h> 18 19 #include "../../pci.h" 20 #include "pcie-designware.h" 21 22 static struct pci_ops dw_pcie_ops; 23 24 static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, 25 u32 *val) 26 { 27 struct dw_pcie *pci; 28 29 if (pp->ops->rd_own_conf) 30 return pp->ops->rd_own_conf(pp, where, size, val); 31 32 pci = to_dw_pcie_from_pp(pp); 33 return dw_pcie_read(pci->dbi_base + where, size, val); 34 } 35 36 static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, 37 u32 val) 38 { 39 struct dw_pcie *pci; 40 41 if (pp->ops->wr_own_conf) 42 return pp->ops->wr_own_conf(pp, where, size, val); 43 44 pci = to_dw_pcie_from_pp(pp); 45 return dw_pcie_write(pci->dbi_base + where, size, val); 46 } 47 48 static void dw_msi_ack_irq(struct irq_data *d) 49 { 50 irq_chip_ack_parent(d); 51 } 52 53 static void dw_msi_mask_irq(struct irq_data *d) 54 { 55 pci_msi_mask_irq(d); 56 irq_chip_mask_parent(d); 57 } 58 59 static void dw_msi_unmask_irq(struct irq_data *d) 60 { 61 pci_msi_unmask_irq(d); 62 irq_chip_unmask_parent(d); 63 } 64 65 static struct irq_chip dw_pcie_msi_irq_chip = { 66 .name = "PCI-MSI", 67 .irq_ack = dw_msi_ack_irq, 68 .irq_mask = dw_msi_mask_irq, 69 .irq_unmask = dw_msi_unmask_irq, 70 }; 71 72 static struct msi_domain_info dw_pcie_msi_domain_info = { 73 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 74 MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI), 75 .chip = &dw_pcie_msi_irq_chip, 76 }; 77 78 /* MSI int handler */ 79 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) 80 { 81 int i, pos, irq; 82 unsigned long val; 83 u32 status, num_ctrls; 84 irqreturn_t ret = IRQ_NONE; 85 86 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; 87 88 for (i = 0; i < num_ctrls; i++) { 89 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + 90 (i * MSI_REG_CTRL_BLOCK_SIZE), 91 4, &status); 92 if (!status) 93 continue; 94 95 ret = IRQ_HANDLED; 96 val = status; 97 pos = 0; 98 while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, 99 pos)) != MAX_MSI_IRQS_PER_CTRL) { 100 irq = irq_find_mapping(pp->irq_domain, 101 (i * MAX_MSI_IRQS_PER_CTRL) + 102 pos); 103 generic_handle_irq(irq); 104 pos++; 105 } 106 } 107 108 return ret; 109 } 110 111 /* Chained MSI interrupt service routine */ 112 static void dw_chained_msi_isr(struct irq_desc *desc) 113 { 114 struct irq_chip *chip = irq_desc_get_chip(desc); 115 struct pcie_port *pp; 116 117 chained_irq_enter(chip, desc); 118 119 pp = irq_desc_get_handler_data(desc); 120 dw_handle_msi_irq(pp); 121 122 chained_irq_exit(chip, desc); 123 } 124 125 static void dw_pci_setup_msi_msg(struct irq_data *d, struct msi_msg *msg) 126 { 127 struct pcie_port *pp = irq_data_get_irq_chip_data(d); 128 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 129 u64 msi_target; 130 131 msi_target = (u64)pp->msi_data; 132 133 msg->address_lo = lower_32_bits(msi_target); 134 msg->address_hi = upper_32_bits(msi_target); 135 136 msg->data = d->hwirq; 137 138 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n", 139 (int)d->hwirq, msg->address_hi, msg->address_lo); 140 } 141 142 static int dw_pci_msi_set_affinity(struct irq_data *d, 143 const struct cpumask *mask, bool force) 144 { 145 return -EINVAL; 146 } 147 148 static void dw_pci_bottom_mask(struct irq_data *d) 149 { 150 struct pcie_port *pp = irq_data_get_irq_chip_data(d); 151 unsigned int res, bit, ctrl; 152 unsigned long flags; 153 154 raw_spin_lock_irqsave(&pp->lock, flags); 155 156 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; 157 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; 158 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; 159 160 pp->irq_mask[ctrl] |= BIT(bit); 161 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4, 162 pp->irq_mask[ctrl]); 163 164 raw_spin_unlock_irqrestore(&pp->lock, flags); 165 } 166 167 static void dw_pci_bottom_unmask(struct irq_data *d) 168 { 169 struct pcie_port *pp = irq_data_get_irq_chip_data(d); 170 unsigned int res, bit, ctrl; 171 unsigned long flags; 172 173 raw_spin_lock_irqsave(&pp->lock, flags); 174 175 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; 176 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; 177 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; 178 179 pp->irq_mask[ctrl] &= ~BIT(bit); 180 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4, 181 pp->irq_mask[ctrl]); 182 183 raw_spin_unlock_irqrestore(&pp->lock, flags); 184 } 185 186 static void dw_pci_bottom_ack(struct irq_data *d) 187 { 188 struct pcie_port *pp = irq_data_get_irq_chip_data(d); 189 unsigned int res, bit, ctrl; 190 191 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; 192 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; 193 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; 194 195 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + res, 4, BIT(bit)); 196 } 197 198 static struct irq_chip dw_pci_msi_bottom_irq_chip = { 199 .name = "DWPCI-MSI", 200 .irq_ack = dw_pci_bottom_ack, 201 .irq_compose_msi_msg = dw_pci_setup_msi_msg, 202 .irq_set_affinity = dw_pci_msi_set_affinity, 203 .irq_mask = dw_pci_bottom_mask, 204 .irq_unmask = dw_pci_bottom_unmask, 205 }; 206 207 static int dw_pcie_irq_domain_alloc(struct irq_domain *domain, 208 unsigned int virq, unsigned int nr_irqs, 209 void *args) 210 { 211 struct pcie_port *pp = domain->host_data; 212 unsigned long flags; 213 u32 i; 214 int bit; 215 216 raw_spin_lock_irqsave(&pp->lock, flags); 217 218 bit = bitmap_find_free_region(pp->msi_irq_in_use, pp->num_vectors, 219 order_base_2(nr_irqs)); 220 221 raw_spin_unlock_irqrestore(&pp->lock, flags); 222 223 if (bit < 0) 224 return -ENOSPC; 225 226 for (i = 0; i < nr_irqs; i++) 227 irq_domain_set_info(domain, virq + i, bit + i, 228 pp->msi_irq_chip, 229 pp, handle_edge_irq, 230 NULL, NULL); 231 232 return 0; 233 } 234 235 static void dw_pcie_irq_domain_free(struct irq_domain *domain, 236 unsigned int virq, unsigned int nr_irqs) 237 { 238 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 239 struct pcie_port *pp = domain->host_data; 240 unsigned long flags; 241 242 raw_spin_lock_irqsave(&pp->lock, flags); 243 244 bitmap_release_region(pp->msi_irq_in_use, d->hwirq, 245 order_base_2(nr_irqs)); 246 247 raw_spin_unlock_irqrestore(&pp->lock, flags); 248 } 249 250 static const struct irq_domain_ops dw_pcie_msi_domain_ops = { 251 .alloc = dw_pcie_irq_domain_alloc, 252 .free = dw_pcie_irq_domain_free, 253 }; 254 255 int dw_pcie_allocate_domains(struct pcie_port *pp) 256 { 257 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 258 struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node); 259 260 pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors, 261 &dw_pcie_msi_domain_ops, pp); 262 if (!pp->irq_domain) { 263 dev_err(pci->dev, "Failed to create IRQ domain\n"); 264 return -ENOMEM; 265 } 266 267 irq_domain_update_bus_token(pp->irq_domain, DOMAIN_BUS_NEXUS); 268 269 pp->msi_domain = pci_msi_create_irq_domain(fwnode, 270 &dw_pcie_msi_domain_info, 271 pp->irq_domain); 272 if (!pp->msi_domain) { 273 dev_err(pci->dev, "Failed to create MSI domain\n"); 274 irq_domain_remove(pp->irq_domain); 275 return -ENOMEM; 276 } 277 278 return 0; 279 } 280 281 void dw_pcie_free_msi(struct pcie_port *pp) 282 { 283 if (pp->msi_irq) { 284 irq_set_chained_handler(pp->msi_irq, NULL); 285 irq_set_handler_data(pp->msi_irq, NULL); 286 } 287 288 irq_domain_remove(pp->msi_domain); 289 irq_domain_remove(pp->irq_domain); 290 291 if (pp->msi_page) 292 __free_page(pp->msi_page); 293 } 294 295 void dw_pcie_msi_init(struct pcie_port *pp) 296 { 297 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 298 struct device *dev = pci->dev; 299 u64 msi_target; 300 301 pp->msi_page = alloc_page(GFP_KERNEL); 302 pp->msi_data = dma_map_page(dev, pp->msi_page, 0, PAGE_SIZE, 303 DMA_FROM_DEVICE); 304 if (dma_mapping_error(dev, pp->msi_data)) { 305 dev_err(dev, "Failed to map MSI data\n"); 306 __free_page(pp->msi_page); 307 pp->msi_page = NULL; 308 return; 309 } 310 msi_target = (u64)pp->msi_data; 311 312 /* Program the msi_data */ 313 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4, 314 lower_32_bits(msi_target)); 315 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 316 upper_32_bits(msi_target)); 317 } 318 EXPORT_SYMBOL_GPL(dw_pcie_msi_init); 319 320 int dw_pcie_host_init(struct pcie_port *pp) 321 { 322 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 323 struct device *dev = pci->dev; 324 struct device_node *np = dev->of_node; 325 struct platform_device *pdev = to_platform_device(dev); 326 struct resource_entry *win; 327 struct pci_bus *child; 328 struct pci_host_bridge *bridge; 329 struct resource *cfg_res; 330 u32 hdr_type; 331 int ret; 332 333 raw_spin_lock_init(&pci->pp.lock); 334 335 cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); 336 if (cfg_res) { 337 pp->cfg0_size = resource_size(cfg_res) >> 1; 338 pp->cfg1_size = resource_size(cfg_res) >> 1; 339 pp->cfg0_base = cfg_res->start; 340 pp->cfg1_base = cfg_res->start + pp->cfg0_size; 341 } else if (!pp->va_cfg0_base) { 342 dev_err(dev, "Missing *config* reg space\n"); 343 } 344 345 bridge = devm_pci_alloc_host_bridge(dev, 0); 346 if (!bridge) 347 return -ENOMEM; 348 349 ret = pci_parse_request_of_pci_ranges(dev, &bridge->windows, 350 &bridge->dma_ranges, NULL); 351 if (ret) 352 return ret; 353 354 /* Get the I/O and memory ranges from DT */ 355 resource_list_for_each_entry(win, &bridge->windows) { 356 switch (resource_type(win->res)) { 357 case IORESOURCE_IO: 358 pp->io = win->res; 359 pp->io->name = "I/O"; 360 pp->io_size = resource_size(pp->io); 361 pp->io_bus_addr = pp->io->start - win->offset; 362 pp->io_base = pci_pio_to_address(pp->io->start); 363 break; 364 case IORESOURCE_MEM: 365 pp->mem = win->res; 366 pp->mem->name = "MEM"; 367 pp->mem_size = resource_size(pp->mem); 368 pp->mem_bus_addr = pp->mem->start - win->offset; 369 break; 370 case 0: 371 pp->cfg = win->res; 372 pp->cfg0_size = resource_size(pp->cfg) >> 1; 373 pp->cfg1_size = resource_size(pp->cfg) >> 1; 374 pp->cfg0_base = pp->cfg->start; 375 pp->cfg1_base = pp->cfg->start + pp->cfg0_size; 376 break; 377 case IORESOURCE_BUS: 378 pp->busn = win->res; 379 break; 380 } 381 } 382 383 if (!pci->dbi_base) { 384 pci->dbi_base = devm_pci_remap_cfgspace(dev, 385 pp->cfg->start, 386 resource_size(pp->cfg)); 387 if (!pci->dbi_base) { 388 dev_err(dev, "Error with ioremap\n"); 389 return -ENOMEM; 390 } 391 } 392 393 pp->mem_base = pp->mem->start; 394 395 if (!pp->va_cfg0_base) { 396 pp->va_cfg0_base = devm_pci_remap_cfgspace(dev, 397 pp->cfg0_base, pp->cfg0_size); 398 if (!pp->va_cfg0_base) { 399 dev_err(dev, "Error with ioremap in function\n"); 400 return -ENOMEM; 401 } 402 } 403 404 if (!pp->va_cfg1_base) { 405 pp->va_cfg1_base = devm_pci_remap_cfgspace(dev, 406 pp->cfg1_base, 407 pp->cfg1_size); 408 if (!pp->va_cfg1_base) { 409 dev_err(dev, "Error with ioremap\n"); 410 return -ENOMEM; 411 } 412 } 413 414 ret = of_property_read_u32(np, "num-viewport", &pci->num_viewport); 415 if (ret) 416 pci->num_viewport = 2; 417 418 if (pci_msi_enabled()) { 419 /* 420 * If a specific SoC driver needs to change the 421 * default number of vectors, it needs to implement 422 * the set_num_vectors callback. 423 */ 424 if (!pp->ops->set_num_vectors) { 425 pp->num_vectors = MSI_DEF_NUM_VECTORS; 426 } else { 427 pp->ops->set_num_vectors(pp); 428 429 if (pp->num_vectors > MAX_MSI_IRQS || 430 pp->num_vectors == 0) { 431 dev_err(dev, 432 "Invalid number of vectors\n"); 433 return -EINVAL; 434 } 435 } 436 437 if (!pp->ops->msi_host_init) { 438 pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; 439 440 ret = dw_pcie_allocate_domains(pp); 441 if (ret) 442 return ret; 443 444 if (pp->msi_irq) 445 irq_set_chained_handler_and_data(pp->msi_irq, 446 dw_chained_msi_isr, 447 pp); 448 } else { 449 ret = pp->ops->msi_host_init(pp); 450 if (ret < 0) 451 return ret; 452 } 453 } 454 455 if (pp->ops->host_init) { 456 ret = pp->ops->host_init(pp); 457 if (ret) 458 goto err_free_msi; 459 } 460 461 ret = dw_pcie_rd_own_conf(pp, PCI_HEADER_TYPE, 1, &hdr_type); 462 if (ret != PCIBIOS_SUCCESSFUL) { 463 dev_err(pci->dev, "Failed reading PCI_HEADER_TYPE cfg space reg (ret: 0x%x)\n", 464 ret); 465 ret = pcibios_err_to_errno(ret); 466 goto err_free_msi; 467 } 468 if (hdr_type != PCI_HEADER_TYPE_BRIDGE) { 469 dev_err(pci->dev, 470 "PCIe controller is not set to bridge type (hdr_type: 0x%x)!\n", 471 hdr_type); 472 ret = -EIO; 473 goto err_free_msi; 474 } 475 476 pp->root_bus_nr = pp->busn->start; 477 478 bridge->dev.parent = dev; 479 bridge->sysdata = pp; 480 bridge->busnr = pp->root_bus_nr; 481 bridge->ops = &dw_pcie_ops; 482 bridge->map_irq = of_irq_parse_and_map_pci; 483 bridge->swizzle_irq = pci_common_swizzle; 484 485 ret = pci_scan_root_bus_bridge(bridge); 486 if (ret) 487 goto err_free_msi; 488 489 pp->root_bus = bridge->bus; 490 491 if (pp->ops->scan_bus) 492 pp->ops->scan_bus(pp); 493 494 pci_bus_size_bridges(pp->root_bus); 495 pci_bus_assign_resources(pp->root_bus); 496 497 list_for_each_entry(child, &pp->root_bus->children, node) 498 pcie_bus_configure_settings(child); 499 500 pci_bus_add_devices(pp->root_bus); 501 return 0; 502 503 err_free_msi: 504 if (pci_msi_enabled() && !pp->ops->msi_host_init) 505 dw_pcie_free_msi(pp); 506 return ret; 507 } 508 EXPORT_SYMBOL_GPL(dw_pcie_host_init); 509 510 void dw_pcie_host_deinit(struct pcie_port *pp) 511 { 512 pci_stop_root_bus(pp->root_bus); 513 pci_remove_root_bus(pp->root_bus); 514 if (pci_msi_enabled() && !pp->ops->msi_host_init) 515 dw_pcie_free_msi(pp); 516 } 517 EXPORT_SYMBOL_GPL(dw_pcie_host_deinit); 518 519 static int dw_pcie_access_other_conf(struct pcie_port *pp, struct pci_bus *bus, 520 u32 devfn, int where, int size, u32 *val, 521 bool write) 522 { 523 int ret, type; 524 u32 busdev, cfg_size; 525 u64 cpu_addr; 526 void __iomem *va_cfg_base; 527 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 528 529 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | 530 PCIE_ATU_FUNC(PCI_FUNC(devfn)); 531 532 if (bus->parent->number == pp->root_bus_nr) { 533 type = PCIE_ATU_TYPE_CFG0; 534 cpu_addr = pp->cfg0_base; 535 cfg_size = pp->cfg0_size; 536 va_cfg_base = pp->va_cfg0_base; 537 } else { 538 type = PCIE_ATU_TYPE_CFG1; 539 cpu_addr = pp->cfg1_base; 540 cfg_size = pp->cfg1_size; 541 va_cfg_base = pp->va_cfg1_base; 542 } 543 544 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1, 545 type, cpu_addr, 546 busdev, cfg_size); 547 if (write) 548 ret = dw_pcie_write(va_cfg_base + where, size, *val); 549 else 550 ret = dw_pcie_read(va_cfg_base + where, size, val); 551 552 if (pci->num_viewport <= 2) 553 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1, 554 PCIE_ATU_TYPE_IO, pp->io_base, 555 pp->io_bus_addr, pp->io_size); 556 557 return ret; 558 } 559 560 static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, 561 u32 devfn, int where, int size, u32 *val) 562 { 563 if (pp->ops->rd_other_conf) 564 return pp->ops->rd_other_conf(pp, bus, devfn, where, 565 size, val); 566 567 return dw_pcie_access_other_conf(pp, bus, devfn, where, size, val, 568 false); 569 } 570 571 static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, 572 u32 devfn, int where, int size, u32 val) 573 { 574 if (pp->ops->wr_other_conf) 575 return pp->ops->wr_other_conf(pp, bus, devfn, where, 576 size, val); 577 578 return dw_pcie_access_other_conf(pp, bus, devfn, where, size, &val, 579 true); 580 } 581 582 static int dw_pcie_valid_device(struct pcie_port *pp, struct pci_bus *bus, 583 int dev) 584 { 585 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 586 587 /* If there is no link, then there is no device */ 588 if (bus->number != pp->root_bus_nr) { 589 if (!dw_pcie_link_up(pci)) 590 return 0; 591 } 592 593 /* Access only one slot on each root port */ 594 if (bus->number == pp->root_bus_nr && dev > 0) 595 return 0; 596 597 return 1; 598 } 599 600 static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, 601 int size, u32 *val) 602 { 603 struct pcie_port *pp = bus->sysdata; 604 605 if (!dw_pcie_valid_device(pp, bus, PCI_SLOT(devfn))) { 606 *val = 0xffffffff; 607 return PCIBIOS_DEVICE_NOT_FOUND; 608 } 609 610 if (bus->number == pp->root_bus_nr) 611 return dw_pcie_rd_own_conf(pp, where, size, val); 612 613 return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val); 614 } 615 616 static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn, 617 int where, int size, u32 val) 618 { 619 struct pcie_port *pp = bus->sysdata; 620 621 if (!dw_pcie_valid_device(pp, bus, PCI_SLOT(devfn))) 622 return PCIBIOS_DEVICE_NOT_FOUND; 623 624 if (bus->number == pp->root_bus_nr) 625 return dw_pcie_wr_own_conf(pp, where, size, val); 626 627 return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val); 628 } 629 630 static struct pci_ops dw_pcie_ops = { 631 .read = dw_pcie_rd_conf, 632 .write = dw_pcie_wr_conf, 633 }; 634 635 void dw_pcie_setup_rc(struct pcie_port *pp) 636 { 637 u32 val, ctrl, num_ctrls; 638 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 639 640 /* 641 * Enable DBI read-only registers for writing/updating configuration. 642 * Write permission gets disabled towards the end of this function. 643 */ 644 dw_pcie_dbi_ro_wr_en(pci); 645 646 dw_pcie_setup(pci); 647 648 if (!pp->ops->msi_host_init) { 649 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; 650 651 /* Initialize IRQ Status array */ 652 for (ctrl = 0; ctrl < num_ctrls; ctrl++) { 653 pp->irq_mask[ctrl] = ~0; 654 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + 655 (ctrl * MSI_REG_CTRL_BLOCK_SIZE), 656 4, pp->irq_mask[ctrl]); 657 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + 658 (ctrl * MSI_REG_CTRL_BLOCK_SIZE), 659 4, ~0); 660 } 661 } 662 663 /* Setup RC BARs */ 664 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004); 665 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000); 666 667 /* Setup interrupt pins */ 668 val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE); 669 val &= 0xffff00ff; 670 val |= 0x00000100; 671 dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val); 672 673 /* Setup bus numbers */ 674 val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS); 675 val &= 0xff000000; 676 val |= 0x00ff0100; 677 dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val); 678 679 /* Setup command register */ 680 val = dw_pcie_readl_dbi(pci, PCI_COMMAND); 681 val &= 0xffff0000; 682 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 683 PCI_COMMAND_MASTER | PCI_COMMAND_SERR; 684 dw_pcie_writel_dbi(pci, PCI_COMMAND, val); 685 686 /* 687 * If the platform provides ->rd_other_conf, it means the platform 688 * uses its own address translation component rather than ATU, so 689 * we should not program the ATU here. 690 */ 691 if (!pp->ops->rd_other_conf) { 692 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0, 693 PCIE_ATU_TYPE_MEM, pp->mem_base, 694 pp->mem_bus_addr, pp->mem_size); 695 if (pci->num_viewport > 2) 696 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX2, 697 PCIE_ATU_TYPE_IO, pp->io_base, 698 pp->io_bus_addr, pp->io_size); 699 } 700 701 dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); 702 703 /* Program correct class for RC */ 704 dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); 705 706 dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); 707 val |= PORT_LOGIC_SPEED_CHANGE; 708 dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); 709 710 dw_pcie_dbi_ro_wr_dis(pci); 711 } 712 EXPORT_SYMBOL_GPL(dw_pcie_setup_rc); 713