1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3328-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3328-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3328"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 serial0 = &uart0; 24 serial1 = &uart1; 25 serial2 = &uart2; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 ethernet0 = &gmac2io; 31 ethernet1 = &gmac2phy; 32 }; 33 34 cpus { 35 #address-cells = <2>; 36 #size-cells = <0>; 37 38 cpu0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a53"; 41 reg = <0x0 0x0>; 42 clocks = <&cru ARMCLK>; 43 #cooling-cells = <2>; 44 cpu-idle-states = <&CPU_SLEEP>; 45 dynamic-power-coefficient = <120>; 46 enable-method = "psci"; 47 next-level-cache = <&l2>; 48 operating-points-v2 = <&cpu0_opp_table>; 49 }; 50 51 cpu1: cpu@1 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53"; 54 reg = <0x0 0x1>; 55 clocks = <&cru ARMCLK>; 56 #cooling-cells = <2>; 57 cpu-idle-states = <&CPU_SLEEP>; 58 dynamic-power-coefficient = <120>; 59 enable-method = "psci"; 60 next-level-cache = <&l2>; 61 operating-points-v2 = <&cpu0_opp_table>; 62 }; 63 64 cpu2: cpu@2 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a53"; 67 reg = <0x0 0x2>; 68 clocks = <&cru ARMCLK>; 69 #cooling-cells = <2>; 70 cpu-idle-states = <&CPU_SLEEP>; 71 dynamic-power-coefficient = <120>; 72 enable-method = "psci"; 73 next-level-cache = <&l2>; 74 operating-points-v2 = <&cpu0_opp_table>; 75 }; 76 77 cpu3: cpu@3 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a53"; 80 reg = <0x0 0x3>; 81 clocks = <&cru ARMCLK>; 82 #cooling-cells = <2>; 83 cpu-idle-states = <&CPU_SLEEP>; 84 dynamic-power-coefficient = <120>; 85 enable-method = "psci"; 86 next-level-cache = <&l2>; 87 operating-points-v2 = <&cpu0_opp_table>; 88 }; 89 90 idle-states { 91 entry-method = "psci"; 92 93 CPU_SLEEP: cpu-sleep { 94 compatible = "arm,idle-state"; 95 local-timer-stop; 96 arm,psci-suspend-param = <0x0010000>; 97 entry-latency-us = <120>; 98 exit-latency-us = <250>; 99 min-residency-us = <900>; 100 }; 101 }; 102 103 l2: l2-cache0 { 104 compatible = "cache"; 105 }; 106 }; 107 108 cpu0_opp_table: opp_table0 { 109 compatible = "operating-points-v2"; 110 opp-shared; 111 112 opp-408000000 { 113 opp-hz = /bits/ 64 <408000000>; 114 opp-microvolt = <950000>; 115 clock-latency-ns = <40000>; 116 opp-suspend; 117 }; 118 opp-600000000 { 119 opp-hz = /bits/ 64 <600000000>; 120 opp-microvolt = <950000>; 121 clock-latency-ns = <40000>; 122 }; 123 opp-816000000 { 124 opp-hz = /bits/ 64 <816000000>; 125 opp-microvolt = <1000000>; 126 clock-latency-ns = <40000>; 127 }; 128 opp-1008000000 { 129 opp-hz = /bits/ 64 <1008000000>; 130 opp-microvolt = <1100000>; 131 clock-latency-ns = <40000>; 132 }; 133 opp-1200000000 { 134 opp-hz = /bits/ 64 <1200000000>; 135 opp-microvolt = <1225000>; 136 clock-latency-ns = <40000>; 137 }; 138 opp-1296000000 { 139 opp-hz = /bits/ 64 <1296000000>; 140 opp-microvolt = <1300000>; 141 clock-latency-ns = <40000>; 142 }; 143 }; 144 145 amba { 146 compatible = "simple-bus"; 147 #address-cells = <2>; 148 #size-cells = <2>; 149 ranges; 150 151 dmac: dmac@ff1f0000 { 152 compatible = "arm,pl330", "arm,primecell"; 153 reg = <0x0 0xff1f0000 0x0 0x4000>; 154 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 156 clocks = <&cru ACLK_DMAC>; 157 clock-names = "apb_pclk"; 158 #dma-cells = <1>; 159 }; 160 }; 161 162 analog_sound: analog-sound { 163 compatible = "simple-audio-card"; 164 simple-audio-card,format = "i2s"; 165 simple-audio-card,mclk-fs = <256>; 166 simple-audio-card,name = "Analog"; 167 status = "disabled"; 168 169 simple-audio-card,cpu { 170 sound-dai = <&i2s1>; 171 }; 172 173 simple-audio-card,codec { 174 sound-dai = <&codec>; 175 }; 176 }; 177 178 arm-pmu { 179 compatible = "arm,cortex-a53-pmu"; 180 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 184 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 185 }; 186 187 display_subsystem: display-subsystem { 188 compatible = "rockchip,display-subsystem"; 189 ports = <&vop_out>; 190 }; 191 192 hdmi_sound: hdmi-sound { 193 compatible = "simple-audio-card"; 194 simple-audio-card,format = "i2s"; 195 simple-audio-card,mclk-fs = <128>; 196 simple-audio-card,name = "HDMI"; 197 status = "disabled"; 198 199 simple-audio-card,cpu { 200 sound-dai = <&i2s0>; 201 }; 202 203 simple-audio-card,codec { 204 sound-dai = <&hdmi>; 205 }; 206 }; 207 208 psci { 209 compatible = "arm,psci-1.0", "arm,psci-0.2"; 210 method = "smc"; 211 }; 212 213 timer { 214 compatible = "arm,armv8-timer"; 215 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 216 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 217 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 218 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 219 }; 220 221 xin24m: xin24m { 222 compatible = "fixed-clock"; 223 #clock-cells = <0>; 224 clock-frequency = <24000000>; 225 clock-output-names = "xin24m"; 226 }; 227 228 i2s0: i2s@ff000000 { 229 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 230 reg = <0x0 0xff000000 0x0 0x1000>; 231 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 232 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 233 clock-names = "i2s_clk", "i2s_hclk"; 234 dmas = <&dmac 11>, <&dmac 12>; 235 dma-names = "tx", "rx"; 236 #sound-dai-cells = <0>; 237 status = "disabled"; 238 }; 239 240 i2s1: i2s@ff010000 { 241 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 242 reg = <0x0 0xff010000 0x0 0x1000>; 243 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 245 clock-names = "i2s_clk", "i2s_hclk"; 246 dmas = <&dmac 14>, <&dmac 15>; 247 dma-names = "tx", "rx"; 248 #sound-dai-cells = <0>; 249 status = "disabled"; 250 }; 251 252 i2s2: i2s@ff020000 { 253 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 254 reg = <0x0 0xff020000 0x0 0x1000>; 255 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 256 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 257 clock-names = "i2s_clk", "i2s_hclk"; 258 dmas = <&dmac 0>, <&dmac 1>; 259 dma-names = "tx", "rx"; 260 #sound-dai-cells = <0>; 261 status = "disabled"; 262 }; 263 264 spdif: spdif@ff030000 { 265 compatible = "rockchip,rk3328-spdif"; 266 reg = <0x0 0xff030000 0x0 0x1000>; 267 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 269 clock-names = "mclk", "hclk"; 270 dmas = <&dmac 10>; 271 dma-names = "tx"; 272 pinctrl-names = "default"; 273 pinctrl-0 = <&spdifm2_tx>; 274 #sound-dai-cells = <0>; 275 status = "disabled"; 276 }; 277 278 pdm: pdm@ff040000 { 279 compatible = "rockchip,pdm"; 280 reg = <0x0 0xff040000 0x0 0x1000>; 281 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 282 clock-names = "pdm_clk", "pdm_hclk"; 283 dmas = <&dmac 16>; 284 dma-names = "rx"; 285 pinctrl-names = "default", "sleep"; 286 pinctrl-0 = <&pdmm0_clk 287 &pdmm0_sdi0 288 &pdmm0_sdi1 289 &pdmm0_sdi2 290 &pdmm0_sdi3>; 291 pinctrl-1 = <&pdmm0_clk_sleep 292 &pdmm0_sdi0_sleep 293 &pdmm0_sdi1_sleep 294 &pdmm0_sdi2_sleep 295 &pdmm0_sdi3_sleep>; 296 status = "disabled"; 297 }; 298 299 grf: syscon@ff100000 { 300 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; 301 reg = <0x0 0xff100000 0x0 0x1000>; 302 #address-cells = <1>; 303 #size-cells = <1>; 304 305 io_domains: io-domains { 306 compatible = "rockchip,rk3328-io-voltage-domain"; 307 status = "disabled"; 308 }; 309 310 grf_gpio: grf-gpio { 311 compatible = "rockchip,rk3328-grf-gpio"; 312 gpio-controller; 313 #gpio-cells = <2>; 314 }; 315 316 power: power-controller { 317 compatible = "rockchip,rk3328-power-controller"; 318 #power-domain-cells = <1>; 319 #address-cells = <1>; 320 #size-cells = <0>; 321 322 pd_hevc@RK3328_PD_HEVC { 323 reg = <RK3328_PD_HEVC>; 324 }; 325 pd_video@RK3328_PD_VIDEO { 326 reg = <RK3328_PD_VIDEO>; 327 }; 328 pd_vpu@RK3328_PD_VPU { 329 reg = <RK3328_PD_VPU>; 330 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 331 }; 332 }; 333 334 reboot-mode { 335 compatible = "syscon-reboot-mode"; 336 offset = <0x5c8>; 337 mode-normal = <BOOT_NORMAL>; 338 mode-recovery = <BOOT_RECOVERY>; 339 mode-bootloader = <BOOT_FASTBOOT>; 340 mode-loader = <BOOT_BL_DOWNLOAD>; 341 }; 342 }; 343 344 uart0: serial@ff110000 { 345 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 346 reg = <0x0 0xff110000 0x0 0x100>; 347 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 349 clock-names = "baudclk", "apb_pclk"; 350 dmas = <&dmac 2>, <&dmac 3>; 351 dma-names = "tx", "rx"; 352 pinctrl-names = "default"; 353 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 354 reg-io-width = <4>; 355 reg-shift = <2>; 356 status = "disabled"; 357 }; 358 359 uart1: serial@ff120000 { 360 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 361 reg = <0x0 0xff120000 0x0 0x100>; 362 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 363 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 364 clock-names = "baudclk", "apb_pclk"; 365 dmas = <&dmac 4>, <&dmac 5>; 366 dma-names = "tx", "rx"; 367 pinctrl-names = "default"; 368 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 369 reg-io-width = <4>; 370 reg-shift = <2>; 371 status = "disabled"; 372 }; 373 374 uart2: serial@ff130000 { 375 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 376 reg = <0x0 0xff130000 0x0 0x100>; 377 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 378 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 379 clock-names = "baudclk", "apb_pclk"; 380 dmas = <&dmac 6>, <&dmac 7>; 381 dma-names = "tx", "rx"; 382 pinctrl-names = "default"; 383 pinctrl-0 = <&uart2m1_xfer>; 384 reg-io-width = <4>; 385 reg-shift = <2>; 386 status = "disabled"; 387 }; 388 389 i2c0: i2c@ff150000 { 390 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 391 reg = <0x0 0xff150000 0x0 0x1000>; 392 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 393 #address-cells = <1>; 394 #size-cells = <0>; 395 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 396 clock-names = "i2c", "pclk"; 397 pinctrl-names = "default"; 398 pinctrl-0 = <&i2c0_xfer>; 399 status = "disabled"; 400 }; 401 402 i2c1: i2c@ff160000 { 403 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 404 reg = <0x0 0xff160000 0x0 0x1000>; 405 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 406 #address-cells = <1>; 407 #size-cells = <0>; 408 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 409 clock-names = "i2c", "pclk"; 410 pinctrl-names = "default"; 411 pinctrl-0 = <&i2c1_xfer>; 412 status = "disabled"; 413 }; 414 415 i2c2: i2c@ff170000 { 416 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 417 reg = <0x0 0xff170000 0x0 0x1000>; 418 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 419 #address-cells = <1>; 420 #size-cells = <0>; 421 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 422 clock-names = "i2c", "pclk"; 423 pinctrl-names = "default"; 424 pinctrl-0 = <&i2c2_xfer>; 425 status = "disabled"; 426 }; 427 428 i2c3: i2c@ff180000 { 429 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 430 reg = <0x0 0xff180000 0x0 0x1000>; 431 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 432 #address-cells = <1>; 433 #size-cells = <0>; 434 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 435 clock-names = "i2c", "pclk"; 436 pinctrl-names = "default"; 437 pinctrl-0 = <&i2c3_xfer>; 438 status = "disabled"; 439 }; 440 441 spi0: spi@ff190000 { 442 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; 443 reg = <0x0 0xff190000 0x0 0x1000>; 444 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 448 clock-names = "spiclk", "apb_pclk"; 449 dmas = <&dmac 8>, <&dmac 9>; 450 dma-names = "tx", "rx"; 451 pinctrl-names = "default"; 452 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; 453 status = "disabled"; 454 }; 455 456 wdt: watchdog@ff1a0000 { 457 compatible = "snps,dw-wdt"; 458 reg = <0x0 0xff1a0000 0x0 0x100>; 459 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&cru PCLK_WDT>; 461 }; 462 463 pwm0: pwm@ff1b0000 { 464 compatible = "rockchip,rk3328-pwm"; 465 reg = <0x0 0xff1b0000 0x0 0x10>; 466 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 467 clock-names = "pwm", "pclk"; 468 pinctrl-names = "default"; 469 pinctrl-0 = <&pwm0_pin>; 470 #pwm-cells = <3>; 471 status = "disabled"; 472 }; 473 474 pwm1: pwm@ff1b0010 { 475 compatible = "rockchip,rk3328-pwm"; 476 reg = <0x0 0xff1b0010 0x0 0x10>; 477 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 478 clock-names = "pwm", "pclk"; 479 pinctrl-names = "default"; 480 pinctrl-0 = <&pwm1_pin>; 481 #pwm-cells = <3>; 482 status = "disabled"; 483 }; 484 485 pwm2: pwm@ff1b0020 { 486 compatible = "rockchip,rk3328-pwm"; 487 reg = <0x0 0xff1b0020 0x0 0x10>; 488 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 489 clock-names = "pwm", "pclk"; 490 pinctrl-names = "default"; 491 pinctrl-0 = <&pwm2_pin>; 492 #pwm-cells = <3>; 493 status = "disabled"; 494 }; 495 496 pwm3: pwm@ff1b0030 { 497 compatible = "rockchip,rk3328-pwm"; 498 reg = <0x0 0xff1b0030 0x0 0x10>; 499 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 500 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 501 clock-names = "pwm", "pclk"; 502 pinctrl-names = "default"; 503 pinctrl-0 = <&pwmir_pin>; 504 #pwm-cells = <3>; 505 status = "disabled"; 506 }; 507 508 thermal-zones { 509 soc_thermal: soc-thermal { 510 polling-delay-passive = <20>; 511 polling-delay = <1000>; 512 sustainable-power = <1000>; 513 514 thermal-sensors = <&tsadc 0>; 515 516 trips { 517 threshold: trip-point0 { 518 temperature = <70000>; 519 hysteresis = <2000>; 520 type = "passive"; 521 }; 522 target: trip-point1 { 523 temperature = <85000>; 524 hysteresis = <2000>; 525 type = "passive"; 526 }; 527 soc_crit: soc-crit { 528 temperature = <95000>; 529 hysteresis = <2000>; 530 type = "critical"; 531 }; 532 }; 533 534 cooling-maps { 535 map0 { 536 trip = <&target>; 537 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 538 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 539 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 540 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 541 contribution = <4096>; 542 }; 543 }; 544 }; 545 546 }; 547 548 tsadc: tsadc@ff250000 { 549 compatible = "rockchip,rk3328-tsadc"; 550 reg = <0x0 0xff250000 0x0 0x100>; 551 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 552 assigned-clocks = <&cru SCLK_TSADC>; 553 assigned-clock-rates = <50000>; 554 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 555 clock-names = "tsadc", "apb_pclk"; 556 pinctrl-names = "init", "default", "sleep"; 557 pinctrl-0 = <&otp_gpio>; 558 pinctrl-1 = <&otp_out>; 559 pinctrl-2 = <&otp_gpio>; 560 resets = <&cru SRST_TSADC>; 561 reset-names = "tsadc-apb"; 562 rockchip,grf = <&grf>; 563 rockchip,hw-tshut-temp = <100000>; 564 #thermal-sensor-cells = <1>; 565 status = "disabled"; 566 }; 567 568 efuse: efuse@ff260000 { 569 compatible = "rockchip,rk3328-efuse"; 570 reg = <0x0 0xff260000 0x0 0x50>; 571 #address-cells = <1>; 572 #size-cells = <1>; 573 clocks = <&cru SCLK_EFUSE>; 574 clock-names = "pclk_efuse"; 575 rockchip,efuse-size = <0x20>; 576 577 /* Data cells */ 578 efuse_id: id@7 { 579 reg = <0x07 0x10>; 580 }; 581 cpu_leakage: cpu-leakage@17 { 582 reg = <0x17 0x1>; 583 }; 584 logic_leakage: logic-leakage@19 { 585 reg = <0x19 0x1>; 586 }; 587 efuse_cpu_version: cpu-version@1a { 588 reg = <0x1a 0x1>; 589 bits = <3 3>; 590 }; 591 }; 592 593 saradc: adc@ff280000 { 594 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc"; 595 reg = <0x0 0xff280000 0x0 0x100>; 596 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 597 #io-channel-cells = <1>; 598 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 599 clock-names = "saradc", "apb_pclk"; 600 resets = <&cru SRST_SARADC_P>; 601 reset-names = "saradc-apb"; 602 status = "disabled"; 603 }; 604 605 gpu: gpu@ff300000 { 606 compatible = "rockchip,rk3328-mali", "arm,mali-450"; 607 reg = <0x0 0xff300000 0x0 0x40000>; 608 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 615 interrupt-names = "gp", 616 "gpmmu", 617 "pp", 618 "pp0", 619 "ppmmu0", 620 "pp1", 621 "ppmmu1"; 622 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 623 clock-names = "bus", "core"; 624 resets = <&cru SRST_GPU_A>; 625 }; 626 627 h265e_mmu: iommu@ff330200 { 628 compatible = "rockchip,iommu"; 629 reg = <0x0 0xff330200 0 0x100>; 630 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 631 interrupt-names = "h265e_mmu"; 632 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>; 633 clock-names = "aclk", "iface"; 634 #iommu-cells = <0>; 635 status = "disabled"; 636 }; 637 638 vepu_mmu: iommu@ff340800 { 639 compatible = "rockchip,iommu"; 640 reg = <0x0 0xff340800 0x0 0x40>; 641 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 642 interrupt-names = "vepu_mmu"; 643 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 644 clock-names = "aclk", "iface"; 645 #iommu-cells = <0>; 646 status = "disabled"; 647 }; 648 649 vpu: video-codec@ff350000 { 650 compatible = "rockchip,rk3328-vpu"; 651 reg = <0x0 0xff350000 0x0 0x800>; 652 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 653 interrupt-names = "vdpu"; 654 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 655 clock-names = "aclk", "hclk"; 656 iommus = <&vpu_mmu>; 657 power-domains = <&power RK3328_PD_VPU>; 658 }; 659 660 vpu_mmu: iommu@ff350800 { 661 compatible = "rockchip,iommu"; 662 reg = <0x0 0xff350800 0x0 0x40>; 663 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 664 interrupt-names = "vpu_mmu"; 665 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 666 clock-names = "aclk", "iface"; 667 #iommu-cells = <0>; 668 power-domains = <&power RK3328_PD_VPU>; 669 }; 670 671 rkvdec_mmu: iommu@ff360480 { 672 compatible = "rockchip,iommu"; 673 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; 674 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 675 interrupt-names = "rkvdec_mmu"; 676 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; 677 clock-names = "aclk", "iface"; 678 #iommu-cells = <0>; 679 status = "disabled"; 680 }; 681 682 vop: vop@ff370000 { 683 compatible = "rockchip,rk3328-vop"; 684 reg = <0x0 0xff370000 0x0 0x3efc>; 685 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 686 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>; 687 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 688 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; 689 reset-names = "axi", "ahb", "dclk"; 690 iommus = <&vop_mmu>; 691 status = "disabled"; 692 693 vop_out: port { 694 #address-cells = <1>; 695 #size-cells = <0>; 696 697 vop_out_hdmi: endpoint@0 { 698 reg = <0>; 699 remote-endpoint = <&hdmi_in_vop>; 700 }; 701 }; 702 }; 703 704 vop_mmu: iommu@ff373f00 { 705 compatible = "rockchip,iommu"; 706 reg = <0x0 0xff373f00 0x0 0x100>; 707 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 708 interrupt-names = "vop_mmu"; 709 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 710 clock-names = "aclk", "iface"; 711 #iommu-cells = <0>; 712 status = "disabled"; 713 }; 714 715 hdmi: hdmi@ff3c0000 { 716 compatible = "rockchip,rk3328-dw-hdmi"; 717 reg = <0x0 0xff3c0000 0x0 0x20000>; 718 reg-io-width = <4>; 719 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&cru PCLK_HDMI>, 722 <&cru SCLK_HDMI_SFC>, 723 <&cru SCLK_RTC32K>; 724 clock-names = "iahb", 725 "isfr", 726 "cec"; 727 phys = <&hdmiphy>; 728 phy-names = "hdmi"; 729 pinctrl-names = "default"; 730 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>; 731 rockchip,grf = <&grf>; 732 #sound-dai-cells = <0>; 733 status = "disabled"; 734 735 ports { 736 hdmi_in: port { 737 hdmi_in_vop: endpoint { 738 remote-endpoint = <&vop_out_hdmi>; 739 }; 740 }; 741 }; 742 }; 743 744 codec: codec@ff410000 { 745 compatible = "rockchip,rk3328-codec"; 746 reg = <0x0 0xff410000 0x0 0x1000>; 747 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>; 748 clock-names = "pclk", "mclk"; 749 rockchip,grf = <&grf>; 750 #sound-dai-cells = <0>; 751 status = "disabled"; 752 }; 753 754 hdmiphy: phy@ff430000 { 755 compatible = "rockchip,rk3328-hdmi-phy"; 756 reg = <0x0 0xff430000 0x0 0x10000>; 757 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 758 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>; 759 clock-names = "sysclk", "refoclk", "refpclk"; 760 clock-output-names = "hdmi_phy"; 761 #clock-cells = <0>; 762 nvmem-cells = <&efuse_cpu_version>; 763 nvmem-cell-names = "cpu-version"; 764 #phy-cells = <0>; 765 status = "disabled"; 766 }; 767 768 cru: clock-controller@ff440000 { 769 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; 770 reg = <0x0 0xff440000 0x0 0x1000>; 771 rockchip,grf = <&grf>; 772 #clock-cells = <1>; 773 #reset-cells = <1>; 774 assigned-clocks = 775 /* 776 * CPLL should run at 1200, but that is to high for 777 * the initial dividers of most of its children. 778 * We need set cpll child clk div first, 779 * and then set the cpll frequency. 780 */ 781 <&cru DCLK_LCDC>, <&cru SCLK_PDM>, 782 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, 783 <&cru SCLK_UART1>, <&cru SCLK_UART2>, 784 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 785 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, 786 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 787 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 788 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 789 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 790 <&cru SCLK_SDIO>, <&cru SCLK_TSP>, 791 <&cru SCLK_WIFI>, <&cru ARMCLK>, 792 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 793 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, 794 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 795 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 796 <&cru SCLK_RTC32K>; 797 assigned-clock-parents = 798 <&cru HDMIPHY>, <&cru PLL_APLL>, 799 <&cru PLL_GPLL>, <&xin24m>, 800 <&xin24m>, <&xin24m>; 801 assigned-clock-rates = 802 <0>, <61440000>, 803 <0>, <24000000>, 804 <24000000>, <24000000>, 805 <15000000>, <15000000>, 806 <100000000>, <100000000>, 807 <100000000>, <100000000>, 808 <50000000>, <100000000>, 809 <100000000>, <100000000>, 810 <50000000>, <50000000>, 811 <50000000>, <50000000>, 812 <24000000>, <600000000>, 813 <491520000>, <1200000000>, 814 <150000000>, <75000000>, 815 <75000000>, <150000000>, 816 <75000000>, <75000000>, 817 <32768>; 818 }; 819 820 usb2phy_grf: syscon@ff450000 { 821 compatible = "rockchip,rk3328-usb2phy-grf", "syscon", 822 "simple-mfd"; 823 reg = <0x0 0xff450000 0x0 0x10000>; 824 #address-cells = <1>; 825 #size-cells = <1>; 826 827 u2phy: usb2-phy@100 { 828 compatible = "rockchip,rk3328-usb2phy"; 829 reg = <0x100 0x10>; 830 clocks = <&xin24m>; 831 clock-names = "phyclk"; 832 clock-output-names = "usb480m_phy"; 833 #clock-cells = <0>; 834 assigned-clocks = <&cru USB480M>; 835 assigned-clock-parents = <&u2phy>; 836 status = "disabled"; 837 838 u2phy_otg: otg-port { 839 #phy-cells = <0>; 840 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 841 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 842 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 843 interrupt-names = "otg-bvalid", "otg-id", 844 "linestate"; 845 status = "disabled"; 846 }; 847 848 u2phy_host: host-port { 849 #phy-cells = <0>; 850 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 851 interrupt-names = "linestate"; 852 status = "disabled"; 853 }; 854 }; 855 }; 856 857 sdmmc: mmc@ff500000 { 858 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 859 reg = <0x0 0xff500000 0x0 0x4000>; 860 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 861 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 862 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 863 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 864 fifo-depth = <0x100>; 865 max-frequency = <150000000>; 866 status = "disabled"; 867 }; 868 869 sdio: mmc@ff510000 { 870 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 871 reg = <0x0 0xff510000 0x0 0x4000>; 872 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 873 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 874 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 875 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 876 fifo-depth = <0x100>; 877 max-frequency = <150000000>; 878 status = "disabled"; 879 }; 880 881 emmc: mmc@ff520000 { 882 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 883 reg = <0x0 0xff520000 0x0 0x4000>; 884 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 885 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 886 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 887 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 888 fifo-depth = <0x100>; 889 max-frequency = <150000000>; 890 status = "disabled"; 891 }; 892 893 gmac2io: ethernet@ff540000 { 894 compatible = "rockchip,rk3328-gmac"; 895 reg = <0x0 0xff540000 0x0 0x10000>; 896 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 897 interrupt-names = "macirq"; 898 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, 899 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>, 900 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>, 901 <&cru PCLK_MAC2IO>; 902 clock-names = "stmmaceth", "mac_clk_rx", 903 "mac_clk_tx", "clk_mac_ref", 904 "clk_mac_refout", "aclk_mac", 905 "pclk_mac"; 906 resets = <&cru SRST_GMAC2IO_A>; 907 reset-names = "stmmaceth"; 908 rockchip,grf = <&grf>; 909 status = "disabled"; 910 }; 911 912 gmac2phy: ethernet@ff550000 { 913 compatible = "rockchip,rk3328-gmac"; 914 reg = <0x0 0xff550000 0x0 0x10000>; 915 rockchip,grf = <&grf>; 916 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 917 interrupt-names = "macirq"; 918 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>, 919 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>, 920 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>, 921 <&cru SCLK_MAC2PHY_OUT>; 922 clock-names = "stmmaceth", "mac_clk_rx", 923 "mac_clk_tx", "clk_mac_ref", 924 "aclk_mac", "pclk_mac", 925 "clk_macphy"; 926 resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>; 927 reset-names = "stmmaceth", "mac-phy"; 928 phy-mode = "rmii"; 929 phy-handle = <&phy>; 930 status = "disabled"; 931 932 mdio { 933 compatible = "snps,dwmac-mdio"; 934 #address-cells = <1>; 935 #size-cells = <0>; 936 937 phy: phy@0 { 938 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; 939 reg = <0>; 940 clocks = <&cru SCLK_MAC2PHY_OUT>; 941 resets = <&cru SRST_MACPHY>; 942 pinctrl-names = "default"; 943 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>; 944 phy-is-integrated; 945 }; 946 }; 947 }; 948 949 usb20_otg: usb@ff580000 { 950 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", 951 "snps,dwc2"; 952 reg = <0x0 0xff580000 0x0 0x40000>; 953 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 954 clocks = <&cru HCLK_OTG>; 955 clock-names = "otg"; 956 dr_mode = "otg"; 957 g-np-tx-fifo-size = <16>; 958 g-rx-fifo-size = <280>; 959 g-tx-fifo-size = <256 128 128 64 32 16>; 960 g-use-dma; 961 phys = <&u2phy_otg>; 962 phy-names = "usb2-phy"; 963 status = "disabled"; 964 }; 965 966 usb_host0_ehci: usb@ff5c0000 { 967 compatible = "generic-ehci"; 968 reg = <0x0 0xff5c0000 0x0 0x10000>; 969 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 970 clocks = <&cru HCLK_HOST0>, <&u2phy>; 971 clock-names = "usbhost", "utmi"; 972 phys = <&u2phy_host>; 973 phy-names = "usb"; 974 status = "disabled"; 975 }; 976 977 usb_host0_ohci: usb@ff5d0000 { 978 compatible = "generic-ohci"; 979 reg = <0x0 0xff5d0000 0x0 0x10000>; 980 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 981 clocks = <&cru HCLK_HOST0>, <&u2phy>; 982 clock-names = "usbhost", "utmi"; 983 phys = <&u2phy_host>; 984 phy-names = "usb"; 985 status = "disabled"; 986 }; 987 988 gic: interrupt-controller@ff811000 { 989 compatible = "arm,gic-400"; 990 #interrupt-cells = <3>; 991 #address-cells = <0>; 992 interrupt-controller; 993 reg = <0x0 0xff811000 0 0x1000>, 994 <0x0 0xff812000 0 0x2000>, 995 <0x0 0xff814000 0 0x2000>, 996 <0x0 0xff816000 0 0x2000>; 997 interrupts = <GIC_PPI 9 998 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 999 }; 1000 1001 pinctrl: pinctrl { 1002 compatible = "rockchip,rk3328-pinctrl"; 1003 rockchip,grf = <&grf>; 1004 #address-cells = <2>; 1005 #size-cells = <2>; 1006 ranges; 1007 1008 gpio0: gpio0@ff210000 { 1009 compatible = "rockchip,gpio-bank"; 1010 reg = <0x0 0xff210000 0x0 0x100>; 1011 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1012 clocks = <&cru PCLK_GPIO0>; 1013 1014 gpio-controller; 1015 #gpio-cells = <2>; 1016 1017 interrupt-controller; 1018 #interrupt-cells = <2>; 1019 }; 1020 1021 gpio1: gpio1@ff220000 { 1022 compatible = "rockchip,gpio-bank"; 1023 reg = <0x0 0xff220000 0x0 0x100>; 1024 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1025 clocks = <&cru PCLK_GPIO1>; 1026 1027 gpio-controller; 1028 #gpio-cells = <2>; 1029 1030 interrupt-controller; 1031 #interrupt-cells = <2>; 1032 }; 1033 1034 gpio2: gpio2@ff230000 { 1035 compatible = "rockchip,gpio-bank"; 1036 reg = <0x0 0xff230000 0x0 0x100>; 1037 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1038 clocks = <&cru PCLK_GPIO2>; 1039 1040 gpio-controller; 1041 #gpio-cells = <2>; 1042 1043 interrupt-controller; 1044 #interrupt-cells = <2>; 1045 }; 1046 1047 gpio3: gpio3@ff240000 { 1048 compatible = "rockchip,gpio-bank"; 1049 reg = <0x0 0xff240000 0x0 0x100>; 1050 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1051 clocks = <&cru PCLK_GPIO3>; 1052 1053 gpio-controller; 1054 #gpio-cells = <2>; 1055 1056 interrupt-controller; 1057 #interrupt-cells = <2>; 1058 }; 1059 1060 pcfg_pull_up: pcfg-pull-up { 1061 bias-pull-up; 1062 }; 1063 1064 pcfg_pull_down: pcfg-pull-down { 1065 bias-pull-down; 1066 }; 1067 1068 pcfg_pull_none: pcfg-pull-none { 1069 bias-disable; 1070 }; 1071 1072 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1073 bias-disable; 1074 drive-strength = <2>; 1075 }; 1076 1077 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1078 bias-pull-up; 1079 drive-strength = <2>; 1080 }; 1081 1082 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1083 bias-pull-up; 1084 drive-strength = <4>; 1085 }; 1086 1087 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1088 bias-disable; 1089 drive-strength = <4>; 1090 }; 1091 1092 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1093 bias-pull-down; 1094 drive-strength = <4>; 1095 }; 1096 1097 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1098 bias-disable; 1099 drive-strength = <8>; 1100 }; 1101 1102 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1103 bias-pull-up; 1104 drive-strength = <8>; 1105 }; 1106 1107 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1108 bias-disable; 1109 drive-strength = <12>; 1110 }; 1111 1112 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1113 bias-pull-up; 1114 drive-strength = <12>; 1115 }; 1116 1117 pcfg_output_high: pcfg-output-high { 1118 output-high; 1119 }; 1120 1121 pcfg_output_low: pcfg-output-low { 1122 output-low; 1123 }; 1124 1125 pcfg_input_high: pcfg-input-high { 1126 bias-pull-up; 1127 input-enable; 1128 }; 1129 1130 pcfg_input: pcfg-input { 1131 input-enable; 1132 }; 1133 1134 i2c0 { 1135 i2c0_xfer: i2c0-xfer { 1136 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>, 1137 <2 RK_PD1 1 &pcfg_pull_none>; 1138 }; 1139 }; 1140 1141 i2c1 { 1142 i2c1_xfer: i2c1-xfer { 1143 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>, 1144 <2 RK_PA5 2 &pcfg_pull_none>; 1145 }; 1146 }; 1147 1148 i2c2 { 1149 i2c2_xfer: i2c2-xfer { 1150 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>, 1151 <2 RK_PB6 1 &pcfg_pull_none>; 1152 }; 1153 }; 1154 1155 i2c3 { 1156 i2c3_xfer: i2c3-xfer { 1157 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>, 1158 <0 RK_PA6 2 &pcfg_pull_none>; 1159 }; 1160 i2c3_gpio: i2c3-gpio { 1161 rockchip,pins = 1162 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, 1163 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1164 }; 1165 }; 1166 1167 hdmi_i2c { 1168 hdmii2c_xfer: hdmii2c-xfer { 1169 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>, 1170 <0 RK_PA6 1 &pcfg_pull_none>; 1171 }; 1172 }; 1173 1174 pdm-0 { 1175 pdmm0_clk: pdmm0-clk { 1176 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>; 1177 }; 1178 1179 pdmm0_fsync: pdmm0-fsync { 1180 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>; 1181 }; 1182 1183 pdmm0_sdi0: pdmm0-sdi0 { 1184 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>; 1185 }; 1186 1187 pdmm0_sdi1: pdmm0-sdi1 { 1188 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>; 1189 }; 1190 1191 pdmm0_sdi2: pdmm0-sdi2 { 1192 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>; 1193 }; 1194 1195 pdmm0_sdi3: pdmm0-sdi3 { 1196 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>; 1197 }; 1198 1199 pdmm0_clk_sleep: pdmm0-clk-sleep { 1200 rockchip,pins = 1201 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>; 1202 }; 1203 1204 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep { 1205 rockchip,pins = 1206 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>; 1207 }; 1208 1209 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep { 1210 rockchip,pins = 1211 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>; 1212 }; 1213 1214 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep { 1215 rockchip,pins = 1216 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1217 }; 1218 1219 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep { 1220 rockchip,pins = 1221 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1222 }; 1223 1224 pdmm0_fsync_sleep: pdmm0-fsync-sleep { 1225 rockchip,pins = 1226 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1227 }; 1228 }; 1229 1230 tsadc { 1231 otp_gpio: otp-gpio { 1232 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1233 }; 1234 1235 otp_out: otp-out { 1236 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>; 1237 }; 1238 }; 1239 1240 uart0 { 1241 uart0_xfer: uart0-xfer { 1242 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>, 1243 <1 RK_PB0 1 &pcfg_pull_none>; 1244 }; 1245 1246 uart0_cts: uart0-cts { 1247 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; 1248 }; 1249 1250 uart0_rts: uart0-rts { 1251 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>; 1252 }; 1253 1254 uart0_rts_gpio: uart0-rts-gpio { 1255 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 1256 }; 1257 }; 1258 1259 uart1 { 1260 uart1_xfer: uart1-xfer { 1261 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>, 1262 <3 RK_PA6 4 &pcfg_pull_none>; 1263 }; 1264 1265 uart1_cts: uart1-cts { 1266 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>; 1267 }; 1268 1269 uart1_rts: uart1-rts { 1270 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>; 1271 }; 1272 1273 uart1_rts_gpio: uart1-rts-gpio { 1274 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 1275 }; 1276 }; 1277 1278 uart2-0 { 1279 uart2m0_xfer: uart2m0-xfer { 1280 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>, 1281 <1 RK_PA1 2 &pcfg_pull_none>; 1282 }; 1283 }; 1284 1285 uart2-1 { 1286 uart2m1_xfer: uart2m1-xfer { 1287 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>, 1288 <2 RK_PA1 1 &pcfg_pull_none>; 1289 }; 1290 }; 1291 1292 spi0-0 { 1293 spi0m0_clk: spi0m0-clk { 1294 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>; 1295 }; 1296 1297 spi0m0_cs0: spi0m0-cs0 { 1298 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; 1299 }; 1300 1301 spi0m0_tx: spi0m0-tx { 1302 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>; 1303 }; 1304 1305 spi0m0_rx: spi0m0-rx { 1306 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; 1307 }; 1308 1309 spi0m0_cs1: spi0m0-cs1 { 1310 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>; 1311 }; 1312 }; 1313 1314 spi0-1 { 1315 spi0m1_clk: spi0m1-clk { 1316 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>; 1317 }; 1318 1319 spi0m1_cs0: spi0m1-cs0 { 1320 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>; 1321 }; 1322 1323 spi0m1_tx: spi0m1-tx { 1324 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>; 1325 }; 1326 1327 spi0m1_rx: spi0m1-rx { 1328 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>; 1329 }; 1330 1331 spi0m1_cs1: spi0m1-cs1 { 1332 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>; 1333 }; 1334 }; 1335 1336 spi0-2 { 1337 spi0m2_clk: spi0m2-clk { 1338 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>; 1339 }; 1340 1341 spi0m2_cs0: spi0m2-cs0 { 1342 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>; 1343 }; 1344 1345 spi0m2_tx: spi0m2-tx { 1346 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>; 1347 }; 1348 1349 spi0m2_rx: spi0m2-rx { 1350 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>; 1351 }; 1352 }; 1353 1354 i2s1 { 1355 i2s1_mclk: i2s1-mclk { 1356 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>; 1357 }; 1358 1359 i2s1_sclk: i2s1-sclk { 1360 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>; 1361 }; 1362 1363 i2s1_lrckrx: i2s1-lrckrx { 1364 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>; 1365 }; 1366 1367 i2s1_lrcktx: i2s1-lrcktx { 1368 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>; 1369 }; 1370 1371 i2s1_sdi: i2s1-sdi { 1372 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>; 1373 }; 1374 1375 i2s1_sdo: i2s1-sdo { 1376 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; 1377 }; 1378 1379 i2s1_sdio1: i2s1-sdio1 { 1380 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>; 1381 }; 1382 1383 i2s1_sdio2: i2s1-sdio2 { 1384 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>; 1385 }; 1386 1387 i2s1_sdio3: i2s1-sdio3 { 1388 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>; 1389 }; 1390 1391 i2s1_sleep: i2s1-sleep { 1392 rockchip,pins = 1393 <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>, 1394 <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>, 1395 <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>, 1396 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>, 1397 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>, 1398 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>, 1399 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1400 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1401 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1402 }; 1403 }; 1404 1405 i2s2-0 { 1406 i2s2m0_mclk: i2s2m0-mclk { 1407 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1408 }; 1409 1410 i2s2m0_sclk: i2s2m0-sclk { 1411 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>; 1412 }; 1413 1414 i2s2m0_lrckrx: i2s2m0-lrckrx { 1415 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>; 1416 }; 1417 1418 i2s2m0_lrcktx: i2s2m0-lrcktx { 1419 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>; 1420 }; 1421 1422 i2s2m0_sdi: i2s2m0-sdi { 1423 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>; 1424 }; 1425 1426 i2s2m0_sdo: i2s2m0-sdo { 1427 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>; 1428 }; 1429 1430 i2s2m0_sleep: i2s2m0-sleep { 1431 rockchip,pins = 1432 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1433 <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1434 <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>, 1435 <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>, 1436 <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>, 1437 <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1438 }; 1439 }; 1440 1441 i2s2-1 { 1442 i2s2m1_mclk: i2s2m1-mclk { 1443 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1444 }; 1445 1446 i2s2m1_sclk: i2s2m1-sclk { 1447 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>; 1448 }; 1449 1450 i2s2m1_lrckrx: i2sm1-lrckrx { 1451 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>; 1452 }; 1453 1454 i2s2m1_lrcktx: i2s2m1-lrcktx { 1455 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>; 1456 }; 1457 1458 i2s2m1_sdi: i2s2m1-sdi { 1459 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>; 1460 }; 1461 1462 i2s2m1_sdo: i2s2m1-sdo { 1463 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>; 1464 }; 1465 1466 i2s2m1_sleep: i2s2m1-sleep { 1467 rockchip,pins = 1468 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1469 <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>, 1470 <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>, 1471 <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>, 1472 <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>; 1473 }; 1474 }; 1475 1476 spdif-0 { 1477 spdifm0_tx: spdifm0-tx { 1478 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 1479 }; 1480 }; 1481 1482 spdif-1 { 1483 spdifm1_tx: spdifm1-tx { 1484 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>; 1485 }; 1486 }; 1487 1488 spdif-2 { 1489 spdifm2_tx: spdifm2-tx { 1490 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>; 1491 }; 1492 }; 1493 1494 sdmmc0-0 { 1495 sdmmc0m0_pwren: sdmmc0m0-pwren { 1496 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>; 1497 }; 1498 1499 sdmmc0m0_gpio: sdmmc0m0-gpio { 1500 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1501 }; 1502 }; 1503 1504 sdmmc0-1 { 1505 sdmmc0m1_pwren: sdmmc0m1-pwren { 1506 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>; 1507 }; 1508 1509 sdmmc0m1_gpio: sdmmc0m1-gpio { 1510 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1511 }; 1512 }; 1513 1514 sdmmc0 { 1515 sdmmc0_clk: sdmmc0-clk { 1516 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>; 1517 }; 1518 1519 sdmmc0_cmd: sdmmc0-cmd { 1520 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>; 1521 }; 1522 1523 sdmmc0_dectn: sdmmc0-dectn { 1524 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>; 1525 }; 1526 1527 sdmmc0_wrprt: sdmmc0-wrprt { 1528 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>; 1529 }; 1530 1531 sdmmc0_bus1: sdmmc0-bus1 { 1532 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>; 1533 }; 1534 1535 sdmmc0_bus4: sdmmc0-bus4 { 1536 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>, 1537 <1 RK_PA1 1 &pcfg_pull_up_8ma>, 1538 <1 RK_PA2 1 &pcfg_pull_up_8ma>, 1539 <1 RK_PA3 1 &pcfg_pull_up_8ma>; 1540 }; 1541 1542 sdmmc0_gpio: sdmmc0-gpio { 1543 rockchip,pins = 1544 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1545 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1546 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1547 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1548 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1549 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1550 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1551 <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1552 }; 1553 }; 1554 1555 sdmmc0ext { 1556 sdmmc0ext_clk: sdmmc0ext-clk { 1557 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>; 1558 }; 1559 1560 sdmmc0ext_cmd: sdmmc0ext-cmd { 1561 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>; 1562 }; 1563 1564 sdmmc0ext_wrprt: sdmmc0ext-wrprt { 1565 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>; 1566 }; 1567 1568 sdmmc0ext_dectn: sdmmc0ext-dectn { 1569 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>; 1570 }; 1571 1572 sdmmc0ext_bus1: sdmmc0ext-bus1 { 1573 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>; 1574 }; 1575 1576 sdmmc0ext_bus4: sdmmc0ext-bus4 { 1577 rockchip,pins = 1578 <3 RK_PA4 3 &pcfg_pull_up_4ma>, 1579 <3 RK_PA5 3 &pcfg_pull_up_4ma>, 1580 <3 RK_PA6 3 &pcfg_pull_up_4ma>, 1581 <3 RK_PA7 3 &pcfg_pull_up_4ma>; 1582 }; 1583 1584 sdmmc0ext_gpio: sdmmc0ext-gpio { 1585 rockchip,pins = 1586 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1587 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1588 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1589 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1590 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1591 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1592 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1593 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1594 }; 1595 }; 1596 1597 sdmmc1 { 1598 sdmmc1_clk: sdmmc1-clk { 1599 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>; 1600 }; 1601 1602 sdmmc1_cmd: sdmmc1-cmd { 1603 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>; 1604 }; 1605 1606 sdmmc1_pwren: sdmmc1-pwren { 1607 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>; 1608 }; 1609 1610 sdmmc1_wrprt: sdmmc1-wrprt { 1611 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>; 1612 }; 1613 1614 sdmmc1_dectn: sdmmc1-dectn { 1615 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>; 1616 }; 1617 1618 sdmmc1_bus1: sdmmc1-bus1 { 1619 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>; 1620 }; 1621 1622 sdmmc1_bus4: sdmmc1-bus4 { 1623 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>, 1624 <1 RK_PB7 1 &pcfg_pull_up_8ma>, 1625 <1 RK_PC0 1 &pcfg_pull_up_8ma>, 1626 <1 RK_PC1 1 &pcfg_pull_up_8ma>; 1627 }; 1628 1629 sdmmc1_gpio: sdmmc1-gpio { 1630 rockchip,pins = 1631 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1632 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1633 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1634 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1635 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1636 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1637 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1638 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1639 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1640 }; 1641 }; 1642 1643 emmc { 1644 emmc_clk: emmc-clk { 1645 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>; 1646 }; 1647 1648 emmc_cmd: emmc-cmd { 1649 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>; 1650 }; 1651 1652 emmc_pwren: emmc-pwren { 1653 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>; 1654 }; 1655 1656 emmc_rstnout: emmc-rstnout { 1657 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>; 1658 }; 1659 1660 emmc_bus1: emmc-bus1 { 1661 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>; 1662 }; 1663 1664 emmc_bus4: emmc-bus4 { 1665 rockchip,pins = 1666 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1667 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1668 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1669 <2 RK_PD6 2 &pcfg_pull_up_12ma>; 1670 }; 1671 1672 emmc_bus8: emmc-bus8 { 1673 rockchip,pins = 1674 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1675 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1676 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1677 <2 RK_PD6 2 &pcfg_pull_up_12ma>, 1678 <2 RK_PD7 2 &pcfg_pull_up_12ma>, 1679 <3 RK_PC0 2 &pcfg_pull_up_12ma>, 1680 <3 RK_PC1 2 &pcfg_pull_up_12ma>, 1681 <3 RK_PC2 2 &pcfg_pull_up_12ma>; 1682 }; 1683 }; 1684 1685 pwm0 { 1686 pwm0_pin: pwm0-pin { 1687 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 1688 }; 1689 }; 1690 1691 pwm1 { 1692 pwm1_pin: pwm1-pin { 1693 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>; 1694 }; 1695 }; 1696 1697 pwm2 { 1698 pwm2_pin: pwm2-pin { 1699 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 1700 }; 1701 }; 1702 1703 pwmir { 1704 pwmir_pin: pwmir-pin { 1705 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 1706 }; 1707 }; 1708 1709 gmac-1 { 1710 rgmiim1_pins: rgmiim1-pins { 1711 rockchip,pins = 1712 /* mac_txclk */ 1713 <1 RK_PB4 2 &pcfg_pull_none_8ma>, 1714 /* mac_rxclk */ 1715 <1 RK_PB5 2 &pcfg_pull_none_4ma>, 1716 /* mac_mdio */ 1717 <1 RK_PC3 2 &pcfg_pull_none_4ma>, 1718 /* mac_txen */ 1719 <1 RK_PD1 2 &pcfg_pull_none_8ma>, 1720 /* mac_clk */ 1721 <1 RK_PC5 2 &pcfg_pull_none_4ma>, 1722 /* mac_rxdv */ 1723 <1 RK_PC6 2 &pcfg_pull_none_4ma>, 1724 /* mac_mdc */ 1725 <1 RK_PC7 2 &pcfg_pull_none_4ma>, 1726 /* mac_rxd1 */ 1727 <1 RK_PB2 2 &pcfg_pull_none_4ma>, 1728 /* mac_rxd0 */ 1729 <1 RK_PB3 2 &pcfg_pull_none_4ma>, 1730 /* mac_txd1 */ 1731 <1 RK_PB0 2 &pcfg_pull_none_8ma>, 1732 /* mac_txd0 */ 1733 <1 RK_PB1 2 &pcfg_pull_none_8ma>, 1734 /* mac_rxd3 */ 1735 <1 RK_PB6 2 &pcfg_pull_none_4ma>, 1736 /* mac_rxd2 */ 1737 <1 RK_PB7 2 &pcfg_pull_none_4ma>, 1738 /* mac_txd3 */ 1739 <1 RK_PC0 2 &pcfg_pull_none_8ma>, 1740 /* mac_txd2 */ 1741 <1 RK_PC1 2 &pcfg_pull_none_8ma>, 1742 1743 /* mac_txclk */ 1744 <0 RK_PB0 1 &pcfg_pull_none_8ma>, 1745 /* mac_txen */ 1746 <0 RK_PB4 1 &pcfg_pull_none_8ma>, 1747 /* mac_clk */ 1748 <0 RK_PD0 1 &pcfg_pull_none_4ma>, 1749 /* mac_txd1 */ 1750 <0 RK_PC0 1 &pcfg_pull_none_8ma>, 1751 /* mac_txd0 */ 1752 <0 RK_PC1 1 &pcfg_pull_none_8ma>, 1753 /* mac_txd3 */ 1754 <0 RK_PC7 1 &pcfg_pull_none_8ma>, 1755 /* mac_txd2 */ 1756 <0 RK_PC6 1 &pcfg_pull_none_8ma>; 1757 }; 1758 1759 rmiim1_pins: rmiim1-pins { 1760 rockchip,pins = 1761 /* mac_mdio */ 1762 <1 RK_PC3 2 &pcfg_pull_none_2ma>, 1763 /* mac_txen */ 1764 <1 RK_PD1 2 &pcfg_pull_none_12ma>, 1765 /* mac_clk */ 1766 <1 RK_PC5 2 &pcfg_pull_none_2ma>, 1767 /* mac_rxer */ 1768 <1 RK_PD0 2 &pcfg_pull_none_2ma>, 1769 /* mac_rxdv */ 1770 <1 RK_PC6 2 &pcfg_pull_none_2ma>, 1771 /* mac_mdc */ 1772 <1 RK_PC7 2 &pcfg_pull_none_2ma>, 1773 /* mac_rxd1 */ 1774 <1 RK_PB2 2 &pcfg_pull_none_2ma>, 1775 /* mac_rxd0 */ 1776 <1 RK_PB3 2 &pcfg_pull_none_2ma>, 1777 /* mac_txd1 */ 1778 <1 RK_PB0 2 &pcfg_pull_none_12ma>, 1779 /* mac_txd0 */ 1780 <1 RK_PB1 2 &pcfg_pull_none_12ma>, 1781 1782 /* mac_mdio */ 1783 <0 RK_PB3 1 &pcfg_pull_none>, 1784 /* mac_txen */ 1785 <0 RK_PB4 1 &pcfg_pull_none>, 1786 /* mac_clk */ 1787 <0 RK_PD0 1 &pcfg_pull_none>, 1788 /* mac_mdc */ 1789 <0 RK_PC3 1 &pcfg_pull_none>, 1790 /* mac_txd1 */ 1791 <0 RK_PC0 1 &pcfg_pull_none>, 1792 /* mac_txd0 */ 1793 <0 RK_PC1 1 &pcfg_pull_none>; 1794 }; 1795 }; 1796 1797 gmac2phy { 1798 fephyled_speed100: fephyled-speed100 { 1799 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>; 1800 }; 1801 1802 fephyled_speed10: fephyled-speed10 { 1803 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; 1804 }; 1805 1806 fephyled_duplex: fephyled-duplex { 1807 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; 1808 }; 1809 1810 fephyled_rxm0: fephyled-rxm0 { 1811 rockchip,pins = <0 RK_PD5 1 &pcfg_pull_none>; 1812 }; 1813 1814 fephyled_txm0: fephyled-txm0 { 1815 rockchip,pins = <0 RK_PD5 2 &pcfg_pull_none>; 1816 }; 1817 1818 fephyled_linkm0: fephyled-linkm0 { 1819 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>; 1820 }; 1821 1822 fephyled_rxm1: fephyled-rxm1 { 1823 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>; 1824 }; 1825 1826 fephyled_txm1: fephyled-txm1 { 1827 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>; 1828 }; 1829 1830 fephyled_linkm1: fephyled-linkm1 { 1831 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>; 1832 }; 1833 }; 1834 1835 tsadc_pin { 1836 tsadc_int: tsadc-int { 1837 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>; 1838 }; 1839 tsadc_gpio: tsadc-gpio { 1840 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1841 }; 1842 }; 1843 1844 hdmi_pin { 1845 hdmi_cec: hdmi-cec { 1846 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; 1847 }; 1848 1849 hdmi_hpd: hdmi-hpd { 1850 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>; 1851 }; 1852 }; 1853 1854 cif-0 { 1855 dvp_d2d9_m0:dvp-d2d9-m0 { 1856 rockchip,pins = 1857 /* cif_d0 */ 1858 <3 RK_PA4 2 &pcfg_pull_none>, 1859 /* cif_d1 */ 1860 <3 RK_PA5 2 &pcfg_pull_none>, 1861 /* cif_d2 */ 1862 <3 RK_PA6 2 &pcfg_pull_none>, 1863 /* cif_d3 */ 1864 <3 RK_PA7 2 &pcfg_pull_none>, 1865 /* cif_d4 */ 1866 <3 RK_PB0 2 &pcfg_pull_none>, 1867 /* cif_d5m0 */ 1868 <3 RK_PB1 2 &pcfg_pull_none>, 1869 /* cif_d6m0 */ 1870 <3 RK_PB2 2 &pcfg_pull_none>, 1871 /* cif_d7m0 */ 1872 <3 RK_PB3 2 &pcfg_pull_none>, 1873 /* cif_href */ 1874 <3 RK_PA1 2 &pcfg_pull_none>, 1875 /* cif_vsync */ 1876 <3 RK_PA0 2 &pcfg_pull_none>, 1877 /* cif_clkoutm0 */ 1878 <3 RK_PA3 2 &pcfg_pull_none>, 1879 /* cif_clkin */ 1880 <3 RK_PA2 2 &pcfg_pull_none>; 1881 }; 1882 }; 1883 1884 cif-1 { 1885 dvp_d2d9_m1:dvp-d2d9-m1 { 1886 rockchip,pins = 1887 /* cif_d0 */ 1888 <3 RK_PA4 2 &pcfg_pull_none>, 1889 /* cif_d1 */ 1890 <3 RK_PA5 2 &pcfg_pull_none>, 1891 /* cif_d2 */ 1892 <3 RK_PA6 2 &pcfg_pull_none>, 1893 /* cif_d3 */ 1894 <3 RK_PA7 2 &pcfg_pull_none>, 1895 /* cif_d4 */ 1896 <3 RK_PB0 2 &pcfg_pull_none>, 1897 /* cif_d5m1 */ 1898 <2 RK_PC0 4 &pcfg_pull_none>, 1899 /* cif_d6m1 */ 1900 <2 RK_PC1 4 &pcfg_pull_none>, 1901 /* cif_d7m1 */ 1902 <2 RK_PC2 4 &pcfg_pull_none>, 1903 /* cif_href */ 1904 <3 RK_PA1 2 &pcfg_pull_none>, 1905 /* cif_vsync */ 1906 <3 RK_PA0 2 &pcfg_pull_none>, 1907 /* cif_clkoutm1 */ 1908 <2 RK_PB7 4 &pcfg_pull_none>, 1909 /* cif_clkin */ 1910 <3 RK_PA2 2 &pcfg_pull_none>; 1911 }; 1912 }; 1913 }; 1914}; 1915