xref: /openbmc/linux/drivers/clk/qcom/apss-ipq-pll.c (revision 29c37341)
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2018, The Linux Foundation. All rights reserved.
3 #include <linux/clk-provider.h>
4 #include <linux/module.h>
5 #include <linux/platform_device.h>
6 #include <linux/regmap.h>
7 
8 #include "clk-alpha-pll.h"
9 
10 static const u8 ipq_pll_offsets[] = {
11 	[PLL_OFF_L_VAL] = 0x08,
12 	[PLL_OFF_ALPHA_VAL] = 0x10,
13 	[PLL_OFF_USER_CTL] = 0x18,
14 	[PLL_OFF_CONFIG_CTL] = 0x20,
15 	[PLL_OFF_CONFIG_CTL_U] = 0x24,
16 	[PLL_OFF_STATUS] = 0x28,
17 	[PLL_OFF_TEST_CTL] = 0x30,
18 	[PLL_OFF_TEST_CTL_U] = 0x34,
19 };
20 
21 static struct clk_alpha_pll ipq_pll = {
22 	.offset = 0x0,
23 	.regs = ipq_pll_offsets,
24 	.flags = SUPPORTS_DYNAMIC_UPDATE,
25 	.clkr = {
26 		.enable_reg = 0x0,
27 		.enable_mask = BIT(0),
28 		.hw.init = &(struct clk_init_data){
29 			.name = "a53pll",
30 			.parent_data = &(const struct clk_parent_data) {
31 				.fw_name = "xo",
32 			},
33 			.num_parents = 1,
34 			.ops = &clk_alpha_pll_huayra_ops,
35 		},
36 	},
37 };
38 
39 static const struct alpha_pll_config ipq_pll_config = {
40 	.l = 0x37,
41 	.config_ctl_val = 0x04141200,
42 	.config_ctl_hi_val = 0x0,
43 	.early_output_mask = BIT(3),
44 	.main_output_mask = BIT(0),
45 };
46 
47 static const struct regmap_config ipq_pll_regmap_config = {
48 	.reg_bits		= 32,
49 	.reg_stride		= 4,
50 	.val_bits		= 32,
51 	.max_register		= 0x40,
52 	.fast_io		= true,
53 };
54 
55 static int apss_ipq_pll_probe(struct platform_device *pdev)
56 {
57 	struct device *dev = &pdev->dev;
58 	struct regmap *regmap;
59 	void __iomem *base;
60 	int ret;
61 
62 	base = devm_platform_ioremap_resource(pdev, 0);
63 	if (IS_ERR(base))
64 		return PTR_ERR(base);
65 
66 	regmap = devm_regmap_init_mmio(dev, base, &ipq_pll_regmap_config);
67 	if (IS_ERR(regmap))
68 		return PTR_ERR(regmap);
69 
70 	clk_alpha_pll_configure(&ipq_pll, regmap, &ipq_pll_config);
71 
72 	ret = devm_clk_register_regmap(dev, &ipq_pll.clkr);
73 	if (ret)
74 		return ret;
75 
76 	return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
77 					   &ipq_pll.clkr.hw);
78 }
79 
80 static const struct of_device_id apss_ipq_pll_match_table[] = {
81 	{ .compatible = "qcom,ipq6018-a53pll" },
82 	{ }
83 };
84 
85 static struct platform_driver apss_ipq_pll_driver = {
86 	.probe = apss_ipq_pll_probe,
87 	.driver = {
88 		.name = "qcom-ipq-apss-pll",
89 		.of_match_table = apss_ipq_pll_match_table,
90 	},
91 };
92 module_platform_driver(apss_ipq_pll_driver);
93 
94 MODULE_DESCRIPTION("Qualcomm technology Inc APSS ALPHA PLL Driver");
95 MODULE_LICENSE("GPL v2");
96