1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Xudong Chen <xudong.chen@mediatek.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/completion.h> 9 #include <linux/delay.h> 10 #include <linux/device.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/err.h> 13 #include <linux/errno.h> 14 #include <linux/i2c.h> 15 #include <linux/init.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/kernel.h> 19 #include <linux/mm.h> 20 #include <linux/module.h> 21 #include <linux/of_address.h> 22 #include <linux/of_device.h> 23 #include <linux/of_irq.h> 24 #include <linux/platform_device.h> 25 #include <linux/scatterlist.h> 26 #include <linux/sched.h> 27 #include <linux/slab.h> 28 29 #define I2C_RS_TRANSFER (1 << 4) 30 #define I2C_ARB_LOST (1 << 3) 31 #define I2C_HS_NACKERR (1 << 2) 32 #define I2C_ACKERR (1 << 1) 33 #define I2C_TRANSAC_COMP (1 << 0) 34 #define I2C_TRANSAC_START (1 << 0) 35 #define I2C_RS_MUL_CNFG (1 << 15) 36 #define I2C_RS_MUL_TRIG (1 << 14) 37 #define I2C_DCM_DISABLE 0x0000 38 #define I2C_IO_CONFIG_OPEN_DRAIN 0x0003 39 #define I2C_IO_CONFIG_PUSH_PULL 0x0000 40 #define I2C_SOFT_RST 0x0001 41 #define I2C_FIFO_ADDR_CLR 0x0001 42 #define I2C_DELAY_LEN 0x0002 43 #define I2C_TIME_CLR_VALUE 0x0000 44 #define I2C_TIME_DEFAULT_VALUE 0x0003 45 #define I2C_WRRD_TRANAC_VALUE 0x0002 46 #define I2C_RD_TRANAC_VALUE 0x0001 47 #define I2C_SCL_MIS_COMP_VALUE 0x0000 48 49 #define I2C_DMA_CON_TX 0x0000 50 #define I2C_DMA_CON_RX 0x0001 51 #define I2C_DMA_ASYNC_MODE 0x0004 52 #define I2C_DMA_SKIP_CONFIG 0x0010 53 #define I2C_DMA_DIR_CHANGE 0x0200 54 #define I2C_DMA_START_EN 0x0001 55 #define I2C_DMA_INT_FLAG_NONE 0x0000 56 #define I2C_DMA_CLR_FLAG 0x0000 57 #define I2C_DMA_HARD_RST 0x0002 58 59 #define MAX_SAMPLE_CNT_DIV 8 60 #define MAX_STEP_CNT_DIV 64 61 #define MAX_CLOCK_DIV 256 62 #define MAX_HS_STEP_CNT_DIV 8 63 #define I2C_STANDARD_MODE_BUFFER (1000 / 2) 64 #define I2C_FAST_MODE_BUFFER (300 / 2) 65 #define I2C_FAST_MODE_PLUS_BUFFER (20 / 2) 66 67 #define I2C_CONTROL_RS (0x1 << 1) 68 #define I2C_CONTROL_DMA_EN (0x1 << 2) 69 #define I2C_CONTROL_CLK_EXT_EN (0x1 << 3) 70 #define I2C_CONTROL_DIR_CHANGE (0x1 << 4) 71 #define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5) 72 #define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6) 73 #define I2C_CONTROL_DMAACK_EN (0x1 << 8) 74 #define I2C_CONTROL_ASYNC_MODE (0x1 << 9) 75 #define I2C_CONTROL_WRAPPER (0x1 << 0) 76 77 #define I2C_DRV_NAME "i2c-mt65xx" 78 79 enum DMA_REGS_OFFSET { 80 OFFSET_INT_FLAG = 0x0, 81 OFFSET_INT_EN = 0x04, 82 OFFSET_EN = 0x08, 83 OFFSET_RST = 0x0c, 84 OFFSET_CON = 0x18, 85 OFFSET_TX_MEM_ADDR = 0x1c, 86 OFFSET_RX_MEM_ADDR = 0x20, 87 OFFSET_TX_LEN = 0x24, 88 OFFSET_RX_LEN = 0x28, 89 OFFSET_TX_4G_MODE = 0x54, 90 OFFSET_RX_4G_MODE = 0x58, 91 }; 92 93 enum i2c_trans_st_rs { 94 I2C_TRANS_STOP = 0, 95 I2C_TRANS_REPEATED_START, 96 }; 97 98 enum mtk_trans_op { 99 I2C_MASTER_WR = 1, 100 I2C_MASTER_RD, 101 I2C_MASTER_WRRD, 102 }; 103 104 enum I2C_REGS_OFFSET { 105 OFFSET_DATA_PORT, 106 OFFSET_SLAVE_ADDR, 107 OFFSET_INTR_MASK, 108 OFFSET_INTR_STAT, 109 OFFSET_CONTROL, 110 OFFSET_TRANSFER_LEN, 111 OFFSET_TRANSAC_LEN, 112 OFFSET_DELAY_LEN, 113 OFFSET_TIMING, 114 OFFSET_START, 115 OFFSET_EXT_CONF, 116 OFFSET_FIFO_STAT, 117 OFFSET_FIFO_THRESH, 118 OFFSET_FIFO_ADDR_CLR, 119 OFFSET_IO_CONFIG, 120 OFFSET_RSV_DEBUG, 121 OFFSET_HS, 122 OFFSET_SOFTRESET, 123 OFFSET_DCM_EN, 124 OFFSET_PATH_DIR, 125 OFFSET_DEBUGSTAT, 126 OFFSET_DEBUGCTRL, 127 OFFSET_TRANSFER_LEN_AUX, 128 OFFSET_CLOCK_DIV, 129 OFFSET_LTIMING, 130 OFFSET_SCL_HIGH_LOW_RATIO, 131 OFFSET_HS_SCL_HIGH_LOW_RATIO, 132 OFFSET_SCL_MIS_COMP_POINT, 133 OFFSET_STA_STO_AC_TIMING, 134 OFFSET_HS_STA_STO_AC_TIMING, 135 OFFSET_SDA_TIMING, 136 }; 137 138 static const u16 mt_i2c_regs_v1[] = { 139 [OFFSET_DATA_PORT] = 0x0, 140 [OFFSET_SLAVE_ADDR] = 0x4, 141 [OFFSET_INTR_MASK] = 0x8, 142 [OFFSET_INTR_STAT] = 0xc, 143 [OFFSET_CONTROL] = 0x10, 144 [OFFSET_TRANSFER_LEN] = 0x14, 145 [OFFSET_TRANSAC_LEN] = 0x18, 146 [OFFSET_DELAY_LEN] = 0x1c, 147 [OFFSET_TIMING] = 0x20, 148 [OFFSET_START] = 0x24, 149 [OFFSET_EXT_CONF] = 0x28, 150 [OFFSET_FIFO_STAT] = 0x30, 151 [OFFSET_FIFO_THRESH] = 0x34, 152 [OFFSET_FIFO_ADDR_CLR] = 0x38, 153 [OFFSET_IO_CONFIG] = 0x40, 154 [OFFSET_RSV_DEBUG] = 0x44, 155 [OFFSET_HS] = 0x48, 156 [OFFSET_SOFTRESET] = 0x50, 157 [OFFSET_DCM_EN] = 0x54, 158 [OFFSET_PATH_DIR] = 0x60, 159 [OFFSET_DEBUGSTAT] = 0x64, 160 [OFFSET_DEBUGCTRL] = 0x68, 161 [OFFSET_TRANSFER_LEN_AUX] = 0x6c, 162 [OFFSET_CLOCK_DIV] = 0x70, 163 [OFFSET_SCL_HIGH_LOW_RATIO] = 0x74, 164 [OFFSET_HS_SCL_HIGH_LOW_RATIO] = 0x78, 165 [OFFSET_SCL_MIS_COMP_POINT] = 0x7C, 166 [OFFSET_STA_STO_AC_TIMING] = 0x80, 167 [OFFSET_HS_STA_STO_AC_TIMING] = 0x84, 168 [OFFSET_SDA_TIMING] = 0x88, 169 }; 170 171 static const u16 mt_i2c_regs_v2[] = { 172 [OFFSET_DATA_PORT] = 0x0, 173 [OFFSET_SLAVE_ADDR] = 0x4, 174 [OFFSET_INTR_MASK] = 0x8, 175 [OFFSET_INTR_STAT] = 0xc, 176 [OFFSET_CONTROL] = 0x10, 177 [OFFSET_TRANSFER_LEN] = 0x14, 178 [OFFSET_TRANSAC_LEN] = 0x18, 179 [OFFSET_DELAY_LEN] = 0x1c, 180 [OFFSET_TIMING] = 0x20, 181 [OFFSET_START] = 0x24, 182 [OFFSET_EXT_CONF] = 0x28, 183 [OFFSET_LTIMING] = 0x2c, 184 [OFFSET_HS] = 0x30, 185 [OFFSET_IO_CONFIG] = 0x34, 186 [OFFSET_FIFO_ADDR_CLR] = 0x38, 187 [OFFSET_SDA_TIMING] = 0x3c, 188 [OFFSET_TRANSFER_LEN_AUX] = 0x44, 189 [OFFSET_CLOCK_DIV] = 0x48, 190 [OFFSET_SOFTRESET] = 0x50, 191 [OFFSET_SCL_MIS_COMP_POINT] = 0x90, 192 [OFFSET_DEBUGSTAT] = 0xe0, 193 [OFFSET_DEBUGCTRL] = 0xe8, 194 [OFFSET_FIFO_STAT] = 0xf4, 195 [OFFSET_FIFO_THRESH] = 0xf8, 196 [OFFSET_DCM_EN] = 0xf88, 197 }; 198 199 struct mtk_i2c_compatible { 200 const struct i2c_adapter_quirks *quirks; 201 const u16 *regs; 202 unsigned char pmic_i2c: 1; 203 unsigned char dcm: 1; 204 unsigned char auto_restart: 1; 205 unsigned char aux_len_reg: 1; 206 unsigned char timing_adjust: 1; 207 unsigned char dma_sync: 1; 208 unsigned char ltiming_adjust: 1; 209 unsigned char apdma_sync: 1; 210 unsigned char max_dma_support; 211 }; 212 213 struct mtk_i2c_ac_timing { 214 u16 htiming; 215 u16 ltiming; 216 u16 hs; 217 u16 ext; 218 u16 inter_clk_div; 219 u16 scl_hl_ratio; 220 u16 hs_scl_hl_ratio; 221 u16 sta_stop; 222 u16 hs_sta_stop; 223 u16 sda_timing; 224 }; 225 226 struct mtk_i2c { 227 struct i2c_adapter adap; /* i2c host adapter */ 228 struct device *dev; 229 struct completion msg_complete; 230 231 /* set in i2c probe */ 232 void __iomem *base; /* i2c base addr */ 233 void __iomem *pdmabase; /* dma base address*/ 234 struct clk *clk_main; /* main clock for i2c bus */ 235 struct clk *clk_dma; /* DMA clock for i2c via DMA */ 236 struct clk *clk_pmic; /* PMIC clock for i2c from PMIC */ 237 struct clk *clk_arb; /* Arbitrator clock for i2c */ 238 bool have_pmic; /* can use i2c pins from PMIC */ 239 bool use_push_pull; /* IO config push-pull mode */ 240 241 u16 irq_stat; /* interrupt status */ 242 unsigned int clk_src_div; 243 unsigned int speed_hz; /* The speed in transfer */ 244 enum mtk_trans_op op; 245 u16 timing_reg; 246 u16 high_speed_reg; 247 u16 ltiming_reg; 248 unsigned char auto_restart; 249 bool ignore_restart_irq; 250 struct mtk_i2c_ac_timing ac_timing; 251 const struct mtk_i2c_compatible *dev_comp; 252 }; 253 254 /** 255 * struct i2c_spec_values: 256 * @min_low_ns: min LOW period of the SCL clock 257 * @min_su_sta_ns: min set-up time for a repeated START condition 258 * @max_hd_dat_ns: max data hold time 259 * @min_su_dat_ns: min data set-up time 260 */ 261 struct i2c_spec_values { 262 unsigned int min_low_ns; 263 unsigned int min_su_sta_ns; 264 unsigned int max_hd_dat_ns; 265 unsigned int min_su_dat_ns; 266 }; 267 268 static const struct i2c_spec_values standard_mode_spec = { 269 .min_low_ns = 4700 + I2C_STANDARD_MODE_BUFFER, 270 .min_su_sta_ns = 4700 + I2C_STANDARD_MODE_BUFFER, 271 .max_hd_dat_ns = 3450 - I2C_STANDARD_MODE_BUFFER, 272 .min_su_dat_ns = 250 + I2C_STANDARD_MODE_BUFFER, 273 }; 274 275 static const struct i2c_spec_values fast_mode_spec = { 276 .min_low_ns = 1300 + I2C_FAST_MODE_BUFFER, 277 .min_su_sta_ns = 600 + I2C_FAST_MODE_BUFFER, 278 .max_hd_dat_ns = 900 - I2C_FAST_MODE_BUFFER, 279 .min_su_dat_ns = 100 + I2C_FAST_MODE_BUFFER, 280 }; 281 282 static const struct i2c_spec_values fast_mode_plus_spec = { 283 .min_low_ns = 500 + I2C_FAST_MODE_PLUS_BUFFER, 284 .min_su_sta_ns = 260 + I2C_FAST_MODE_PLUS_BUFFER, 285 .max_hd_dat_ns = 400 - I2C_FAST_MODE_PLUS_BUFFER, 286 .min_su_dat_ns = 50 + I2C_FAST_MODE_PLUS_BUFFER, 287 }; 288 289 static const struct i2c_adapter_quirks mt6577_i2c_quirks = { 290 .flags = I2C_AQ_COMB_WRITE_THEN_READ, 291 .max_num_msgs = 1, 292 .max_write_len = 255, 293 .max_read_len = 255, 294 .max_comb_1st_msg_len = 255, 295 .max_comb_2nd_msg_len = 31, 296 }; 297 298 static const struct i2c_adapter_quirks mt7622_i2c_quirks = { 299 .max_num_msgs = 255, 300 }; 301 302 static const struct i2c_adapter_quirks mt8183_i2c_quirks = { 303 .flags = I2C_AQ_NO_ZERO_LEN, 304 }; 305 306 static const struct mtk_i2c_compatible mt2712_compat = { 307 .regs = mt_i2c_regs_v1, 308 .pmic_i2c = 0, 309 .dcm = 1, 310 .auto_restart = 1, 311 .aux_len_reg = 1, 312 .timing_adjust = 1, 313 .dma_sync = 0, 314 .ltiming_adjust = 0, 315 .apdma_sync = 0, 316 .max_dma_support = 33, 317 }; 318 319 static const struct mtk_i2c_compatible mt6577_compat = { 320 .quirks = &mt6577_i2c_quirks, 321 .regs = mt_i2c_regs_v1, 322 .pmic_i2c = 0, 323 .dcm = 1, 324 .auto_restart = 0, 325 .aux_len_reg = 0, 326 .timing_adjust = 0, 327 .dma_sync = 0, 328 .ltiming_adjust = 0, 329 .apdma_sync = 0, 330 .max_dma_support = 32, 331 }; 332 333 static const struct mtk_i2c_compatible mt6589_compat = { 334 .quirks = &mt6577_i2c_quirks, 335 .regs = mt_i2c_regs_v1, 336 .pmic_i2c = 1, 337 .dcm = 0, 338 .auto_restart = 0, 339 .aux_len_reg = 0, 340 .timing_adjust = 0, 341 .dma_sync = 0, 342 .ltiming_adjust = 0, 343 .apdma_sync = 0, 344 .max_dma_support = 32, 345 }; 346 347 static const struct mtk_i2c_compatible mt7622_compat = { 348 .quirks = &mt7622_i2c_quirks, 349 .regs = mt_i2c_regs_v1, 350 .pmic_i2c = 0, 351 .dcm = 1, 352 .auto_restart = 1, 353 .aux_len_reg = 1, 354 .timing_adjust = 0, 355 .dma_sync = 0, 356 .ltiming_adjust = 0, 357 .apdma_sync = 0, 358 .max_dma_support = 32, 359 }; 360 361 static const struct mtk_i2c_compatible mt8173_compat = { 362 .regs = mt_i2c_regs_v1, 363 .pmic_i2c = 0, 364 .dcm = 1, 365 .auto_restart = 1, 366 .aux_len_reg = 1, 367 .timing_adjust = 0, 368 .dma_sync = 0, 369 .ltiming_adjust = 0, 370 .apdma_sync = 0, 371 .max_dma_support = 33, 372 }; 373 374 static const struct mtk_i2c_compatible mt8183_compat = { 375 .quirks = &mt8183_i2c_quirks, 376 .regs = mt_i2c_regs_v2, 377 .pmic_i2c = 0, 378 .dcm = 0, 379 .auto_restart = 1, 380 .aux_len_reg = 1, 381 .timing_adjust = 1, 382 .dma_sync = 1, 383 .ltiming_adjust = 1, 384 .apdma_sync = 0, 385 .max_dma_support = 33, 386 }; 387 388 static const struct mtk_i2c_compatible mt8192_compat = { 389 .quirks = &mt8183_i2c_quirks, 390 .regs = mt_i2c_regs_v2, 391 .pmic_i2c = 0, 392 .dcm = 0, 393 .auto_restart = 1, 394 .aux_len_reg = 1, 395 .timing_adjust = 1, 396 .dma_sync = 1, 397 .ltiming_adjust = 1, 398 .apdma_sync = 1, 399 .max_dma_support = 36, 400 }; 401 402 static const struct of_device_id mtk_i2c_of_match[] = { 403 { .compatible = "mediatek,mt2712-i2c", .data = &mt2712_compat }, 404 { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat }, 405 { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat }, 406 { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat }, 407 { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, 408 { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat }, 409 { .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat }, 410 {} 411 }; 412 MODULE_DEVICE_TABLE(of, mtk_i2c_of_match); 413 414 static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg) 415 { 416 return readw(i2c->base + i2c->dev_comp->regs[reg]); 417 } 418 419 static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val, 420 enum I2C_REGS_OFFSET reg) 421 { 422 writew(val, i2c->base + i2c->dev_comp->regs[reg]); 423 } 424 425 static int mtk_i2c_clock_enable(struct mtk_i2c *i2c) 426 { 427 int ret; 428 429 ret = clk_prepare_enable(i2c->clk_dma); 430 if (ret) 431 return ret; 432 433 ret = clk_prepare_enable(i2c->clk_main); 434 if (ret) 435 goto err_main; 436 437 if (i2c->have_pmic) { 438 ret = clk_prepare_enable(i2c->clk_pmic); 439 if (ret) 440 goto err_pmic; 441 } 442 443 if (i2c->clk_arb) { 444 ret = clk_prepare_enable(i2c->clk_arb); 445 if (ret) 446 goto err_arb; 447 } 448 449 return 0; 450 451 err_arb: 452 if (i2c->have_pmic) 453 clk_disable_unprepare(i2c->clk_pmic); 454 err_pmic: 455 clk_disable_unprepare(i2c->clk_main); 456 err_main: 457 clk_disable_unprepare(i2c->clk_dma); 458 459 return ret; 460 } 461 462 static void mtk_i2c_clock_disable(struct mtk_i2c *i2c) 463 { 464 if (i2c->clk_arb) 465 clk_disable_unprepare(i2c->clk_arb); 466 467 if (i2c->have_pmic) 468 clk_disable_unprepare(i2c->clk_pmic); 469 470 clk_disable_unprepare(i2c->clk_main); 471 clk_disable_unprepare(i2c->clk_dma); 472 } 473 474 static void mtk_i2c_init_hw(struct mtk_i2c *i2c) 475 { 476 u16 control_reg; 477 478 mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET); 479 480 /* Set ioconfig */ 481 if (i2c->use_push_pull) 482 mtk_i2c_writew(i2c, I2C_IO_CONFIG_PUSH_PULL, OFFSET_IO_CONFIG); 483 else 484 mtk_i2c_writew(i2c, I2C_IO_CONFIG_OPEN_DRAIN, OFFSET_IO_CONFIG); 485 486 if (i2c->dev_comp->dcm) 487 mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN); 488 489 mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING); 490 mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS); 491 if (i2c->dev_comp->ltiming_adjust) 492 mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING); 493 494 if (i2c->dev_comp->timing_adjust) { 495 mtk_i2c_writew(i2c, i2c->ac_timing.ext, OFFSET_EXT_CONF); 496 mtk_i2c_writew(i2c, i2c->ac_timing.inter_clk_div, 497 OFFSET_CLOCK_DIV); 498 mtk_i2c_writew(i2c, I2C_SCL_MIS_COMP_VALUE, 499 OFFSET_SCL_MIS_COMP_POINT); 500 mtk_i2c_writew(i2c, i2c->ac_timing.sda_timing, 501 OFFSET_SDA_TIMING); 502 503 if (i2c->dev_comp->ltiming_adjust) { 504 mtk_i2c_writew(i2c, i2c->ac_timing.htiming, 505 OFFSET_TIMING); 506 mtk_i2c_writew(i2c, i2c->ac_timing.hs, OFFSET_HS); 507 mtk_i2c_writew(i2c, i2c->ac_timing.ltiming, 508 OFFSET_LTIMING); 509 } else { 510 mtk_i2c_writew(i2c, i2c->ac_timing.scl_hl_ratio, 511 OFFSET_SCL_HIGH_LOW_RATIO); 512 mtk_i2c_writew(i2c, i2c->ac_timing.hs_scl_hl_ratio, 513 OFFSET_HS_SCL_HIGH_LOW_RATIO); 514 mtk_i2c_writew(i2c, i2c->ac_timing.sta_stop, 515 OFFSET_STA_STO_AC_TIMING); 516 mtk_i2c_writew(i2c, i2c->ac_timing.hs_sta_stop, 517 OFFSET_HS_STA_STO_AC_TIMING); 518 } 519 } 520 521 /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */ 522 if (i2c->have_pmic) 523 mtk_i2c_writew(i2c, I2C_CONTROL_WRAPPER, OFFSET_PATH_DIR); 524 525 control_reg = I2C_CONTROL_ACKERR_DET_EN | 526 I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN; 527 if (i2c->dev_comp->dma_sync) 528 control_reg |= I2C_CONTROL_DMAACK_EN | I2C_CONTROL_ASYNC_MODE; 529 530 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); 531 mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN); 532 533 writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST); 534 udelay(50); 535 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); 536 } 537 538 static const struct i2c_spec_values *mtk_i2c_get_spec(unsigned int speed) 539 { 540 if (speed <= I2C_MAX_STANDARD_MODE_FREQ) 541 return &standard_mode_spec; 542 else if (speed <= I2C_MAX_FAST_MODE_FREQ) 543 return &fast_mode_spec; 544 else 545 return &fast_mode_plus_spec; 546 } 547 548 static int mtk_i2c_max_step_cnt(unsigned int target_speed) 549 { 550 if (target_speed > I2C_MAX_FAST_MODE_FREQ) 551 return MAX_HS_STEP_CNT_DIV; 552 else 553 return MAX_STEP_CNT_DIV; 554 } 555 556 /* 557 * Check and Calculate i2c ac-timing 558 * 559 * Hardware design: 560 * sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src 561 * xxx_cnt_div = spec->min_xxx_ns / sample_ns 562 * 563 * Sample_ns is rounded down for xxx_cnt_div would be greater 564 * than the smallest spec. 565 * The sda_timing is chosen as the middle value between 566 * the largest and smallest. 567 */ 568 static int mtk_i2c_check_ac_timing(struct mtk_i2c *i2c, 569 unsigned int clk_src, 570 unsigned int check_speed, 571 unsigned int step_cnt, 572 unsigned int sample_cnt) 573 { 574 const struct i2c_spec_values *spec; 575 unsigned int su_sta_cnt, low_cnt, high_cnt, max_step_cnt; 576 unsigned int sda_max, sda_min, clk_ns, max_sta_cnt = 0x3f; 577 unsigned int sample_ns = div_u64(1000000000ULL * (sample_cnt + 1), 578 clk_src); 579 580 if (!i2c->dev_comp->timing_adjust) 581 return 0; 582 583 if (i2c->dev_comp->ltiming_adjust) 584 max_sta_cnt = 0x100; 585 586 spec = mtk_i2c_get_spec(check_speed); 587 588 if (i2c->dev_comp->ltiming_adjust) 589 clk_ns = 1000000000 / clk_src; 590 else 591 clk_ns = sample_ns / 2; 592 593 su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns, clk_ns); 594 if (su_sta_cnt > max_sta_cnt) 595 return -1; 596 597 low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns); 598 max_step_cnt = mtk_i2c_max_step_cnt(check_speed); 599 if ((2 * step_cnt) > low_cnt && low_cnt < max_step_cnt) { 600 if (low_cnt > step_cnt) { 601 high_cnt = 2 * step_cnt - low_cnt; 602 } else { 603 high_cnt = step_cnt; 604 low_cnt = step_cnt; 605 } 606 } else { 607 return -2; 608 } 609 610 sda_max = spec->max_hd_dat_ns / sample_ns; 611 if (sda_max > low_cnt) 612 sda_max = 0; 613 614 sda_min = DIV_ROUND_UP(spec->min_su_dat_ns, sample_ns); 615 if (sda_min < low_cnt) 616 sda_min = 0; 617 618 if (sda_min > sda_max) 619 return -3; 620 621 if (check_speed > I2C_MAX_FAST_MODE_FREQ) { 622 if (i2c->dev_comp->ltiming_adjust) { 623 i2c->ac_timing.hs = I2C_TIME_DEFAULT_VALUE | 624 (sample_cnt << 12) | (high_cnt << 8); 625 i2c->ac_timing.ltiming &= ~GENMASK(15, 9); 626 i2c->ac_timing.ltiming |= (sample_cnt << 12) | 627 (low_cnt << 9); 628 i2c->ac_timing.ext &= ~GENMASK(7, 1); 629 i2c->ac_timing.ext |= (su_sta_cnt << 1) | (1 << 0); 630 } else { 631 i2c->ac_timing.hs_scl_hl_ratio = (1 << 12) | 632 (high_cnt << 6) | low_cnt; 633 i2c->ac_timing.hs_sta_stop = (su_sta_cnt << 8) | 634 su_sta_cnt; 635 } 636 i2c->ac_timing.sda_timing &= ~GENMASK(11, 6); 637 i2c->ac_timing.sda_timing |= (1 << 12) | 638 ((sda_max + sda_min) / 2) << 6; 639 } else { 640 if (i2c->dev_comp->ltiming_adjust) { 641 i2c->ac_timing.htiming = (sample_cnt << 8) | (high_cnt); 642 i2c->ac_timing.ltiming = (sample_cnt << 6) | (low_cnt); 643 i2c->ac_timing.ext = (su_sta_cnt << 8) | (1 << 0); 644 } else { 645 i2c->ac_timing.scl_hl_ratio = (1 << 12) | 646 (high_cnt << 6) | low_cnt; 647 i2c->ac_timing.sta_stop = (su_sta_cnt << 8) | 648 su_sta_cnt; 649 } 650 651 i2c->ac_timing.sda_timing = (1 << 12) | 652 (sda_max + sda_min) / 2; 653 } 654 655 return 0; 656 } 657 658 /* 659 * Calculate i2c port speed 660 * 661 * Hardware design: 662 * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt) 663 * clock_div: fixed in hardware, but may be various in different SoCs 664 * 665 * The calculation want to pick the highest bus frequency that is still 666 * less than or equal to i2c->speed_hz. The calculation try to get 667 * sample_cnt and step_cn 668 */ 669 static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src, 670 unsigned int target_speed, 671 unsigned int *timing_step_cnt, 672 unsigned int *timing_sample_cnt) 673 { 674 unsigned int step_cnt; 675 unsigned int sample_cnt; 676 unsigned int max_step_cnt; 677 unsigned int base_sample_cnt = MAX_SAMPLE_CNT_DIV; 678 unsigned int base_step_cnt; 679 unsigned int opt_div; 680 unsigned int best_mul; 681 unsigned int cnt_mul; 682 int ret = -EINVAL; 683 684 if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) 685 target_speed = I2C_MAX_FAST_MODE_PLUS_FREQ; 686 687 max_step_cnt = mtk_i2c_max_step_cnt(target_speed); 688 base_step_cnt = max_step_cnt; 689 /* Find the best combination */ 690 opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed); 691 best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt; 692 693 /* Search for the best pair (sample_cnt, step_cnt) with 694 * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV 695 * 0 < step_cnt < max_step_cnt 696 * sample_cnt * step_cnt >= opt_div 697 * optimizing for sample_cnt * step_cnt being minimal 698 */ 699 for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) { 700 step_cnt = DIV_ROUND_UP(opt_div, sample_cnt); 701 cnt_mul = step_cnt * sample_cnt; 702 if (step_cnt > max_step_cnt) 703 continue; 704 705 if (cnt_mul < best_mul) { 706 ret = mtk_i2c_check_ac_timing(i2c, clk_src, 707 target_speed, step_cnt - 1, sample_cnt - 1); 708 if (ret) 709 continue; 710 711 best_mul = cnt_mul; 712 base_sample_cnt = sample_cnt; 713 base_step_cnt = step_cnt; 714 if (best_mul == opt_div) 715 break; 716 } 717 } 718 719 if (ret) 720 return -EINVAL; 721 722 sample_cnt = base_sample_cnt; 723 step_cnt = base_step_cnt; 724 725 if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) { 726 /* In this case, hardware can't support such 727 * low i2c_bus_freq 728 */ 729 dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed); 730 return -EINVAL; 731 } 732 733 *timing_step_cnt = step_cnt - 1; 734 *timing_sample_cnt = sample_cnt - 1; 735 736 return 0; 737 } 738 739 static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk) 740 { 741 unsigned int clk_src; 742 unsigned int step_cnt; 743 unsigned int sample_cnt; 744 unsigned int l_step_cnt; 745 unsigned int l_sample_cnt; 746 unsigned int target_speed; 747 unsigned int clk_div; 748 unsigned int max_clk_div; 749 int ret; 750 751 target_speed = i2c->speed_hz; 752 parent_clk /= i2c->clk_src_div; 753 754 if (i2c->dev_comp->timing_adjust) 755 max_clk_div = MAX_CLOCK_DIV; 756 else 757 max_clk_div = 1; 758 759 for (clk_div = 1; clk_div <= max_clk_div; clk_div++) { 760 clk_src = parent_clk / clk_div; 761 762 if (target_speed > I2C_MAX_FAST_MODE_FREQ) { 763 /* Set master code speed register */ 764 ret = mtk_i2c_calculate_speed(i2c, clk_src, 765 I2C_MAX_FAST_MODE_FREQ, 766 &l_step_cnt, 767 &l_sample_cnt); 768 if (ret < 0) 769 continue; 770 771 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt; 772 773 /* Set the high speed mode register */ 774 ret = mtk_i2c_calculate_speed(i2c, clk_src, 775 target_speed, &step_cnt, 776 &sample_cnt); 777 if (ret < 0) 778 continue; 779 780 i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE | 781 (sample_cnt << 12) | (step_cnt << 8); 782 783 if (i2c->dev_comp->ltiming_adjust) 784 i2c->ltiming_reg = 785 (l_sample_cnt << 6) | l_step_cnt | 786 (sample_cnt << 12) | (step_cnt << 9); 787 } else { 788 ret = mtk_i2c_calculate_speed(i2c, clk_src, 789 target_speed, &l_step_cnt, 790 &l_sample_cnt); 791 if (ret < 0) 792 continue; 793 794 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt; 795 796 /* Disable the high speed transaction */ 797 i2c->high_speed_reg = I2C_TIME_CLR_VALUE; 798 799 if (i2c->dev_comp->ltiming_adjust) 800 i2c->ltiming_reg = 801 (l_sample_cnt << 6) | l_step_cnt; 802 } 803 804 break; 805 } 806 807 i2c->ac_timing.inter_clk_div = clk_div - 1; 808 809 return 0; 810 } 811 812 static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, 813 int num, int left_num) 814 { 815 u16 addr_reg; 816 u16 start_reg; 817 u16 control_reg; 818 u16 restart_flag = 0; 819 u16 dma_sync = 0; 820 u32 reg_4g_mode; 821 u8 *dma_rd_buf = NULL; 822 u8 *dma_wr_buf = NULL; 823 dma_addr_t rpaddr = 0; 824 dma_addr_t wpaddr = 0; 825 int ret; 826 827 i2c->irq_stat = 0; 828 829 if (i2c->auto_restart) 830 restart_flag = I2C_RS_TRANSFER; 831 832 reinit_completion(&i2c->msg_complete); 833 834 control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) & 835 ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS); 836 if ((i2c->speed_hz > I2C_MAX_FAST_MODE_FREQ) || (left_num >= 1)) 837 control_reg |= I2C_CONTROL_RS; 838 839 if (i2c->op == I2C_MASTER_WRRD) 840 control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS; 841 842 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); 843 844 addr_reg = i2c_8bit_addr_from_msg(msgs); 845 mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR); 846 847 /* Clear interrupt status */ 848 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 849 I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_STAT); 850 851 mtk_i2c_writew(i2c, I2C_FIFO_ADDR_CLR, OFFSET_FIFO_ADDR_CLR); 852 853 /* Enable interrupt */ 854 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 855 I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_MASK); 856 857 /* Set transfer and transaction len */ 858 if (i2c->op == I2C_MASTER_WRRD) { 859 if (i2c->dev_comp->aux_len_reg) { 860 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN); 861 mtk_i2c_writew(i2c, (msgs + 1)->len, 862 OFFSET_TRANSFER_LEN_AUX); 863 } else { 864 mtk_i2c_writew(i2c, msgs->len | ((msgs + 1)->len) << 8, 865 OFFSET_TRANSFER_LEN); 866 } 867 mtk_i2c_writew(i2c, I2C_WRRD_TRANAC_VALUE, OFFSET_TRANSAC_LEN); 868 } else { 869 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN); 870 mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN); 871 } 872 873 if (i2c->dev_comp->apdma_sync) { 874 dma_sync = I2C_DMA_SKIP_CONFIG | I2C_DMA_ASYNC_MODE; 875 if (i2c->op == I2C_MASTER_WRRD) 876 dma_sync |= I2C_DMA_DIR_CHANGE; 877 } 878 879 /* Prepare buffer data to start transfer */ 880 if (i2c->op == I2C_MASTER_RD) { 881 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); 882 writel(I2C_DMA_CON_RX | dma_sync, i2c->pdmabase + OFFSET_CON); 883 884 dma_rd_buf = i2c_get_dma_safe_msg_buf(msgs, 1); 885 if (!dma_rd_buf) 886 return -ENOMEM; 887 888 rpaddr = dma_map_single(i2c->dev, dma_rd_buf, 889 msgs->len, DMA_FROM_DEVICE); 890 if (dma_mapping_error(i2c->dev, rpaddr)) { 891 i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, false); 892 893 return -ENOMEM; 894 } 895 896 if (i2c->dev_comp->max_dma_support > 32) { 897 reg_4g_mode = upper_32_bits(rpaddr); 898 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE); 899 } 900 901 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR); 902 writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN); 903 } else if (i2c->op == I2C_MASTER_WR) { 904 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); 905 writel(I2C_DMA_CON_TX | dma_sync, i2c->pdmabase + OFFSET_CON); 906 907 dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1); 908 if (!dma_wr_buf) 909 return -ENOMEM; 910 911 wpaddr = dma_map_single(i2c->dev, dma_wr_buf, 912 msgs->len, DMA_TO_DEVICE); 913 if (dma_mapping_error(i2c->dev, wpaddr)) { 914 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 915 916 return -ENOMEM; 917 } 918 919 if (i2c->dev_comp->max_dma_support > 32) { 920 reg_4g_mode = upper_32_bits(wpaddr); 921 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE); 922 } 923 924 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); 925 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); 926 } else { 927 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG); 928 writel(I2C_DMA_CLR_FLAG | dma_sync, i2c->pdmabase + OFFSET_CON); 929 930 dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1); 931 if (!dma_wr_buf) 932 return -ENOMEM; 933 934 wpaddr = dma_map_single(i2c->dev, dma_wr_buf, 935 msgs->len, DMA_TO_DEVICE); 936 if (dma_mapping_error(i2c->dev, wpaddr)) { 937 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 938 939 return -ENOMEM; 940 } 941 942 dma_rd_buf = i2c_get_dma_safe_msg_buf((msgs + 1), 1); 943 if (!dma_rd_buf) { 944 dma_unmap_single(i2c->dev, wpaddr, 945 msgs->len, DMA_TO_DEVICE); 946 947 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 948 949 return -ENOMEM; 950 } 951 952 rpaddr = dma_map_single(i2c->dev, dma_rd_buf, 953 (msgs + 1)->len, 954 DMA_FROM_DEVICE); 955 if (dma_mapping_error(i2c->dev, rpaddr)) { 956 dma_unmap_single(i2c->dev, wpaddr, 957 msgs->len, DMA_TO_DEVICE); 958 959 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false); 960 i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), false); 961 962 return -ENOMEM; 963 } 964 965 if (i2c->dev_comp->max_dma_support > 32) { 966 reg_4g_mode = upper_32_bits(wpaddr); 967 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE); 968 969 reg_4g_mode = upper_32_bits(rpaddr); 970 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE); 971 } 972 973 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); 974 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR); 975 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); 976 writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN); 977 } 978 979 writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN); 980 981 if (!i2c->auto_restart) { 982 start_reg = I2C_TRANSAC_START; 983 } else { 984 start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG; 985 if (left_num >= 1) 986 start_reg |= I2C_RS_MUL_CNFG; 987 } 988 mtk_i2c_writew(i2c, start_reg, OFFSET_START); 989 990 ret = wait_for_completion_timeout(&i2c->msg_complete, 991 i2c->adap.timeout); 992 993 /* Clear interrupt mask */ 994 mtk_i2c_writew(i2c, ~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR | 995 I2C_ARB_LOST | I2C_TRANSAC_COMP), OFFSET_INTR_MASK); 996 997 if (i2c->op == I2C_MASTER_WR) { 998 dma_unmap_single(i2c->dev, wpaddr, 999 msgs->len, DMA_TO_DEVICE); 1000 1001 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true); 1002 } else if (i2c->op == I2C_MASTER_RD) { 1003 dma_unmap_single(i2c->dev, rpaddr, 1004 msgs->len, DMA_FROM_DEVICE); 1005 1006 i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, true); 1007 } else { 1008 dma_unmap_single(i2c->dev, wpaddr, msgs->len, 1009 DMA_TO_DEVICE); 1010 dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len, 1011 DMA_FROM_DEVICE); 1012 1013 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true); 1014 i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), true); 1015 } 1016 1017 if (ret == 0) { 1018 dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr); 1019 mtk_i2c_init_hw(i2c); 1020 return -ETIMEDOUT; 1021 } 1022 1023 if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) { 1024 dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr); 1025 mtk_i2c_init_hw(i2c); 1026 return -ENXIO; 1027 } 1028 1029 return 0; 1030 } 1031 1032 static int mtk_i2c_transfer(struct i2c_adapter *adap, 1033 struct i2c_msg msgs[], int num) 1034 { 1035 int ret; 1036 int left_num = num; 1037 struct mtk_i2c *i2c = i2c_get_adapdata(adap); 1038 1039 ret = mtk_i2c_clock_enable(i2c); 1040 if (ret) 1041 return ret; 1042 1043 i2c->auto_restart = i2c->dev_comp->auto_restart; 1044 1045 /* checking if we can skip restart and optimize using WRRD mode */ 1046 if (i2c->auto_restart && num == 2) { 1047 if (!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD) && 1048 msgs[0].addr == msgs[1].addr) { 1049 i2c->auto_restart = 0; 1050 } 1051 } 1052 1053 if (i2c->auto_restart && num >= 2 && i2c->speed_hz > I2C_MAX_FAST_MODE_FREQ) 1054 /* ignore the first restart irq after the master code, 1055 * otherwise the first transfer will be discarded. 1056 */ 1057 i2c->ignore_restart_irq = true; 1058 else 1059 i2c->ignore_restart_irq = false; 1060 1061 while (left_num--) { 1062 if (!msgs->buf) { 1063 dev_dbg(i2c->dev, "data buffer is NULL.\n"); 1064 ret = -EINVAL; 1065 goto err_exit; 1066 } 1067 1068 if (msgs->flags & I2C_M_RD) 1069 i2c->op = I2C_MASTER_RD; 1070 else 1071 i2c->op = I2C_MASTER_WR; 1072 1073 if (!i2c->auto_restart) { 1074 if (num > 1) { 1075 /* combined two messages into one transaction */ 1076 i2c->op = I2C_MASTER_WRRD; 1077 left_num--; 1078 } 1079 } 1080 1081 /* always use DMA mode. */ 1082 ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num); 1083 if (ret < 0) 1084 goto err_exit; 1085 1086 msgs++; 1087 } 1088 /* the return value is number of executed messages */ 1089 ret = num; 1090 1091 err_exit: 1092 mtk_i2c_clock_disable(i2c); 1093 return ret; 1094 } 1095 1096 static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id) 1097 { 1098 struct mtk_i2c *i2c = dev_id; 1099 u16 restart_flag = 0; 1100 u16 intr_stat; 1101 1102 if (i2c->auto_restart) 1103 restart_flag = I2C_RS_TRANSFER; 1104 1105 intr_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT); 1106 mtk_i2c_writew(i2c, intr_stat, OFFSET_INTR_STAT); 1107 1108 /* 1109 * when occurs ack error, i2c controller generate two interrupts 1110 * first is the ack error interrupt, then the complete interrupt 1111 * i2c->irq_stat need keep the two interrupt value. 1112 */ 1113 i2c->irq_stat |= intr_stat; 1114 1115 if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) { 1116 i2c->ignore_restart_irq = false; 1117 i2c->irq_stat = 0; 1118 mtk_i2c_writew(i2c, I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG | 1119 I2C_TRANSAC_START, OFFSET_START); 1120 } else { 1121 if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag)) 1122 complete(&i2c->msg_complete); 1123 } 1124 1125 return IRQ_HANDLED; 1126 } 1127 1128 static u32 mtk_i2c_functionality(struct i2c_adapter *adap) 1129 { 1130 if (i2c_check_quirks(adap, I2C_AQ_NO_ZERO_LEN)) 1131 return I2C_FUNC_I2C | 1132 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 1133 else 1134 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 1135 } 1136 1137 static const struct i2c_algorithm mtk_i2c_algorithm = { 1138 .master_xfer = mtk_i2c_transfer, 1139 .functionality = mtk_i2c_functionality, 1140 }; 1141 1142 static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c) 1143 { 1144 int ret; 1145 1146 ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz); 1147 if (ret < 0) 1148 i2c->speed_hz = I2C_MAX_STANDARD_MODE_FREQ; 1149 1150 ret = of_property_read_u32(np, "clock-div", &i2c->clk_src_div); 1151 if (ret < 0) 1152 return ret; 1153 1154 if (i2c->clk_src_div == 0) 1155 return -EINVAL; 1156 1157 i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic"); 1158 i2c->use_push_pull = 1159 of_property_read_bool(np, "mediatek,use-push-pull"); 1160 1161 return 0; 1162 } 1163 1164 static int mtk_i2c_probe(struct platform_device *pdev) 1165 { 1166 int ret = 0; 1167 struct mtk_i2c *i2c; 1168 struct clk *clk; 1169 struct resource *res; 1170 int irq; 1171 1172 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 1173 if (!i2c) 1174 return -ENOMEM; 1175 1176 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1177 i2c->base = devm_ioremap_resource(&pdev->dev, res); 1178 if (IS_ERR(i2c->base)) 1179 return PTR_ERR(i2c->base); 1180 1181 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1182 i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res); 1183 if (IS_ERR(i2c->pdmabase)) 1184 return PTR_ERR(i2c->pdmabase); 1185 1186 irq = platform_get_irq(pdev, 0); 1187 if (irq <= 0) 1188 return irq; 1189 1190 init_completion(&i2c->msg_complete); 1191 1192 i2c->dev_comp = of_device_get_match_data(&pdev->dev); 1193 i2c->adap.dev.of_node = pdev->dev.of_node; 1194 i2c->dev = &pdev->dev; 1195 i2c->adap.dev.parent = &pdev->dev; 1196 i2c->adap.owner = THIS_MODULE; 1197 i2c->adap.algo = &mtk_i2c_algorithm; 1198 i2c->adap.quirks = i2c->dev_comp->quirks; 1199 i2c->adap.timeout = 2 * HZ; 1200 i2c->adap.retries = 1; 1201 1202 ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c); 1203 if (ret) 1204 return -EINVAL; 1205 1206 if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c) 1207 return -EINVAL; 1208 1209 i2c->clk_main = devm_clk_get(&pdev->dev, "main"); 1210 if (IS_ERR(i2c->clk_main)) { 1211 dev_err(&pdev->dev, "cannot get main clock\n"); 1212 return PTR_ERR(i2c->clk_main); 1213 } 1214 1215 i2c->clk_dma = devm_clk_get(&pdev->dev, "dma"); 1216 if (IS_ERR(i2c->clk_dma)) { 1217 dev_err(&pdev->dev, "cannot get dma clock\n"); 1218 return PTR_ERR(i2c->clk_dma); 1219 } 1220 1221 i2c->clk_arb = devm_clk_get(&pdev->dev, "arb"); 1222 if (IS_ERR(i2c->clk_arb)) 1223 i2c->clk_arb = NULL; 1224 1225 clk = i2c->clk_main; 1226 if (i2c->have_pmic) { 1227 i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic"); 1228 if (IS_ERR(i2c->clk_pmic)) { 1229 dev_err(&pdev->dev, "cannot get pmic clock\n"); 1230 return PTR_ERR(i2c->clk_pmic); 1231 } 1232 clk = i2c->clk_pmic; 1233 } 1234 1235 strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name)); 1236 1237 ret = mtk_i2c_set_speed(i2c, clk_get_rate(clk)); 1238 if (ret) { 1239 dev_err(&pdev->dev, "Failed to set the speed.\n"); 1240 return -EINVAL; 1241 } 1242 1243 if (i2c->dev_comp->max_dma_support > 32) { 1244 ret = dma_set_mask(&pdev->dev, 1245 DMA_BIT_MASK(i2c->dev_comp->max_dma_support)); 1246 if (ret) { 1247 dev_err(&pdev->dev, "dma_set_mask return error.\n"); 1248 return ret; 1249 } 1250 } 1251 1252 ret = mtk_i2c_clock_enable(i2c); 1253 if (ret) { 1254 dev_err(&pdev->dev, "clock enable failed!\n"); 1255 return ret; 1256 } 1257 mtk_i2c_init_hw(i2c); 1258 mtk_i2c_clock_disable(i2c); 1259 1260 ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq, 1261 IRQF_TRIGGER_NONE, I2C_DRV_NAME, i2c); 1262 if (ret < 0) { 1263 dev_err(&pdev->dev, 1264 "Request I2C IRQ %d fail\n", irq); 1265 return ret; 1266 } 1267 1268 i2c_set_adapdata(&i2c->adap, i2c); 1269 ret = i2c_add_adapter(&i2c->adap); 1270 if (ret) 1271 return ret; 1272 1273 platform_set_drvdata(pdev, i2c); 1274 1275 return 0; 1276 } 1277 1278 static int mtk_i2c_remove(struct platform_device *pdev) 1279 { 1280 struct mtk_i2c *i2c = platform_get_drvdata(pdev); 1281 1282 i2c_del_adapter(&i2c->adap); 1283 1284 return 0; 1285 } 1286 1287 #ifdef CONFIG_PM_SLEEP 1288 static int mtk_i2c_resume(struct device *dev) 1289 { 1290 int ret; 1291 struct mtk_i2c *i2c = dev_get_drvdata(dev); 1292 1293 ret = mtk_i2c_clock_enable(i2c); 1294 if (ret) { 1295 dev_err(dev, "clock enable failed!\n"); 1296 return ret; 1297 } 1298 1299 mtk_i2c_init_hw(i2c); 1300 1301 mtk_i2c_clock_disable(i2c); 1302 1303 return 0; 1304 } 1305 #endif 1306 1307 static const struct dev_pm_ops mtk_i2c_pm = { 1308 SET_SYSTEM_SLEEP_PM_OPS(NULL, mtk_i2c_resume) 1309 }; 1310 1311 static struct platform_driver mtk_i2c_driver = { 1312 .probe = mtk_i2c_probe, 1313 .remove = mtk_i2c_remove, 1314 .driver = { 1315 .name = I2C_DRV_NAME, 1316 .pm = &mtk_i2c_pm, 1317 .of_match_table = of_match_ptr(mtk_i2c_of_match), 1318 }, 1319 }; 1320 1321 module_platform_driver(mtk_i2c_driver); 1322 1323 MODULE_LICENSE("GPL v2"); 1324 MODULE_DESCRIPTION("MediaTek I2C Bus Driver"); 1325 MODULE_AUTHOR("Xudong Chen <xudong.chen@mediatek.com>"); 1326