1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_BOOK3S_32_PGTABLE_H 3 #define _ASM_POWERPC_BOOK3S_32_PGTABLE_H 4 5 #include <asm-generic/pgtable-nopmd.h> 6 7 #include <asm/book3s/32/hash.h> 8 9 /* And here we include common definitions */ 10 11 #define _PAGE_KERNEL_RO 0 12 #define _PAGE_KERNEL_ROX (_PAGE_EXEC) 13 #define _PAGE_KERNEL_RW (_PAGE_DIRTY | _PAGE_RW) 14 #define _PAGE_KERNEL_RWX (_PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC) 15 16 #define _PAGE_HPTEFLAGS _PAGE_HASHPTE 17 18 #ifndef __ASSEMBLY__ 19 20 static inline bool pte_user(pte_t pte) 21 { 22 return pte_val(pte) & _PAGE_USER; 23 } 24 #endif /* __ASSEMBLY__ */ 25 26 /* 27 * Location of the PFN in the PTE. Most 32-bit platforms use the same 28 * as _PAGE_SHIFT here (ie, naturally aligned). 29 * Platform who don't just pre-define the value so we don't override it here. 30 */ 31 #define PTE_RPN_SHIFT (PAGE_SHIFT) 32 33 /* 34 * The mask covered by the RPN must be a ULL on 32-bit platforms with 35 * 64-bit PTEs. 36 */ 37 #ifdef CONFIG_PTE_64BIT 38 #define PTE_RPN_MASK (~((1ULL << PTE_RPN_SHIFT) - 1)) 39 #else 40 #define PTE_RPN_MASK (~((1UL << PTE_RPN_SHIFT) - 1)) 41 #endif 42 43 /* 44 * _PAGE_CHG_MASK masks of bits that are to be preserved across 45 * pgprot changes. 46 */ 47 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HASHPTE | _PAGE_DIRTY | \ 48 _PAGE_ACCESSED | _PAGE_SPECIAL) 49 50 /* 51 * We define 2 sets of base prot bits, one for basic pages (ie, 52 * cacheable kernel and user pages) and one for non cacheable 53 * pages. We always set _PAGE_COHERENT when SMP is enabled or 54 * the processor might need it for DMA coherency. 55 */ 56 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED) 57 #define _PAGE_BASE (_PAGE_BASE_NC | _PAGE_COHERENT) 58 59 /* 60 * Permission masks used to generate the __P and __S table. 61 * 62 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h 63 * 64 * Write permissions imply read permissions for now. 65 */ 66 #define PAGE_NONE __pgprot(_PAGE_BASE) 67 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW) 68 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC) 69 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER) 70 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) 71 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER) 72 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) 73 74 /* Permission masks used for kernel mappings */ 75 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) 76 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_NO_CACHE) 77 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 78 _PAGE_NO_CACHE | _PAGE_GUARDED) 79 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) 80 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) 81 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) 82 83 /* 84 * Protection used for kernel text. We want the debuggers to be able to 85 * set breakpoints anywhere, so don't write protect the kernel text 86 * on platforms where such control is possible. 87 */ 88 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) ||\ 89 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE) 90 #define PAGE_KERNEL_TEXT PAGE_KERNEL_X 91 #else 92 #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX 93 #endif 94 95 /* Make modules code happy. We don't set RO yet */ 96 #define PAGE_KERNEL_EXEC PAGE_KERNEL_X 97 98 /* Advertise special mapping type for AGP */ 99 #define PAGE_AGP (PAGE_KERNEL_NC) 100 #define HAVE_PAGE_AGP 101 102 #define PTE_INDEX_SIZE PTE_SHIFT 103 #define PMD_INDEX_SIZE 0 104 #define PUD_INDEX_SIZE 0 105 #define PGD_INDEX_SIZE (32 - PGDIR_SHIFT) 106 107 #define PMD_CACHE_INDEX PMD_INDEX_SIZE 108 #define PUD_CACHE_INDEX PUD_INDEX_SIZE 109 110 #ifndef __ASSEMBLY__ 111 #define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_INDEX_SIZE) 112 #define PMD_TABLE_SIZE 0 113 #define PUD_TABLE_SIZE 0 114 #define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE) 115 116 /* Bits to mask out from a PMD to get to the PTE page */ 117 #define PMD_MASKED_BITS (PTE_TABLE_SIZE - 1) 118 #endif /* __ASSEMBLY__ */ 119 120 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 121 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 122 123 /* 124 * The normal case is that PTEs are 32-bits and we have a 1-page 125 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus 126 * 127 * For any >32-bit physical address platform, we can use the following 128 * two level page table layout where the pgdir is 8KB and the MS 13 bits 129 * are an index to the second level table. The combined pgdir/pmd first 130 * level has 2048 entries and the second level has 512 64-bit PTE entries. 131 * -Matt 132 */ 133 /* PGDIR_SHIFT determines what a top-level page table entry can map */ 134 #define PGDIR_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) 135 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 136 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 137 138 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 139 140 #ifndef __ASSEMBLY__ 141 142 int map_kernel_page(unsigned long va, phys_addr_t pa, pgprot_t prot); 143 144 #endif /* !__ASSEMBLY__ */ 145 146 /* 147 * This is the bottom of the PKMAP area with HIGHMEM or an arbitrary 148 * value (for now) on others, from where we can start layout kernel 149 * virtual space that goes below PKMAP and FIXMAP 150 */ 151 #include <asm/fixmap.h> 152 153 /* 154 * ioremap_bot starts at that address. Early ioremaps move down from there, 155 * until mem_init() at which point this becomes the top of the vmalloc 156 * and ioremap space 157 */ 158 #ifdef CONFIG_HIGHMEM 159 #define IOREMAP_TOP PKMAP_BASE 160 #else 161 #define IOREMAP_TOP FIXADDR_START 162 #endif 163 164 /* PPC32 shares vmalloc area with ioremap */ 165 #define IOREMAP_START VMALLOC_START 166 #define IOREMAP_END VMALLOC_END 167 168 /* 169 * Just any arbitrary offset to the start of the vmalloc VM area: the 170 * current 16MB value just means that there will be a 64MB "hole" after the 171 * physical memory until the kernel virtual memory starts. That means that 172 * any out-of-bounds memory accesses will hopefully be caught. 173 * The vmalloc() routines leaves a hole of 4kB between each vmalloced 174 * area for the same reason. ;) 175 * 176 * We no longer map larger than phys RAM with the BATs so we don't have 177 * to worry about the VMALLOC_OFFSET causing problems. We do have to worry 178 * about clashes between our early calls to ioremap() that start growing down 179 * from ioremap_base being run into the VM area allocations (growing upwards 180 * from VMALLOC_START). For this reason we have ioremap_bot to check when 181 * we actually run into our mappings setup in the early boot with the VM 182 * system. This really does become a problem for machines with good amounts 183 * of RAM. -- Cort 184 */ 185 #define VMALLOC_OFFSET (0x1000000) /* 16M */ 186 187 #define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))) 188 189 #ifdef CONFIG_KASAN_VMALLOC 190 #define VMALLOC_END ALIGN_DOWN(ioremap_bot, PAGE_SIZE << KASAN_SHADOW_SCALE_SHIFT) 191 #else 192 #define VMALLOC_END ioremap_bot 193 #endif 194 195 #ifdef CONFIG_STRICT_KERNEL_RWX 196 #define MODULES_END ALIGN_DOWN(PAGE_OFFSET, SZ_256M) 197 #define MODULES_VADDR (MODULES_END - SZ_256M) 198 #endif 199 200 #ifndef __ASSEMBLY__ 201 #include <linux/sched.h> 202 #include <linux/threads.h> 203 204 /* Bits to mask out from a PGD to get to the PUD page */ 205 #define PGD_MASKED_BITS 0 206 207 #define pte_ERROR(e) \ 208 pr_err("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \ 209 (unsigned long long)pte_val(e)) 210 #define pgd_ERROR(e) \ 211 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 212 /* 213 * Bits in a linux-style PTE. These match the bits in the 214 * (hardware-defined) PowerPC PTE as closely as possible. 215 */ 216 217 #define pte_clear(mm, addr, ptep) \ 218 do { pte_update(mm, addr, ptep, ~_PAGE_HASHPTE, 0, 0); } while (0) 219 220 #define pmd_none(pmd) (!pmd_val(pmd)) 221 #define pmd_bad(pmd) (pmd_val(pmd) & _PMD_BAD) 222 #define pmd_present(pmd) (pmd_val(pmd) & _PMD_PRESENT_MASK) 223 static inline void pmd_clear(pmd_t *pmdp) 224 { 225 *pmdp = __pmd(0); 226 } 227 228 229 /* 230 * When flushing the tlb entry for a page, we also need to flush the hash 231 * table entry. flush_hash_pages is assembler (for speed) in hashtable.S. 232 */ 233 extern int flush_hash_pages(unsigned context, unsigned long va, 234 unsigned long pmdval, int count); 235 236 /* Add an HPTE to the hash table */ 237 extern void add_hash_page(unsigned context, unsigned long va, 238 unsigned long pmdval); 239 240 /* Flush an entry from the TLB/hash table */ 241 extern void flush_hash_entry(struct mm_struct *mm, pte_t *ptep, 242 unsigned long address); 243 244 /* 245 * PTE updates. This function is called whenever an existing 246 * valid PTE is updated. This does -not- include set_pte_at() 247 * which nowadays only sets a new PTE. 248 * 249 * Depending on the type of MMU, we may need to use atomic updates 250 * and the PTE may be either 32 or 64 bit wide. In the later case, 251 * when using atomic updates, only the low part of the PTE is 252 * accessed atomically. 253 */ 254 static inline pte_basic_t pte_update(struct mm_struct *mm, unsigned long addr, pte_t *p, 255 unsigned long clr, unsigned long set, int huge) 256 { 257 pte_basic_t old; 258 unsigned long tmp; 259 260 __asm__ __volatile__( 261 #ifndef CONFIG_PTE_64BIT 262 "1: lwarx %0, 0, %3\n" 263 " andc %1, %0, %4\n" 264 #else 265 "1: lwarx %L0, 0, %3\n" 266 " lwz %0, -4(%3)\n" 267 " andc %1, %L0, %4\n" 268 #endif 269 " or %1, %1, %5\n" 270 " stwcx. %1, 0, %3\n" 271 " bne- 1b" 272 : "=&r" (old), "=&r" (tmp), "=m" (*p) 273 #ifndef CONFIG_PTE_64BIT 274 : "r" (p), 275 #else 276 : "b" ((unsigned long)(p) + 4), 277 #endif 278 "r" (clr), "r" (set), "m" (*p) 279 : "cc" ); 280 281 return old; 282 } 283 284 /* 285 * 2.6 calls this without flushing the TLB entry; this is wrong 286 * for our hash-based implementation, we fix that up here. 287 */ 288 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 289 static inline int __ptep_test_and_clear_young(struct mm_struct *mm, 290 unsigned long addr, pte_t *ptep) 291 { 292 unsigned long old; 293 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); 294 if (old & _PAGE_HASHPTE) { 295 unsigned long ptephys = __pa(ptep) & PAGE_MASK; 296 flush_hash_pages(mm->context.id, addr, ptephys, 1); 297 } 298 return (old & _PAGE_ACCESSED) != 0; 299 } 300 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ 301 __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep) 302 303 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 304 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, 305 pte_t *ptep) 306 { 307 return __pte(pte_update(mm, addr, ptep, ~_PAGE_HASHPTE, 0, 0)); 308 } 309 310 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 311 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, 312 pte_t *ptep) 313 { 314 pte_update(mm, addr, ptep, _PAGE_RW, 0, 0); 315 } 316 317 static inline void __ptep_set_access_flags(struct vm_area_struct *vma, 318 pte_t *ptep, pte_t entry, 319 unsigned long address, 320 int psize) 321 { 322 unsigned long set = pte_val(entry) & 323 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC); 324 325 pte_update(vma->vm_mm, address, ptep, 0, set, 0); 326 327 flush_tlb_page(vma, address); 328 } 329 330 #define __HAVE_ARCH_PTE_SAME 331 #define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0) 332 333 #define pmd_page(pmd) \ 334 pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT) 335 336 /* 337 * Encode and decode a swap entry. 338 * Note that the bits we use in a PTE for representing a swap entry 339 * must not include the _PAGE_PRESENT bit or the _PAGE_HASHPTE bit (if used). 340 * -- paulus 341 */ 342 #define __swp_type(entry) ((entry).val & 0x1f) 343 #define __swp_offset(entry) ((entry).val >> 5) 344 #define __swp_entry(type, offset) ((swp_entry_t) { (type) | ((offset) << 5) }) 345 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 3 }) 346 #define __swp_entry_to_pte(x) ((pte_t) { (x).val << 3 }) 347 348 /* Generic accessors to PTE bits */ 349 static inline int pte_write(pte_t pte) { return !!(pte_val(pte) & _PAGE_RW);} 350 static inline int pte_read(pte_t pte) { return 1; } 351 static inline int pte_dirty(pte_t pte) { return !!(pte_val(pte) & _PAGE_DIRTY); } 352 static inline int pte_young(pte_t pte) { return !!(pte_val(pte) & _PAGE_ACCESSED); } 353 static inline int pte_special(pte_t pte) { return !!(pte_val(pte) & _PAGE_SPECIAL); } 354 static inline int pte_none(pte_t pte) { return (pte_val(pte) & ~_PTE_NONE_MASK) == 0; } 355 static inline bool pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; } 356 357 static inline int pte_present(pte_t pte) 358 { 359 return pte_val(pte) & _PAGE_PRESENT; 360 } 361 362 static inline bool pte_hw_valid(pte_t pte) 363 { 364 return pte_val(pte) & _PAGE_PRESENT; 365 } 366 367 static inline bool pte_hashpte(pte_t pte) 368 { 369 return !!(pte_val(pte) & _PAGE_HASHPTE); 370 } 371 372 static inline bool pte_ci(pte_t pte) 373 { 374 return !!(pte_val(pte) & _PAGE_NO_CACHE); 375 } 376 377 /* 378 * We only find page table entry in the last level 379 * Hence no need for other accessors 380 */ 381 #define pte_access_permitted pte_access_permitted 382 static inline bool pte_access_permitted(pte_t pte, bool write) 383 { 384 /* 385 * A read-only access is controlled by _PAGE_USER bit. 386 * We have _PAGE_READ set for WRITE and EXECUTE 387 */ 388 if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte)) 389 return false; 390 391 if (write && !pte_write(pte)) 392 return false; 393 394 return true; 395 } 396 397 /* Conversion functions: convert a page and protection to a page entry, 398 * and a page entry and page directory to the page they refer to. 399 * 400 * Even if PTEs can be unsigned long long, a PFN is always an unsigned 401 * long for now. 402 */ 403 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 404 { 405 return __pte(((pte_basic_t)(pfn) << PTE_RPN_SHIFT) | 406 pgprot_val(pgprot)); 407 } 408 409 static inline unsigned long pte_pfn(pte_t pte) 410 { 411 return pte_val(pte) >> PTE_RPN_SHIFT; 412 } 413 414 /* Generic modifiers for PTE bits */ 415 static inline pte_t pte_wrprotect(pte_t pte) 416 { 417 return __pte(pte_val(pte) & ~_PAGE_RW); 418 } 419 420 static inline pte_t pte_exprotect(pte_t pte) 421 { 422 return __pte(pte_val(pte) & ~_PAGE_EXEC); 423 } 424 425 static inline pte_t pte_mkclean(pte_t pte) 426 { 427 return __pte(pte_val(pte) & ~_PAGE_DIRTY); 428 } 429 430 static inline pte_t pte_mkold(pte_t pte) 431 { 432 return __pte(pte_val(pte) & ~_PAGE_ACCESSED); 433 } 434 435 static inline pte_t pte_mkexec(pte_t pte) 436 { 437 return __pte(pte_val(pte) | _PAGE_EXEC); 438 } 439 440 static inline pte_t pte_mkpte(pte_t pte) 441 { 442 return pte; 443 } 444 445 static inline pte_t pte_mkwrite(pte_t pte) 446 { 447 return __pte(pte_val(pte) | _PAGE_RW); 448 } 449 450 static inline pte_t pte_mkdirty(pte_t pte) 451 { 452 return __pte(pte_val(pte) | _PAGE_DIRTY); 453 } 454 455 static inline pte_t pte_mkyoung(pte_t pte) 456 { 457 return __pte(pte_val(pte) | _PAGE_ACCESSED); 458 } 459 460 static inline pte_t pte_mkspecial(pte_t pte) 461 { 462 return __pte(pte_val(pte) | _PAGE_SPECIAL); 463 } 464 465 static inline pte_t pte_mkhuge(pte_t pte) 466 { 467 return pte; 468 } 469 470 static inline pte_t pte_mkprivileged(pte_t pte) 471 { 472 return __pte(pte_val(pte) & ~_PAGE_USER); 473 } 474 475 static inline pte_t pte_mkuser(pte_t pte) 476 { 477 return __pte(pte_val(pte) | _PAGE_USER); 478 } 479 480 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 481 { 482 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); 483 } 484 485 486 487 /* This low level function performs the actual PTE insertion 488 * Setting the PTE depends on the MMU type and other factors. It's 489 * an horrible mess that I'm not going to try to clean up now but 490 * I'm keeping it in one place rather than spread around 491 */ 492 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 493 pte_t *ptep, pte_t pte, int percpu) 494 { 495 #if defined(CONFIG_SMP) && !defined(CONFIG_PTE_64BIT) 496 /* First case is 32-bit Hash MMU in SMP mode with 32-bit PTEs. We use the 497 * helper pte_update() which does an atomic update. We need to do that 498 * because a concurrent invalidation can clear _PAGE_HASHPTE. If it's a 499 * per-CPU PTE such as a kmap_atomic, we do a simple update preserving 500 * the hash bits instead (ie, same as the non-SMP case) 501 */ 502 if (percpu) 503 *ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE) 504 | (pte_val(pte) & ~_PAGE_HASHPTE)); 505 else 506 pte_update(mm, addr, ptep, ~_PAGE_HASHPTE, pte_val(pte), 0); 507 508 #elif defined(CONFIG_PTE_64BIT) 509 /* Second case is 32-bit with 64-bit PTE. In this case, we 510 * can just store as long as we do the two halves in the right order 511 * with a barrier in between. This is possible because we take care, 512 * in the hash code, to pre-invalidate if the PTE was already hashed, 513 * which synchronizes us with any concurrent invalidation. 514 * In the percpu case, we also fallback to the simple update preserving 515 * the hash bits 516 */ 517 if (percpu) { 518 *ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE) 519 | (pte_val(pte) & ~_PAGE_HASHPTE)); 520 return; 521 } 522 if (pte_val(*ptep) & _PAGE_HASHPTE) 523 flush_hash_entry(mm, ptep, addr); 524 __asm__ __volatile__("\ 525 stw%U0%X0 %2,%0\n\ 526 eieio\n\ 527 stw%U0%X0 %L2,%1" 528 : "=m" (*ptep), "=m" (*((unsigned char *)ptep+4)) 529 : "r" (pte) : "memory"); 530 531 #else 532 /* Third case is 32-bit hash table in UP mode, we need to preserve 533 * the _PAGE_HASHPTE bit since we may not have invalidated the previous 534 * translation in the hash yet (done in a subsequent flush_tlb_xxx()) 535 * and see we need to keep track that this PTE needs invalidating 536 */ 537 *ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE) 538 | (pte_val(pte) & ~_PAGE_HASHPTE)); 539 #endif 540 } 541 542 /* 543 * Macro to mark a page protection value as "uncacheable". 544 */ 545 546 #define _PAGE_CACHE_CTL (_PAGE_COHERENT | _PAGE_GUARDED | _PAGE_NO_CACHE | \ 547 _PAGE_WRITETHRU) 548 549 #define pgprot_noncached pgprot_noncached 550 static inline pgprot_t pgprot_noncached(pgprot_t prot) 551 { 552 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 553 _PAGE_NO_CACHE | _PAGE_GUARDED); 554 } 555 556 #define pgprot_noncached_wc pgprot_noncached_wc 557 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) 558 { 559 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 560 _PAGE_NO_CACHE); 561 } 562 563 #define pgprot_cached pgprot_cached 564 static inline pgprot_t pgprot_cached(pgprot_t prot) 565 { 566 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 567 _PAGE_COHERENT); 568 } 569 570 #define pgprot_cached_wthru pgprot_cached_wthru 571 static inline pgprot_t pgprot_cached_wthru(pgprot_t prot) 572 { 573 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 574 _PAGE_COHERENT | _PAGE_WRITETHRU); 575 } 576 577 #define pgprot_cached_noncoherent pgprot_cached_noncoherent 578 static inline pgprot_t pgprot_cached_noncoherent(pgprot_t prot) 579 { 580 return __pgprot(pgprot_val(prot) & ~_PAGE_CACHE_CTL); 581 } 582 583 #define pgprot_writecombine pgprot_writecombine 584 static inline pgprot_t pgprot_writecombine(pgprot_t prot) 585 { 586 return pgprot_noncached_wc(prot); 587 } 588 589 #endif /* !__ASSEMBLY__ */ 590 591 #endif /* _ASM_POWERPC_BOOK3S_32_PGTABLE_H */ 592