1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
4 */
5
6#include <dt-bindings/phy/phy.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/clock/g12a-clkc.h>
9#include <dt-bindings/clock/g12a-aoclkc.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
13#include <dt-bindings/thermal/thermal.h>
14
15/ {
16	interrupt-parent = <&gic>;
17	#address-cells = <2>;
18	#size-cells = <2>;
19
20	chosen {
21		#address-cells = <2>;
22		#size-cells = <2>;
23		ranges;
24
25		simplefb_cvbs: framebuffer-cvbs {
26			compatible = "amlogic,simple-framebuffer",
27				     "simple-framebuffer";
28			amlogic,pipeline = "vpu-cvbs";
29			clocks = <&clkc CLKID_HDMI>,
30				 <&clkc CLKID_HTX_PCLK>,
31				 <&clkc CLKID_VPU_INTR>;
32			status = "disabled";
33		};
34
35		simplefb_hdmi: framebuffer-hdmi {
36			compatible = "amlogic,simple-framebuffer",
37				    "simple-framebuffer";
38			amlogic,pipeline = "vpu-hdmi";
39			clocks = <&clkc CLKID_HDMI>,
40				 <&clkc CLKID_HTX_PCLK>,
41				 <&clkc CLKID_VPU_INTR>;
42			status = "disabled";
43		};
44	};
45
46	efuse: efuse {
47		compatible = "amlogic,meson-gxbb-efuse";
48		clocks = <&clkc CLKID_EFUSE>;
49		#address-cells = <1>;
50		#size-cells = <1>;
51		read-only;
52		secure-monitor = <&sm>;
53	};
54
55	psci {
56		compatible = "arm,psci-1.0";
57		method = "smc";
58	};
59
60	reserved-memory {
61		#address-cells = <2>;
62		#size-cells = <2>;
63		ranges;
64
65		/* 3 MiB reserved for ARM Trusted Firmware (BL31) */
66		secmon_reserved: secmon@5000000 {
67			reg = <0x0 0x05000000 0x0 0x300000>;
68			no-map;
69		};
70
71		linux,cma {
72			compatible = "shared-dma-pool";
73			reusable;
74			size = <0x0 0x10000000>;
75			alignment = <0x0 0x400000>;
76			linux,cma-default;
77		};
78	};
79
80	sm: secure-monitor {
81		compatible = "amlogic,meson-gxbb-sm";
82	};
83
84	soc {
85		compatible = "simple-bus";
86		#address-cells = <2>;
87		#size-cells = <2>;
88		ranges;
89
90		pcie: pcie@fc000000 {
91			compatible = "amlogic,g12a-pcie", "snps,dw-pcie";
92			reg = <0x0 0xfc000000 0x0 0x400000
93			       0x0 0xff648000 0x0 0x2000
94			       0x0 0xfc400000 0x0 0x200000>;
95			reg-names = "elbi", "cfg", "config";
96			interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
97			#interrupt-cells = <1>;
98			interrupt-map-mask = <0 0 0 0>;
99			interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
100			bus-range = <0x0 0xff>;
101			#address-cells = <3>;
102			#size-cells = <2>;
103			device_type = "pci";
104			ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000
105				  0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>;
106
107			clocks = <&clkc CLKID_PCIE_PHY
108				  &clkc CLKID_PCIE_COMB
109				  &clkc CLKID_PCIE_PLL>;
110			clock-names = "general",
111				      "pclk",
112				      "port";
113			resets = <&reset RESET_PCIE_CTRL_A>,
114				 <&reset RESET_PCIE_APB>;
115			reset-names = "port",
116				      "apb";
117			num-lanes = <1>;
118			phys = <&usb3_pcie_phy PHY_TYPE_PCIE>;
119			phy-names = "pcie";
120			status = "disabled";
121		};
122
123		thermal-zones {
124			cpu_thermal: cpu-thermal {
125				polling-delay = <1000>;
126				polling-delay-passive = <100>;
127				thermal-sensors = <&cpu_temp>;
128
129				trips {
130					cpu_passive: cpu-passive {
131						temperature = <85000>; /* millicelsius */
132						hysteresis = <2000>; /* millicelsius */
133						type = "passive";
134					};
135
136					cpu_hot: cpu-hot {
137						temperature = <95000>; /* millicelsius */
138						hysteresis = <2000>; /* millicelsius */
139						type = "hot";
140					};
141
142					cpu_critical: cpu-critical {
143						temperature = <110000>; /* millicelsius */
144						hysteresis = <2000>; /* millicelsius */
145						type = "critical";
146					};
147				};
148			};
149
150			ddr_thermal: ddr-thermal {
151				polling-delay = <1000>;
152				polling-delay-passive = <100>;
153				thermal-sensors = <&ddr_temp>;
154
155				trips {
156					ddr_passive: ddr-passive {
157						temperature = <85000>; /* millicelsius */
158						hysteresis = <2000>; /* millicelsius */
159						type = "passive";
160					};
161
162					ddr_critical: ddr-critical {
163						temperature = <110000>; /* millicelsius */
164						hysteresis = <2000>; /* millicelsius */
165						type = "critical";
166					};
167				};
168
169				cooling-maps {
170					map {
171						trip = <&ddr_passive>;
172						cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
173					};
174				};
175			};
176		};
177
178		ethmac: ethernet@ff3f0000 {
179			compatible = "amlogic,meson-axg-dwmac",
180				     "snps,dwmac-3.70a",
181				     "snps,dwmac";
182			reg = <0x0 0xff3f0000 0x0 0x10000>,
183			      <0x0 0xff634540 0x0 0x8>;
184			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
185			interrupt-names = "macirq";
186			clocks = <&clkc CLKID_ETH>,
187				 <&clkc CLKID_FCLK_DIV2>,
188				 <&clkc CLKID_MPLL2>;
189			clock-names = "stmmaceth", "clkin0", "clkin1";
190			rx-fifo-depth = <4096>;
191			tx-fifo-depth = <2048>;
192			status = "disabled";
193
194			mdio0: mdio {
195				#address-cells = <1>;
196				#size-cells = <0>;
197				compatible = "snps,dwmac-mdio";
198			};
199		};
200
201		apb: bus@ff600000 {
202			compatible = "simple-bus";
203			reg = <0x0 0xff600000 0x0 0x200000>;
204			#address-cells = <2>;
205			#size-cells = <2>;
206			ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;
207
208			hdmi_tx: hdmi-tx@0 {
209				compatible = "amlogic,meson-g12a-dw-hdmi";
210				reg = <0x0 0x0 0x0 0x10000>;
211				interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
212				resets = <&reset RESET_HDMITX_CAPB3>,
213					 <&reset RESET_HDMITX_PHY>,
214					 <&reset RESET_HDMITX>;
215				reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
216				clocks = <&clkc CLKID_HDMI>,
217					 <&clkc CLKID_HTX_PCLK>,
218					 <&clkc CLKID_VPU_INTR>;
219				clock-names = "isfr", "iahb", "venci";
220				#address-cells = <1>;
221				#size-cells = <0>;
222				#sound-dai-cells = <0>;
223				status = "disabled";
224
225				/* VPU VENC Input */
226				hdmi_tx_venc_port: port@0 {
227					reg = <0>;
228
229					hdmi_tx_in: endpoint {
230						remote-endpoint = <&hdmi_tx_out>;
231					};
232				};
233
234				/* TMDS Output */
235				hdmi_tx_tmds_port: port@1 {
236					reg = <1>;
237				};
238			};
239
240			apb_efuse: bus@30000 {
241				compatible = "simple-bus";
242				reg = <0x0 0x30000 0x0 0x2000>;
243				#address-cells = <2>;
244				#size-cells = <2>;
245				ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>;
246
247				hwrng: rng@218 {
248					compatible = "amlogic,meson-rng";
249					reg = <0x0 0x218 0x0 0x4>;
250				};
251			};
252
253			acodec: audio-controller@32000 {
254				compatible = "amlogic,t9015";
255				reg = <0x0 0x32000 0x0 0x14>;
256				#sound-dai-cells = <0>;
257				sound-name-prefix = "ACODEC";
258				clocks = <&clkc CLKID_AUDIO_CODEC>;
259				clock-names = "pclk";
260				resets = <&reset RESET_AUDIO_CODEC>;
261				status = "disabled";
262			};
263
264			periphs: bus@34400 {
265				compatible = "simple-bus";
266				reg = <0x0 0x34400 0x0 0x400>;
267				#address-cells = <2>;
268				#size-cells = <2>;
269				ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>;
270
271				periphs_pinctrl: pinctrl@40 {
272					compatible = "amlogic,meson-g12a-periphs-pinctrl";
273					#address-cells = <2>;
274					#size-cells = <2>;
275					ranges;
276
277					gpio: bank@40 {
278						reg = <0x0 0x40  0x0 0x4c>,
279						      <0x0 0xe8  0x0 0x18>,
280						      <0x0 0x120 0x0 0x18>,
281						      <0x0 0x2c0 0x0 0x40>,
282						      <0x0 0x340 0x0 0x1c>;
283						reg-names = "gpio",
284							    "pull",
285							    "pull-enable",
286							    "mux",
287							    "ds";
288						gpio-controller;
289						#gpio-cells = <2>;
290						gpio-ranges = <&periphs_pinctrl 0 0 86>;
291					};
292
293					cec_ao_a_h_pins: cec_ao_a_h {
294						mux {
295							groups = "cec_ao_a_h";
296							function = "cec_ao_a_h";
297							bias-disable;
298						};
299					};
300
301					cec_ao_b_h_pins: cec_ao_b_h {
302						mux {
303							groups = "cec_ao_b_h";
304							function = "cec_ao_b_h";
305							bias-disable;
306						};
307					};
308
309					emmc_ctrl_pins: emmc-ctrl {
310						mux-0 {
311							groups = "emmc_cmd";
312							function = "emmc";
313							bias-pull-up;
314							drive-strength-microamp = <4000>;
315						};
316
317						mux-1 {
318							groups = "emmc_clk";
319							function = "emmc";
320							bias-disable;
321							drive-strength-microamp = <4000>;
322						};
323					};
324
325					emmc_data_4b_pins: emmc-data-4b {
326						mux-0 {
327							groups = "emmc_nand_d0",
328								 "emmc_nand_d1",
329								 "emmc_nand_d2",
330								 "emmc_nand_d3";
331							function = "emmc";
332							bias-pull-up;
333							drive-strength-microamp = <4000>;
334						};
335					};
336
337					emmc_data_8b_pins: emmc-data-8b {
338						mux-0 {
339							groups = "emmc_nand_d0",
340								 "emmc_nand_d1",
341								 "emmc_nand_d2",
342								 "emmc_nand_d3",
343								 "emmc_nand_d4",
344								 "emmc_nand_d5",
345								 "emmc_nand_d6",
346								 "emmc_nand_d7";
347							function = "emmc";
348							bias-pull-up;
349							drive-strength-microamp = <4000>;
350						};
351					};
352
353					emmc_ds_pins: emmc-ds {
354						mux {
355							groups = "emmc_nand_ds";
356							function = "emmc";
357							bias-pull-down;
358							drive-strength-microamp = <4000>;
359						};
360					};
361
362					emmc_clk_gate_pins: emmc_clk_gate {
363						mux {
364							groups = "BOOT_8";
365							function = "gpio_periphs";
366							bias-pull-down;
367							drive-strength-microamp = <4000>;
368						};
369					};
370
371					hdmitx_ddc_pins: hdmitx_ddc {
372						mux {
373							groups = "hdmitx_sda",
374								 "hdmitx_sck";
375							function = "hdmitx";
376							bias-disable;
377							drive-strength-microamp = <4000>;
378						};
379					};
380
381					hdmitx_hpd_pins: hdmitx_hpd {
382						mux {
383							groups = "hdmitx_hpd_in";
384							function = "hdmitx";
385							bias-disable;
386						};
387					};
388
389
390					i2c0_sda_c_pins: i2c0-sda-c {
391						mux {
392							groups = "i2c0_sda_c";
393							function = "i2c0";
394							bias-disable;
395							drive-strength-microamp = <3000>;
396
397						};
398					};
399
400					i2c0_sck_c_pins: i2c0-sck-c {
401						mux {
402							groups = "i2c0_sck_c";
403							function = "i2c0";
404							bias-disable;
405							drive-strength-microamp = <3000>;
406						};
407					};
408
409					i2c0_sda_z0_pins: i2c0-sda-z0 {
410						mux {
411							groups = "i2c0_sda_z0";
412							function = "i2c0";
413							bias-disable;
414							drive-strength-microamp = <3000>;
415						};
416					};
417
418					i2c0_sck_z1_pins: i2c0-sck-z1 {
419						mux {
420							groups = "i2c0_sck_z1";
421							function = "i2c0";
422							bias-disable;
423							drive-strength-microamp = <3000>;
424						};
425					};
426
427					i2c0_sda_z7_pins: i2c0-sda-z7 {
428						mux {
429							groups = "i2c0_sda_z7";
430							function = "i2c0";
431							bias-disable;
432							drive-strength-microamp = <3000>;
433						};
434					};
435
436					i2c0_sda_z8_pins: i2c0-sda-z8 {
437						mux {
438							groups = "i2c0_sda_z8";
439							function = "i2c0";
440							bias-disable;
441							drive-strength-microamp = <3000>;
442						};
443					};
444
445					i2c1_sda_x_pins: i2c1-sda-x {
446						mux {
447							groups = "i2c1_sda_x";
448							function = "i2c1";
449							bias-disable;
450							drive-strength-microamp = <3000>;
451						};
452					};
453
454					i2c1_sck_x_pins: i2c1-sck-x {
455						mux {
456							groups = "i2c1_sck_x";
457							function = "i2c1";
458							bias-disable;
459							drive-strength-microamp = <3000>;
460						};
461					};
462
463					i2c1_sda_h2_pins: i2c1-sda-h2 {
464						mux {
465							groups = "i2c1_sda_h2";
466							function = "i2c1";
467							bias-disable;
468							drive-strength-microamp = <3000>;
469						};
470					};
471
472					i2c1_sck_h3_pins: i2c1-sck-h3 {
473						mux {
474							groups = "i2c1_sck_h3";
475							function = "i2c1";
476							bias-disable;
477							drive-strength-microamp = <3000>;
478						};
479					};
480
481					i2c1_sda_h6_pins: i2c1-sda-h6 {
482						mux {
483							groups = "i2c1_sda_h6";
484							function = "i2c1";
485							bias-disable;
486							drive-strength-microamp = <3000>;
487						};
488					};
489
490					i2c1_sck_h7_pins: i2c1-sck-h7 {
491						mux {
492							groups = "i2c1_sck_h7";
493							function = "i2c1";
494							bias-disable;
495							drive-strength-microamp = <3000>;
496						};
497					};
498
499					i2c2_sda_x_pins: i2c2-sda-x {
500						mux {
501							groups = "i2c2_sda_x";
502							function = "i2c2";
503							bias-disable;
504							drive-strength-microamp = <3000>;
505						};
506					};
507
508					i2c2_sck_x_pins: i2c2-sck-x {
509						mux {
510							groups = "i2c2_sck_x";
511							function = "i2c2";
512							bias-disable;
513							drive-strength-microamp = <3000>;
514						};
515					};
516
517					i2c2_sda_z_pins: i2c2-sda-z {
518						mux {
519							groups = "i2c2_sda_z";
520							function = "i2c2";
521							bias-disable;
522							drive-strength-microamp = <3000>;
523						};
524					};
525
526					i2c2_sck_z_pins: i2c2-sck-z {
527						mux {
528							groups = "i2c2_sck_z";
529							function = "i2c2";
530							bias-disable;
531							drive-strength-microamp = <3000>;
532						};
533					};
534
535					i2c3_sda_h_pins: i2c3-sda-h {
536						mux {
537							groups = "i2c3_sda_h";
538							function = "i2c3";
539							bias-disable;
540							drive-strength-microamp = <3000>;
541						};
542					};
543
544					i2c3_sck_h_pins: i2c3-sck-h {
545						mux {
546							groups = "i2c3_sck_h";
547							function = "i2c3";
548							bias-disable;
549							drive-strength-microamp = <3000>;
550						};
551					};
552
553					i2c3_sda_a_pins: i2c3-sda-a {
554						mux {
555							groups = "i2c3_sda_a";
556							function = "i2c3";
557							bias-disable;
558							drive-strength-microamp = <3000>;
559						};
560					};
561
562					i2c3_sck_a_pins: i2c3-sck-a {
563						mux {
564							groups = "i2c3_sck_a";
565							function = "i2c3";
566							bias-disable;
567							drive-strength-microamp = <3000>;
568						};
569					};
570
571					mclk0_a_pins: mclk0-a {
572						mux {
573							groups = "mclk0_a";
574							function = "mclk0";
575							bias-disable;
576							drive-strength-microamp = <3000>;
577						};
578					};
579
580					mclk1_a_pins: mclk1-a {
581						mux {
582							groups = "mclk1_a";
583							function = "mclk1";
584							bias-disable;
585							drive-strength-microamp = <3000>;
586						};
587					};
588
589					mclk1_x_pins: mclk1-x {
590						mux {
591							groups = "mclk1_x";
592							function = "mclk1";
593							bias-disable;
594							drive-strength-microamp = <3000>;
595						};
596					};
597
598					mclk1_z_pins: mclk1-z {
599						mux {
600							groups = "mclk1_z";
601							function = "mclk1";
602							bias-disable;
603							drive-strength-microamp = <3000>;
604						};
605					};
606
607					nor_pins: nor {
608						mux {
609							groups = "nor_d",
610							       "nor_q",
611							       "nor_c",
612							       "nor_cs";
613							function = "nor";
614							bias-disable;
615						};
616					};
617
618					pdm_din0_a_pins: pdm-din0-a {
619						mux {
620							groups = "pdm_din0_a";
621							function = "pdm";
622							bias-disable;
623						};
624					};
625
626					pdm_din0_c_pins: pdm-din0-c {
627						mux {
628							groups = "pdm_din0_c";
629							function = "pdm";
630							bias-disable;
631						};
632					};
633
634					pdm_din0_x_pins: pdm-din0-x {
635						mux {
636							groups = "pdm_din0_x";
637							function = "pdm";
638							bias-disable;
639						};
640					};
641
642					pdm_din0_z_pins: pdm-din0-z {
643						mux {
644							groups = "pdm_din0_z";
645							function = "pdm";
646							bias-disable;
647						};
648					};
649
650					pdm_din1_a_pins: pdm-din1-a {
651						mux {
652							groups = "pdm_din1_a";
653							function = "pdm";
654							bias-disable;
655						};
656					};
657
658					pdm_din1_c_pins: pdm-din1-c {
659						mux {
660							groups = "pdm_din1_c";
661							function = "pdm";
662							bias-disable;
663						};
664					};
665
666					pdm_din1_x_pins: pdm-din1-x {
667						mux {
668							groups = "pdm_din1_x";
669							function = "pdm";
670							bias-disable;
671						};
672					};
673
674					pdm_din1_z_pins: pdm-din1-z {
675						mux {
676							groups = "pdm_din1_z";
677							function = "pdm";
678							bias-disable;
679						};
680					};
681
682					pdm_din2_a_pins: pdm-din2-a {
683						mux {
684							groups = "pdm_din2_a";
685							function = "pdm";
686							bias-disable;
687						};
688					};
689
690					pdm_din2_c_pins: pdm-din2-c {
691						mux {
692							groups = "pdm_din2_c";
693							function = "pdm";
694							bias-disable;
695						};
696					};
697
698					pdm_din2_x_pins: pdm-din2-x {
699						mux {
700							groups = "pdm_din2_x";
701							function = "pdm";
702							bias-disable;
703						};
704					};
705
706					pdm_din2_z_pins: pdm-din2-z {
707						mux {
708							groups = "pdm_din2_z";
709							function = "pdm";
710							bias-disable;
711						};
712					};
713
714					pdm_din3_a_pins: pdm-din3-a {
715						mux {
716							groups = "pdm_din3_a";
717							function = "pdm";
718							bias-disable;
719						};
720					};
721
722					pdm_din3_c_pins: pdm-din3-c {
723						mux {
724							groups = "pdm_din3_c";
725							function = "pdm";
726							bias-disable;
727						};
728					};
729
730					pdm_din3_x_pins: pdm-din3-x {
731						mux {
732							groups = "pdm_din3_x";
733							function = "pdm";
734							bias-disable;
735						};
736					};
737
738					pdm_din3_z_pins: pdm-din3-z {
739						mux {
740							groups = "pdm_din3_z";
741							function = "pdm";
742							bias-disable;
743						};
744					};
745
746					pdm_dclk_a_pins: pdm-dclk-a {
747						mux {
748							groups = "pdm_dclk_a";
749							function = "pdm";
750							bias-disable;
751							drive-strength-microamp = <500>;
752						};
753					};
754
755					pdm_dclk_c_pins: pdm-dclk-c {
756						mux {
757							groups = "pdm_dclk_c";
758							function = "pdm";
759							bias-disable;
760							drive-strength-microamp = <500>;
761						};
762					};
763
764					pdm_dclk_x_pins: pdm-dclk-x {
765						mux {
766							groups = "pdm_dclk_x";
767							function = "pdm";
768							bias-disable;
769							drive-strength-microamp = <500>;
770						};
771					};
772
773					pdm_dclk_z_pins: pdm-dclk-z {
774						mux {
775							groups = "pdm_dclk_z";
776							function = "pdm";
777							bias-disable;
778							drive-strength-microamp = <500>;
779						};
780					};
781
782					pwm_a_pins: pwm-a {
783						mux {
784							groups = "pwm_a";
785							function = "pwm_a";
786							bias-disable;
787						};
788					};
789
790					pwm_b_x7_pins: pwm-b-x7 {
791						mux {
792							groups = "pwm_b_x7";
793							function = "pwm_b";
794							bias-disable;
795						};
796					};
797
798					pwm_b_x19_pins: pwm-b-x19 {
799						mux {
800							groups = "pwm_b_x19";
801							function = "pwm_b";
802							bias-disable;
803						};
804					};
805
806					pwm_c_c_pins: pwm-c-c {
807						mux {
808							groups = "pwm_c_c";
809							function = "pwm_c";
810							bias-disable;
811						};
812					};
813
814					pwm_c_x5_pins: pwm-c-x5 {
815						mux {
816							groups = "pwm_c_x5";
817							function = "pwm_c";
818							bias-disable;
819						};
820					};
821
822					pwm_c_x8_pins: pwm-c-x8 {
823						mux {
824							groups = "pwm_c_x8";
825							function = "pwm_c";
826							bias-disable;
827						};
828					};
829
830					pwm_d_x3_pins: pwm-d-x3 {
831						mux {
832							groups = "pwm_d_x3";
833							function = "pwm_d";
834							bias-disable;
835						};
836					};
837
838					pwm_d_x6_pins: pwm-d-x6 {
839						mux {
840							groups = "pwm_d_x6";
841							function = "pwm_d";
842							bias-disable;
843						};
844					};
845
846					pwm_e_pins: pwm-e {
847						mux {
848							groups = "pwm_e";
849							function = "pwm_e";
850							bias-disable;
851						};
852					};
853
854					pwm_f_x_pins: pwm-f-x {
855						mux {
856							groups = "pwm_f_x";
857							function = "pwm_f";
858							bias-disable;
859						};
860					};
861
862					pwm_f_h_pins: pwm-f-h {
863						mux {
864							groups = "pwm_f_h";
865							function = "pwm_f";
866							bias-disable;
867						};
868					};
869
870					sdcard_c_pins: sdcard_c {
871						mux-0 {
872							groups = "sdcard_d0_c",
873								 "sdcard_d1_c",
874								 "sdcard_d2_c",
875								 "sdcard_d3_c",
876								 "sdcard_cmd_c";
877							function = "sdcard";
878							bias-pull-up;
879							drive-strength-microamp = <4000>;
880						};
881
882						mux-1 {
883							groups = "sdcard_clk_c";
884							function = "sdcard";
885							bias-disable;
886							drive-strength-microamp = <4000>;
887						};
888					};
889
890					sdcard_clk_gate_c_pins: sdcard_clk_gate_c {
891						mux {
892							groups = "GPIOC_4";
893							function = "gpio_periphs";
894							bias-pull-down;
895							drive-strength-microamp = <4000>;
896						};
897					};
898
899					sdcard_z_pins: sdcard_z {
900						mux-0 {
901							groups = "sdcard_d0_z",
902								 "sdcard_d1_z",
903								 "sdcard_d2_z",
904								 "sdcard_d3_z",
905								 "sdcard_cmd_z";
906							function = "sdcard";
907							bias-pull-up;
908							drive-strength-microamp = <4000>;
909						};
910
911						mux-1 {
912							groups = "sdcard_clk_z";
913							function = "sdcard";
914							bias-disable;
915							drive-strength-microamp = <4000>;
916						};
917					};
918
919					sdcard_clk_gate_z_pins: sdcard_clk_gate_z {
920						mux {
921							groups = "GPIOZ_6";
922							function = "gpio_periphs";
923							bias-pull-down;
924							drive-strength-microamp = <4000>;
925						};
926					};
927
928					sdio_pins: sdio {
929						mux {
930							groups = "sdio_d0",
931								 "sdio_d1",
932								 "sdio_d2",
933								 "sdio_d3",
934								 "sdio_clk",
935								 "sdio_cmd";
936							function = "sdio";
937							bias-disable;
938							drive-strength-microamp = <4000>;
939						};
940					};
941
942					sdio_clk_gate_pins: sdio_clk_gate {
943						mux {
944							groups = "GPIOX_4";
945							function = "gpio_periphs";
946							bias-pull-down;
947							drive-strength-microamp = <4000>;
948						};
949					};
950
951					spdif_in_a10_pins: spdif-in-a10 {
952						mux {
953							groups = "spdif_in_a10";
954							function = "spdif_in";
955							bias-disable;
956						};
957					};
958
959					spdif_in_a12_pins: spdif-in-a12 {
960						mux {
961							groups = "spdif_in_a12";
962							function = "spdif_in";
963							bias-disable;
964						};
965					};
966
967					spdif_in_h_pins: spdif-in-h {
968						mux {
969							groups = "spdif_in_h";
970							function = "spdif_in";
971							bias-disable;
972						};
973					};
974
975					spdif_out_h_pins: spdif-out-h {
976						mux {
977							groups = "spdif_out_h";
978							function = "spdif_out";
979							drive-strength-microamp = <500>;
980							bias-disable;
981						};
982					};
983
984					spdif_out_a11_pins: spdif-out-a11 {
985						mux {
986							groups = "spdif_out_a11";
987							function = "spdif_out";
988							drive-strength-microamp = <500>;
989							bias-disable;
990						};
991					};
992
993					spdif_out_a13_pins: spdif-out-a13 {
994						mux {
995							groups = "spdif_out_a13";
996							function = "spdif_out";
997							drive-strength-microamp = <500>;
998							bias-disable;
999						};
1000					};
1001
1002					spicc0_x_pins: spicc0-x {
1003						mux {
1004							groups = "spi0_mosi_x",
1005							       "spi0_miso_x",
1006							       "spi0_clk_x";
1007							function = "spi0";
1008							drive-strength-microamp = <4000>;
1009							bias-disable;
1010						};
1011					};
1012
1013					spicc0_ss0_x_pins: spicc0-ss0-x {
1014						mux {
1015							groups = "spi0_ss0_x";
1016							function = "spi0";
1017							drive-strength-microamp = <4000>;
1018							bias-disable;
1019						};
1020					};
1021
1022					spicc0_c_pins: spicc0-c {
1023						mux {
1024							groups = "spi0_mosi_c",
1025							       "spi0_miso_c",
1026							       "spi0_ss0_c",
1027							       "spi0_clk_c";
1028							function = "spi0";
1029							drive-strength-microamp = <4000>;
1030							bias-disable;
1031						};
1032					};
1033
1034					spicc1_pins: spicc1 {
1035						mux {
1036							groups = "spi1_mosi",
1037							       "spi1_miso",
1038							       "spi1_clk";
1039							function = "spi1";
1040							drive-strength-microamp = <4000>;
1041						};
1042					};
1043
1044					spicc1_ss0_pins: spicc1-ss0 {
1045						mux {
1046							groups = "spi1_ss0";
1047							function = "spi1";
1048							drive-strength-microamp = <4000>;
1049							bias-disable;
1050						};
1051					};
1052
1053					tdm_a_din0_pins: tdm-a-din0 {
1054						mux {
1055							groups = "tdm_a_din0";
1056							function = "tdm_a";
1057							bias-disable;
1058						};
1059					};
1060
1061
1062					tdm_a_din1_pins: tdm-a-din1 {
1063						mux {
1064							groups = "tdm_a_din1";
1065							function = "tdm_a";
1066							bias-disable;
1067						};
1068					};
1069
1070					tdm_a_dout0_pins: tdm-a-dout0 {
1071						mux {
1072							groups = "tdm_a_dout0";
1073							function = "tdm_a";
1074							bias-disable;
1075							drive-strength-microamp = <3000>;
1076						};
1077					};
1078
1079					tdm_a_dout1_pins: tdm-a-dout1 {
1080						mux {
1081							groups = "tdm_a_dout1";
1082							function = "tdm_a";
1083							bias-disable;
1084							drive-strength-microamp = <3000>;
1085						};
1086					};
1087
1088					tdm_a_fs_pins: tdm-a-fs {
1089						mux {
1090							groups = "tdm_a_fs";
1091							function = "tdm_a";
1092							bias-disable;
1093							drive-strength-microamp = <3000>;
1094						};
1095					};
1096
1097					tdm_a_sclk_pins: tdm-a-sclk {
1098						mux {
1099							groups = "tdm_a_sclk";
1100							function = "tdm_a";
1101							bias-disable;
1102							drive-strength-microamp = <3000>;
1103						};
1104					};
1105
1106					tdm_a_slv_fs_pins: tdm-a-slv-fs {
1107						mux {
1108							groups = "tdm_a_slv_fs";
1109							function = "tdm_a";
1110							bias-disable;
1111						};
1112					};
1113
1114
1115					tdm_a_slv_sclk_pins: tdm-a-slv-sclk {
1116						mux {
1117							groups = "tdm_a_slv_sclk";
1118							function = "tdm_a";
1119							bias-disable;
1120						};
1121					};
1122
1123					tdm_b_din0_pins: tdm-b-din0 {
1124						mux {
1125							groups = "tdm_b_din0";
1126							function = "tdm_b";
1127							bias-disable;
1128						};
1129					};
1130
1131					tdm_b_din1_pins: tdm-b-din1 {
1132						mux {
1133							groups = "tdm_b_din1";
1134							function = "tdm_b";
1135							bias-disable;
1136						};
1137					};
1138
1139					tdm_b_din2_pins: tdm-b-din2 {
1140						mux {
1141							groups = "tdm_b_din2";
1142							function = "tdm_b";
1143							bias-disable;
1144						};
1145					};
1146
1147					tdm_b_din3_a_pins: tdm-b-din3-a {
1148						mux {
1149							groups = "tdm_b_din3_a";
1150							function = "tdm_b";
1151							bias-disable;
1152						};
1153					};
1154
1155					tdm_b_din3_h_pins: tdm-b-din3-h {
1156						mux {
1157							groups = "tdm_b_din3_h";
1158							function = "tdm_b";
1159							bias-disable;
1160						};
1161					};
1162
1163					tdm_b_dout0_pins: tdm-b-dout0 {
1164						mux {
1165							groups = "tdm_b_dout0";
1166							function = "tdm_b";
1167							bias-disable;
1168							drive-strength-microamp = <3000>;
1169						};
1170					};
1171
1172					tdm_b_dout1_pins: tdm-b-dout1 {
1173						mux {
1174							groups = "tdm_b_dout1";
1175							function = "tdm_b";
1176							bias-disable;
1177							drive-strength-microamp = <3000>;
1178						};
1179					};
1180
1181					tdm_b_dout2_pins: tdm-b-dout2 {
1182						mux {
1183							groups = "tdm_b_dout2";
1184							function = "tdm_b";
1185							bias-disable;
1186							drive-strength-microamp = <3000>;
1187						};
1188					};
1189
1190					tdm_b_dout3_a_pins: tdm-b-dout3-a {
1191						mux {
1192							groups = "tdm_b_dout3_a";
1193							function = "tdm_b";
1194							bias-disable;
1195							drive-strength-microamp = <3000>;
1196						};
1197					};
1198
1199					tdm_b_dout3_h_pins: tdm-b-dout3-h {
1200						mux {
1201							groups = "tdm_b_dout3_h";
1202							function = "tdm_b";
1203							bias-disable;
1204							drive-strength-microamp = <3000>;
1205						};
1206					};
1207
1208					tdm_b_fs_pins: tdm-b-fs {
1209						mux {
1210							groups = "tdm_b_fs";
1211							function = "tdm_b";
1212							bias-disable;
1213							drive-strength-microamp = <3000>;
1214						};
1215					};
1216
1217					tdm_b_sclk_pins: tdm-b-sclk {
1218						mux {
1219							groups = "tdm_b_sclk";
1220							function = "tdm_b";
1221							bias-disable;
1222							drive-strength-microamp = <3000>;
1223						};
1224					};
1225
1226					tdm_b_slv_fs_pins: tdm-b-slv-fs {
1227						mux {
1228							groups = "tdm_b_slv_fs";
1229							function = "tdm_b";
1230							bias-disable;
1231						};
1232					};
1233
1234					tdm_b_slv_sclk_pins: tdm-b-slv-sclk {
1235						mux {
1236							groups = "tdm_b_slv_sclk";
1237							function = "tdm_b";
1238							bias-disable;
1239						};
1240					};
1241
1242					tdm_c_din0_a_pins: tdm-c-din0-a {
1243						mux {
1244							groups = "tdm_c_din0_a";
1245							function = "tdm_c";
1246							bias-disable;
1247						};
1248					};
1249
1250					tdm_c_din0_z_pins: tdm-c-din0-z {
1251						mux {
1252							groups = "tdm_c_din0_z";
1253							function = "tdm_c";
1254							bias-disable;
1255						};
1256					};
1257
1258					tdm_c_din1_a_pins: tdm-c-din1-a {
1259						mux {
1260							groups = "tdm_c_din1_a";
1261							function = "tdm_c";
1262							bias-disable;
1263						};
1264					};
1265
1266					tdm_c_din1_z_pins: tdm-c-din1-z {
1267						mux {
1268							groups = "tdm_c_din1_z";
1269							function = "tdm_c";
1270							bias-disable;
1271						};
1272					};
1273
1274					tdm_c_din2_a_pins: tdm-c-din2-a {
1275						mux {
1276							groups = "tdm_c_din2_a";
1277							function = "tdm_c";
1278							bias-disable;
1279						};
1280					};
1281
1282					eth_leds_pins: eth-leds {
1283						mux {
1284							groups = "eth_link_led",
1285								 "eth_act_led";
1286							function = "eth";
1287							bias-disable;
1288						};
1289					};
1290
1291					eth_pins: eth {
1292						mux {
1293							groups = "eth_mdio",
1294								 "eth_mdc",
1295								 "eth_rgmii_rx_clk",
1296								 "eth_rx_dv",
1297								 "eth_rxd0",
1298								 "eth_rxd1",
1299								 "eth_txen",
1300								 "eth_txd0",
1301								 "eth_txd1";
1302							function = "eth";
1303							drive-strength-microamp = <4000>;
1304							bias-disable;
1305						};
1306					};
1307
1308					eth_rgmii_pins: eth-rgmii {
1309						mux {
1310							groups = "eth_rxd2_rgmii",
1311								 "eth_rxd3_rgmii",
1312								 "eth_rgmii_tx_clk",
1313								 "eth_txd2_rgmii",
1314								 "eth_txd3_rgmii";
1315							function = "eth";
1316							drive-strength-microamp = <4000>;
1317							bias-disable;
1318						};
1319					};
1320
1321					tdm_c_din2_z_pins: tdm-c-din2-z {
1322						mux {
1323							groups = "tdm_c_din2_z";
1324							function = "tdm_c";
1325							bias-disable;
1326						};
1327					};
1328
1329					tdm_c_din3_a_pins: tdm-c-din3-a {
1330						mux {
1331							groups = "tdm_c_din3_a";
1332							function = "tdm_c";
1333							bias-disable;
1334						};
1335					};
1336
1337					tdm_c_din3_z_pins: tdm-c-din3-z {
1338						mux {
1339							groups = "tdm_c_din3_z";
1340							function = "tdm_c";
1341							bias-disable;
1342						};
1343					};
1344
1345					tdm_c_dout0_a_pins: tdm-c-dout0-a {
1346						mux {
1347							groups = "tdm_c_dout0_a";
1348							function = "tdm_c";
1349							bias-disable;
1350							drive-strength-microamp = <3000>;
1351						};
1352					};
1353
1354					tdm_c_dout0_z_pins: tdm-c-dout0-z {
1355						mux {
1356							groups = "tdm_c_dout0_z";
1357							function = "tdm_c";
1358							bias-disable;
1359							drive-strength-microamp = <3000>;
1360						};
1361					};
1362
1363					tdm_c_dout1_a_pins: tdm-c-dout1-a {
1364						mux {
1365							groups = "tdm_c_dout1_a";
1366							function = "tdm_c";
1367							bias-disable;
1368							drive-strength-microamp = <3000>;
1369						};
1370					};
1371
1372					tdm_c_dout1_z_pins: tdm-c-dout1-z {
1373						mux {
1374							groups = "tdm_c_dout1_z";
1375							function = "tdm_c";
1376							bias-disable;
1377							drive-strength-microamp = <3000>;
1378						};
1379					};
1380
1381					tdm_c_dout2_a_pins: tdm-c-dout2-a {
1382						mux {
1383							groups = "tdm_c_dout2_a";
1384							function = "tdm_c";
1385							bias-disable;
1386							drive-strength-microamp = <3000>;
1387						};
1388					};
1389
1390					tdm_c_dout2_z_pins: tdm-c-dout2-z {
1391						mux {
1392							groups = "tdm_c_dout2_z";
1393							function = "tdm_c";
1394							bias-disable;
1395							drive-strength-microamp = <3000>;
1396						};
1397					};
1398
1399					tdm_c_dout3_a_pins: tdm-c-dout3-a {
1400						mux {
1401							groups = "tdm_c_dout3_a";
1402							function = "tdm_c";
1403							bias-disable;
1404							drive-strength-microamp = <3000>;
1405						};
1406					};
1407
1408					tdm_c_dout3_z_pins: tdm-c-dout3-z {
1409						mux {
1410							groups = "tdm_c_dout3_z";
1411							function = "tdm_c";
1412							bias-disable;
1413							drive-strength-microamp = <3000>;
1414						};
1415					};
1416
1417					tdm_c_fs_a_pins: tdm-c-fs-a {
1418						mux {
1419							groups = "tdm_c_fs_a";
1420							function = "tdm_c";
1421							bias-disable;
1422							drive-strength-microamp = <3000>;
1423						};
1424					};
1425
1426					tdm_c_fs_z_pins: tdm-c-fs-z {
1427						mux {
1428							groups = "tdm_c_fs_z";
1429							function = "tdm_c";
1430							bias-disable;
1431							drive-strength-microamp = <3000>;
1432						};
1433					};
1434
1435					tdm_c_sclk_a_pins: tdm-c-sclk-a {
1436						mux {
1437							groups = "tdm_c_sclk_a";
1438							function = "tdm_c";
1439							bias-disable;
1440							drive-strength-microamp = <3000>;
1441						};
1442					};
1443
1444					tdm_c_sclk_z_pins: tdm-c-sclk-z {
1445						mux {
1446							groups = "tdm_c_sclk_z";
1447							function = "tdm_c";
1448							bias-disable;
1449							drive-strength-microamp = <3000>;
1450						};
1451					};
1452
1453					tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a {
1454						mux {
1455							groups = "tdm_c_slv_fs_a";
1456							function = "tdm_c";
1457							bias-disable;
1458						};
1459					};
1460
1461					tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z {
1462						mux {
1463							groups = "tdm_c_slv_fs_z";
1464							function = "tdm_c";
1465							bias-disable;
1466						};
1467					};
1468
1469					tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a {
1470						mux {
1471							groups = "tdm_c_slv_sclk_a";
1472							function = "tdm_c";
1473							bias-disable;
1474						};
1475					};
1476
1477					tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z {
1478						mux {
1479							groups = "tdm_c_slv_sclk_z";
1480							function = "tdm_c";
1481							bias-disable;
1482						};
1483					};
1484
1485					uart_a_pins: uart-a {
1486						mux {
1487							groups = "uart_a_tx",
1488								 "uart_a_rx";
1489							function = "uart_a";
1490							bias-disable;
1491						};
1492					};
1493
1494					uart_a_cts_rts_pins: uart-a-cts-rts {
1495						mux {
1496							groups = "uart_a_cts",
1497								 "uart_a_rts";
1498							function = "uart_a";
1499							bias-disable;
1500						};
1501					};
1502
1503					uart_b_pins: uart-b {
1504						mux {
1505							groups = "uart_b_tx",
1506								 "uart_b_rx";
1507							function = "uart_b";
1508							bias-disable;
1509						};
1510					};
1511
1512					uart_c_pins: uart-c {
1513						mux {
1514							groups = "uart_c_tx",
1515								 "uart_c_rx";
1516							function = "uart_c";
1517							bias-disable;
1518						};
1519					};
1520
1521					uart_c_cts_rts_pins: uart-c-cts-rts {
1522						mux {
1523							groups = "uart_c_cts",
1524								 "uart_c_rts";
1525							function = "uart_c";
1526							bias-disable;
1527						};
1528					};
1529				};
1530			};
1531
1532			cpu_temp: temperature-sensor@34800 {
1533				compatible = "amlogic,g12a-cpu-thermal",
1534					     "amlogic,g12a-thermal";
1535				reg = <0x0 0x34800 0x0 0x50>;
1536				interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>;
1537				clocks = <&clkc CLKID_TS>;
1538				#thermal-sensor-cells = <0>;
1539				amlogic,ao-secure = <&sec_AO>;
1540			};
1541
1542			ddr_temp: temperature-sensor@34c00 {
1543				compatible = "amlogic,g12a-ddr-thermal",
1544					     "amlogic,g12a-thermal";
1545				reg = <0x0 0x34c00 0x0 0x50>;
1546				interrupts = <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>;
1547				clocks = <&clkc CLKID_TS>;
1548				#thermal-sensor-cells = <0>;
1549				amlogic,ao-secure = <&sec_AO>;
1550			};
1551
1552			usb2_phy0: phy@36000 {
1553				compatible = "amlogic,g12a-usb2-phy";
1554				reg = <0x0 0x36000 0x0 0x2000>;
1555				clocks = <&xtal>;
1556				clock-names = "xtal";
1557				resets = <&reset RESET_USB_PHY20>;
1558				reset-names = "phy";
1559				#phy-cells = <0>;
1560			};
1561
1562			dmc: bus@38000 {
1563				compatible = "simple-bus";
1564				reg = <0x0 0x38000 0x0 0x400>;
1565				#address-cells = <2>;
1566				#size-cells = <2>;
1567				ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>;
1568
1569				canvas: video-lut@48 {
1570					compatible = "amlogic,canvas";
1571					reg = <0x0 0x48 0x0 0x14>;
1572				};
1573			};
1574
1575			usb2_phy1: phy@3a000 {
1576				compatible = "amlogic,g12a-usb2-phy";
1577				reg = <0x0 0x3a000 0x0 0x2000>;
1578				clocks = <&xtal>;
1579				clock-names = "xtal";
1580				resets = <&reset RESET_USB_PHY21>;
1581				reset-names = "phy";
1582				#phy-cells = <0>;
1583			};
1584
1585			hiu: bus@3c000 {
1586				compatible = "simple-bus";
1587				reg = <0x0 0x3c000 0x0 0x1400>;
1588				#address-cells = <2>;
1589				#size-cells = <2>;
1590				ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>;
1591
1592				hhi: system-controller@0 {
1593					compatible = "amlogic,meson-gx-hhi-sysctrl",
1594						     "simple-mfd", "syscon";
1595					reg = <0 0 0 0x400>;
1596
1597					clkc: clock-controller {
1598						compatible = "amlogic,g12a-clkc";
1599						#clock-cells = <1>;
1600						clocks = <&xtal>;
1601						clock-names = "xtal";
1602					};
1603
1604					pwrc: power-controller {
1605						compatible = "amlogic,meson-g12a-pwrc";
1606						#power-domain-cells = <1>;
1607						amlogic,ao-sysctrl = <&rti>;
1608						resets = <&reset RESET_VIU>,
1609							 <&reset RESET_VENC>,
1610							 <&reset RESET_VCBUS>,
1611							 <&reset RESET_BT656>,
1612							 <&reset RESET_RDMA>,
1613							 <&reset RESET_VENCI>,
1614							 <&reset RESET_VENCP>,
1615							 <&reset RESET_VDAC>,
1616							 <&reset RESET_VDI6>,
1617							 <&reset RESET_VENCL>,
1618							 <&reset RESET_VID_LOCK>;
1619						reset-names = "viu", "venc", "vcbus", "bt656",
1620							      "rdma", "venci", "vencp", "vdac",
1621							      "vdi6", "vencl", "vid_lock";
1622						clocks = <&clkc CLKID_VPU>,
1623							 <&clkc CLKID_VAPB>;
1624						clock-names = "vpu", "vapb";
1625						/*
1626						 * VPU clocking is provided by two identical clock paths
1627						 * VPU_0 and VPU_1 muxed to a single clock by a glitch
1628						 * free mux to safely change frequency while running.
1629						 * Same for VAPB but with a final gate after the glitch free mux.
1630						 */
1631						assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
1632								  <&clkc CLKID_VPU_0>,
1633								  <&clkc CLKID_VPU>, /* Glitch free mux */
1634								  <&clkc CLKID_VAPB_0_SEL>,
1635								  <&clkc CLKID_VAPB_0>,
1636								  <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
1637						assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
1638									 <0>, /* Do Nothing */
1639									 <&clkc CLKID_VPU_0>,
1640									 <&clkc CLKID_FCLK_DIV4>,
1641									 <0>, /* Do Nothing */
1642									 <&clkc CLKID_VAPB_0>;
1643						assigned-clock-rates = <0>, /* Do Nothing */
1644								       <666666666>,
1645								       <0>, /* Do Nothing */
1646								       <0>, /* Do Nothing */
1647								       <250000000>,
1648								       <0>; /* Do Nothing */
1649					};
1650				};
1651			};
1652
1653			usb3_pcie_phy: phy@46000 {
1654				compatible = "amlogic,g12a-usb3-pcie-phy";
1655				reg = <0x0 0x46000 0x0 0x2000>;
1656				clocks = <&clkc CLKID_PCIE_PLL>;
1657				clock-names = "ref_clk";
1658				resets = <&reset RESET_PCIE_PHY>;
1659				reset-names = "phy";
1660				assigned-clocks = <&clkc CLKID_PCIE_PLL>;
1661				assigned-clock-rates = <100000000>;
1662				#phy-cells = <1>;
1663			};
1664
1665			eth_phy: mdio-multiplexer@4c000 {
1666				compatible = "amlogic,g12a-mdio-mux";
1667				reg = <0x0 0x4c000 0x0 0xa4>;
1668				clocks = <&clkc CLKID_ETH_PHY>,
1669					 <&xtal>,
1670					 <&clkc CLKID_MPLL_50M>;
1671				clock-names = "pclk", "clkin0", "clkin1";
1672				mdio-parent-bus = <&mdio0>;
1673				#address-cells = <1>;
1674				#size-cells = <0>;
1675
1676				ext_mdio: mdio@0 {
1677					reg = <0>;
1678					#address-cells = <1>;
1679					#size-cells = <0>;
1680				};
1681
1682				int_mdio: mdio@1 {
1683					reg = <1>;
1684					#address-cells = <1>;
1685					#size-cells = <0>;
1686
1687					internal_ephy: ethernet_phy@8 {
1688						compatible = "ethernet-phy-id0180.3301",
1689							     "ethernet-phy-ieee802.3-c22";
1690						interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1691						reg = <8>;
1692						max-speed = <100>;
1693					};
1694				};
1695			};
1696		};
1697
1698		aobus: bus@ff800000 {
1699			compatible = "simple-bus";
1700			reg = <0x0 0xff800000 0x0 0x100000>;
1701			#address-cells = <2>;
1702			#size-cells = <2>;
1703			ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1704
1705			rti: sys-ctrl@0 {
1706				compatible = "amlogic,meson-gx-ao-sysctrl",
1707					     "simple-mfd", "syscon";
1708				reg = <0x0 0x0 0x0 0x100>;
1709				#address-cells = <2>;
1710				#size-cells = <2>;
1711				ranges = <0x0 0x0 0x0 0x0 0x0 0x100>;
1712
1713				clkc_AO: clock-controller {
1714					compatible = "amlogic,meson-g12a-aoclkc";
1715					#clock-cells = <1>;
1716					#reset-cells = <1>;
1717					clocks = <&xtal>, <&clkc CLKID_CLK81>;
1718					clock-names = "xtal", "mpeg-clk";
1719				};
1720
1721				ao_pinctrl: pinctrl@14 {
1722					compatible = "amlogic,meson-g12a-aobus-pinctrl";
1723					#address-cells = <2>;
1724					#size-cells = <2>;
1725					ranges;
1726
1727					gpio_ao: bank@14 {
1728						reg = <0x0 0x14 0x0 0x8>,
1729						      <0x0 0x1c 0x0 0x8>,
1730						      <0x0 0x24 0x0 0x14>;
1731						reg-names = "mux",
1732							    "ds",
1733							    "gpio";
1734						gpio-controller;
1735						#gpio-cells = <2>;
1736						gpio-ranges = <&ao_pinctrl 0 0 15>;
1737					};
1738
1739					i2c_ao_sck_pins: i2c_ao_sck_pins {
1740						mux {
1741							groups = "i2c_ao_sck";
1742							function = "i2c_ao";
1743							bias-disable;
1744							drive-strength-microamp = <3000>;
1745						};
1746					};
1747
1748					i2c_ao_sda_pins: i2c_ao_sda {
1749						mux {
1750							groups = "i2c_ao_sda";
1751							function = "i2c_ao";
1752							bias-disable;
1753							drive-strength-microamp = <3000>;
1754						};
1755					};
1756
1757					i2c_ao_sck_e_pins: i2c_ao_sck_e {
1758						mux {
1759							groups = "i2c_ao_sck_e";
1760							function = "i2c_ao";
1761							bias-disable;
1762							drive-strength-microamp = <3000>;
1763						};
1764					};
1765
1766					i2c_ao_sda_e_pins: i2c_ao_sda_e {
1767						mux {
1768							groups = "i2c_ao_sda_e";
1769							function = "i2c_ao";
1770							bias-disable;
1771							drive-strength-microamp = <3000>;
1772						};
1773					};
1774
1775					mclk0_ao_pins: mclk0-ao {
1776						mux {
1777							groups = "mclk0_ao";
1778							function = "mclk0_ao";
1779							bias-disable;
1780							drive-strength-microamp = <3000>;
1781						};
1782					};
1783
1784					tdm_ao_b_din0_pins: tdm-ao-b-din0 {
1785						mux {
1786							groups = "tdm_ao_b_din0";
1787							function = "tdm_ao_b";
1788							bias-disable;
1789						};
1790					};
1791
1792					spdif_ao_out_pins: spdif-ao-out {
1793						mux {
1794							groups = "spdif_ao_out";
1795							function = "spdif_ao_out";
1796							drive-strength-microamp = <500>;
1797							bias-disable;
1798						};
1799					};
1800
1801					tdm_ao_b_din1_pins: tdm-ao-b-din1 {
1802						mux {
1803							groups = "tdm_ao_b_din1";
1804							function = "tdm_ao_b";
1805							bias-disable;
1806						};
1807					};
1808
1809					tdm_ao_b_din2_pins: tdm-ao-b-din2 {
1810						mux {
1811							groups = "tdm_ao_b_din2";
1812							function = "tdm_ao_b";
1813							bias-disable;
1814						};
1815					};
1816
1817					tdm_ao_b_dout0_pins: tdm-ao-b-dout0 {
1818						mux {
1819							groups = "tdm_ao_b_dout0";
1820							function = "tdm_ao_b";
1821							bias-disable;
1822							drive-strength-microamp = <3000>;
1823						};
1824					};
1825
1826					tdm_ao_b_dout1_pins: tdm-ao-b-dout1 {
1827						mux {
1828							groups = "tdm_ao_b_dout1";
1829							function = "tdm_ao_b";
1830							bias-disable;
1831							drive-strength-microamp = <3000>;
1832						};
1833					};
1834
1835					tdm_ao_b_dout2_pins: tdm-ao-b-dout2 {
1836						mux {
1837							groups = "tdm_ao_b_dout2";
1838							function = "tdm_ao_b";
1839							bias-disable;
1840							drive-strength-microamp = <3000>;
1841						};
1842					};
1843
1844					tdm_ao_b_fs_pins: tdm-ao-b-fs {
1845						mux {
1846							groups = "tdm_ao_b_fs";
1847							function = "tdm_ao_b";
1848							bias-disable;
1849							drive-strength-microamp = <3000>;
1850						};
1851					};
1852
1853					tdm_ao_b_sclk_pins: tdm-ao-b-sclk {
1854						mux {
1855							groups = "tdm_ao_b_sclk";
1856							function = "tdm_ao_b";
1857							bias-disable;
1858							drive-strength-microamp = <3000>;
1859						};
1860					};
1861
1862					tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs {
1863						mux {
1864							groups = "tdm_ao_b_slv_fs";
1865							function = "tdm_ao_b";
1866							bias-disable;
1867						};
1868					};
1869
1870					tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk {
1871						mux {
1872							groups = "tdm_ao_b_slv_sclk";
1873							function = "tdm_ao_b";
1874							bias-disable;
1875						};
1876					};
1877
1878					uart_ao_a_pins: uart-a-ao {
1879						mux {
1880							groups = "uart_ao_a_tx",
1881								 "uart_ao_a_rx";
1882							function = "uart_ao_a";
1883							bias-disable;
1884						};
1885					};
1886
1887					uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts {
1888						mux {
1889							groups = "uart_ao_a_cts",
1890								 "uart_ao_a_rts";
1891							function = "uart_ao_a";
1892							bias-disable;
1893						};
1894					};
1895
1896					pwm_a_e_pins: pwm-a-e {
1897						mux {
1898							groups = "pwm_a_e";
1899							function = "pwm_a_e";
1900							bias-disable;
1901						};
1902					};
1903
1904					pwm_ao_a_pins: pwm-ao-a {
1905						mux {
1906							groups = "pwm_ao_a";
1907							function = "pwm_ao_a";
1908							bias-disable;
1909						};
1910					};
1911
1912					pwm_ao_b_pins: pwm-ao-b {
1913						mux {
1914							groups = "pwm_ao_b";
1915							function = "pwm_ao_b";
1916							bias-disable;
1917						};
1918					};
1919
1920					pwm_ao_c_4_pins: pwm-ao-c-4 {
1921						mux {
1922							groups = "pwm_ao_c_4";
1923							function = "pwm_ao_c";
1924							bias-disable;
1925						};
1926					};
1927
1928					pwm_ao_c_6_pins: pwm-ao-c-6 {
1929						mux {
1930							groups = "pwm_ao_c_6";
1931							function = "pwm_ao_c";
1932							bias-disable;
1933						};
1934					};
1935
1936					pwm_ao_d_5_pins: pwm-ao-d-5 {
1937						mux {
1938							groups = "pwm_ao_d_5";
1939							function = "pwm_ao_d";
1940							bias-disable;
1941						};
1942					};
1943
1944					pwm_ao_d_10_pins: pwm-ao-d-10 {
1945						mux {
1946							groups = "pwm_ao_d_10";
1947							function = "pwm_ao_d";
1948							bias-disable;
1949						};
1950					};
1951
1952					pwm_ao_d_e_pins: pwm-ao-d-e {
1953						mux {
1954							groups = "pwm_ao_d_e";
1955							function = "pwm_ao_d";
1956						};
1957					};
1958
1959					remote_input_ao_pins: remote-input-ao {
1960						mux {
1961							groups = "remote_ao_input";
1962							function = "remote_ao_input";
1963							bias-disable;
1964						};
1965					};
1966				};
1967			};
1968
1969			vrtc: rtc@0a8 {
1970				compatible = "amlogic,meson-vrtc";
1971				reg = <0x0 0x000a8 0x0 0x4>;
1972			};
1973
1974			cec_AO: cec@100 {
1975				compatible = "amlogic,meson-gx-ao-cec";
1976				reg = <0x0 0x00100 0x0 0x14>;
1977				interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
1978				clocks = <&clkc_AO CLKID_AO_CEC>;
1979				clock-names = "core";
1980				status = "disabled";
1981			};
1982
1983			sec_AO: ao-secure@140 {
1984				compatible = "amlogic,meson-gx-ao-secure", "syscon";
1985				reg = <0x0 0x140 0x0 0x140>;
1986				amlogic,has-chip-id;
1987			};
1988
1989			cecb_AO: cec@280 {
1990				compatible = "amlogic,meson-g12a-ao-cec";
1991				reg = <0x0 0x00280 0x0 0x1c>;
1992				interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
1993				clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>;
1994				clock-names = "oscin";
1995				status = "disabled";
1996			};
1997
1998			pwm_AO_cd: pwm@2000 {
1999				compatible = "amlogic,meson-g12a-ao-pwm-cd";
2000				reg = <0x0 0x2000 0x0 0x20>;
2001				#pwm-cells = <3>;
2002				status = "disabled";
2003			};
2004
2005			uart_AO: serial@3000 {
2006				compatible = "amlogic,meson-gx-uart",
2007					     "amlogic,meson-ao-uart";
2008				reg = <0x0 0x3000 0x0 0x18>;
2009				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
2010				clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>;
2011				clock-names = "xtal", "pclk", "baud";
2012				status = "disabled";
2013			};
2014
2015			uart_AO_B: serial@4000 {
2016				compatible = "amlogic,meson-gx-uart",
2017					     "amlogic,meson-ao-uart";
2018				reg = <0x0 0x4000 0x0 0x18>;
2019				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
2020				clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
2021				clock-names = "xtal", "pclk", "baud";
2022				status = "disabled";
2023			};
2024
2025			i2c_AO: i2c@5000 {
2026				compatible = "amlogic,meson-axg-i2c";
2027				status = "disabled";
2028				reg = <0x0 0x05000 0x0 0x20>;
2029				interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
2030				#address-cells = <1>;
2031				#size-cells = <0>;
2032				clocks = <&clkc CLKID_I2C>;
2033			};
2034
2035			pwm_AO_ab: pwm@7000 {
2036				compatible = "amlogic,meson-g12a-ao-pwm-ab";
2037				reg = <0x0 0x7000 0x0 0x20>;
2038				#pwm-cells = <3>;
2039				status = "disabled";
2040			};
2041
2042			ir: ir@8000 {
2043				compatible = "amlogic,meson-gxbb-ir";
2044				reg = <0x0 0x8000 0x0 0x20>;
2045				interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
2046				status = "disabled";
2047			};
2048
2049			saradc: adc@9000 {
2050				compatible = "amlogic,meson-g12a-saradc",
2051					     "amlogic,meson-saradc";
2052				reg = <0x0 0x9000 0x0 0x48>;
2053				#io-channel-cells = <1>;
2054				interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>;
2055				clocks = <&xtal>,
2056					 <&clkc_AO CLKID_AO_SAR_ADC>,
2057					 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
2058					 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
2059				clock-names = "clkin", "core", "adc_clk", "adc_sel";
2060				status = "disabled";
2061			};
2062		};
2063
2064		vdec: video-decoder@ff620000 {
2065			compatible = "amlogic,g12a-vdec";
2066			reg = <0x0 0xff620000 0x0 0x10000>,
2067			      <0x0 0xffd0e180 0x0 0xe4>;
2068			reg-names = "dos", "esparser";
2069			interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
2070				     <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
2071			interrupt-names = "vdec", "esparser";
2072
2073			amlogic,ao-sysctrl = <&rti>;
2074			amlogic,canvas = <&canvas>;
2075
2076			clocks = <&clkc CLKID_PARSER>,
2077				 <&clkc CLKID_DOS>,
2078				 <&clkc CLKID_VDEC_1>,
2079				 <&clkc CLKID_VDEC_HEVC>,
2080				 <&clkc CLKID_VDEC_HEVCF>;
2081			clock-names = "dos_parser", "dos", "vdec_1",
2082				      "vdec_hevc", "vdec_hevcf";
2083			resets = <&reset RESET_PARSER>;
2084			reset-names = "esparser";
2085		};
2086
2087		vpu: vpu@ff900000 {
2088			compatible = "amlogic,meson-g12a-vpu";
2089			reg = <0x0 0xff900000 0x0 0x100000>,
2090			      <0x0 0xff63c000 0x0 0x1000>;
2091			reg-names = "vpu", "hhi";
2092			interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
2093			#address-cells = <1>;
2094			#size-cells = <0>;
2095			amlogic,canvas = <&canvas>;
2096
2097			/* CVBS VDAC output port */
2098			cvbs_vdac_port: port@0 {
2099				reg = <0>;
2100			};
2101
2102			/* HDMI-TX output port */
2103			hdmi_tx_port: port@1 {
2104				reg = <1>;
2105
2106				hdmi_tx_out: endpoint {
2107					remote-endpoint = <&hdmi_tx_in>;
2108				};
2109			};
2110		};
2111
2112		gic: interrupt-controller@ffc01000 {
2113			compatible = "arm,gic-400";
2114			reg = <0x0 0xffc01000 0 0x1000>,
2115			      <0x0 0xffc02000 0 0x2000>,
2116			      <0x0 0xffc04000 0 0x2000>,
2117			      <0x0 0xffc06000 0 0x2000>;
2118			interrupt-controller;
2119			interrupts = <GIC_PPI 9
2120				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
2121			#interrupt-cells = <3>;
2122			#address-cells = <0>;
2123		};
2124
2125		cbus: bus@ffd00000 {
2126			compatible = "simple-bus";
2127			reg = <0x0 0xffd00000 0x0 0x100000>;
2128			#address-cells = <2>;
2129			#size-cells = <2>;
2130			ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
2131
2132			reset: reset-controller@1004 {
2133				compatible = "amlogic,meson-axg-reset";
2134				reg = <0x0 0x1004 0x0 0x9c>;
2135				#reset-cells = <1>;
2136			};
2137
2138			gpio_intc: interrupt-controller@f080 {
2139				compatible = "amlogic,meson-g12a-gpio-intc",
2140					     "amlogic,meson-gpio-intc";
2141				reg = <0x0 0xf080 0x0 0x10>;
2142				interrupt-controller;
2143				#interrupt-cells = <2>;
2144				amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
2145			};
2146
2147			spicc0: spi@13000 {
2148				compatible = "amlogic,meson-g12a-spicc";
2149				reg = <0x0 0x13000 0x0 0x44>;
2150				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
2151				clocks = <&clkc CLKID_SPICC0>,
2152					 <&clkc CLKID_SPICC0_SCLK>;
2153				clock-names = "core", "pclk";
2154				#address-cells = <1>;
2155				#size-cells = <0>;
2156				status = "disabled";
2157			};
2158
2159			spicc1: spi@15000 {
2160				compatible = "amlogic,meson-g12a-spicc";
2161				reg = <0x0 0x15000 0x0 0x44>;
2162				interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
2163				clocks = <&clkc CLKID_SPICC1>,
2164					 <&clkc CLKID_SPICC1_SCLK>;
2165				clock-names = "core", "pclk";
2166				#address-cells = <1>;
2167				#size-cells = <0>;
2168				status = "disabled";
2169			};
2170
2171			spifc: spi@14000 {
2172				compatible = "amlogic,meson-gxbb-spifc";
2173				status = "disabled";
2174				reg = <0x0 0x14000 0x0 0x80>;
2175				#address-cells = <1>;
2176				#size-cells = <0>;
2177				clocks = <&clkc CLKID_CLK81>;
2178			};
2179
2180			pwm_ef: pwm@19000 {
2181				compatible = "amlogic,meson-g12a-ee-pwm";
2182				reg = <0x0 0x19000 0x0 0x20>;
2183				#pwm-cells = <3>;
2184				status = "disabled";
2185			};
2186
2187			pwm_cd: pwm@1a000 {
2188				compatible = "amlogic,meson-g12a-ee-pwm";
2189				reg = <0x0 0x1a000 0x0 0x20>;
2190				#pwm-cells = <3>;
2191				status = "disabled";
2192			};
2193
2194			pwm_ab: pwm@1b000 {
2195				compatible = "amlogic,meson-g12a-ee-pwm";
2196				reg = <0x0 0x1b000 0x0 0x20>;
2197				#pwm-cells = <3>;
2198				status = "disabled";
2199			};
2200
2201			i2c3: i2c@1c000 {
2202				compatible = "amlogic,meson-axg-i2c";
2203				status = "disabled";
2204				reg = <0x0 0x1c000 0x0 0x20>;
2205				interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
2206				#address-cells = <1>;
2207				#size-cells = <0>;
2208				clocks = <&clkc CLKID_I2C>;
2209			};
2210
2211			i2c2: i2c@1d000 {
2212				compatible = "amlogic,meson-axg-i2c";
2213				status = "disabled";
2214				reg = <0x0 0x1d000 0x0 0x20>;
2215				interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
2216				#address-cells = <1>;
2217				#size-cells = <0>;
2218				clocks = <&clkc CLKID_I2C>;
2219			};
2220
2221			i2c1: i2c@1e000 {
2222				compatible = "amlogic,meson-axg-i2c";
2223				status = "disabled";
2224				reg = <0x0 0x1e000 0x0 0x20>;
2225				interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
2226				#address-cells = <1>;
2227				#size-cells = <0>;
2228				clocks = <&clkc CLKID_I2C>;
2229			};
2230
2231			i2c0: i2c@1f000 {
2232				compatible = "amlogic,meson-axg-i2c";
2233				status = "disabled";
2234				reg = <0x0 0x1f000 0x0 0x20>;
2235				interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
2236				#address-cells = <1>;
2237				#size-cells = <0>;
2238				clocks = <&clkc CLKID_I2C>;
2239			};
2240
2241			clk_msr: clock-measure@18000 {
2242				compatible = "amlogic,meson-g12a-clk-measure";
2243				reg = <0x0 0x18000 0x0 0x10>;
2244			};
2245
2246			uart_C: serial@22000 {
2247				compatible = "amlogic,meson-gx-uart";
2248				reg = <0x0 0x22000 0x0 0x18>;
2249				interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
2250				clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
2251				clock-names = "xtal", "pclk", "baud";
2252				status = "disabled";
2253			};
2254
2255			uart_B: serial@23000 {
2256				compatible = "amlogic,meson-gx-uart";
2257				reg = <0x0 0x23000 0x0 0x18>;
2258				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
2259				clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
2260				clock-names = "xtal", "pclk", "baud";
2261				status = "disabled";
2262			};
2263
2264			uart_A: serial@24000 {
2265				compatible = "amlogic,meson-gx-uart";
2266				reg = <0x0 0x24000 0x0 0x18>;
2267				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
2268				clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
2269				clock-names = "xtal", "pclk", "baud";
2270				status = "disabled";
2271			};
2272		};
2273
2274		sd_emmc_a: sd@ffe03000 {
2275			compatible = "amlogic,meson-axg-mmc";
2276			reg = <0x0 0xffe03000 0x0 0x800>;
2277			interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
2278			status = "disabled";
2279			clocks = <&clkc CLKID_SD_EMMC_A>,
2280				 <&clkc CLKID_SD_EMMC_A_CLK0>,
2281				 <&clkc CLKID_FCLK_DIV2>;
2282			clock-names = "core", "clkin0", "clkin1";
2283			resets = <&reset RESET_SD_EMMC_A>;
2284		};
2285
2286		sd_emmc_b: sd@ffe05000 {
2287			compatible = "amlogic,meson-axg-mmc";
2288			reg = <0x0 0xffe05000 0x0 0x800>;
2289			interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>;
2290			status = "disabled";
2291			clocks = <&clkc CLKID_SD_EMMC_B>,
2292				 <&clkc CLKID_SD_EMMC_B_CLK0>,
2293				 <&clkc CLKID_FCLK_DIV2>;
2294			clock-names = "core", "clkin0", "clkin1";
2295			resets = <&reset RESET_SD_EMMC_B>;
2296		};
2297
2298		sd_emmc_c: mmc@ffe07000 {
2299			compatible = "amlogic,meson-axg-mmc";
2300			reg = <0x0 0xffe07000 0x0 0x800>;
2301			interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>;
2302			status = "disabled";
2303			clocks = <&clkc CLKID_SD_EMMC_C>,
2304				 <&clkc CLKID_SD_EMMC_C_CLK0>,
2305				 <&clkc CLKID_FCLK_DIV2>;
2306			clock-names = "core", "clkin0", "clkin1";
2307			resets = <&reset RESET_SD_EMMC_C>;
2308		};
2309
2310		usb: usb@ffe09000 {
2311			status = "disabled";
2312			compatible = "amlogic,meson-g12a-usb-ctrl";
2313			reg = <0x0 0xffe09000 0x0 0xa0>;
2314			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
2315			#address-cells = <2>;
2316			#size-cells = <2>;
2317			ranges;
2318
2319			clocks = <&clkc CLKID_USB>;
2320			resets = <&reset RESET_USB>;
2321
2322			dr_mode = "otg";
2323
2324			phys = <&usb2_phy0>, <&usb2_phy1>,
2325			       <&usb3_pcie_phy PHY_TYPE_USB3>;
2326			phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";
2327
2328			dwc2: usb@ff400000 {
2329				compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
2330				reg = <0x0 0xff400000 0x0 0x40000>;
2331				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
2332				clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
2333				clock-names = "otg";
2334				phys = <&usb2_phy1>;
2335				phy-names = "usb2-phy";
2336				dr_mode = "peripheral";
2337				g-rx-fifo-size = <192>;
2338				g-np-tx-fifo-size = <128>;
2339				g-tx-fifo-size = <128 128 16 16 16>;
2340			};
2341
2342			dwc3: usb@ff500000 {
2343				compatible = "snps,dwc3";
2344				reg = <0x0 0xff500000 0x0 0x100000>;
2345				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
2346				dr_mode = "host";
2347				snps,dis_u2_susphy_quirk;
2348				snps,quirk-frame-length-adjustment;
2349				snps,parkmode-disable-ss-quirk;
2350			};
2351		};
2352
2353		mali: gpu@ffe40000 {
2354			compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
2355			reg = <0x0 0xffe40000 0x0 0x40000>;
2356			interrupt-parent = <&gic>;
2357			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
2358				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
2359				     <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
2360			interrupt-names = "job", "mmu", "gpu";
2361			clocks = <&clkc CLKID_MALI>;
2362			resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;
2363
2364			/*
2365			 * Mali clocking is provided by two identical clock paths
2366			 * MALI_0 and MALI_1 muxed to a single clock by a glitch
2367			 * free mux to safely change frequency while running.
2368			 */
2369			assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
2370					  <&clkc CLKID_MALI_0>,
2371					  <&clkc CLKID_MALI>; /* Glitch free mux */
2372			assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>,
2373						 <0>, /* Do Nothing */
2374						 <&clkc CLKID_MALI_0>;
2375			assigned-clock-rates = <0>, /* Do Nothing */
2376					       <800000000>,
2377					       <0>; /* Do Nothing */
2378			#cooling-cells = <2>;
2379		};
2380	};
2381
2382	timer {
2383		compatible = "arm,armv8-timer";
2384		interrupts = <GIC_PPI 13
2385			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
2386			     <GIC_PPI 14
2387			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
2388			     <GIC_PPI 11
2389			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
2390			     <GIC_PPI 10
2391			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
2392		arm,no-tick-in-suspend;
2393	};
2394
2395	xtal: xtal-clk {
2396		compatible = "fixed-clock";
2397		clock-frequency = <24000000>;
2398		clock-output-names = "xtal";
2399		#clock-cells = <0>;
2400	};
2401
2402};
2403