1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2019, Intel Corporation 4 */ 5 6/dts-v1/; 7#include <dt-bindings/reset/altr,rst-mgr-s10.h> 8#include <dt-bindings/gpio/gpio.h> 9 10/ { 11 compatible = "intel,socfpga-agilex"; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 reserved-memory { 16 #address-cells = <2>; 17 #size-cells = <2>; 18 ranges; 19 20 service_reserved: svcbuffer@0 { 21 compatible = "shared-dma-pool"; 22 reg = <0x0 0x0 0x0 0x1000000>; 23 alignment = <0x1000>; 24 no-map; 25 }; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 cpu0: cpu@0 { 33 compatible = "arm,cortex-a53"; 34 device_type = "cpu"; 35 enable-method = "psci"; 36 reg = <0x0>; 37 }; 38 39 cpu1: cpu@1 { 40 compatible = "arm,cortex-a53"; 41 device_type = "cpu"; 42 enable-method = "psci"; 43 reg = <0x1>; 44 }; 45 46 cpu2: cpu@2 { 47 compatible = "arm,cortex-a53"; 48 device_type = "cpu"; 49 enable-method = "psci"; 50 reg = <0x2>; 51 }; 52 53 cpu3: cpu@3 { 54 compatible = "arm,cortex-a53"; 55 device_type = "cpu"; 56 enable-method = "psci"; 57 reg = <0x3>; 58 }; 59 }; 60 61 pmu { 62 compatible = "arm,armv8-pmuv3"; 63 interrupts = <0 170 4>, 64 <0 171 4>, 65 <0 172 4>, 66 <0 173 4>; 67 interrupt-affinity = <&cpu0>, 68 <&cpu1>, 69 <&cpu2>, 70 <&cpu3>; 71 interrupt-parent = <&intc>; 72 }; 73 74 psci { 75 compatible = "arm,psci-0.2"; 76 method = "smc"; 77 }; 78 79 intc: intc@fffc1000 { 80 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 81 #interrupt-cells = <3>; 82 interrupt-controller; 83 reg = <0x0 0xfffc1000 0x0 0x1000>, 84 <0x0 0xfffc2000 0x0 0x2000>, 85 <0x0 0xfffc4000 0x0 0x2000>, 86 <0x0 0xfffc6000 0x0 0x2000>; 87 }; 88 89 soc { 90 #address-cells = <1>; 91 #size-cells = <1>; 92 compatible = "simple-bus"; 93 device_type = "soc"; 94 interrupt-parent = <&intc>; 95 ranges = <0 0 0 0xffffffff>; 96 97 base_fpga_region { 98 #address-cells = <0x1>; 99 #size-cells = <0x1>; 100 compatible = "fpga-region"; 101 fpga-mgr = <&fpga_mgr>; 102 }; 103 104 gmac0: ethernet@ff800000 { 105 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 106 reg = <0xff800000 0x2000>; 107 interrupts = <0 90 4>; 108 interrupt-names = "macirq"; 109 mac-address = [00 00 00 00 00 00]; 110 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; 111 reset-names = "stmmaceth", "stmmaceth-ocp"; 112 tx-fifo-depth = <16384>; 113 rx-fifo-depth = <16384>; 114 snps,multicast-filter-bins = <256>; 115 iommus = <&smmu 1>; 116 altr,sysmgr-syscon = <&sysmgr 0x44 0>; 117 status = "disabled"; 118 }; 119 120 gmac1: ethernet@ff802000 { 121 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 122 reg = <0xff802000 0x2000>; 123 interrupts = <0 91 4>; 124 interrupt-names = "macirq"; 125 mac-address = [00 00 00 00 00 00]; 126 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; 127 reset-names = "stmmaceth", "stmmaceth-ocp"; 128 tx-fifo-depth = <16384>; 129 rx-fifo-depth = <16384>; 130 snps,multicast-filter-bins = <256>; 131 iommus = <&smmu 2>; 132 altr,sysmgr-syscon = <&sysmgr 0x48 8>; 133 status = "disabled"; 134 }; 135 136 gmac2: ethernet@ff804000 { 137 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 138 reg = <0xff804000 0x2000>; 139 interrupts = <0 92 4>; 140 interrupt-names = "macirq"; 141 mac-address = [00 00 00 00 00 00]; 142 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; 143 reset-names = "stmmaceth", "stmmaceth-ocp"; 144 tx-fifo-depth = <16384>; 145 rx-fifo-depth = <16384>; 146 snps,multicast-filter-bins = <256>; 147 iommus = <&smmu 3>; 148 altr,sysmgr-syscon = <&sysmgr 0x4c 16>; 149 status = "disabled"; 150 }; 151 152 gpio0: gpio@ffc03200 { 153 #address-cells = <1>; 154 #size-cells = <0>; 155 compatible = "snps,dw-apb-gpio"; 156 reg = <0xffc03200 0x100>; 157 resets = <&rst GPIO0_RESET>; 158 status = "disabled"; 159 160 porta: gpio-controller@0 { 161 compatible = "snps,dw-apb-gpio-port"; 162 gpio-controller; 163 #gpio-cells = <2>; 164 snps,nr-gpios = <24>; 165 reg = <0>; 166 interrupt-controller; 167 #interrupt-cells = <2>; 168 interrupts = <0 110 4>; 169 }; 170 }; 171 172 gpio1: gpio@ffc03300 { 173 #address-cells = <1>; 174 #size-cells = <0>; 175 compatible = "snps,dw-apb-gpio"; 176 reg = <0xffc03300 0x100>; 177 resets = <&rst GPIO1_RESET>; 178 status = "disabled"; 179 180 portb: gpio-controller@0 { 181 compatible = "snps,dw-apb-gpio-port"; 182 gpio-controller; 183 #gpio-cells = <2>; 184 snps,nr-gpios = <24>; 185 reg = <0>; 186 interrupt-controller; 187 #interrupt-cells = <2>; 188 interrupts = <0 111 4>; 189 }; 190 }; 191 192 i2c0: i2c@ffc02800 { 193 #address-cells = <1>; 194 #size-cells = <0>; 195 compatible = "snps,designware-i2c"; 196 reg = <0xffc02800 0x100>; 197 interrupts = <0 103 4>; 198 resets = <&rst I2C0_RESET>; 199 status = "disabled"; 200 }; 201 202 i2c1: i2c@ffc02900 { 203 #address-cells = <1>; 204 #size-cells = <0>; 205 compatible = "snps,designware-i2c"; 206 reg = <0xffc02900 0x100>; 207 interrupts = <0 104 4>; 208 resets = <&rst I2C1_RESET>; 209 status = "disabled"; 210 }; 211 212 i2c2: i2c@ffc02a00 { 213 #address-cells = <1>; 214 #size-cells = <0>; 215 compatible = "snps,designware-i2c"; 216 reg = <0xffc02a00 0x100>; 217 interrupts = <0 105 4>; 218 resets = <&rst I2C2_RESET>; 219 status = "disabled"; 220 }; 221 222 i2c3: i2c@ffc02b00 { 223 #address-cells = <1>; 224 #size-cells = <0>; 225 compatible = "snps,designware-i2c"; 226 reg = <0xffc02b00 0x100>; 227 interrupts = <0 106 4>; 228 resets = <&rst I2C3_RESET>; 229 status = "disabled"; 230 }; 231 232 i2c4: i2c@ffc02c00 { 233 #address-cells = <1>; 234 #size-cells = <0>; 235 compatible = "snps,designware-i2c"; 236 reg = <0xffc02c00 0x100>; 237 interrupts = <0 107 4>; 238 resets = <&rst I2C4_RESET>; 239 status = "disabled"; 240 }; 241 242 mmc: dwmmc0@ff808000 { 243 #address-cells = <1>; 244 #size-cells = <0>; 245 compatible = "altr,socfpga-dw-mshc"; 246 reg = <0xff808000 0x1000>; 247 interrupts = <0 96 4>; 248 fifo-depth = <0x400>; 249 resets = <&rst SDMMC_RESET>; 250 reset-names = "reset"; 251 iommus = <&smmu 5>; 252 status = "disabled"; 253 }; 254 255 nand: nand@ffb90000 { 256 #address-cells = <1>; 257 #size-cells = <0>; 258 compatible = "altr,socfpga-denali-nand"; 259 reg = <0xffb90000 0x10000>, 260 <0xffb80000 0x1000>; 261 reg-names = "nand_data", "denali_reg"; 262 interrupts = <0 97 4>; 263 resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>; 264 status = "disabled"; 265 }; 266 267 ocram: sram@ffe00000 { 268 compatible = "mmio-sram"; 269 reg = <0xffe00000 0x40000>; 270 }; 271 272 pdma: pdma@ffda0000 { 273 compatible = "arm,pl330", "arm,primecell"; 274 reg = <0xffda0000 0x1000>; 275 interrupts = <0 81 4>, 276 <0 82 4>, 277 <0 83 4>, 278 <0 84 4>, 279 <0 85 4>, 280 <0 86 4>, 281 <0 87 4>, 282 <0 88 4>, 283 <0 89 4>; 284 #dma-cells = <1>; 285 #dma-channels = <8>; 286 #dma-requests = <32>; 287 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; 288 reset-names = "dma", "dma-ocp"; 289 }; 290 291 rst: rstmgr@ffd11000 { 292 #reset-cells = <1>; 293 compatible = "altr,stratix10-rst-mgr"; 294 reg = <0xffd11000 0x100>; 295 }; 296 297 smmu: iommu@fa000000 { 298 compatible = "arm,mmu-500", "arm,smmu-v2"; 299 reg = <0xfa000000 0x40000>; 300 #global-interrupts = <2>; 301 #iommu-cells = <1>; 302 interrupt-parent = <&intc>; 303 interrupts = <0 128 4>, /* Global Secure Fault */ 304 <0 129 4>, /* Global Non-secure Fault */ 305 /* Non-secure Context Interrupts (32) */ 306 <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>, 307 <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>, 308 <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>, 309 <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>, 310 <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>, 311 <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>, 312 <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>, 313 <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>; 314 stream-match-mask = <0x7ff0>; 315 status = "disabled"; 316 }; 317 318 spi0: spi@ffda4000 { 319 compatible = "snps,dw-apb-ssi"; 320 #address-cells = <1>; 321 #size-cells = <0>; 322 reg = <0xffda4000 0x1000>; 323 interrupts = <0 99 4>; 324 resets = <&rst SPIM0_RESET>; 325 reg-io-width = <4>; 326 num-cs = <4>; 327 status = "disabled"; 328 }; 329 330 spi1: spi@ffda5000 { 331 compatible = "snps,dw-apb-ssi"; 332 #address-cells = <1>; 333 #size-cells = <0>; 334 reg = <0xffda5000 0x1000>; 335 interrupts = <0 100 4>; 336 resets = <&rst SPIM1_RESET>; 337 reg-io-width = <4>; 338 num-cs = <4>; 339 status = "disabled"; 340 }; 341 342 sysmgr: sysmgr@ffd12000 { 343 compatible = "altr,sys-mgr-s10","altr,sys-mgr"; 344 reg = <0xffd12000 0x500>; 345 }; 346 347 /* Local timer */ 348 timer { 349 compatible = "arm,armv8-timer"; 350 interrupts = <1 13 0xf08>, 351 <1 14 0xf08>, 352 <1 11 0xf08>, 353 <1 10 0xf08>; 354 }; 355 356 timer0: timer0@ffc03000 { 357 compatible = "snps,dw-apb-timer"; 358 interrupts = <0 113 4>; 359 reg = <0xffc03000 0x100>; 360 }; 361 362 timer1: timer1@ffc03100 { 363 compatible = "snps,dw-apb-timer"; 364 interrupts = <0 114 4>; 365 reg = <0xffc03100 0x100>; 366 }; 367 368 timer2: timer2@ffd00000 { 369 compatible = "snps,dw-apb-timer"; 370 interrupts = <0 115 4>; 371 reg = <0xffd00000 0x100>; 372 }; 373 374 timer3: timer3@ffd00100 { 375 compatible = "snps,dw-apb-timer"; 376 interrupts = <0 116 4>; 377 reg = <0xffd00100 0x100>; 378 }; 379 380 uart0: serial0@ffc02000 { 381 compatible = "snps,dw-apb-uart"; 382 reg = <0xffc02000 0x100>; 383 interrupts = <0 108 4>; 384 reg-shift = <2>; 385 reg-io-width = <4>; 386 resets = <&rst UART0_RESET>; 387 status = "disabled"; 388 }; 389 390 uart1: serial1@ffc02100 { 391 compatible = "snps,dw-apb-uart"; 392 reg = <0xffc02100 0x100>; 393 interrupts = <0 109 4>; 394 reg-shift = <2>; 395 reg-io-width = <4>; 396 resets = <&rst UART1_RESET>; 397 status = "disabled"; 398 }; 399 400 usbphy0: usbphy@0 { 401 #phy-cells = <0>; 402 compatible = "usb-nop-xceiv"; 403 status = "okay"; 404 }; 405 406 usb0: usb@ffb00000 { 407 compatible = "snps,dwc2"; 408 reg = <0xffb00000 0x40000>; 409 interrupts = <0 93 4>; 410 phys = <&usbphy0>; 411 phy-names = "usb2-phy"; 412 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; 413 reset-names = "dwc2", "dwc2-ecc"; 414 iommus = <&smmu 6>; 415 status = "disabled"; 416 }; 417 418 usb1: usb@ffb40000 { 419 compatible = "snps,dwc2"; 420 reg = <0xffb40000 0x40000>; 421 interrupts = <0 94 4>; 422 phys = <&usbphy0>; 423 phy-names = "usb2-phy"; 424 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; 425 reset-names = "dwc2", "dwc2-ecc"; 426 iommus = <&smmu 7>; 427 status = "disabled"; 428 }; 429 430 watchdog0: watchdog@ffd00200 { 431 compatible = "snps,dw-wdt"; 432 reg = <0xffd00200 0x100>; 433 interrupts = <0 117 4>; 434 resets = <&rst WATCHDOG0_RESET>; 435 status = "disabled"; 436 }; 437 438 watchdog1: watchdog@ffd00300 { 439 compatible = "snps,dw-wdt"; 440 reg = <0xffd00300 0x100>; 441 interrupts = <0 118 4>; 442 resets = <&rst WATCHDOG1_RESET>; 443 status = "disabled"; 444 }; 445 446 watchdog2: watchdog@ffd00400 { 447 compatible = "snps,dw-wdt"; 448 reg = <0xffd00400 0x100>; 449 interrupts = <0 125 4>; 450 resets = <&rst WATCHDOG2_RESET>; 451 status = "disabled"; 452 }; 453 454 watchdog3: watchdog@ffd00500 { 455 compatible = "snps,dw-wdt"; 456 reg = <0xffd00500 0x100>; 457 interrupts = <0 126 4>; 458 resets = <&rst WATCHDOG3_RESET>; 459 status = "disabled"; 460 }; 461 462 sdr: sdr@f8011100 { 463 compatible = "altr,sdr-ctl", "syscon"; 464 reg = <0xf8011100 0xc0>; 465 }; 466 467 eccmgr { 468 compatible = "altr,socfpga-s10-ecc-manager", 469 "altr,socfpga-a10-ecc-manager"; 470 altr,sysmgr-syscon = <&sysmgr>; 471 #address-cells = <1>; 472 #size-cells = <1>; 473 interrupts = <0 15 4>; 474 interrupt-controller; 475 #interrupt-cells = <2>; 476 ranges; 477 478 sdramedac { 479 compatible = "altr,sdram-edac-s10"; 480 altr,sdr-syscon = <&sdr>; 481 interrupts = <16 4>; 482 }; 483 484 ocram-ecc@ff8cc000 { 485 compatible = "altr,socfpga-s10-ocram-ecc", 486 "altr,socfpga-a10-ocram-ecc"; 487 reg = <0xff8cc000 0x100>; 488 altr,ecc-parent = <&ocram>; 489 interrupts = <1 4>; 490 }; 491 492 usb0-ecc@ff8c4000 { 493 compatible = "altr,socfpga-s10-usb-ecc", 494 "altr,socfpga-usb-ecc"; 495 reg = <0xff8c4000 0x100>; 496 altr,ecc-parent = <&usb0>; 497 interrupts = <2 4>; 498 }; 499 500 emac0-rx-ecc@ff8c0000 { 501 compatible = "altr,socfpga-s10-eth-mac-ecc", 502 "altr,socfpga-eth-mac-ecc"; 503 reg = <0xff8c0000 0x100>; 504 altr,ecc-parent = <&gmac0>; 505 interrupts = <4 4>; 506 }; 507 508 emac0-tx-ecc@ff8c0400 { 509 compatible = "altr,socfpga-s10-eth-mac-ecc", 510 "altr,socfpga-eth-mac-ecc"; 511 reg = <0xff8c0400 0x100>; 512 altr,ecc-parent = <&gmac0>; 513 interrupts = <5 4>; 514 }; 515 516 sdmmca-ecc@ff8c8c00 { 517 compatible = "altr,socfpga-s10-sdmmc-ecc", 518 "altr,socfpga-sdmmc-ecc"; 519 reg = <0xff8c8c00 0x100>; 520 altr,ecc-parent = <&mmc>; 521 interrupts = <14 4>, 522 <15 4>; 523 }; 524 }; 525 526 qspi: spi@ff8d2000 { 527 compatible = "cdns,qspi-nor"; 528 #address-cells = <1>; 529 #size-cells = <0>; 530 reg = <0xff8d2000 0x100>, 531 <0xff900000 0x100000>; 532 interrupts = <0 3 4>; 533 cdns,fifo-depth = <128>; 534 cdns,fifo-width = <4>; 535 cdns,trigger-address = <0x00000000>; 536 537 status = "disabled"; 538 }; 539 540 firmware { 541 svc { 542 compatible = "intel,stratix10-svc"; 543 method = "smc"; 544 memory-region = <&service_reserved>; 545 546 fpga_mgr: fpga-mgr { 547 compatible = "intel,stratix10-soc-fpga-mgr"; 548 }; 549 }; 550 }; 551 }; 552}; 553