1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Tegra Power Management Controller (PMC) 8 9maintainers: 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jonathan Hunter <jonathanh@nvidia.com> 12 13properties: 14 compatible: 15 enum: 16 - nvidia,tegra20-pmc 17 - nvidia,tegra20-pmc 18 - nvidia,tegra30-pmc 19 - nvidia,tegra114-pmc 20 - nvidia,tegra124-pmc 21 - nvidia,tegra210-pmc 22 23 reg: 24 maxItems: 1 25 description: 26 Offset and length of the register set for the device. 27 28 clock-names: 29 items: 30 - const: pclk 31 - const: clk32k_in 32 description: 33 Must includes entries pclk and clk32k_in. 34 pclk is the Tegra clock of that name and clk32k_in is 32KHz clock 35 input to Tegra. 36 37 clocks: 38 maxItems: 2 39 description: 40 Must contain an entry for each entry in clock-names. 41 See ../clocks/clocks-bindings.txt for details. 42 43 '#clock-cells': 44 const: 1 45 description: 46 Tegra PMC has clk_out_1, clk_out_2, and clk_out_3. 47 PMC also has blink control which allows 32Khz clock output to 48 Tegra blink pad. 49 Consumer of PMC clock should specify the desired clock by having 50 the clock ID in its "clocks" phandle cell with pmc clock provider. 51 See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC 52 clock IDs. 53 54 '#interrupt-cells': 55 const: 2 56 description: 57 Specifies number of cells needed to encode an interrupt source. 58 The value must be 2. 59 60 interrupt-controller: true 61 62 nvidia,invert-interrupt: 63 $ref: /schemas/types.yaml#/definitions/flag 64 description: Inverts the PMU interrupt signal. 65 The PMU is an external Power Management Unit, whose interrupt output 66 signal is fed into the PMC. This signal is optionally inverted, and 67 then fed into the ARM GIC. The PMC is not involved in the detection 68 or handling of this interrupt signal, merely its inversion. 69 70 nvidia,core-power-req-active-high: 71 $ref: /schemas/types.yaml#/definitions/flag 72 description: Core power request active-high. 73 74 nvidia,sys-clock-req-active-high: 75 $ref: /schemas/types.yaml#/definitions/flag 76 description: System clock request active-high. 77 78 nvidia,combined-power-req: 79 $ref: /schemas/types.yaml#/definitions/flag 80 description: combined power request for CPU and Core. 81 82 nvidia,cpu-pwr-good-en: 83 $ref: /schemas/types.yaml#/definitions/flag 84 description: 85 CPU power good signal from external PMIC to PMC is enabled. 86 87 nvidia,suspend-mode: 88 allOf: 89 - $ref: /schemas/types.yaml#/definitions/uint32 90 - enum: [0, 1, 2] 91 description: 92 The suspend mode that the platform should use. 93 Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh 94 Mode 1 is for LP1, CPU voltage off and DRAM in self-refresh 95 Mode 2 is for LP2, CPU voltage off 96 97 nvidia,cpu-pwr-good-time: 98 $ref: /schemas/types.yaml#/definitions/uint32 99 description: CPU power good time in uSec. 100 101 nvidia,cpu-pwr-off-time: 102 $ref: /schemas/types.yaml#/definitions/uint32 103 description: CPU power off time in uSec. 104 105 nvidia,core-pwr-good-time: 106 $ref: /schemas/types.yaml#/definitions/uint32-array 107 description: 108 <Oscillator-stable-time Power-stable-time> 109 Core power good time in uSec. 110 111 nvidia,core-pwr-off-time: 112 $ref: /schemas/types.yaml#/definitions/uint32 113 description: Core power off time in uSec. 114 115 nvidia,lp0-vec: 116 $ref: /schemas/types.yaml#/definitions/uint32-array 117 description: 118 <start length> Starting address and length of LP0 vector. 119 The LP0 vector contains the warm boot code that is executed 120 by AVP when resuming from the LP0 state. 121 The AVP (Audio-Video Processor) is an ARM7 processor and 122 always being the first boot processor when chip is power on 123 or resume from deep sleep mode. When the system is resumed 124 from the deep sleep mode, the warm boot code will restore 125 some PLLs, clocks and then brings up CPU0 for resuming the 126 system. 127 128 i2c-thermtrip: 129 type: object 130 description: 131 On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists, 132 hardware-triggered thermal reset will be enabled. 133 134 properties: 135 nvidia,i2c-controller-id: 136 $ref: /schemas/types.yaml#/definitions/uint32 137 description: 138 ID of I2C controller to send poweroff command to PMU. 139 Valid values are described in section 9.2.148 140 "APBDEV_PMC_SCRATCH53_0" of the Tegra K1 Technical Reference 141 Manual. 142 143 nvidia,bus-addr: 144 $ref: /schemas/types.yaml#/definitions/uint32 145 description: Bus address of the PMU on the I2C bus. 146 147 nvidia,reg-addr: 148 $ref: /schemas/types.yaml#/definitions/uint32 149 description: PMU I2C register address to issue poweroff command. 150 151 nvidia,reg-data: 152 $ref: /schemas/types.yaml#/definitions/uint32 153 description: Poweroff command to write to PMU. 154 155 nvidia,pinmux-id: 156 $ref: /schemas/types.yaml#/definitions/uint32 157 description: 158 Pinmux used by the hardware when issuing Poweroff command. 159 Defaults to 0. Valid values are described in section 12.5.2 160 "Pinmux Support" of the Tegra4 Technical Reference Manual. 161 162 required: 163 - nvidia,i2c-controller-id 164 - nvidia,bus-addr 165 - nvidia,reg-addr 166 - nvidia,reg-data 167 168 additionalProperties: false 169 170 powergates: 171 type: object 172 description: | 173 This node contains a hierarchy of power domain nodes, which should 174 match the powergates on the Tegra SoC. Each powergate node 175 represents a power-domain on the Tegra SoC that can be power-gated 176 by the Tegra PMC. 177 Hardware blocks belonging to a power domain should contain 178 "power-domains" property that is a phandle pointing to corresponding 179 powergate node. 180 The name of the powergate node should be one of the below. Note that 181 not every powergate is applicable to all Tegra devices and the following 182 list shows which powergates are applicable to which devices. 183 Please refer to Tegra TRM for mode details on the powergate nodes to 184 use for each power-gate block inside Tegra. 185 Name Description Devices Applicable 186 3d 3D Graphics Tegra20/114/124/210 187 3d0 3D Graphics 0 Tegra30 188 3d1 3D Graphics 1 Tegra30 189 aud Audio Tegra210 190 dfd Debug Tegra210 191 dis Display A Tegra114/124/210 192 disb Display B Tegra114/124/210 193 heg 2D Graphics Tegra30/114/124/210 194 iram Internal RAM Tegra124/210 195 mpe MPEG Encode All 196 nvdec NVIDIA Video Decode Engine Tegra210 197 nvjpg NVIDIA JPEG Engine Tegra210 198 pcie PCIE Tegra20/30/124/210 199 sata SATA Tegra30/124/210 200 sor Display interfaces Tegra124/210 201 ve2 Video Encode Engine 2 Tegra210 202 venc Video Encode Engine All 203 vdec Video Decode Engine Tegra20/30/114/124 204 vic Video Imaging Compositor Tegra124/210 205 xusba USB Partition A Tegra114/124/210 206 xusbb USB Partition B Tegra114/124/210 207 xusbc USB Partition C Tegra114/124/210 208 209 patternProperties: 210 "^[a-z0-9]+$": 211 type: object 212 213 patternProperties: 214 clocks: 215 minItems: 1 216 maxItems: 8 217 description: 218 Must contain an entry for each clock required by the PMC 219 for controlling a power-gate. 220 See ../clocks/clock-bindings.txt document for more details. 221 222 resets: 223 minItems: 1 224 maxItems: 8 225 description: 226 Must contain an entry for each reset required by the PMC 227 for controlling a power-gate. 228 See ../reset/reset.txt for more details. 229 230 '#power-domain-cells': 231 const: 0 232 description: Must be 0. 233 234 required: 235 - clocks 236 - resets 237 - '#power-domain-cells' 238 239 additionalProperties: false 240 241patternProperties: 242 "^[a-f0-9]+-[a-f0-9]+$": 243 type: object 244 description: 245 This is a Pad configuration node. On Tegra SOCs a pad is a set of 246 pins which are configured as a group. The pin grouping is a fixed 247 attribute of the hardware. The PMC can be used to set pad power state 248 and signaling voltage. A pad can be either in active or power down mode. 249 The support for power state and signaling voltage configuration varies 250 depending on the pad in question. 3.3V and 1.8V signaling voltages 251 are supported on pins where software controllable signaling voltage 252 switching is available. 253 254 The pad configuration state nodes are placed under the pmc node and they 255 are referred to by the pinctrl client properties. For more information 256 see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt. 257 The pad name should be used as the value of the pins property in pin 258 configuration nodes. 259 260 The following pads are present on Tegra124 and Tegra132 261 audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi, hsic, 262 hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, pex-cntrl, 263 sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, usb_bias. 264 265 The following pads are present on Tegra210 266 audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg, 267 debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, hdmi, 268 hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1, 269 sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias. 270 271 properties: 272 pins: 273 $ref: /schemas/types.yaml#/definitions/string 274 description: Must contain name of the pad(s) to be configured. 275 276 low-power-enable: 277 $ref: /schemas/types.yaml#/definitions/flag 278 description: Configure the pad into power down mode. 279 280 low-power-disable: 281 $ref: /schemas/types.yaml#/definitions/flag 282 description: Configure the pad into active mode. 283 284 power-source: 285 $ref: /schemas/types.yaml#/definitions/uint32 286 description: 287 Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or 288 TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages. 289 The values are defined in 290 include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h. 291 Power state can be configured on all Tegra124 and Tegra132 292 pads. None of the Tegra124 or Tegra132 pads support signaling 293 voltage switching. 294 All of the listed Tegra210 pads except pex-cntrl support power 295 state configuration. Signaling voltage switching is supported 296 on below Tegra210 pads. 297 audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1, 298 sdmmc3, spi, spi-hv, and uart. 299 300 required: 301 - pins 302 303 additionalProperties: false 304 305required: 306 - compatible 307 - reg 308 - clock-names 309 - clocks 310 - '#clock-cells' 311 312dependencies: 313 "nvidia,suspend-mode": ["nvidia,core-pwr-off-time", "nvidia,cpu-pwr-off-time"] 314 "nvidia,core-pwr-off-time": ["nvidia,core-pwr-good-time"] 315 "nvidia,cpu-pwr-off-time": ["nvidia,cpu-pwr-good-time"] 316 317examples: 318 - | 319 320 #include <dt-bindings/clock/tegra210-car.h> 321 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 322 #include <dt-bindings/soc/tegra-pmc.h> 323 324 tegra_pmc: pmc@7000e400 { 325 compatible = "nvidia,tegra210-pmc"; 326 reg = <0x0 0x7000e400 0x0 0x400>; 327 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 328 clock-names = "pclk", "clk32k_in"; 329 #clock-cells = <1>; 330 331 nvidia,invert-interrupt; 332 nvidia,suspend-mode = <0>; 333 nvidia,cpu-pwr-good-time = <0>; 334 nvidia,cpu-pwr-off-time = <0>; 335 nvidia,core-pwr-good-time = <4587 3876>; 336 nvidia,core-pwr-off-time = <39065>; 337 nvidia,core-power-req-active-high; 338 nvidia,sys-clock-req-active-high; 339 340 powergates { 341 pd_audio: aud { 342 clocks = <&tegra_car TEGRA210_CLK_APE>, 343 <&tegra_car TEGRA210_CLK_APB2APE>; 344 resets = <&tegra_car 198>; 345 #power-domain-cells = <0>; 346 }; 347 348 pd_xusbss: xusba { 349 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 350 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 351 #power-domain-cells = <0>; 352 }; 353 }; 354 }; 355