1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-usb-phy.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Allwinner A31 USB PHY Device Tree Bindings 8 9maintainers: 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 12 13properties: 14 "#phy-cells": 15 const: 1 16 17 compatible: 18 const: allwinner,sun6i-a31-usb-phy 19 20 reg: 21 items: 22 - description: PHY Control registers 23 - description: PHY PMU1 registers 24 - description: PHY PMU2 registers 25 26 reg-names: 27 items: 28 - const: phy_ctrl 29 - const: pmu1 30 - const: pmu2 31 32 clocks: 33 items: 34 - description: USB OTG PHY bus clock 35 - description: USB Host 0 PHY bus clock 36 - description: USB Host 1 PHY bus clock 37 38 clock-names: 39 items: 40 - const: usb0_phy 41 - const: usb1_phy 42 - const: usb2_phy 43 44 resets: 45 items: 46 - description: USB OTG reset 47 - description: USB Host 1 Controller reset 48 - description: USB Host 2 Controller reset 49 50 reset-names: 51 items: 52 - const: usb0_reset 53 - const: usb1_reset 54 - const: usb2_reset 55 56 usb0_id_det-gpios: 57 description: GPIO to the USB OTG ID pin 58 59 usb0_vbus_det-gpios: 60 description: GPIO to the USB OTG VBUS detect pin 61 62 usb0_vbus_power-supply: 63 description: Power supply to detect the USB OTG VBUS 64 65 usb0_vbus-supply: 66 description: Regulator controlling USB OTG VBUS 67 68 usb1_vbus-supply: 69 description: Regulator controlling USB1 Host controller 70 71 usb2_vbus-supply: 72 description: Regulator controlling USB2 Host controller 73 74required: 75 - "#phy-cells" 76 - compatible 77 - clocks 78 - clock-names 79 - reg 80 - reg-names 81 - resets 82 - reset-names 83 84additionalProperties: false 85 86examples: 87 - | 88 #include <dt-bindings/gpio/gpio.h> 89 #include <dt-bindings/clock/sun6i-a31-ccu.h> 90 #include <dt-bindings/reset/sun6i-a31-ccu.h> 91 92 phy@1c19400 { 93 #phy-cells = <1>; 94 compatible = "allwinner,sun6i-a31-usb-phy"; 95 reg = <0x01c19400 0x10>, 96 <0x01c1a800 0x4>, 97 <0x01c1b800 0x4>; 98 reg-names = "phy_ctrl", 99 "pmu1", 100 "pmu2"; 101 clocks = <&ccu CLK_USB_PHY0>, 102 <&ccu CLK_USB_PHY1>, 103 <&ccu CLK_USB_PHY2>; 104 clock-names = "usb0_phy", 105 "usb1_phy", 106 "usb2_phy"; 107 resets = <&ccu RST_USB_PHY0>, 108 <&ccu RST_USB_PHY1>, 109 <&ccu RST_USB_PHY2>; 110 reset-names = "usb0_reset", 111 "usb1_reset", 112 "usb2_reset"; 113 usb0_id_det-gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ 114 usb0_vbus_det-gpios = <&pio 0 16 GPIO_ACTIVE_HIGH>; /* PA16 */ 115 usb0_vbus_power-supply = <&usb_power_supply>; 116 usb0_vbus-supply = <®_drivevbus>; 117 usb1_vbus-supply = <®_usb1_vbus>; 118 usb2_vbus-supply = <®_usb2_vbus>; 119 }; 120