1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: The TI AM654x/J721E SoC Gigabit Ethernet MAC (Media Access Controller) Device Tree Bindings
8
9maintainers:
10  - Grygorii Strashko <grygorii.strashko@ti.com>
11  - Sekhar Nori <nsekhar@ti.com>
12
13description:
14  The TI AM654x/J721E SoC Gigabit Ethernet MAC (CPSW2G NUSS) has two ports
15  (one external) and provides Ethernet packet communication for the device.
16  CPSW2G NUSS features - the Reduced Gigabit Media Independent Interface (RGMII),
17  Reduced Media Independent Interface (RMII), the Management Data
18  Input/Output (MDIO) interface for physical layer device (PHY) management,
19  new version of Common Platform Time Sync (CPTS), updated Address Lookup
20  Engine (ALE).
21  One external Ethernet port (port 1) with selectable RGMII/RMII interfaces and
22  an internal Communications Port Programming Interface (CPPI5) (Host port 0).
23  Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels
24  and one RX channels and operating by TI AM654x/J721E NAVSS Unified DMA
25  Peripheral Root Complex (UDMA-P) controller.
26  The CPSW2G NUSS is integrated into device MCU domain named MCU_CPSW0.
27
28  Additional features
29  priority level Quality Of Service (QOS) support (802.1p)
30  Support for Audio/Video Bridging (P802.1Qav/D6.0)
31  Support for IEEE 1588 Clock Synchronization (2008 Annex D, Annex E and Annex F)
32  Flow Control (802.3x) Support
33  Time Sensitive Network Support
34  IEEE P902.3br/D2.0 Interspersing Express Traffic
35  IEEE 802.1Qbv/D2.2 Enhancements for Scheduled Traffic
36  Configurable number of addresses plus VLANs
37  Configurable number of classifier/policers
38  VLAN support, 802.1Q compliant, Auto add port VLAN for untagged frames on
39  ingress, Auto VLAN removal on egress and auto pad to minimum frame size.
40  RX/TX csum offload
41
42  Specifications can be found at
43    http://www.ti.com/lit/ug/spruid7e/spruid7e.pdf
44    http://www.ti.com/lit/ug/spruil1a/spruil1a.pdf
45
46properties:
47  "#address-cells": true
48  "#size-cells": true
49
50  compatible:
51    oneOf:
52      - const: ti,am654-cpsw-nuss
53      - const: ti,j721e-cpsw-nuss
54
55  reg:
56    maxItems: 1
57    description:
58       The physical base address and size of full the CPSW2G NUSS IO range
59
60  reg-names:
61    items:
62      - const: cpsw_nuss
63
64  ranges: true
65
66  dma-coherent: true
67
68  clocks:
69    description: CPSW2G NUSS functional clock
70
71  clock-names:
72    items:
73      - const: fck
74
75  power-domains:
76    maxItems: 1
77
78  dmas:
79    maxItems: 9
80
81  dma-names:
82    items:
83      - const: tx0
84      - const: tx1
85      - const: tx2
86      - const: tx3
87      - const: tx4
88      - const: tx5
89      - const: tx6
90      - const: tx7
91      - const: rx
92
93  ethernet-ports:
94    type: object
95    properties:
96      '#address-cells':
97        const: 1
98      '#size-cells':
99        const: 0
100
101    patternProperties:
102      port@1:
103       type: object
104       description: CPSW2G NUSS external ports
105
106       allOf:
107         - $ref: ethernet-controller.yaml#
108
109       properties:
110         reg:
111           items:
112             - const: 1
113           description: CPSW port number
114
115         phys:
116           maxItems: 1
117           description:  phandle on phy-gmii-sel PHY
118
119         label:
120           description: label associated with this port
121
122         ti,mac-only:
123           $ref: /schemas/types.yaml#definitions/flag
124           description:
125             Specifies the port works in mac-only mode.
126
127         ti,syscon-efuse:
128           $ref: /schemas/types.yaml#definitions/phandle-array
129           description:
130             Phandle to the system control device node which provides access
131             to efuse IO range with MAC addresses
132
133       required:
134         - reg
135         - phys
136
137    additionalProperties: false
138
139patternProperties:
140  "^mdio@[0-9a-f]+$":
141    type: object
142    allOf:
143      - $ref: "ti,davinci-mdio.yaml#"
144    description:
145      CPSW MDIO bus.
146
147required:
148  - compatible
149  - reg
150  - reg-names
151  - ranges
152  - clocks
153  - clock-names
154  - power-domains
155  - dmas
156  - dma-names
157  - '#address-cells'
158  - '#size-cells'
159
160additionalProperties: false
161
162examples:
163  - |
164    #include <dt-bindings/pinctrl/k3.h>
165    #include <dt-bindings/soc/ti,sci_pm_domain.h>
166    #include <dt-bindings/net/ti-dp83867.h>
167
168    mcu_cpsw: ethernet@46000000 {
169        compatible = "ti,am654-cpsw-nuss";
170        #address-cells = <2>;
171        #size-cells = <2>;
172        reg = <0x0 0x46000000 0x0 0x200000>;
173        reg-names = "cpsw_nuss";
174        ranges = <0x0 0x0 0x46000000 0x0 0x200000>;
175        dma-coherent;
176        clocks = <&k3_clks 5 10>;
177        clock-names = "fck";
178        power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
179        pinctrl-names = "default";
180        pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
181
182        dmas = <&mcu_udmap 0xf000>,
183               <&mcu_udmap 0xf001>,
184               <&mcu_udmap 0xf002>,
185               <&mcu_udmap 0xf003>,
186               <&mcu_udmap 0xf004>,
187               <&mcu_udmap 0xf005>,
188               <&mcu_udmap 0xf006>,
189               <&mcu_udmap 0xf007>,
190               <&mcu_udmap 0x7000>;
191        dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
192                    "rx";
193
194        ethernet-ports {
195              #address-cells = <1>;
196              #size-cells = <0>;
197
198              cpsw_port1: port@1 {
199                    reg = <1>;
200                    ti,mac-only;
201                    label = "port1";
202                    ti,syscon-efuse = <&mcu_conf 0x200>;
203                    phys = <&phy_gmii_sel 1>;
204
205                    phy-mode = "rgmii-rxid";
206                    phy-handle = <&phy0>;
207              };
208        };
209
210        davinci_mdio: mdio@f00 {
211              compatible = "ti,cpsw-mdio","ti,davinci_mdio";
212              reg = <0x0 0xf00 0x0 0x100>;
213              #address-cells = <1>;
214              #size-cells = <0>;
215              clocks = <&k3_clks 5 10>;
216              clock-names = "fck";
217              bus_freq = <1000000>;
218
219              phy0: ethernet-phy@0 {
220                    reg = <0>;
221                    ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
222                    ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
223              };
224        };
225    };
226