1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 4 ST Ethernet IPs are built around a Synopsys IP Core. 5 6 Copyright(C) 2007-2011 STMicroelectronics Ltd 7 8 9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 10 11 Documentation available at: 12 http://www.stlinux.com 13 Support available at: 14 https://bugzilla.stlinux.com/ 15 *******************************************************************************/ 16 17 #include <linux/clk.h> 18 #include <linux/kernel.h> 19 #include <linux/interrupt.h> 20 #include <linux/ip.h> 21 #include <linux/tcp.h> 22 #include <linux/skbuff.h> 23 #include <linux/ethtool.h> 24 #include <linux/if_ether.h> 25 #include <linux/crc32.h> 26 #include <linux/mii.h> 27 #include <linux/if.h> 28 #include <linux/if_vlan.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/slab.h> 31 #include <linux/prefetch.h> 32 #include <linux/pinctrl/consumer.h> 33 #ifdef CONFIG_DEBUG_FS 34 #include <linux/debugfs.h> 35 #include <linux/seq_file.h> 36 #endif /* CONFIG_DEBUG_FS */ 37 #include <linux/net_tstamp.h> 38 #include <linux/phylink.h> 39 #include <linux/udp.h> 40 #include <net/pkt_cls.h> 41 #include "stmmac_ptp.h" 42 #include "stmmac.h" 43 #include <linux/reset.h> 44 #include <linux/of_mdio.h> 45 #include "dwmac1000.h" 46 #include "dwxgmac2.h" 47 #include "hwif.h" 48 49 #define STMMAC_ALIGN(x) ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16) 50 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1) 51 52 /* Module parameters */ 53 #define TX_TIMEO 5000 54 static int watchdog = TX_TIMEO; 55 module_param(watchdog, int, 0644); 56 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 57 58 static int debug = -1; 59 module_param(debug, int, 0644); 60 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 61 62 static int phyaddr = -1; 63 module_param(phyaddr, int, 0444); 64 MODULE_PARM_DESC(phyaddr, "Physical device address"); 65 66 #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4) 67 #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4) 68 69 static int flow_ctrl = FLOW_AUTO; 70 module_param(flow_ctrl, int, 0644); 71 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 72 73 static int pause = PAUSE_TIME; 74 module_param(pause, int, 0644); 75 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 76 77 #define TC_DEFAULT 64 78 static int tc = TC_DEFAULT; 79 module_param(tc, int, 0644); 80 MODULE_PARM_DESC(tc, "DMA threshold control value"); 81 82 #define DEFAULT_BUFSIZE 1536 83 static int buf_sz = DEFAULT_BUFSIZE; 84 module_param(buf_sz, int, 0644); 85 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 86 87 #define STMMAC_RX_COPYBREAK 256 88 89 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 90 NETIF_MSG_LINK | NETIF_MSG_IFUP | 91 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 92 93 #define STMMAC_DEFAULT_LPI_TIMER 1000 94 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 95 module_param(eee_timer, int, 0644); 96 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 97 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x)) 98 99 /* By default the driver will use the ring mode to manage tx and rx descriptors, 100 * but allow user to force to use the chain instead of the ring 101 */ 102 static unsigned int chain_mode; 103 module_param(chain_mode, int, 0444); 104 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 105 106 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 107 108 #ifdef CONFIG_DEBUG_FS 109 static const struct net_device_ops stmmac_netdev_ops; 110 static void stmmac_init_fs(struct net_device *dev); 111 static void stmmac_exit_fs(struct net_device *dev); 112 #endif 113 114 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) 115 116 /** 117 * stmmac_verify_args - verify the driver parameters. 118 * Description: it checks the driver parameters and set a default in case of 119 * errors. 120 */ 121 static void stmmac_verify_args(void) 122 { 123 if (unlikely(watchdog < 0)) 124 watchdog = TX_TIMEO; 125 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) 126 buf_sz = DEFAULT_BUFSIZE; 127 if (unlikely(flow_ctrl > 1)) 128 flow_ctrl = FLOW_AUTO; 129 else if (likely(flow_ctrl < 0)) 130 flow_ctrl = FLOW_OFF; 131 if (unlikely((pause < 0) || (pause > 0xffff))) 132 pause = PAUSE_TIME; 133 if (eee_timer < 0) 134 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 135 } 136 137 /** 138 * stmmac_disable_all_queues - Disable all queues 139 * @priv: driver private structure 140 */ 141 static void stmmac_disable_all_queues(struct stmmac_priv *priv) 142 { 143 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 144 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 145 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 146 u32 queue; 147 148 for (queue = 0; queue < maxq; queue++) { 149 struct stmmac_channel *ch = &priv->channel[queue]; 150 151 if (queue < rx_queues_cnt) 152 napi_disable(&ch->rx_napi); 153 if (queue < tx_queues_cnt) 154 napi_disable(&ch->tx_napi); 155 } 156 } 157 158 /** 159 * stmmac_enable_all_queues - Enable all queues 160 * @priv: driver private structure 161 */ 162 static void stmmac_enable_all_queues(struct stmmac_priv *priv) 163 { 164 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 165 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 166 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 167 u32 queue; 168 169 for (queue = 0; queue < maxq; queue++) { 170 struct stmmac_channel *ch = &priv->channel[queue]; 171 172 if (queue < rx_queues_cnt) 173 napi_enable(&ch->rx_napi); 174 if (queue < tx_queues_cnt) 175 napi_enable(&ch->tx_napi); 176 } 177 } 178 179 /** 180 * stmmac_stop_all_queues - Stop all queues 181 * @priv: driver private structure 182 */ 183 static void stmmac_stop_all_queues(struct stmmac_priv *priv) 184 { 185 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 186 u32 queue; 187 188 for (queue = 0; queue < tx_queues_cnt; queue++) 189 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 190 } 191 192 /** 193 * stmmac_start_all_queues - Start all queues 194 * @priv: driver private structure 195 */ 196 static void stmmac_start_all_queues(struct stmmac_priv *priv) 197 { 198 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 199 u32 queue; 200 201 for (queue = 0; queue < tx_queues_cnt; queue++) 202 netif_tx_start_queue(netdev_get_tx_queue(priv->dev, queue)); 203 } 204 205 static void stmmac_service_event_schedule(struct stmmac_priv *priv) 206 { 207 if (!test_bit(STMMAC_DOWN, &priv->state) && 208 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state)) 209 queue_work(priv->wq, &priv->service_task); 210 } 211 212 static void stmmac_global_err(struct stmmac_priv *priv) 213 { 214 netif_carrier_off(priv->dev); 215 set_bit(STMMAC_RESET_REQUESTED, &priv->state); 216 stmmac_service_event_schedule(priv); 217 } 218 219 /** 220 * stmmac_clk_csr_set - dynamically set the MDC clock 221 * @priv: driver private structure 222 * Description: this is to dynamically set the MDC clock according to the csr 223 * clock input. 224 * Note: 225 * If a specific clk_csr value is passed from the platform 226 * this means that the CSR Clock Range selection cannot be 227 * changed at run-time and it is fixed (as reported in the driver 228 * documentation). Viceversa the driver will try to set the MDC 229 * clock dynamically according to the actual clock input. 230 */ 231 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 232 { 233 u32 clk_rate; 234 235 clk_rate = clk_get_rate(priv->plat->stmmac_clk); 236 237 /* Platform provided default clk_csr would be assumed valid 238 * for all other cases except for the below mentioned ones. 239 * For values higher than the IEEE 802.3 specified frequency 240 * we can not estimate the proper divider as it is not known 241 * the frequency of clk_csr_i. So we do not change the default 242 * divider. 243 */ 244 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 245 if (clk_rate < CSR_F_35M) 246 priv->clk_csr = STMMAC_CSR_20_35M; 247 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 248 priv->clk_csr = STMMAC_CSR_35_60M; 249 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 250 priv->clk_csr = STMMAC_CSR_60_100M; 251 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 252 priv->clk_csr = STMMAC_CSR_100_150M; 253 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 254 priv->clk_csr = STMMAC_CSR_150_250M; 255 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) 256 priv->clk_csr = STMMAC_CSR_250_300M; 257 } 258 259 if (priv->plat->has_sun8i) { 260 if (clk_rate > 160000000) 261 priv->clk_csr = 0x03; 262 else if (clk_rate > 80000000) 263 priv->clk_csr = 0x02; 264 else if (clk_rate > 40000000) 265 priv->clk_csr = 0x01; 266 else 267 priv->clk_csr = 0; 268 } 269 270 if (priv->plat->has_xgmac) { 271 if (clk_rate > 400000000) 272 priv->clk_csr = 0x5; 273 else if (clk_rate > 350000000) 274 priv->clk_csr = 0x4; 275 else if (clk_rate > 300000000) 276 priv->clk_csr = 0x3; 277 else if (clk_rate > 250000000) 278 priv->clk_csr = 0x2; 279 else if (clk_rate > 150000000) 280 priv->clk_csr = 0x1; 281 else 282 priv->clk_csr = 0x0; 283 } 284 } 285 286 static void print_pkt(unsigned char *buf, int len) 287 { 288 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); 289 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); 290 } 291 292 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue) 293 { 294 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 295 u32 avail; 296 297 if (tx_q->dirty_tx > tx_q->cur_tx) 298 avail = tx_q->dirty_tx - tx_q->cur_tx - 1; 299 else 300 avail = DMA_TX_SIZE - tx_q->cur_tx + tx_q->dirty_tx - 1; 301 302 return avail; 303 } 304 305 /** 306 * stmmac_rx_dirty - Get RX queue dirty 307 * @priv: driver private structure 308 * @queue: RX queue index 309 */ 310 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue) 311 { 312 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 313 u32 dirty; 314 315 if (rx_q->dirty_rx <= rx_q->cur_rx) 316 dirty = rx_q->cur_rx - rx_q->dirty_rx; 317 else 318 dirty = DMA_RX_SIZE - rx_q->dirty_rx + rx_q->cur_rx; 319 320 return dirty; 321 } 322 323 /** 324 * stmmac_enable_eee_mode - check and enter in LPI mode 325 * @priv: driver private structure 326 * Description: this function is to verify and enter in LPI mode in case of 327 * EEE. 328 */ 329 static void stmmac_enable_eee_mode(struct stmmac_priv *priv) 330 { 331 u32 tx_cnt = priv->plat->tx_queues_to_use; 332 u32 queue; 333 334 /* check if all TX queues have the work finished */ 335 for (queue = 0; queue < tx_cnt; queue++) { 336 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 337 338 if (tx_q->dirty_tx != tx_q->cur_tx) 339 return; /* still unfinished work */ 340 } 341 342 /* Check and enter in LPI mode */ 343 if (!priv->tx_path_in_lpi_mode) 344 stmmac_set_eee_mode(priv, priv->hw, 345 priv->plat->en_tx_lpi_clockgating); 346 } 347 348 /** 349 * stmmac_disable_eee_mode - disable and exit from LPI mode 350 * @priv: driver private structure 351 * Description: this function is to exit and disable EEE in case of 352 * LPI state is true. This is called by the xmit. 353 */ 354 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 355 { 356 stmmac_reset_eee_mode(priv, priv->hw); 357 del_timer_sync(&priv->eee_ctrl_timer); 358 priv->tx_path_in_lpi_mode = false; 359 } 360 361 /** 362 * stmmac_eee_ctrl_timer - EEE TX SW timer. 363 * @arg : data hook 364 * Description: 365 * if there is no data transfer and if we are not in LPI state, 366 * then MAC Transmitter can be moved to LPI state. 367 */ 368 static void stmmac_eee_ctrl_timer(struct timer_list *t) 369 { 370 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer); 371 372 stmmac_enable_eee_mode(priv); 373 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 374 } 375 376 /** 377 * stmmac_eee_init - init EEE 378 * @priv: driver private structure 379 * Description: 380 * if the GMAC supports the EEE (from the HW cap reg) and the phy device 381 * can also manage EEE, this function enable the LPI state and start related 382 * timer. 383 */ 384 bool stmmac_eee_init(struct stmmac_priv *priv) 385 { 386 int tx_lpi_timer = priv->tx_lpi_timer; 387 388 /* Using PCS we cannot dial with the phy registers at this stage 389 * so we do not support extra feature like EEE. 390 */ 391 if (priv->hw->pcs == STMMAC_PCS_TBI || 392 priv->hw->pcs == STMMAC_PCS_RTBI) 393 return false; 394 395 /* Check if MAC core supports the EEE feature. */ 396 if (!priv->dma_cap.eee) 397 return false; 398 399 mutex_lock(&priv->lock); 400 401 /* Check if it needs to be deactivated */ 402 if (!priv->eee_active) { 403 if (priv->eee_enabled) { 404 netdev_dbg(priv->dev, "disable EEE\n"); 405 del_timer_sync(&priv->eee_ctrl_timer); 406 stmmac_set_eee_timer(priv, priv->hw, 0, tx_lpi_timer); 407 } 408 mutex_unlock(&priv->lock); 409 return false; 410 } 411 412 if (priv->eee_active && !priv->eee_enabled) { 413 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0); 414 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 415 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS, 416 tx_lpi_timer); 417 } 418 419 mutex_unlock(&priv->lock); 420 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n"); 421 return true; 422 } 423 424 /* stmmac_get_tx_hwtstamp - get HW TX timestamps 425 * @priv: driver private structure 426 * @p : descriptor pointer 427 * @skb : the socket buffer 428 * Description : 429 * This function will read timestamp from the descriptor & pass it to stack. 430 * and also perform some sanity checks. 431 */ 432 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 433 struct dma_desc *p, struct sk_buff *skb) 434 { 435 struct skb_shared_hwtstamps shhwtstamp; 436 bool found = false; 437 u64 ns = 0; 438 439 if (!priv->hwts_tx_en) 440 return; 441 442 /* exit if skb doesn't support hw tstamp */ 443 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 444 return; 445 446 /* check tx tstamp status */ 447 if (stmmac_get_tx_timestamp_status(priv, p)) { 448 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns); 449 found = true; 450 } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) { 451 found = true; 452 } 453 454 if (found) { 455 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 456 shhwtstamp.hwtstamp = ns_to_ktime(ns); 457 458 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns); 459 /* pass tstamp to stack */ 460 skb_tstamp_tx(skb, &shhwtstamp); 461 } 462 } 463 464 /* stmmac_get_rx_hwtstamp - get HW RX timestamps 465 * @priv: driver private structure 466 * @p : descriptor pointer 467 * @np : next descriptor pointer 468 * @skb : the socket buffer 469 * Description : 470 * This function will read received packet's timestamp from the descriptor 471 * and pass it to stack. It also perform some sanity checks. 472 */ 473 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, 474 struct dma_desc *np, struct sk_buff *skb) 475 { 476 struct skb_shared_hwtstamps *shhwtstamp = NULL; 477 struct dma_desc *desc = p; 478 u64 ns = 0; 479 480 if (!priv->hwts_rx_en) 481 return; 482 /* For GMAC4, the valid timestamp is from CTX next desc. */ 483 if (priv->plat->has_gmac4 || priv->plat->has_xgmac) 484 desc = np; 485 486 /* Check if timestamp is available */ 487 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) { 488 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns); 489 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns); 490 shhwtstamp = skb_hwtstamps(skb); 491 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 492 shhwtstamp->hwtstamp = ns_to_ktime(ns); 493 } else { 494 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n"); 495 } 496 } 497 498 /** 499 * stmmac_hwtstamp_set - control hardware timestamping. 500 * @dev: device pointer. 501 * @ifr: An IOCTL specific structure, that can contain a pointer to 502 * a proprietary structure used to pass information to the driver. 503 * Description: 504 * This function configures the MAC to enable/disable both outgoing(TX) 505 * and incoming(RX) packets time stamping based on user input. 506 * Return Value: 507 * 0 on success and an appropriate -ve integer on failure. 508 */ 509 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 510 { 511 struct stmmac_priv *priv = netdev_priv(dev); 512 struct hwtstamp_config config; 513 struct timespec64 now; 514 u64 temp = 0; 515 u32 ptp_v2 = 0; 516 u32 tstamp_all = 0; 517 u32 ptp_over_ipv4_udp = 0; 518 u32 ptp_over_ipv6_udp = 0; 519 u32 ptp_over_ethernet = 0; 520 u32 snap_type_sel = 0; 521 u32 ts_master_en = 0; 522 u32 ts_event_en = 0; 523 u32 sec_inc = 0; 524 u32 value = 0; 525 bool xmac; 526 527 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 528 529 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 530 netdev_alert(priv->dev, "No support for HW time stamping\n"); 531 priv->hwts_tx_en = 0; 532 priv->hwts_rx_en = 0; 533 534 return -EOPNOTSUPP; 535 } 536 537 if (copy_from_user(&config, ifr->ifr_data, 538 sizeof(config))) 539 return -EFAULT; 540 541 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 542 __func__, config.flags, config.tx_type, config.rx_filter); 543 544 /* reserved for future extensions */ 545 if (config.flags) 546 return -EINVAL; 547 548 if (config.tx_type != HWTSTAMP_TX_OFF && 549 config.tx_type != HWTSTAMP_TX_ON) 550 return -ERANGE; 551 552 if (priv->adv_ts) { 553 switch (config.rx_filter) { 554 case HWTSTAMP_FILTER_NONE: 555 /* time stamp no incoming packet at all */ 556 config.rx_filter = HWTSTAMP_FILTER_NONE; 557 break; 558 559 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 560 /* PTP v1, UDP, any kind of event packet */ 561 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 562 /* 'xmac' hardware can support Sync, Pdelay_Req and 563 * Pdelay_resp by setting bit14 and bits17/16 to 01 564 * This leaves Delay_Req timestamps out. 565 * Enable all events *and* general purpose message 566 * timestamping 567 */ 568 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 569 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 570 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 571 break; 572 573 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 574 /* PTP v1, UDP, Sync packet */ 575 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 576 /* take time stamp for SYNC messages only */ 577 ts_event_en = PTP_TCR_TSEVNTENA; 578 579 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 580 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 581 break; 582 583 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 584 /* PTP v1, UDP, Delay_req packet */ 585 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 586 /* take time stamp for Delay_Req messages only */ 587 ts_master_en = PTP_TCR_TSMSTRENA; 588 ts_event_en = PTP_TCR_TSEVNTENA; 589 590 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 591 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 592 break; 593 594 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 595 /* PTP v2, UDP, any kind of event packet */ 596 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 597 ptp_v2 = PTP_TCR_TSVER2ENA; 598 /* take time stamp for all event messages */ 599 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 600 601 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 602 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 603 break; 604 605 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 606 /* PTP v2, UDP, Sync packet */ 607 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 608 ptp_v2 = PTP_TCR_TSVER2ENA; 609 /* take time stamp for SYNC messages only */ 610 ts_event_en = PTP_TCR_TSEVNTENA; 611 612 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 613 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 614 break; 615 616 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 617 /* PTP v2, UDP, Delay_req packet */ 618 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 619 ptp_v2 = PTP_TCR_TSVER2ENA; 620 /* take time stamp for Delay_Req messages only */ 621 ts_master_en = PTP_TCR_TSMSTRENA; 622 ts_event_en = PTP_TCR_TSEVNTENA; 623 624 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 625 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 626 break; 627 628 case HWTSTAMP_FILTER_PTP_V2_EVENT: 629 /* PTP v2/802.AS1 any layer, any kind of event packet */ 630 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 631 ptp_v2 = PTP_TCR_TSVER2ENA; 632 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 633 if (priv->synopsys_id != DWMAC_CORE_5_10) 634 ts_event_en = PTP_TCR_TSEVNTENA; 635 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 636 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 637 ptp_over_ethernet = PTP_TCR_TSIPENA; 638 break; 639 640 case HWTSTAMP_FILTER_PTP_V2_SYNC: 641 /* PTP v2/802.AS1, any layer, Sync packet */ 642 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 643 ptp_v2 = PTP_TCR_TSVER2ENA; 644 /* take time stamp for SYNC messages only */ 645 ts_event_en = PTP_TCR_TSEVNTENA; 646 647 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 648 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 649 ptp_over_ethernet = PTP_TCR_TSIPENA; 650 break; 651 652 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 653 /* PTP v2/802.AS1, any layer, Delay_req packet */ 654 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 655 ptp_v2 = PTP_TCR_TSVER2ENA; 656 /* take time stamp for Delay_Req messages only */ 657 ts_master_en = PTP_TCR_TSMSTRENA; 658 ts_event_en = PTP_TCR_TSEVNTENA; 659 660 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 661 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 662 ptp_over_ethernet = PTP_TCR_TSIPENA; 663 break; 664 665 case HWTSTAMP_FILTER_NTP_ALL: 666 case HWTSTAMP_FILTER_ALL: 667 /* time stamp any incoming packet */ 668 config.rx_filter = HWTSTAMP_FILTER_ALL; 669 tstamp_all = PTP_TCR_TSENALL; 670 break; 671 672 default: 673 return -ERANGE; 674 } 675 } else { 676 switch (config.rx_filter) { 677 case HWTSTAMP_FILTER_NONE: 678 config.rx_filter = HWTSTAMP_FILTER_NONE; 679 break; 680 default: 681 /* PTP v1, UDP, any kind of event packet */ 682 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 683 break; 684 } 685 } 686 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 687 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 688 689 if (!priv->hwts_tx_en && !priv->hwts_rx_en) 690 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0); 691 else { 692 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | 693 tstamp_all | ptp_v2 | ptp_over_ethernet | 694 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | 695 ts_master_en | snap_type_sel); 696 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value); 697 698 /* program Sub Second Increment reg */ 699 stmmac_config_sub_second_increment(priv, 700 priv->ptpaddr, priv->plat->clk_ptp_rate, 701 xmac, &sec_inc); 702 temp = div_u64(1000000000ULL, sec_inc); 703 704 /* Store sub second increment and flags for later use */ 705 priv->sub_second_inc = sec_inc; 706 priv->systime_flags = value; 707 708 /* calculate default added value: 709 * formula is : 710 * addend = (2^32)/freq_div_ratio; 711 * where, freq_div_ratio = 1e9ns/sec_inc 712 */ 713 temp = (u64)(temp << 32); 714 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate); 715 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend); 716 717 /* initialize system time */ 718 ktime_get_real_ts64(&now); 719 720 /* lower 32 bits of tv_sec are safe until y2106 */ 721 stmmac_init_systime(priv, priv->ptpaddr, 722 (u32)now.tv_sec, now.tv_nsec); 723 } 724 725 memcpy(&priv->tstamp_config, &config, sizeof(config)); 726 727 return copy_to_user(ifr->ifr_data, &config, 728 sizeof(config)) ? -EFAULT : 0; 729 } 730 731 /** 732 * stmmac_hwtstamp_get - read hardware timestamping. 733 * @dev: device pointer. 734 * @ifr: An IOCTL specific structure, that can contain a pointer to 735 * a proprietary structure used to pass information to the driver. 736 * Description: 737 * This function obtain the current hardware timestamping settings 738 as requested. 739 */ 740 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 741 { 742 struct stmmac_priv *priv = netdev_priv(dev); 743 struct hwtstamp_config *config = &priv->tstamp_config; 744 745 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 746 return -EOPNOTSUPP; 747 748 return copy_to_user(ifr->ifr_data, config, 749 sizeof(*config)) ? -EFAULT : 0; 750 } 751 752 /** 753 * stmmac_init_ptp - init PTP 754 * @priv: driver private structure 755 * Description: this is to verify if the HW supports the PTPv1 or PTPv2. 756 * This is done by looking at the HW cap. register. 757 * This function also registers the ptp driver. 758 */ 759 static int stmmac_init_ptp(struct stmmac_priv *priv) 760 { 761 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 762 763 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 764 return -EOPNOTSUPP; 765 766 priv->adv_ts = 0; 767 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */ 768 if (xmac && priv->dma_cap.atime_stamp) 769 priv->adv_ts = 1; 770 /* Dwmac 3.x core with extend_desc can support adv_ts */ 771 else if (priv->extend_desc && priv->dma_cap.atime_stamp) 772 priv->adv_ts = 1; 773 774 if (priv->dma_cap.time_stamp) 775 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); 776 777 if (priv->adv_ts) 778 netdev_info(priv->dev, 779 "IEEE 1588-2008 Advanced Timestamp supported\n"); 780 781 priv->hwts_tx_en = 0; 782 priv->hwts_rx_en = 0; 783 784 stmmac_ptp_register(priv); 785 786 return 0; 787 } 788 789 static void stmmac_release_ptp(struct stmmac_priv *priv) 790 { 791 if (priv->plat->clk_ptp_ref) 792 clk_disable_unprepare(priv->plat->clk_ptp_ref); 793 stmmac_ptp_unregister(priv); 794 } 795 796 /** 797 * stmmac_mac_flow_ctrl - Configure flow control in all queues 798 * @priv: driver private structure 799 * Description: It is used for configuring the flow control in all queues 800 */ 801 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex) 802 { 803 u32 tx_cnt = priv->plat->tx_queues_to_use; 804 805 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl, 806 priv->pause, tx_cnt); 807 } 808 809 static void stmmac_validate(struct phylink_config *config, 810 unsigned long *supported, 811 struct phylink_link_state *state) 812 { 813 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 814 __ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, }; 815 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 816 int tx_cnt = priv->plat->tx_queues_to_use; 817 int max_speed = priv->plat->max_speed; 818 819 phylink_set(mac_supported, 10baseT_Half); 820 phylink_set(mac_supported, 10baseT_Full); 821 phylink_set(mac_supported, 100baseT_Half); 822 phylink_set(mac_supported, 100baseT_Full); 823 phylink_set(mac_supported, 1000baseT_Half); 824 phylink_set(mac_supported, 1000baseT_Full); 825 phylink_set(mac_supported, 1000baseKX_Full); 826 827 phylink_set(mac_supported, Autoneg); 828 phylink_set(mac_supported, Pause); 829 phylink_set(mac_supported, Asym_Pause); 830 phylink_set_port_modes(mac_supported); 831 832 /* Cut down 1G if asked to */ 833 if ((max_speed > 0) && (max_speed < 1000)) { 834 phylink_set(mask, 1000baseT_Full); 835 phylink_set(mask, 1000baseX_Full); 836 } else if (priv->plat->has_xgmac) { 837 if (!max_speed || (max_speed >= 2500)) { 838 phylink_set(mac_supported, 2500baseT_Full); 839 phylink_set(mac_supported, 2500baseX_Full); 840 } 841 if (!max_speed || (max_speed >= 5000)) { 842 phylink_set(mac_supported, 5000baseT_Full); 843 } 844 if (!max_speed || (max_speed >= 10000)) { 845 phylink_set(mac_supported, 10000baseSR_Full); 846 phylink_set(mac_supported, 10000baseLR_Full); 847 phylink_set(mac_supported, 10000baseER_Full); 848 phylink_set(mac_supported, 10000baseLRM_Full); 849 phylink_set(mac_supported, 10000baseT_Full); 850 phylink_set(mac_supported, 10000baseKX4_Full); 851 phylink_set(mac_supported, 10000baseKR_Full); 852 } 853 if (!max_speed || (max_speed >= 25000)) { 854 phylink_set(mac_supported, 25000baseCR_Full); 855 phylink_set(mac_supported, 25000baseKR_Full); 856 phylink_set(mac_supported, 25000baseSR_Full); 857 } 858 if (!max_speed || (max_speed >= 40000)) { 859 phylink_set(mac_supported, 40000baseKR4_Full); 860 phylink_set(mac_supported, 40000baseCR4_Full); 861 phylink_set(mac_supported, 40000baseSR4_Full); 862 phylink_set(mac_supported, 40000baseLR4_Full); 863 } 864 if (!max_speed || (max_speed >= 50000)) { 865 phylink_set(mac_supported, 50000baseCR2_Full); 866 phylink_set(mac_supported, 50000baseKR2_Full); 867 phylink_set(mac_supported, 50000baseSR2_Full); 868 phylink_set(mac_supported, 50000baseKR_Full); 869 phylink_set(mac_supported, 50000baseSR_Full); 870 phylink_set(mac_supported, 50000baseCR_Full); 871 phylink_set(mac_supported, 50000baseLR_ER_FR_Full); 872 phylink_set(mac_supported, 50000baseDR_Full); 873 } 874 if (!max_speed || (max_speed >= 100000)) { 875 phylink_set(mac_supported, 100000baseKR4_Full); 876 phylink_set(mac_supported, 100000baseSR4_Full); 877 phylink_set(mac_supported, 100000baseCR4_Full); 878 phylink_set(mac_supported, 100000baseLR4_ER4_Full); 879 phylink_set(mac_supported, 100000baseKR2_Full); 880 phylink_set(mac_supported, 100000baseSR2_Full); 881 phylink_set(mac_supported, 100000baseCR2_Full); 882 phylink_set(mac_supported, 100000baseLR2_ER2_FR2_Full); 883 phylink_set(mac_supported, 100000baseDR2_Full); 884 } 885 } 886 887 /* Half-Duplex can only work with single queue */ 888 if (tx_cnt > 1) { 889 phylink_set(mask, 10baseT_Half); 890 phylink_set(mask, 100baseT_Half); 891 phylink_set(mask, 1000baseT_Half); 892 } 893 894 linkmode_and(supported, supported, mac_supported); 895 linkmode_andnot(supported, supported, mask); 896 897 linkmode_and(state->advertising, state->advertising, mac_supported); 898 linkmode_andnot(state->advertising, state->advertising, mask); 899 900 /* If PCS is supported, check which modes it supports. */ 901 stmmac_xpcs_validate(priv, &priv->hw->xpcs_args, supported, state); 902 } 903 904 static void stmmac_mac_pcs_get_state(struct phylink_config *config, 905 struct phylink_link_state *state) 906 { 907 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 908 909 state->link = 0; 910 stmmac_xpcs_get_state(priv, &priv->hw->xpcs_args, state); 911 } 912 913 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode, 914 const struct phylink_link_state *state) 915 { 916 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 917 918 stmmac_xpcs_config(priv, &priv->hw->xpcs_args, state); 919 } 920 921 static void stmmac_mac_an_restart(struct phylink_config *config) 922 { 923 /* Not Supported */ 924 } 925 926 static void stmmac_mac_link_down(struct phylink_config *config, 927 unsigned int mode, phy_interface_t interface) 928 { 929 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 930 931 stmmac_mac_set(priv, priv->ioaddr, false); 932 priv->eee_active = false; 933 stmmac_eee_init(priv); 934 stmmac_set_eee_pls(priv, priv->hw, false); 935 } 936 937 static void stmmac_mac_link_up(struct phylink_config *config, 938 struct phy_device *phy, 939 unsigned int mode, phy_interface_t interface, 940 int speed, int duplex, 941 bool tx_pause, bool rx_pause) 942 { 943 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 944 u32 ctrl; 945 946 stmmac_xpcs_link_up(priv, &priv->hw->xpcs_args, speed, interface); 947 948 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 949 ctrl &= ~priv->hw->link.speed_mask; 950 951 if (interface == PHY_INTERFACE_MODE_USXGMII) { 952 switch (speed) { 953 case SPEED_10000: 954 ctrl |= priv->hw->link.xgmii.speed10000; 955 break; 956 case SPEED_5000: 957 ctrl |= priv->hw->link.xgmii.speed5000; 958 break; 959 case SPEED_2500: 960 ctrl |= priv->hw->link.xgmii.speed2500; 961 break; 962 default: 963 return; 964 } 965 } else if (interface == PHY_INTERFACE_MODE_XLGMII) { 966 switch (speed) { 967 case SPEED_100000: 968 ctrl |= priv->hw->link.xlgmii.speed100000; 969 break; 970 case SPEED_50000: 971 ctrl |= priv->hw->link.xlgmii.speed50000; 972 break; 973 case SPEED_40000: 974 ctrl |= priv->hw->link.xlgmii.speed40000; 975 break; 976 case SPEED_25000: 977 ctrl |= priv->hw->link.xlgmii.speed25000; 978 break; 979 case SPEED_10000: 980 ctrl |= priv->hw->link.xgmii.speed10000; 981 break; 982 case SPEED_2500: 983 ctrl |= priv->hw->link.speed2500; 984 break; 985 case SPEED_1000: 986 ctrl |= priv->hw->link.speed1000; 987 break; 988 default: 989 return; 990 } 991 } else { 992 switch (speed) { 993 case SPEED_2500: 994 ctrl |= priv->hw->link.speed2500; 995 break; 996 case SPEED_1000: 997 ctrl |= priv->hw->link.speed1000; 998 break; 999 case SPEED_100: 1000 ctrl |= priv->hw->link.speed100; 1001 break; 1002 case SPEED_10: 1003 ctrl |= priv->hw->link.speed10; 1004 break; 1005 default: 1006 return; 1007 } 1008 } 1009 1010 priv->speed = speed; 1011 1012 if (priv->plat->fix_mac_speed) 1013 priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed); 1014 1015 if (!duplex) 1016 ctrl &= ~priv->hw->link.duplex; 1017 else 1018 ctrl |= priv->hw->link.duplex; 1019 1020 /* Flow Control operation */ 1021 if (tx_pause && rx_pause) 1022 stmmac_mac_flow_ctrl(priv, duplex); 1023 1024 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 1025 1026 stmmac_mac_set(priv, priv->ioaddr, true); 1027 if (phy && priv->dma_cap.eee) { 1028 priv->eee_active = phy_init_eee(phy, 1) >= 0; 1029 priv->eee_enabled = stmmac_eee_init(priv); 1030 stmmac_set_eee_pls(priv, priv->hw, true); 1031 } 1032 } 1033 1034 static const struct phylink_mac_ops stmmac_phylink_mac_ops = { 1035 .validate = stmmac_validate, 1036 .mac_pcs_get_state = stmmac_mac_pcs_get_state, 1037 .mac_config = stmmac_mac_config, 1038 .mac_an_restart = stmmac_mac_an_restart, 1039 .mac_link_down = stmmac_mac_link_down, 1040 .mac_link_up = stmmac_mac_link_up, 1041 }; 1042 1043 /** 1044 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported 1045 * @priv: driver private structure 1046 * Description: this is to verify if the HW supports the PCS. 1047 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 1048 * configured for the TBI, RTBI, or SGMII PHY interface. 1049 */ 1050 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 1051 { 1052 int interface = priv->plat->interface; 1053 1054 if (priv->dma_cap.pcs) { 1055 if ((interface == PHY_INTERFACE_MODE_RGMII) || 1056 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 1057 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 1058 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 1059 netdev_dbg(priv->dev, "PCS RGMII support enabled\n"); 1060 priv->hw->pcs = STMMAC_PCS_RGMII; 1061 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 1062 netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); 1063 priv->hw->pcs = STMMAC_PCS_SGMII; 1064 } 1065 } 1066 } 1067 1068 /** 1069 * stmmac_init_phy - PHY initialization 1070 * @dev: net device structure 1071 * Description: it initializes the driver's PHY state, and attaches the PHY 1072 * to the mac driver. 1073 * Return value: 1074 * 0 on success 1075 */ 1076 static int stmmac_init_phy(struct net_device *dev) 1077 { 1078 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 1079 struct stmmac_priv *priv = netdev_priv(dev); 1080 struct device_node *node; 1081 int ret; 1082 1083 node = priv->plat->phylink_node; 1084 1085 if (node) 1086 ret = phylink_of_phy_connect(priv->phylink, node, 0); 1087 1088 /* Some DT bindings do not set-up the PHY handle. Let's try to 1089 * manually parse it 1090 */ 1091 if (!node || ret) { 1092 int addr = priv->plat->phy_addr; 1093 struct phy_device *phydev; 1094 1095 phydev = mdiobus_get_phy(priv->mii, addr); 1096 if (!phydev) { 1097 netdev_err(priv->dev, "no phy at addr %d\n", addr); 1098 return -ENODEV; 1099 } 1100 1101 ret = phylink_connect_phy(priv->phylink, phydev); 1102 } 1103 1104 phylink_ethtool_get_wol(priv->phylink, &wol); 1105 device_set_wakeup_capable(priv->device, !!wol.supported); 1106 1107 return ret; 1108 } 1109 1110 static int stmmac_phy_setup(struct stmmac_priv *priv) 1111 { 1112 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node); 1113 int mode = priv->plat->phy_interface; 1114 struct phylink *phylink; 1115 1116 priv->phylink_config.dev = &priv->dev->dev; 1117 priv->phylink_config.type = PHYLINK_NETDEV; 1118 priv->phylink_config.pcs_poll = true; 1119 1120 if (!fwnode) 1121 fwnode = dev_fwnode(priv->device); 1122 1123 phylink = phylink_create(&priv->phylink_config, fwnode, 1124 mode, &stmmac_phylink_mac_ops); 1125 if (IS_ERR(phylink)) 1126 return PTR_ERR(phylink); 1127 1128 priv->phylink = phylink; 1129 return 0; 1130 } 1131 1132 static void stmmac_display_rx_rings(struct stmmac_priv *priv) 1133 { 1134 u32 rx_cnt = priv->plat->rx_queues_to_use; 1135 void *head_rx; 1136 u32 queue; 1137 1138 /* Display RX rings */ 1139 for (queue = 0; queue < rx_cnt; queue++) { 1140 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1141 1142 pr_info("\tRX Queue %u rings\n", queue); 1143 1144 if (priv->extend_desc) 1145 head_rx = (void *)rx_q->dma_erx; 1146 else 1147 head_rx = (void *)rx_q->dma_rx; 1148 1149 /* Display RX ring */ 1150 stmmac_display_ring(priv, head_rx, DMA_RX_SIZE, true); 1151 } 1152 } 1153 1154 static void stmmac_display_tx_rings(struct stmmac_priv *priv) 1155 { 1156 u32 tx_cnt = priv->plat->tx_queues_to_use; 1157 void *head_tx; 1158 u32 queue; 1159 1160 /* Display TX rings */ 1161 for (queue = 0; queue < tx_cnt; queue++) { 1162 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1163 1164 pr_info("\tTX Queue %d rings\n", queue); 1165 1166 if (priv->extend_desc) 1167 head_tx = (void *)tx_q->dma_etx; 1168 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1169 head_tx = (void *)tx_q->dma_entx; 1170 else 1171 head_tx = (void *)tx_q->dma_tx; 1172 1173 stmmac_display_ring(priv, head_tx, DMA_TX_SIZE, false); 1174 } 1175 } 1176 1177 static void stmmac_display_rings(struct stmmac_priv *priv) 1178 { 1179 /* Display RX ring */ 1180 stmmac_display_rx_rings(priv); 1181 1182 /* Display TX ring */ 1183 stmmac_display_tx_rings(priv); 1184 } 1185 1186 static int stmmac_set_bfsize(int mtu, int bufsize) 1187 { 1188 int ret = bufsize; 1189 1190 if (mtu >= BUF_SIZE_8KiB) 1191 ret = BUF_SIZE_16KiB; 1192 else if (mtu >= BUF_SIZE_4KiB) 1193 ret = BUF_SIZE_8KiB; 1194 else if (mtu >= BUF_SIZE_2KiB) 1195 ret = BUF_SIZE_4KiB; 1196 else if (mtu > DEFAULT_BUFSIZE) 1197 ret = BUF_SIZE_2KiB; 1198 else 1199 ret = DEFAULT_BUFSIZE; 1200 1201 return ret; 1202 } 1203 1204 /** 1205 * stmmac_clear_rx_descriptors - clear RX descriptors 1206 * @priv: driver private structure 1207 * @queue: RX queue index 1208 * Description: this function is called to clear the RX descriptors 1209 * in case of both basic and extended descriptors are used. 1210 */ 1211 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue) 1212 { 1213 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1214 int i; 1215 1216 /* Clear the RX descriptors */ 1217 for (i = 0; i < DMA_RX_SIZE; i++) 1218 if (priv->extend_desc) 1219 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic, 1220 priv->use_riwt, priv->mode, 1221 (i == DMA_RX_SIZE - 1), 1222 priv->dma_buf_sz); 1223 else 1224 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i], 1225 priv->use_riwt, priv->mode, 1226 (i == DMA_RX_SIZE - 1), 1227 priv->dma_buf_sz); 1228 } 1229 1230 /** 1231 * stmmac_clear_tx_descriptors - clear tx descriptors 1232 * @priv: driver private structure 1233 * @queue: TX queue index. 1234 * Description: this function is called to clear the TX descriptors 1235 * in case of both basic and extended descriptors are used. 1236 */ 1237 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue) 1238 { 1239 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1240 int i; 1241 1242 /* Clear the TX descriptors */ 1243 for (i = 0; i < DMA_TX_SIZE; i++) { 1244 int last = (i == (DMA_TX_SIZE - 1)); 1245 struct dma_desc *p; 1246 1247 if (priv->extend_desc) 1248 p = &tx_q->dma_etx[i].basic; 1249 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1250 p = &tx_q->dma_entx[i].basic; 1251 else 1252 p = &tx_q->dma_tx[i]; 1253 1254 stmmac_init_tx_desc(priv, p, priv->mode, last); 1255 } 1256 } 1257 1258 /** 1259 * stmmac_clear_descriptors - clear descriptors 1260 * @priv: driver private structure 1261 * Description: this function is called to clear the TX and RX descriptors 1262 * in case of both basic and extended descriptors are used. 1263 */ 1264 static void stmmac_clear_descriptors(struct stmmac_priv *priv) 1265 { 1266 u32 rx_queue_cnt = priv->plat->rx_queues_to_use; 1267 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1268 u32 queue; 1269 1270 /* Clear the RX descriptors */ 1271 for (queue = 0; queue < rx_queue_cnt; queue++) 1272 stmmac_clear_rx_descriptors(priv, queue); 1273 1274 /* Clear the TX descriptors */ 1275 for (queue = 0; queue < tx_queue_cnt; queue++) 1276 stmmac_clear_tx_descriptors(priv, queue); 1277 } 1278 1279 /** 1280 * stmmac_init_rx_buffers - init the RX descriptor buffer. 1281 * @priv: driver private structure 1282 * @p: descriptor pointer 1283 * @i: descriptor index 1284 * @flags: gfp flag 1285 * @queue: RX queue index 1286 * Description: this function is called to allocate a receive buffer, perform 1287 * the DMA mapping and init the descriptor. 1288 */ 1289 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, 1290 int i, gfp_t flags, u32 queue) 1291 { 1292 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1293 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1294 1295 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); 1296 if (!buf->page) 1297 return -ENOMEM; 1298 1299 if (priv->sph) { 1300 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); 1301 if (!buf->sec_page) 1302 return -ENOMEM; 1303 1304 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 1305 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr); 1306 } else { 1307 buf->sec_page = NULL; 1308 } 1309 1310 buf->addr = page_pool_get_dma_addr(buf->page); 1311 stmmac_set_desc_addr(priv, p, buf->addr); 1312 if (priv->dma_buf_sz == BUF_SIZE_16KiB) 1313 stmmac_init_desc3(priv, p); 1314 1315 return 0; 1316 } 1317 1318 /** 1319 * stmmac_free_rx_buffer - free RX dma buffers 1320 * @priv: private structure 1321 * @queue: RX queue index 1322 * @i: buffer index. 1323 */ 1324 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i) 1325 { 1326 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1327 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1328 1329 if (buf->page) 1330 page_pool_put_full_page(rx_q->page_pool, buf->page, false); 1331 buf->page = NULL; 1332 1333 if (buf->sec_page) 1334 page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false); 1335 buf->sec_page = NULL; 1336 } 1337 1338 /** 1339 * stmmac_free_tx_buffer - free RX dma buffers 1340 * @priv: private structure 1341 * @queue: RX queue index 1342 * @i: buffer index. 1343 */ 1344 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i) 1345 { 1346 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1347 1348 if (tx_q->tx_skbuff_dma[i].buf) { 1349 if (tx_q->tx_skbuff_dma[i].map_as_page) 1350 dma_unmap_page(priv->device, 1351 tx_q->tx_skbuff_dma[i].buf, 1352 tx_q->tx_skbuff_dma[i].len, 1353 DMA_TO_DEVICE); 1354 else 1355 dma_unmap_single(priv->device, 1356 tx_q->tx_skbuff_dma[i].buf, 1357 tx_q->tx_skbuff_dma[i].len, 1358 DMA_TO_DEVICE); 1359 } 1360 1361 if (tx_q->tx_skbuff[i]) { 1362 dev_kfree_skb_any(tx_q->tx_skbuff[i]); 1363 tx_q->tx_skbuff[i] = NULL; 1364 tx_q->tx_skbuff_dma[i].buf = 0; 1365 tx_q->tx_skbuff_dma[i].map_as_page = false; 1366 } 1367 } 1368 1369 /** 1370 * init_dma_rx_desc_rings - init the RX descriptor rings 1371 * @dev: net device structure 1372 * @flags: gfp flag. 1373 * Description: this function initializes the DMA RX descriptors 1374 * and allocates the socket buffers. It supports the chained and ring 1375 * modes. 1376 */ 1377 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags) 1378 { 1379 struct stmmac_priv *priv = netdev_priv(dev); 1380 u32 rx_count = priv->plat->rx_queues_to_use; 1381 int ret = -ENOMEM; 1382 int queue; 1383 int i; 1384 1385 /* RX INITIALIZATION */ 1386 netif_dbg(priv, probe, priv->dev, 1387 "SKB addresses:\nskb\t\tskb data\tdma data\n"); 1388 1389 for (queue = 0; queue < rx_count; queue++) { 1390 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1391 1392 netif_dbg(priv, probe, priv->dev, 1393 "(%s) dma_rx_phy=0x%08x\n", __func__, 1394 (u32)rx_q->dma_rx_phy); 1395 1396 stmmac_clear_rx_descriptors(priv, queue); 1397 1398 for (i = 0; i < DMA_RX_SIZE; i++) { 1399 struct dma_desc *p; 1400 1401 if (priv->extend_desc) 1402 p = &((rx_q->dma_erx + i)->basic); 1403 else 1404 p = rx_q->dma_rx + i; 1405 1406 ret = stmmac_init_rx_buffers(priv, p, i, flags, 1407 queue); 1408 if (ret) 1409 goto err_init_rx_buffers; 1410 } 1411 1412 rx_q->cur_rx = 0; 1413 rx_q->dirty_rx = (unsigned int)(i - DMA_RX_SIZE); 1414 1415 /* Setup the chained descriptor addresses */ 1416 if (priv->mode == STMMAC_CHAIN_MODE) { 1417 if (priv->extend_desc) 1418 stmmac_mode_init(priv, rx_q->dma_erx, 1419 rx_q->dma_rx_phy, DMA_RX_SIZE, 1); 1420 else 1421 stmmac_mode_init(priv, rx_q->dma_rx, 1422 rx_q->dma_rx_phy, DMA_RX_SIZE, 0); 1423 } 1424 } 1425 1426 return 0; 1427 1428 err_init_rx_buffers: 1429 while (queue >= 0) { 1430 while (--i >= 0) 1431 stmmac_free_rx_buffer(priv, queue, i); 1432 1433 if (queue == 0) 1434 break; 1435 1436 i = DMA_RX_SIZE; 1437 queue--; 1438 } 1439 1440 return ret; 1441 } 1442 1443 /** 1444 * init_dma_tx_desc_rings - init the TX descriptor rings 1445 * @dev: net device structure. 1446 * Description: this function initializes the DMA TX descriptors 1447 * and allocates the socket buffers. It supports the chained and ring 1448 * modes. 1449 */ 1450 static int init_dma_tx_desc_rings(struct net_device *dev) 1451 { 1452 struct stmmac_priv *priv = netdev_priv(dev); 1453 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1454 u32 queue; 1455 int i; 1456 1457 for (queue = 0; queue < tx_queue_cnt; queue++) { 1458 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1459 1460 netif_dbg(priv, probe, priv->dev, 1461 "(%s) dma_tx_phy=0x%08x\n", __func__, 1462 (u32)tx_q->dma_tx_phy); 1463 1464 /* Setup the chained descriptor addresses */ 1465 if (priv->mode == STMMAC_CHAIN_MODE) { 1466 if (priv->extend_desc) 1467 stmmac_mode_init(priv, tx_q->dma_etx, 1468 tx_q->dma_tx_phy, DMA_TX_SIZE, 1); 1469 else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) 1470 stmmac_mode_init(priv, tx_q->dma_tx, 1471 tx_q->dma_tx_phy, DMA_TX_SIZE, 0); 1472 } 1473 1474 for (i = 0; i < DMA_TX_SIZE; i++) { 1475 struct dma_desc *p; 1476 if (priv->extend_desc) 1477 p = &((tx_q->dma_etx + i)->basic); 1478 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1479 p = &((tx_q->dma_entx + i)->basic); 1480 else 1481 p = tx_q->dma_tx + i; 1482 1483 stmmac_clear_desc(priv, p); 1484 1485 tx_q->tx_skbuff_dma[i].buf = 0; 1486 tx_q->tx_skbuff_dma[i].map_as_page = false; 1487 tx_q->tx_skbuff_dma[i].len = 0; 1488 tx_q->tx_skbuff_dma[i].last_segment = false; 1489 tx_q->tx_skbuff[i] = NULL; 1490 } 1491 1492 tx_q->dirty_tx = 0; 1493 tx_q->cur_tx = 0; 1494 tx_q->mss = 0; 1495 1496 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); 1497 } 1498 1499 return 0; 1500 } 1501 1502 /** 1503 * init_dma_desc_rings - init the RX/TX descriptor rings 1504 * @dev: net device structure 1505 * @flags: gfp flag. 1506 * Description: this function initializes the DMA RX/TX descriptors 1507 * and allocates the socket buffers. It supports the chained and ring 1508 * modes. 1509 */ 1510 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags) 1511 { 1512 struct stmmac_priv *priv = netdev_priv(dev); 1513 int ret; 1514 1515 ret = init_dma_rx_desc_rings(dev, flags); 1516 if (ret) 1517 return ret; 1518 1519 ret = init_dma_tx_desc_rings(dev); 1520 1521 stmmac_clear_descriptors(priv); 1522 1523 if (netif_msg_hw(priv)) 1524 stmmac_display_rings(priv); 1525 1526 return ret; 1527 } 1528 1529 /** 1530 * dma_free_rx_skbufs - free RX dma buffers 1531 * @priv: private structure 1532 * @queue: RX queue index 1533 */ 1534 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue) 1535 { 1536 int i; 1537 1538 for (i = 0; i < DMA_RX_SIZE; i++) 1539 stmmac_free_rx_buffer(priv, queue, i); 1540 } 1541 1542 /** 1543 * dma_free_tx_skbufs - free TX dma buffers 1544 * @priv: private structure 1545 * @queue: TX queue index 1546 */ 1547 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue) 1548 { 1549 int i; 1550 1551 for (i = 0; i < DMA_TX_SIZE; i++) 1552 stmmac_free_tx_buffer(priv, queue, i); 1553 } 1554 1555 /** 1556 * free_dma_rx_desc_resources - free RX dma desc resources 1557 * @priv: private structure 1558 */ 1559 static void free_dma_rx_desc_resources(struct stmmac_priv *priv) 1560 { 1561 u32 rx_count = priv->plat->rx_queues_to_use; 1562 u32 queue; 1563 1564 /* Free RX queue resources */ 1565 for (queue = 0; queue < rx_count; queue++) { 1566 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1567 1568 /* Release the DMA RX socket buffers */ 1569 dma_free_rx_skbufs(priv, queue); 1570 1571 /* Free DMA regions of consistent memory previously allocated */ 1572 if (!priv->extend_desc) 1573 dma_free_coherent(priv->device, 1574 DMA_RX_SIZE * sizeof(struct dma_desc), 1575 rx_q->dma_rx, rx_q->dma_rx_phy); 1576 else 1577 dma_free_coherent(priv->device, DMA_RX_SIZE * 1578 sizeof(struct dma_extended_desc), 1579 rx_q->dma_erx, rx_q->dma_rx_phy); 1580 1581 kfree(rx_q->buf_pool); 1582 if (rx_q->page_pool) 1583 page_pool_destroy(rx_q->page_pool); 1584 } 1585 } 1586 1587 /** 1588 * free_dma_tx_desc_resources - free TX dma desc resources 1589 * @priv: private structure 1590 */ 1591 static void free_dma_tx_desc_resources(struct stmmac_priv *priv) 1592 { 1593 u32 tx_count = priv->plat->tx_queues_to_use; 1594 u32 queue; 1595 1596 /* Free TX queue resources */ 1597 for (queue = 0; queue < tx_count; queue++) { 1598 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1599 size_t size; 1600 void *addr; 1601 1602 /* Release the DMA TX socket buffers */ 1603 dma_free_tx_skbufs(priv, queue); 1604 1605 if (priv->extend_desc) { 1606 size = sizeof(struct dma_extended_desc); 1607 addr = tx_q->dma_etx; 1608 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1609 size = sizeof(struct dma_edesc); 1610 addr = tx_q->dma_entx; 1611 } else { 1612 size = sizeof(struct dma_desc); 1613 addr = tx_q->dma_tx; 1614 } 1615 1616 size *= DMA_TX_SIZE; 1617 1618 dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy); 1619 1620 kfree(tx_q->tx_skbuff_dma); 1621 kfree(tx_q->tx_skbuff); 1622 } 1623 } 1624 1625 /** 1626 * alloc_dma_rx_desc_resources - alloc RX resources. 1627 * @priv: private structure 1628 * Description: according to which descriptor can be used (extend or basic) 1629 * this function allocates the resources for TX and RX paths. In case of 1630 * reception, for example, it pre-allocated the RX socket buffer in order to 1631 * allow zero-copy mechanism. 1632 */ 1633 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv) 1634 { 1635 u32 rx_count = priv->plat->rx_queues_to_use; 1636 int ret = -ENOMEM; 1637 u32 queue; 1638 1639 /* RX queues buffers and DMA */ 1640 for (queue = 0; queue < rx_count; queue++) { 1641 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1642 struct page_pool_params pp_params = { 0 }; 1643 unsigned int num_pages; 1644 1645 rx_q->queue_index = queue; 1646 rx_q->priv_data = priv; 1647 1648 pp_params.flags = PP_FLAG_DMA_MAP; 1649 pp_params.pool_size = DMA_RX_SIZE; 1650 num_pages = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE); 1651 pp_params.order = ilog2(num_pages); 1652 pp_params.nid = dev_to_node(priv->device); 1653 pp_params.dev = priv->device; 1654 pp_params.dma_dir = DMA_FROM_DEVICE; 1655 1656 rx_q->page_pool = page_pool_create(&pp_params); 1657 if (IS_ERR(rx_q->page_pool)) { 1658 ret = PTR_ERR(rx_q->page_pool); 1659 rx_q->page_pool = NULL; 1660 goto err_dma; 1661 } 1662 1663 rx_q->buf_pool = kcalloc(DMA_RX_SIZE, sizeof(*rx_q->buf_pool), 1664 GFP_KERNEL); 1665 if (!rx_q->buf_pool) 1666 goto err_dma; 1667 1668 if (priv->extend_desc) { 1669 rx_q->dma_erx = dma_alloc_coherent(priv->device, 1670 DMA_RX_SIZE * sizeof(struct dma_extended_desc), 1671 &rx_q->dma_rx_phy, 1672 GFP_KERNEL); 1673 if (!rx_q->dma_erx) 1674 goto err_dma; 1675 1676 } else { 1677 rx_q->dma_rx = dma_alloc_coherent(priv->device, 1678 DMA_RX_SIZE * sizeof(struct dma_desc), 1679 &rx_q->dma_rx_phy, 1680 GFP_KERNEL); 1681 if (!rx_q->dma_rx) 1682 goto err_dma; 1683 } 1684 } 1685 1686 return 0; 1687 1688 err_dma: 1689 free_dma_rx_desc_resources(priv); 1690 1691 return ret; 1692 } 1693 1694 /** 1695 * alloc_dma_tx_desc_resources - alloc TX resources. 1696 * @priv: private structure 1697 * Description: according to which descriptor can be used (extend or basic) 1698 * this function allocates the resources for TX and RX paths. In case of 1699 * reception, for example, it pre-allocated the RX socket buffer in order to 1700 * allow zero-copy mechanism. 1701 */ 1702 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv) 1703 { 1704 u32 tx_count = priv->plat->tx_queues_to_use; 1705 int ret = -ENOMEM; 1706 u32 queue; 1707 1708 /* TX queues buffers and DMA */ 1709 for (queue = 0; queue < tx_count; queue++) { 1710 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1711 size_t size; 1712 void *addr; 1713 1714 tx_q->queue_index = queue; 1715 tx_q->priv_data = priv; 1716 1717 tx_q->tx_skbuff_dma = kcalloc(DMA_TX_SIZE, 1718 sizeof(*tx_q->tx_skbuff_dma), 1719 GFP_KERNEL); 1720 if (!tx_q->tx_skbuff_dma) 1721 goto err_dma; 1722 1723 tx_q->tx_skbuff = kcalloc(DMA_TX_SIZE, 1724 sizeof(struct sk_buff *), 1725 GFP_KERNEL); 1726 if (!tx_q->tx_skbuff) 1727 goto err_dma; 1728 1729 if (priv->extend_desc) 1730 size = sizeof(struct dma_extended_desc); 1731 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1732 size = sizeof(struct dma_edesc); 1733 else 1734 size = sizeof(struct dma_desc); 1735 1736 size *= DMA_TX_SIZE; 1737 1738 addr = dma_alloc_coherent(priv->device, size, 1739 &tx_q->dma_tx_phy, GFP_KERNEL); 1740 if (!addr) 1741 goto err_dma; 1742 1743 if (priv->extend_desc) 1744 tx_q->dma_etx = addr; 1745 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1746 tx_q->dma_entx = addr; 1747 else 1748 tx_q->dma_tx = addr; 1749 } 1750 1751 return 0; 1752 1753 err_dma: 1754 free_dma_tx_desc_resources(priv); 1755 return ret; 1756 } 1757 1758 /** 1759 * alloc_dma_desc_resources - alloc TX/RX resources. 1760 * @priv: private structure 1761 * Description: according to which descriptor can be used (extend or basic) 1762 * this function allocates the resources for TX and RX paths. In case of 1763 * reception, for example, it pre-allocated the RX socket buffer in order to 1764 * allow zero-copy mechanism. 1765 */ 1766 static int alloc_dma_desc_resources(struct stmmac_priv *priv) 1767 { 1768 /* RX Allocation */ 1769 int ret = alloc_dma_rx_desc_resources(priv); 1770 1771 if (ret) 1772 return ret; 1773 1774 ret = alloc_dma_tx_desc_resources(priv); 1775 1776 return ret; 1777 } 1778 1779 /** 1780 * free_dma_desc_resources - free dma desc resources 1781 * @priv: private structure 1782 */ 1783 static void free_dma_desc_resources(struct stmmac_priv *priv) 1784 { 1785 /* Release the DMA RX socket buffers */ 1786 free_dma_rx_desc_resources(priv); 1787 1788 /* Release the DMA TX socket buffers */ 1789 free_dma_tx_desc_resources(priv); 1790 } 1791 1792 /** 1793 * stmmac_mac_enable_rx_queues - Enable MAC rx queues 1794 * @priv: driver private structure 1795 * Description: It is used for enabling the rx queues in the MAC 1796 */ 1797 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) 1798 { 1799 u32 rx_queues_count = priv->plat->rx_queues_to_use; 1800 int queue; 1801 u8 mode; 1802 1803 for (queue = 0; queue < rx_queues_count; queue++) { 1804 mode = priv->plat->rx_queues_cfg[queue].mode_to_use; 1805 stmmac_rx_queue_enable(priv, priv->hw, mode, queue); 1806 } 1807 } 1808 1809 /** 1810 * stmmac_start_rx_dma - start RX DMA channel 1811 * @priv: driver private structure 1812 * @chan: RX channel index 1813 * Description: 1814 * This starts a RX DMA channel 1815 */ 1816 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan) 1817 { 1818 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan); 1819 stmmac_start_rx(priv, priv->ioaddr, chan); 1820 } 1821 1822 /** 1823 * stmmac_start_tx_dma - start TX DMA channel 1824 * @priv: driver private structure 1825 * @chan: TX channel index 1826 * Description: 1827 * This starts a TX DMA channel 1828 */ 1829 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan) 1830 { 1831 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan); 1832 stmmac_start_tx(priv, priv->ioaddr, chan); 1833 } 1834 1835 /** 1836 * stmmac_stop_rx_dma - stop RX DMA channel 1837 * @priv: driver private structure 1838 * @chan: RX channel index 1839 * Description: 1840 * This stops a RX DMA channel 1841 */ 1842 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan) 1843 { 1844 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan); 1845 stmmac_stop_rx(priv, priv->ioaddr, chan); 1846 } 1847 1848 /** 1849 * stmmac_stop_tx_dma - stop TX DMA channel 1850 * @priv: driver private structure 1851 * @chan: TX channel index 1852 * Description: 1853 * This stops a TX DMA channel 1854 */ 1855 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan) 1856 { 1857 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan); 1858 stmmac_stop_tx(priv, priv->ioaddr, chan); 1859 } 1860 1861 /** 1862 * stmmac_start_all_dma - start all RX and TX DMA channels 1863 * @priv: driver private structure 1864 * Description: 1865 * This starts all the RX and TX DMA channels 1866 */ 1867 static void stmmac_start_all_dma(struct stmmac_priv *priv) 1868 { 1869 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1870 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1871 u32 chan = 0; 1872 1873 for (chan = 0; chan < rx_channels_count; chan++) 1874 stmmac_start_rx_dma(priv, chan); 1875 1876 for (chan = 0; chan < tx_channels_count; chan++) 1877 stmmac_start_tx_dma(priv, chan); 1878 } 1879 1880 /** 1881 * stmmac_stop_all_dma - stop all RX and TX DMA channels 1882 * @priv: driver private structure 1883 * Description: 1884 * This stops the RX and TX DMA channels 1885 */ 1886 static void stmmac_stop_all_dma(struct stmmac_priv *priv) 1887 { 1888 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1889 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1890 u32 chan = 0; 1891 1892 for (chan = 0; chan < rx_channels_count; chan++) 1893 stmmac_stop_rx_dma(priv, chan); 1894 1895 for (chan = 0; chan < tx_channels_count; chan++) 1896 stmmac_stop_tx_dma(priv, chan); 1897 } 1898 1899 /** 1900 * stmmac_dma_operation_mode - HW DMA operation mode 1901 * @priv: driver private structure 1902 * Description: it is used for configuring the DMA operation mode register in 1903 * order to program the tx/rx DMA thresholds or Store-And-Forward mode. 1904 */ 1905 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 1906 { 1907 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1908 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1909 int rxfifosz = priv->plat->rx_fifo_size; 1910 int txfifosz = priv->plat->tx_fifo_size; 1911 u32 txmode = 0; 1912 u32 rxmode = 0; 1913 u32 chan = 0; 1914 u8 qmode = 0; 1915 1916 if (rxfifosz == 0) 1917 rxfifosz = priv->dma_cap.rx_fifo_size; 1918 if (txfifosz == 0) 1919 txfifosz = priv->dma_cap.tx_fifo_size; 1920 1921 /* Adjust for real per queue fifo size */ 1922 rxfifosz /= rx_channels_count; 1923 txfifosz /= tx_channels_count; 1924 1925 if (priv->plat->force_thresh_dma_mode) { 1926 txmode = tc; 1927 rxmode = tc; 1928 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 1929 /* 1930 * In case of GMAC, SF mode can be enabled 1931 * to perform the TX COE in HW. This depends on: 1932 * 1) TX COE if actually supported 1933 * 2) There is no bugged Jumbo frame support 1934 * that needs to not insert csum in the TDES. 1935 */ 1936 txmode = SF_DMA_MODE; 1937 rxmode = SF_DMA_MODE; 1938 priv->xstats.threshold = SF_DMA_MODE; 1939 } else { 1940 txmode = tc; 1941 rxmode = SF_DMA_MODE; 1942 } 1943 1944 /* configure all channels */ 1945 for (chan = 0; chan < rx_channels_count; chan++) { 1946 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 1947 1948 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, 1949 rxfifosz, qmode); 1950 stmmac_set_dma_bfsize(priv, priv->ioaddr, priv->dma_buf_sz, 1951 chan); 1952 } 1953 1954 for (chan = 0; chan < tx_channels_count; chan++) { 1955 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 1956 1957 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, 1958 txfifosz, qmode); 1959 } 1960 } 1961 1962 /** 1963 * stmmac_tx_clean - to manage the transmission completion 1964 * @priv: driver private structure 1965 * @queue: TX queue index 1966 * Description: it reclaims the transmit resources after transmission completes. 1967 */ 1968 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue) 1969 { 1970 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1971 unsigned int bytes_compl = 0, pkts_compl = 0; 1972 unsigned int entry, count = 0; 1973 1974 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue)); 1975 1976 priv->xstats.tx_clean++; 1977 1978 entry = tx_q->dirty_tx; 1979 while ((entry != tx_q->cur_tx) && (count < budget)) { 1980 struct sk_buff *skb = tx_q->tx_skbuff[entry]; 1981 struct dma_desc *p; 1982 int status; 1983 1984 if (priv->extend_desc) 1985 p = (struct dma_desc *)(tx_q->dma_etx + entry); 1986 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1987 p = &tx_q->dma_entx[entry].basic; 1988 else 1989 p = tx_q->dma_tx + entry; 1990 1991 status = stmmac_tx_status(priv, &priv->dev->stats, 1992 &priv->xstats, p, priv->ioaddr); 1993 /* Check if the descriptor is owned by the DMA */ 1994 if (unlikely(status & tx_dma_own)) 1995 break; 1996 1997 count++; 1998 1999 /* Make sure descriptor fields are read after reading 2000 * the own bit. 2001 */ 2002 dma_rmb(); 2003 2004 /* Just consider the last segment and ...*/ 2005 if (likely(!(status & tx_not_ls))) { 2006 /* ... verify the status error condition */ 2007 if (unlikely(status & tx_err)) { 2008 priv->dev->stats.tx_errors++; 2009 } else { 2010 priv->dev->stats.tx_packets++; 2011 priv->xstats.tx_pkt_n++; 2012 } 2013 stmmac_get_tx_hwtstamp(priv, p, skb); 2014 } 2015 2016 if (likely(tx_q->tx_skbuff_dma[entry].buf)) { 2017 if (tx_q->tx_skbuff_dma[entry].map_as_page) 2018 dma_unmap_page(priv->device, 2019 tx_q->tx_skbuff_dma[entry].buf, 2020 tx_q->tx_skbuff_dma[entry].len, 2021 DMA_TO_DEVICE); 2022 else 2023 dma_unmap_single(priv->device, 2024 tx_q->tx_skbuff_dma[entry].buf, 2025 tx_q->tx_skbuff_dma[entry].len, 2026 DMA_TO_DEVICE); 2027 tx_q->tx_skbuff_dma[entry].buf = 0; 2028 tx_q->tx_skbuff_dma[entry].len = 0; 2029 tx_q->tx_skbuff_dma[entry].map_as_page = false; 2030 } 2031 2032 stmmac_clean_desc3(priv, tx_q, p); 2033 2034 tx_q->tx_skbuff_dma[entry].last_segment = false; 2035 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 2036 2037 if (likely(skb != NULL)) { 2038 pkts_compl++; 2039 bytes_compl += skb->len; 2040 dev_consume_skb_any(skb); 2041 tx_q->tx_skbuff[entry] = NULL; 2042 } 2043 2044 stmmac_release_tx_desc(priv, p, priv->mode); 2045 2046 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 2047 } 2048 tx_q->dirty_tx = entry; 2049 2050 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue), 2051 pkts_compl, bytes_compl); 2052 2053 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev, 2054 queue))) && 2055 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH) { 2056 2057 netif_dbg(priv, tx_done, priv->dev, 2058 "%s: restart transmit\n", __func__); 2059 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue)); 2060 } 2061 2062 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) { 2063 stmmac_enable_eee_mode(priv); 2064 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 2065 } 2066 2067 /* We still have pending packets, let's call for a new scheduling */ 2068 if (tx_q->dirty_tx != tx_q->cur_tx) 2069 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer)); 2070 2071 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue)); 2072 2073 return count; 2074 } 2075 2076 /** 2077 * stmmac_tx_err - to manage the tx error 2078 * @priv: driver private structure 2079 * @chan: channel index 2080 * Description: it cleans the descriptors and restarts the transmission 2081 * in case of transmission errors. 2082 */ 2083 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan) 2084 { 2085 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2086 2087 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan)); 2088 2089 stmmac_stop_tx_dma(priv, chan); 2090 dma_free_tx_skbufs(priv, chan); 2091 stmmac_clear_tx_descriptors(priv, chan); 2092 tx_q->dirty_tx = 0; 2093 tx_q->cur_tx = 0; 2094 tx_q->mss = 0; 2095 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan)); 2096 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2097 tx_q->dma_tx_phy, chan); 2098 stmmac_start_tx_dma(priv, chan); 2099 2100 priv->dev->stats.tx_errors++; 2101 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan)); 2102 } 2103 2104 /** 2105 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel 2106 * @priv: driver private structure 2107 * @txmode: TX operating mode 2108 * @rxmode: RX operating mode 2109 * @chan: channel index 2110 * Description: it is used for configuring of the DMA operation mode in 2111 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward 2112 * mode. 2113 */ 2114 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 2115 u32 rxmode, u32 chan) 2116 { 2117 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2118 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2119 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2120 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2121 int rxfifosz = priv->plat->rx_fifo_size; 2122 int txfifosz = priv->plat->tx_fifo_size; 2123 2124 if (rxfifosz == 0) 2125 rxfifosz = priv->dma_cap.rx_fifo_size; 2126 if (txfifosz == 0) 2127 txfifosz = priv->dma_cap.tx_fifo_size; 2128 2129 /* Adjust for real per queue fifo size */ 2130 rxfifosz /= rx_channels_count; 2131 txfifosz /= tx_channels_count; 2132 2133 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode); 2134 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode); 2135 } 2136 2137 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv) 2138 { 2139 int ret; 2140 2141 ret = stmmac_safety_feat_irq_status(priv, priv->dev, 2142 priv->ioaddr, priv->dma_cap.asp, &priv->sstats); 2143 if (ret && (ret != -EINVAL)) { 2144 stmmac_global_err(priv); 2145 return true; 2146 } 2147 2148 return false; 2149 } 2150 2151 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan) 2152 { 2153 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr, 2154 &priv->xstats, chan); 2155 struct stmmac_channel *ch = &priv->channel[chan]; 2156 unsigned long flags; 2157 2158 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) { 2159 if (napi_schedule_prep(&ch->rx_napi)) { 2160 spin_lock_irqsave(&ch->lock, flags); 2161 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 2162 spin_unlock_irqrestore(&ch->lock, flags); 2163 __napi_schedule_irqoff(&ch->rx_napi); 2164 } 2165 } 2166 2167 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) { 2168 if (napi_schedule_prep(&ch->tx_napi)) { 2169 spin_lock_irqsave(&ch->lock, flags); 2170 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 2171 spin_unlock_irqrestore(&ch->lock, flags); 2172 __napi_schedule_irqoff(&ch->tx_napi); 2173 } 2174 } 2175 2176 return status; 2177 } 2178 2179 /** 2180 * stmmac_dma_interrupt - DMA ISR 2181 * @priv: driver private structure 2182 * Description: this is the DMA ISR. It is called by the main ISR. 2183 * It calls the dwmac dma routine and schedule poll method in case of some 2184 * work can be done. 2185 */ 2186 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 2187 { 2188 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2189 u32 rx_channel_count = priv->plat->rx_queues_to_use; 2190 u32 channels_to_check = tx_channel_count > rx_channel_count ? 2191 tx_channel_count : rx_channel_count; 2192 u32 chan; 2193 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)]; 2194 2195 /* Make sure we never check beyond our status buffer. */ 2196 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status))) 2197 channels_to_check = ARRAY_SIZE(status); 2198 2199 for (chan = 0; chan < channels_to_check; chan++) 2200 status[chan] = stmmac_napi_check(priv, chan); 2201 2202 for (chan = 0; chan < tx_channel_count; chan++) { 2203 if (unlikely(status[chan] & tx_hard_error_bump_tc)) { 2204 /* Try to bump up the dma threshold on this failure */ 2205 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && 2206 (tc <= 256)) { 2207 tc += 64; 2208 if (priv->plat->force_thresh_dma_mode) 2209 stmmac_set_dma_operation_mode(priv, 2210 tc, 2211 tc, 2212 chan); 2213 else 2214 stmmac_set_dma_operation_mode(priv, 2215 tc, 2216 SF_DMA_MODE, 2217 chan); 2218 priv->xstats.threshold = tc; 2219 } 2220 } else if (unlikely(status[chan] == tx_hard_error)) { 2221 stmmac_tx_err(priv, chan); 2222 } 2223 } 2224 } 2225 2226 /** 2227 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 2228 * @priv: driver private structure 2229 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 2230 */ 2231 static void stmmac_mmc_setup(struct stmmac_priv *priv) 2232 { 2233 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 2234 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 2235 2236 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr); 2237 2238 if (priv->dma_cap.rmon) { 2239 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode); 2240 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 2241 } else 2242 netdev_info(priv->dev, "No MAC Management Counters available\n"); 2243 } 2244 2245 /** 2246 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. 2247 * @priv: driver private structure 2248 * Description: 2249 * new GMAC chip generations have a new register to indicate the 2250 * presence of the optional feature/functions. 2251 * This can be also used to override the value passed through the 2252 * platform and necessary for old MAC10/100 and GMAC chips. 2253 */ 2254 static int stmmac_get_hw_features(struct stmmac_priv *priv) 2255 { 2256 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0; 2257 } 2258 2259 /** 2260 * stmmac_check_ether_addr - check if the MAC addr is valid 2261 * @priv: driver private structure 2262 * Description: 2263 * it is to verify if the MAC address is valid, in case of failures it 2264 * generates a random MAC address 2265 */ 2266 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 2267 { 2268 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 2269 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0); 2270 if (!is_valid_ether_addr(priv->dev->dev_addr)) 2271 eth_hw_addr_random(priv->dev); 2272 dev_info(priv->device, "device MAC address %pM\n", 2273 priv->dev->dev_addr); 2274 } 2275 } 2276 2277 /** 2278 * stmmac_init_dma_engine - DMA init. 2279 * @priv: driver private structure 2280 * Description: 2281 * It inits the DMA invoking the specific MAC/GMAC callback. 2282 * Some DMA parameters can be passed from the platform; 2283 * in case of these are not passed a default is kept for the MAC or GMAC. 2284 */ 2285 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 2286 { 2287 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2288 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2289 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); 2290 struct stmmac_rx_queue *rx_q; 2291 struct stmmac_tx_queue *tx_q; 2292 u32 chan = 0; 2293 int atds = 0; 2294 int ret = 0; 2295 2296 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) { 2297 dev_err(priv->device, "Invalid DMA configuration\n"); 2298 return -EINVAL; 2299 } 2300 2301 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 2302 atds = 1; 2303 2304 ret = stmmac_reset(priv, priv->ioaddr); 2305 if (ret) { 2306 dev_err(priv->device, "Failed to reset the dma\n"); 2307 return ret; 2308 } 2309 2310 /* DMA Configuration */ 2311 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds); 2312 2313 if (priv->plat->axi) 2314 stmmac_axi(priv, priv->ioaddr, priv->plat->axi); 2315 2316 /* DMA CSR Channel configuration */ 2317 for (chan = 0; chan < dma_csr_ch; chan++) 2318 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 2319 2320 /* DMA RX Channel Configuration */ 2321 for (chan = 0; chan < rx_channels_count; chan++) { 2322 rx_q = &priv->rx_queue[chan]; 2323 2324 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2325 rx_q->dma_rx_phy, chan); 2326 2327 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 2328 (DMA_RX_SIZE * sizeof(struct dma_desc)); 2329 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 2330 rx_q->rx_tail_addr, chan); 2331 } 2332 2333 /* DMA TX Channel Configuration */ 2334 for (chan = 0; chan < tx_channels_count; chan++) { 2335 tx_q = &priv->tx_queue[chan]; 2336 2337 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2338 tx_q->dma_tx_phy, chan); 2339 2340 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 2341 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 2342 tx_q->tx_tail_addr, chan); 2343 } 2344 2345 return ret; 2346 } 2347 2348 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue) 2349 { 2350 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2351 2352 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer)); 2353 } 2354 2355 /** 2356 * stmmac_tx_timer - mitigation sw timer for tx. 2357 * @data: data pointer 2358 * Description: 2359 * This is the timer handler to directly invoke the stmmac_tx_clean. 2360 */ 2361 static void stmmac_tx_timer(struct timer_list *t) 2362 { 2363 struct stmmac_tx_queue *tx_q = from_timer(tx_q, t, txtimer); 2364 struct stmmac_priv *priv = tx_q->priv_data; 2365 struct stmmac_channel *ch; 2366 2367 ch = &priv->channel[tx_q->queue_index]; 2368 2369 if (likely(napi_schedule_prep(&ch->tx_napi))) { 2370 unsigned long flags; 2371 2372 spin_lock_irqsave(&ch->lock, flags); 2373 stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1); 2374 spin_unlock_irqrestore(&ch->lock, flags); 2375 __napi_schedule(&ch->tx_napi); 2376 } 2377 } 2378 2379 /** 2380 * stmmac_init_coalesce - init mitigation options. 2381 * @priv: driver private structure 2382 * Description: 2383 * This inits the coalesce parameters: i.e. timer rate, 2384 * timer handler and default threshold used for enabling the 2385 * interrupt on completion bit. 2386 */ 2387 static void stmmac_init_coalesce(struct stmmac_priv *priv) 2388 { 2389 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2390 u32 chan; 2391 2392 priv->tx_coal_frames = STMMAC_TX_FRAMES; 2393 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER; 2394 priv->rx_coal_frames = STMMAC_RX_FRAMES; 2395 2396 for (chan = 0; chan < tx_channel_count; chan++) { 2397 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2398 2399 timer_setup(&tx_q->txtimer, stmmac_tx_timer, 0); 2400 } 2401 } 2402 2403 static void stmmac_set_rings_length(struct stmmac_priv *priv) 2404 { 2405 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2406 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2407 u32 chan; 2408 2409 /* set TX ring length */ 2410 for (chan = 0; chan < tx_channels_count; chan++) 2411 stmmac_set_tx_ring_len(priv, priv->ioaddr, 2412 (DMA_TX_SIZE - 1), chan); 2413 2414 /* set RX ring length */ 2415 for (chan = 0; chan < rx_channels_count; chan++) 2416 stmmac_set_rx_ring_len(priv, priv->ioaddr, 2417 (DMA_RX_SIZE - 1), chan); 2418 } 2419 2420 /** 2421 * stmmac_set_tx_queue_weight - Set TX queue weight 2422 * @priv: driver private structure 2423 * Description: It is used for setting TX queues weight 2424 */ 2425 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv) 2426 { 2427 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2428 u32 weight; 2429 u32 queue; 2430 2431 for (queue = 0; queue < tx_queues_count; queue++) { 2432 weight = priv->plat->tx_queues_cfg[queue].weight; 2433 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue); 2434 } 2435 } 2436 2437 /** 2438 * stmmac_configure_cbs - Configure CBS in TX queue 2439 * @priv: driver private structure 2440 * Description: It is used for configuring CBS in AVB TX queues 2441 */ 2442 static void stmmac_configure_cbs(struct stmmac_priv *priv) 2443 { 2444 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2445 u32 mode_to_use; 2446 u32 queue; 2447 2448 /* queue 0 is reserved for legacy traffic */ 2449 for (queue = 1; queue < tx_queues_count; queue++) { 2450 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use; 2451 if (mode_to_use == MTL_QUEUE_DCB) 2452 continue; 2453 2454 stmmac_config_cbs(priv, priv->hw, 2455 priv->plat->tx_queues_cfg[queue].send_slope, 2456 priv->plat->tx_queues_cfg[queue].idle_slope, 2457 priv->plat->tx_queues_cfg[queue].high_credit, 2458 priv->plat->tx_queues_cfg[queue].low_credit, 2459 queue); 2460 } 2461 } 2462 2463 /** 2464 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel 2465 * @priv: driver private structure 2466 * Description: It is used for mapping RX queues to RX dma channels 2467 */ 2468 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv) 2469 { 2470 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2471 u32 queue; 2472 u32 chan; 2473 2474 for (queue = 0; queue < rx_queues_count; queue++) { 2475 chan = priv->plat->rx_queues_cfg[queue].chan; 2476 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan); 2477 } 2478 } 2479 2480 /** 2481 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority 2482 * @priv: driver private structure 2483 * Description: It is used for configuring the RX Queue Priority 2484 */ 2485 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv) 2486 { 2487 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2488 u32 queue; 2489 u32 prio; 2490 2491 for (queue = 0; queue < rx_queues_count; queue++) { 2492 if (!priv->plat->rx_queues_cfg[queue].use_prio) 2493 continue; 2494 2495 prio = priv->plat->rx_queues_cfg[queue].prio; 2496 stmmac_rx_queue_prio(priv, priv->hw, prio, queue); 2497 } 2498 } 2499 2500 /** 2501 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority 2502 * @priv: driver private structure 2503 * Description: It is used for configuring the TX Queue Priority 2504 */ 2505 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv) 2506 { 2507 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2508 u32 queue; 2509 u32 prio; 2510 2511 for (queue = 0; queue < tx_queues_count; queue++) { 2512 if (!priv->plat->tx_queues_cfg[queue].use_prio) 2513 continue; 2514 2515 prio = priv->plat->tx_queues_cfg[queue].prio; 2516 stmmac_tx_queue_prio(priv, priv->hw, prio, queue); 2517 } 2518 } 2519 2520 /** 2521 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing 2522 * @priv: driver private structure 2523 * Description: It is used for configuring the RX queue routing 2524 */ 2525 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv) 2526 { 2527 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2528 u32 queue; 2529 u8 packet; 2530 2531 for (queue = 0; queue < rx_queues_count; queue++) { 2532 /* no specific packet type routing specified for the queue */ 2533 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0) 2534 continue; 2535 2536 packet = priv->plat->rx_queues_cfg[queue].pkt_route; 2537 stmmac_rx_queue_routing(priv, priv->hw, packet, queue); 2538 } 2539 } 2540 2541 static void stmmac_mac_config_rss(struct stmmac_priv *priv) 2542 { 2543 if (!priv->dma_cap.rssen || !priv->plat->rss_en) { 2544 priv->rss.enable = false; 2545 return; 2546 } 2547 2548 if (priv->dev->features & NETIF_F_RXHASH) 2549 priv->rss.enable = true; 2550 else 2551 priv->rss.enable = false; 2552 2553 stmmac_rss_configure(priv, priv->hw, &priv->rss, 2554 priv->plat->rx_queues_to_use); 2555 } 2556 2557 /** 2558 * stmmac_mtl_configuration - Configure MTL 2559 * @priv: driver private structure 2560 * Description: It is used for configurring MTL 2561 */ 2562 static void stmmac_mtl_configuration(struct stmmac_priv *priv) 2563 { 2564 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2565 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2566 2567 if (tx_queues_count > 1) 2568 stmmac_set_tx_queue_weight(priv); 2569 2570 /* Configure MTL RX algorithms */ 2571 if (rx_queues_count > 1) 2572 stmmac_prog_mtl_rx_algorithms(priv, priv->hw, 2573 priv->plat->rx_sched_algorithm); 2574 2575 /* Configure MTL TX algorithms */ 2576 if (tx_queues_count > 1) 2577 stmmac_prog_mtl_tx_algorithms(priv, priv->hw, 2578 priv->plat->tx_sched_algorithm); 2579 2580 /* Configure CBS in AVB TX queues */ 2581 if (tx_queues_count > 1) 2582 stmmac_configure_cbs(priv); 2583 2584 /* Map RX MTL to DMA channels */ 2585 stmmac_rx_queue_dma_chan_map(priv); 2586 2587 /* Enable MAC RX Queues */ 2588 stmmac_mac_enable_rx_queues(priv); 2589 2590 /* Set RX priorities */ 2591 if (rx_queues_count > 1) 2592 stmmac_mac_config_rx_queues_prio(priv); 2593 2594 /* Set TX priorities */ 2595 if (tx_queues_count > 1) 2596 stmmac_mac_config_tx_queues_prio(priv); 2597 2598 /* Set RX routing */ 2599 if (rx_queues_count > 1) 2600 stmmac_mac_config_rx_queues_routing(priv); 2601 2602 /* Receive Side Scaling */ 2603 if (rx_queues_count > 1) 2604 stmmac_mac_config_rss(priv); 2605 } 2606 2607 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv) 2608 { 2609 if (priv->dma_cap.asp) { 2610 netdev_info(priv->dev, "Enabling Safety Features\n"); 2611 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp); 2612 } else { 2613 netdev_info(priv->dev, "No Safety Features support found\n"); 2614 } 2615 } 2616 2617 /** 2618 * stmmac_hw_setup - setup mac in a usable state. 2619 * @dev : pointer to the device structure. 2620 * Description: 2621 * this is the main function to setup the HW in a usable state because the 2622 * dma engine is reset, the core registers are configured (e.g. AXI, 2623 * Checksum features, timers). The DMA is ready to start receiving and 2624 * transmitting. 2625 * Return value: 2626 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2627 * file on failure. 2628 */ 2629 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) 2630 { 2631 struct stmmac_priv *priv = netdev_priv(dev); 2632 u32 rx_cnt = priv->plat->rx_queues_to_use; 2633 u32 tx_cnt = priv->plat->tx_queues_to_use; 2634 u32 chan; 2635 int ret; 2636 2637 /* DMA initialization and SW reset */ 2638 ret = stmmac_init_dma_engine(priv); 2639 if (ret < 0) { 2640 netdev_err(priv->dev, "%s: DMA engine initialization failed\n", 2641 __func__); 2642 return ret; 2643 } 2644 2645 /* Copy the MAC addr into the HW */ 2646 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0); 2647 2648 /* PS and related bits will be programmed according to the speed */ 2649 if (priv->hw->pcs) { 2650 int speed = priv->plat->mac_port_sel_speed; 2651 2652 if ((speed == SPEED_10) || (speed == SPEED_100) || 2653 (speed == SPEED_1000)) { 2654 priv->hw->ps = speed; 2655 } else { 2656 dev_warn(priv->device, "invalid port speed\n"); 2657 priv->hw->ps = 0; 2658 } 2659 } 2660 2661 /* Initialize the MAC Core */ 2662 stmmac_core_init(priv, priv->hw, dev); 2663 2664 /* Initialize MTL*/ 2665 stmmac_mtl_configuration(priv); 2666 2667 /* Initialize Safety Features */ 2668 stmmac_safety_feat_configuration(priv); 2669 2670 ret = stmmac_rx_ipc(priv, priv->hw); 2671 if (!ret) { 2672 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); 2673 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 2674 priv->hw->rx_csum = 0; 2675 } 2676 2677 /* Enable the MAC Rx/Tx */ 2678 stmmac_mac_set(priv, priv->ioaddr, true); 2679 2680 /* Set the HW DMA mode and the COE */ 2681 stmmac_dma_operation_mode(priv); 2682 2683 stmmac_mmc_setup(priv); 2684 2685 if (init_ptp) { 2686 ret = clk_prepare_enable(priv->plat->clk_ptp_ref); 2687 if (ret < 0) 2688 netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret); 2689 2690 ret = stmmac_init_ptp(priv); 2691 if (ret == -EOPNOTSUPP) 2692 netdev_warn(priv->dev, "PTP not supported by HW\n"); 2693 else if (ret) 2694 netdev_warn(priv->dev, "PTP init failed\n"); 2695 } 2696 2697 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS; 2698 2699 if (priv->use_riwt) { 2700 if (!priv->rx_riwt) 2701 priv->rx_riwt = DEF_DMA_RIWT; 2702 2703 ret = stmmac_rx_watchdog(priv, priv->ioaddr, priv->rx_riwt, rx_cnt); 2704 } 2705 2706 if (priv->hw->pcs) 2707 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); 2708 2709 /* set TX and RX rings length */ 2710 stmmac_set_rings_length(priv); 2711 2712 /* Enable TSO */ 2713 if (priv->tso) { 2714 for (chan = 0; chan < tx_cnt; chan++) 2715 stmmac_enable_tso(priv, priv->ioaddr, 1, chan); 2716 } 2717 2718 /* Enable Split Header */ 2719 if (priv->sph && priv->hw->rx_csum) { 2720 for (chan = 0; chan < rx_cnt; chan++) 2721 stmmac_enable_sph(priv, priv->ioaddr, 1, chan); 2722 } 2723 2724 /* VLAN Tag Insertion */ 2725 if (priv->dma_cap.vlins) 2726 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT); 2727 2728 /* TBS */ 2729 for (chan = 0; chan < tx_cnt; chan++) { 2730 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2731 int enable = tx_q->tbs & STMMAC_TBS_AVAIL; 2732 2733 stmmac_enable_tbs(priv, priv->ioaddr, enable, chan); 2734 } 2735 2736 /* Start the ball rolling... */ 2737 stmmac_start_all_dma(priv); 2738 2739 return 0; 2740 } 2741 2742 static void stmmac_hw_teardown(struct net_device *dev) 2743 { 2744 struct stmmac_priv *priv = netdev_priv(dev); 2745 2746 clk_disable_unprepare(priv->plat->clk_ptp_ref); 2747 } 2748 2749 /** 2750 * stmmac_open - open entry point of the driver 2751 * @dev : pointer to the device structure. 2752 * Description: 2753 * This function is the open entry point of the driver. 2754 * Return value: 2755 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2756 * file on failure. 2757 */ 2758 static int stmmac_open(struct net_device *dev) 2759 { 2760 struct stmmac_priv *priv = netdev_priv(dev); 2761 int bfsize = 0; 2762 u32 chan; 2763 int ret; 2764 2765 if (priv->hw->pcs != STMMAC_PCS_TBI && 2766 priv->hw->pcs != STMMAC_PCS_RTBI && 2767 priv->hw->xpcs == NULL) { 2768 ret = stmmac_init_phy(dev); 2769 if (ret) { 2770 netdev_err(priv->dev, 2771 "%s: Cannot attach to PHY (error: %d)\n", 2772 __func__, ret); 2773 return ret; 2774 } 2775 } 2776 2777 /* Extra statistics */ 2778 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 2779 priv->xstats.threshold = tc; 2780 2781 bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu); 2782 if (bfsize < 0) 2783 bfsize = 0; 2784 2785 if (bfsize < BUF_SIZE_16KiB) 2786 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); 2787 2788 priv->dma_buf_sz = bfsize; 2789 buf_sz = bfsize; 2790 2791 priv->rx_copybreak = STMMAC_RX_COPYBREAK; 2792 2793 /* Earlier check for TBS */ 2794 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) { 2795 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2796 int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en; 2797 2798 tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0; 2799 if (stmmac_enable_tbs(priv, priv->ioaddr, tbs_en, chan)) 2800 tx_q->tbs &= ~STMMAC_TBS_AVAIL; 2801 } 2802 2803 ret = alloc_dma_desc_resources(priv); 2804 if (ret < 0) { 2805 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n", 2806 __func__); 2807 goto dma_desc_error; 2808 } 2809 2810 ret = init_dma_desc_rings(dev, GFP_KERNEL); 2811 if (ret < 0) { 2812 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n", 2813 __func__); 2814 goto init_error; 2815 } 2816 2817 ret = stmmac_hw_setup(dev, true); 2818 if (ret < 0) { 2819 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); 2820 goto init_error; 2821 } 2822 2823 stmmac_init_coalesce(priv); 2824 2825 phylink_start(priv->phylink); 2826 /* We may have called phylink_speed_down before */ 2827 phylink_speed_up(priv->phylink); 2828 2829 /* Request the IRQ lines */ 2830 ret = request_irq(dev->irq, stmmac_interrupt, 2831 IRQF_SHARED, dev->name, dev); 2832 if (unlikely(ret < 0)) { 2833 netdev_err(priv->dev, 2834 "%s: ERROR: allocating the IRQ %d (error: %d)\n", 2835 __func__, dev->irq, ret); 2836 goto irq_error; 2837 } 2838 2839 /* Request the Wake IRQ in case of another line is used for WoL */ 2840 if (priv->wol_irq != dev->irq) { 2841 ret = request_irq(priv->wol_irq, stmmac_interrupt, 2842 IRQF_SHARED, dev->name, dev); 2843 if (unlikely(ret < 0)) { 2844 netdev_err(priv->dev, 2845 "%s: ERROR: allocating the WoL IRQ %d (%d)\n", 2846 __func__, priv->wol_irq, ret); 2847 goto wolirq_error; 2848 } 2849 } 2850 2851 /* Request the IRQ lines */ 2852 if (priv->lpi_irq > 0) { 2853 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED, 2854 dev->name, dev); 2855 if (unlikely(ret < 0)) { 2856 netdev_err(priv->dev, 2857 "%s: ERROR: allocating the LPI IRQ %d (%d)\n", 2858 __func__, priv->lpi_irq, ret); 2859 goto lpiirq_error; 2860 } 2861 } 2862 2863 stmmac_enable_all_queues(priv); 2864 stmmac_start_all_queues(priv); 2865 2866 return 0; 2867 2868 lpiirq_error: 2869 if (priv->wol_irq != dev->irq) 2870 free_irq(priv->wol_irq, dev); 2871 wolirq_error: 2872 free_irq(dev->irq, dev); 2873 irq_error: 2874 phylink_stop(priv->phylink); 2875 2876 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 2877 del_timer_sync(&priv->tx_queue[chan].txtimer); 2878 2879 stmmac_hw_teardown(dev); 2880 init_error: 2881 free_dma_desc_resources(priv); 2882 dma_desc_error: 2883 phylink_disconnect_phy(priv->phylink); 2884 return ret; 2885 } 2886 2887 /** 2888 * stmmac_release - close entry point of the driver 2889 * @dev : device pointer. 2890 * Description: 2891 * This is the stop entry point of the driver. 2892 */ 2893 static int stmmac_release(struct net_device *dev) 2894 { 2895 struct stmmac_priv *priv = netdev_priv(dev); 2896 u32 chan; 2897 2898 if (priv->eee_enabled) 2899 del_timer_sync(&priv->eee_ctrl_timer); 2900 2901 if (device_may_wakeup(priv->device)) 2902 phylink_speed_down(priv->phylink, false); 2903 /* Stop and disconnect the PHY */ 2904 phylink_stop(priv->phylink); 2905 phylink_disconnect_phy(priv->phylink); 2906 2907 stmmac_stop_all_queues(priv); 2908 2909 stmmac_disable_all_queues(priv); 2910 2911 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 2912 del_timer_sync(&priv->tx_queue[chan].txtimer); 2913 2914 /* Free the IRQ lines */ 2915 free_irq(dev->irq, dev); 2916 if (priv->wol_irq != dev->irq) 2917 free_irq(priv->wol_irq, dev); 2918 if (priv->lpi_irq > 0) 2919 free_irq(priv->lpi_irq, dev); 2920 2921 /* Stop TX/RX DMA and clear the descriptors */ 2922 stmmac_stop_all_dma(priv); 2923 2924 /* Release and free the Rx/Tx resources */ 2925 free_dma_desc_resources(priv); 2926 2927 /* Disable the MAC Rx/Tx */ 2928 stmmac_mac_set(priv, priv->ioaddr, false); 2929 2930 netif_carrier_off(dev); 2931 2932 stmmac_release_ptp(priv); 2933 2934 return 0; 2935 } 2936 2937 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb, 2938 struct stmmac_tx_queue *tx_q) 2939 { 2940 u16 tag = 0x0, inner_tag = 0x0; 2941 u32 inner_type = 0x0; 2942 struct dma_desc *p; 2943 2944 if (!priv->dma_cap.vlins) 2945 return false; 2946 if (!skb_vlan_tag_present(skb)) 2947 return false; 2948 if (skb->vlan_proto == htons(ETH_P_8021AD)) { 2949 inner_tag = skb_vlan_tag_get(skb); 2950 inner_type = STMMAC_VLAN_INSERT; 2951 } 2952 2953 tag = skb_vlan_tag_get(skb); 2954 2955 if (tx_q->tbs & STMMAC_TBS_AVAIL) 2956 p = &tx_q->dma_entx[tx_q->cur_tx].basic; 2957 else 2958 p = &tx_q->dma_tx[tx_q->cur_tx]; 2959 2960 if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type)) 2961 return false; 2962 2963 stmmac_set_tx_owner(priv, p); 2964 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 2965 return true; 2966 } 2967 2968 /** 2969 * stmmac_tso_allocator - close entry point of the driver 2970 * @priv: driver private structure 2971 * @des: buffer start address 2972 * @total_len: total length to fill in descriptors 2973 * @last_segmant: condition for the last descriptor 2974 * @queue: TX queue index 2975 * Description: 2976 * This function fills descriptor and request new descriptors according to 2977 * buffer length to fill 2978 */ 2979 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des, 2980 int total_len, bool last_segment, u32 queue) 2981 { 2982 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2983 struct dma_desc *desc; 2984 u32 buff_size; 2985 int tmp_len; 2986 2987 tmp_len = total_len; 2988 2989 while (tmp_len > 0) { 2990 dma_addr_t curr_addr; 2991 2992 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 2993 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 2994 2995 if (tx_q->tbs & STMMAC_TBS_AVAIL) 2996 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 2997 else 2998 desc = &tx_q->dma_tx[tx_q->cur_tx]; 2999 3000 curr_addr = des + (total_len - tmp_len); 3001 if (priv->dma_cap.addr64 <= 32) 3002 desc->des0 = cpu_to_le32(curr_addr); 3003 else 3004 stmmac_set_desc_addr(priv, desc, curr_addr); 3005 3006 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? 3007 TSO_MAX_BUFF_SIZE : tmp_len; 3008 3009 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size, 3010 0, 1, 3011 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE), 3012 0, 0); 3013 3014 tmp_len -= TSO_MAX_BUFF_SIZE; 3015 } 3016 } 3017 3018 /** 3019 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) 3020 * @skb : the socket buffer 3021 * @dev : device pointer 3022 * Description: this is the transmit function that is called on TSO frames 3023 * (support available on GMAC4 and newer chips). 3024 * Diagram below show the ring programming in case of TSO frames: 3025 * 3026 * First Descriptor 3027 * -------- 3028 * | DES0 |---> buffer1 = L2/L3/L4 header 3029 * | DES1 |---> TCP Payload (can continue on next descr...) 3030 * | DES2 |---> buffer 1 and 2 len 3031 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] 3032 * -------- 3033 * | 3034 * ... 3035 * | 3036 * -------- 3037 * | DES0 | --| Split TCP Payload on Buffers 1 and 2 3038 * | DES1 | --| 3039 * | DES2 | --> buffer 1 and 2 len 3040 * | DES3 | 3041 * -------- 3042 * 3043 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. 3044 */ 3045 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) 3046 { 3047 struct dma_desc *desc, *first, *mss_desc = NULL; 3048 struct stmmac_priv *priv = netdev_priv(dev); 3049 int desc_size, tmp_pay_len = 0, first_tx; 3050 int nfrags = skb_shinfo(skb)->nr_frags; 3051 u32 queue = skb_get_queue_mapping(skb); 3052 unsigned int first_entry, tx_packets; 3053 struct stmmac_tx_queue *tx_q; 3054 bool has_vlan, set_ic; 3055 u8 proto_hdr_len, hdr; 3056 u32 pay_len, mss; 3057 dma_addr_t des; 3058 int i; 3059 3060 tx_q = &priv->tx_queue[queue]; 3061 first_tx = tx_q->cur_tx; 3062 3063 /* Compute header lengths */ 3064 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 3065 proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr); 3066 hdr = sizeof(struct udphdr); 3067 } else { 3068 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 3069 hdr = tcp_hdrlen(skb); 3070 } 3071 3072 /* Desc availability based on threshold should be enough safe */ 3073 if (unlikely(stmmac_tx_avail(priv, queue) < 3074 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { 3075 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 3076 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 3077 queue)); 3078 /* This is a hard error, log it. */ 3079 netdev_err(priv->dev, 3080 "%s: Tx Ring full when queue awake\n", 3081 __func__); 3082 } 3083 return NETDEV_TX_BUSY; 3084 } 3085 3086 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ 3087 3088 mss = skb_shinfo(skb)->gso_size; 3089 3090 /* set new MSS value if needed */ 3091 if (mss != tx_q->mss) { 3092 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3093 mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 3094 else 3095 mss_desc = &tx_q->dma_tx[tx_q->cur_tx]; 3096 3097 stmmac_set_mss(priv, mss_desc, mss); 3098 tx_q->mss = mss; 3099 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 3100 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 3101 } 3102 3103 if (netif_msg_tx_queued(priv)) { 3104 pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n", 3105 __func__, hdr, proto_hdr_len, pay_len, mss); 3106 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, 3107 skb->data_len); 3108 } 3109 3110 /* Check if VLAN can be inserted by HW */ 3111 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 3112 3113 first_entry = tx_q->cur_tx; 3114 WARN_ON(tx_q->tx_skbuff[first_entry]); 3115 3116 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3117 desc = &tx_q->dma_entx[first_entry].basic; 3118 else 3119 desc = &tx_q->dma_tx[first_entry]; 3120 first = desc; 3121 3122 if (has_vlan) 3123 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 3124 3125 /* first descriptor: fill Headers on Buf1 */ 3126 des = dma_map_single(priv->device, skb->data, skb_headlen(skb), 3127 DMA_TO_DEVICE); 3128 if (dma_mapping_error(priv->device, des)) 3129 goto dma_map_err; 3130 3131 tx_q->tx_skbuff_dma[first_entry].buf = des; 3132 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb); 3133 3134 if (priv->dma_cap.addr64 <= 32) { 3135 first->des0 = cpu_to_le32(des); 3136 3137 /* Fill start of payload in buff2 of first descriptor */ 3138 if (pay_len) 3139 first->des1 = cpu_to_le32(des + proto_hdr_len); 3140 3141 /* If needed take extra descriptors to fill the remaining payload */ 3142 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; 3143 } else { 3144 stmmac_set_desc_addr(priv, first, des); 3145 tmp_pay_len = pay_len; 3146 des += proto_hdr_len; 3147 pay_len = 0; 3148 } 3149 3150 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue); 3151 3152 /* Prepare fragments */ 3153 for (i = 0; i < nfrags; i++) { 3154 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 3155 3156 des = skb_frag_dma_map(priv->device, frag, 0, 3157 skb_frag_size(frag), 3158 DMA_TO_DEVICE); 3159 if (dma_mapping_error(priv->device, des)) 3160 goto dma_map_err; 3161 3162 stmmac_tso_allocator(priv, des, skb_frag_size(frag), 3163 (i == nfrags - 1), queue); 3164 3165 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des; 3166 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag); 3167 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true; 3168 } 3169 3170 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true; 3171 3172 /* Only the last descriptor gets to point to the skb. */ 3173 tx_q->tx_skbuff[tx_q->cur_tx] = skb; 3174 3175 /* Manage tx mitigation */ 3176 tx_packets = (tx_q->cur_tx + 1) - first_tx; 3177 tx_q->tx_count_frames += tx_packets; 3178 3179 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 3180 set_ic = true; 3181 else if (!priv->tx_coal_frames) 3182 set_ic = false; 3183 else if (tx_packets > priv->tx_coal_frames) 3184 set_ic = true; 3185 else if ((tx_q->tx_count_frames % priv->tx_coal_frames) < tx_packets) 3186 set_ic = true; 3187 else 3188 set_ic = false; 3189 3190 if (set_ic) { 3191 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3192 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 3193 else 3194 desc = &tx_q->dma_tx[tx_q->cur_tx]; 3195 3196 tx_q->tx_count_frames = 0; 3197 stmmac_set_tx_ic(priv, desc); 3198 priv->xstats.tx_set_ic_bit++; 3199 } 3200 3201 /* We've used all descriptors we need for this skb, however, 3202 * advance cur_tx so that it references a fresh descriptor. 3203 * ndo_start_xmit will fill this descriptor the next time it's 3204 * called and stmmac_tx_clean may clean up to this descriptor. 3205 */ 3206 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 3207 3208 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 3209 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 3210 __func__); 3211 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 3212 } 3213 3214 dev->stats.tx_bytes += skb->len; 3215 priv->xstats.tx_tso_frames++; 3216 priv->xstats.tx_tso_nfrags += nfrags; 3217 3218 if (priv->sarc_type) 3219 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 3220 3221 skb_tx_timestamp(skb); 3222 3223 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 3224 priv->hwts_tx_en)) { 3225 /* declare that device is doing timestamping */ 3226 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 3227 stmmac_enable_tx_timestamp(priv, first); 3228 } 3229 3230 /* Complete the first descriptor before granting the DMA */ 3231 stmmac_prepare_tso_tx_desc(priv, first, 1, 3232 proto_hdr_len, 3233 pay_len, 3234 1, tx_q->tx_skbuff_dma[first_entry].last_segment, 3235 hdr / 4, (skb->len - proto_hdr_len)); 3236 3237 /* If context desc is used to change MSS */ 3238 if (mss_desc) { 3239 /* Make sure that first descriptor has been completely 3240 * written, including its own bit. This is because MSS is 3241 * actually before first descriptor, so we need to make 3242 * sure that MSS's own bit is the last thing written. 3243 */ 3244 dma_wmb(); 3245 stmmac_set_tx_owner(priv, mss_desc); 3246 } 3247 3248 /* The own bit must be the latest setting done when prepare the 3249 * descriptor and then barrier is needed to make sure that 3250 * all is coherent before granting the DMA engine. 3251 */ 3252 wmb(); 3253 3254 if (netif_msg_pktdata(priv)) { 3255 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", 3256 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 3257 tx_q->cur_tx, first, nfrags); 3258 pr_info(">>> frame to be transmitted: "); 3259 print_pkt(skb->data, skb_headlen(skb)); 3260 } 3261 3262 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 3263 3264 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3265 desc_size = sizeof(struct dma_edesc); 3266 else 3267 desc_size = sizeof(struct dma_desc); 3268 3269 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size); 3270 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 3271 stmmac_tx_timer_arm(priv, queue); 3272 3273 return NETDEV_TX_OK; 3274 3275 dma_map_err: 3276 dev_err(priv->device, "Tx dma map failed\n"); 3277 dev_kfree_skb(skb); 3278 priv->dev->stats.tx_dropped++; 3279 return NETDEV_TX_OK; 3280 } 3281 3282 /** 3283 * stmmac_xmit - Tx entry point of the driver 3284 * @skb : the socket buffer 3285 * @dev : device pointer 3286 * Description : this is the tx entry point of the driver. 3287 * It programs the chain or the ring and supports oversized frames 3288 * and SG feature. 3289 */ 3290 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 3291 { 3292 unsigned int first_entry, tx_packets, enh_desc; 3293 struct stmmac_priv *priv = netdev_priv(dev); 3294 unsigned int nopaged_len = skb_headlen(skb); 3295 int i, csum_insertion = 0, is_jumbo = 0; 3296 u32 queue = skb_get_queue_mapping(skb); 3297 int nfrags = skb_shinfo(skb)->nr_frags; 3298 int gso = skb_shinfo(skb)->gso_type; 3299 struct dma_edesc *tbs_desc = NULL; 3300 int entry, desc_size, first_tx; 3301 struct dma_desc *desc, *first; 3302 struct stmmac_tx_queue *tx_q; 3303 bool has_vlan, set_ic; 3304 dma_addr_t des; 3305 3306 tx_q = &priv->tx_queue[queue]; 3307 first_tx = tx_q->cur_tx; 3308 3309 if (priv->tx_path_in_lpi_mode) 3310 stmmac_disable_eee_mode(priv); 3311 3312 /* Manage oversized TCP frames for GMAC4 device */ 3313 if (skb_is_gso(skb) && priv->tso) { 3314 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) 3315 return stmmac_tso_xmit(skb, dev); 3316 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4)) 3317 return stmmac_tso_xmit(skb, dev); 3318 } 3319 3320 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) { 3321 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 3322 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 3323 queue)); 3324 /* This is a hard error, log it. */ 3325 netdev_err(priv->dev, 3326 "%s: Tx Ring full when queue awake\n", 3327 __func__); 3328 } 3329 return NETDEV_TX_BUSY; 3330 } 3331 3332 /* Check if VLAN can be inserted by HW */ 3333 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 3334 3335 entry = tx_q->cur_tx; 3336 first_entry = entry; 3337 WARN_ON(tx_q->tx_skbuff[first_entry]); 3338 3339 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 3340 3341 if (likely(priv->extend_desc)) 3342 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 3343 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3344 desc = &tx_q->dma_entx[entry].basic; 3345 else 3346 desc = tx_q->dma_tx + entry; 3347 3348 first = desc; 3349 3350 if (has_vlan) 3351 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 3352 3353 enh_desc = priv->plat->enh_desc; 3354 /* To program the descriptors according to the size of the frame */ 3355 if (enh_desc) 3356 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc); 3357 3358 if (unlikely(is_jumbo)) { 3359 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion); 3360 if (unlikely(entry < 0) && (entry != -EINVAL)) 3361 goto dma_map_err; 3362 } 3363 3364 for (i = 0; i < nfrags; i++) { 3365 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 3366 int len = skb_frag_size(frag); 3367 bool last_segment = (i == (nfrags - 1)); 3368 3369 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 3370 WARN_ON(tx_q->tx_skbuff[entry]); 3371 3372 if (likely(priv->extend_desc)) 3373 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 3374 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3375 desc = &tx_q->dma_entx[entry].basic; 3376 else 3377 desc = tx_q->dma_tx + entry; 3378 3379 des = skb_frag_dma_map(priv->device, frag, 0, len, 3380 DMA_TO_DEVICE); 3381 if (dma_mapping_error(priv->device, des)) 3382 goto dma_map_err; /* should reuse desc w/o issues */ 3383 3384 tx_q->tx_skbuff_dma[entry].buf = des; 3385 3386 stmmac_set_desc_addr(priv, desc, des); 3387 3388 tx_q->tx_skbuff_dma[entry].map_as_page = true; 3389 tx_q->tx_skbuff_dma[entry].len = len; 3390 tx_q->tx_skbuff_dma[entry].last_segment = last_segment; 3391 3392 /* Prepare the descriptor and set the own bit too */ 3393 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion, 3394 priv->mode, 1, last_segment, skb->len); 3395 } 3396 3397 /* Only the last descriptor gets to point to the skb. */ 3398 tx_q->tx_skbuff[entry] = skb; 3399 3400 /* According to the coalesce parameter the IC bit for the latest 3401 * segment is reset and the timer re-started to clean the tx status. 3402 * This approach takes care about the fragments: desc is the first 3403 * element in case of no SG. 3404 */ 3405 tx_packets = (entry + 1) - first_tx; 3406 tx_q->tx_count_frames += tx_packets; 3407 3408 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 3409 set_ic = true; 3410 else if (!priv->tx_coal_frames) 3411 set_ic = false; 3412 else if (tx_packets > priv->tx_coal_frames) 3413 set_ic = true; 3414 else if ((tx_q->tx_count_frames % priv->tx_coal_frames) < tx_packets) 3415 set_ic = true; 3416 else 3417 set_ic = false; 3418 3419 if (set_ic) { 3420 if (likely(priv->extend_desc)) 3421 desc = &tx_q->dma_etx[entry].basic; 3422 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3423 desc = &tx_q->dma_entx[entry].basic; 3424 else 3425 desc = &tx_q->dma_tx[entry]; 3426 3427 tx_q->tx_count_frames = 0; 3428 stmmac_set_tx_ic(priv, desc); 3429 priv->xstats.tx_set_ic_bit++; 3430 } 3431 3432 /* We've used all descriptors we need for this skb, however, 3433 * advance cur_tx so that it references a fresh descriptor. 3434 * ndo_start_xmit will fill this descriptor the next time it's 3435 * called and stmmac_tx_clean may clean up to this descriptor. 3436 */ 3437 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 3438 tx_q->cur_tx = entry; 3439 3440 if (netif_msg_pktdata(priv)) { 3441 netdev_dbg(priv->dev, 3442 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", 3443 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 3444 entry, first, nfrags); 3445 3446 netdev_dbg(priv->dev, ">>> frame to be transmitted: "); 3447 print_pkt(skb->data, skb->len); 3448 } 3449 3450 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 3451 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 3452 __func__); 3453 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 3454 } 3455 3456 dev->stats.tx_bytes += skb->len; 3457 3458 if (priv->sarc_type) 3459 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 3460 3461 skb_tx_timestamp(skb); 3462 3463 /* Ready to fill the first descriptor and set the OWN bit w/o any 3464 * problems because all the descriptors are actually ready to be 3465 * passed to the DMA engine. 3466 */ 3467 if (likely(!is_jumbo)) { 3468 bool last_segment = (nfrags == 0); 3469 3470 des = dma_map_single(priv->device, skb->data, 3471 nopaged_len, DMA_TO_DEVICE); 3472 if (dma_mapping_error(priv->device, des)) 3473 goto dma_map_err; 3474 3475 tx_q->tx_skbuff_dma[first_entry].buf = des; 3476 3477 stmmac_set_desc_addr(priv, first, des); 3478 3479 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len; 3480 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment; 3481 3482 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 3483 priv->hwts_tx_en)) { 3484 /* declare that device is doing timestamping */ 3485 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 3486 stmmac_enable_tx_timestamp(priv, first); 3487 } 3488 3489 /* Prepare the first descriptor setting the OWN bit too */ 3490 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len, 3491 csum_insertion, priv->mode, 0, last_segment, 3492 skb->len); 3493 } 3494 3495 if (tx_q->tbs & STMMAC_TBS_EN) { 3496 struct timespec64 ts = ns_to_timespec64(skb->tstamp); 3497 3498 tbs_desc = &tx_q->dma_entx[first_entry]; 3499 stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec); 3500 } 3501 3502 stmmac_set_tx_owner(priv, first); 3503 3504 /* The own bit must be the latest setting done when prepare the 3505 * descriptor and then barrier is needed to make sure that 3506 * all is coherent before granting the DMA engine. 3507 */ 3508 wmb(); 3509 3510 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 3511 3512 stmmac_enable_dma_transmission(priv, priv->ioaddr); 3513 3514 if (likely(priv->extend_desc)) 3515 desc_size = sizeof(struct dma_extended_desc); 3516 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3517 desc_size = sizeof(struct dma_edesc); 3518 else 3519 desc_size = sizeof(struct dma_desc); 3520 3521 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size); 3522 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 3523 stmmac_tx_timer_arm(priv, queue); 3524 3525 return NETDEV_TX_OK; 3526 3527 dma_map_err: 3528 netdev_err(priv->dev, "Tx DMA map failed\n"); 3529 dev_kfree_skb(skb); 3530 priv->dev->stats.tx_dropped++; 3531 return NETDEV_TX_OK; 3532 } 3533 3534 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 3535 { 3536 struct vlan_ethhdr *veth; 3537 __be16 vlan_proto; 3538 u16 vlanid; 3539 3540 veth = (struct vlan_ethhdr *)skb->data; 3541 vlan_proto = veth->h_vlan_proto; 3542 3543 if ((vlan_proto == htons(ETH_P_8021Q) && 3544 dev->features & NETIF_F_HW_VLAN_CTAG_RX) || 3545 (vlan_proto == htons(ETH_P_8021AD) && 3546 dev->features & NETIF_F_HW_VLAN_STAG_RX)) { 3547 /* pop the vlan tag */ 3548 vlanid = ntohs(veth->h_vlan_TCI); 3549 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2); 3550 skb_pull(skb, VLAN_HLEN); 3551 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid); 3552 } 3553 } 3554 3555 /** 3556 * stmmac_rx_refill - refill used skb preallocated buffers 3557 * @priv: driver private structure 3558 * @queue: RX queue index 3559 * Description : this is to reallocate the skb for the reception process 3560 * that is based on zero-copy. 3561 */ 3562 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) 3563 { 3564 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 3565 int len, dirty = stmmac_rx_dirty(priv, queue); 3566 unsigned int entry = rx_q->dirty_rx; 3567 3568 len = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE) * PAGE_SIZE; 3569 3570 while (dirty-- > 0) { 3571 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 3572 struct dma_desc *p; 3573 bool use_rx_wd; 3574 3575 if (priv->extend_desc) 3576 p = (struct dma_desc *)(rx_q->dma_erx + entry); 3577 else 3578 p = rx_q->dma_rx + entry; 3579 3580 if (!buf->page) { 3581 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); 3582 if (!buf->page) 3583 break; 3584 } 3585 3586 if (priv->sph && !buf->sec_page) { 3587 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); 3588 if (!buf->sec_page) 3589 break; 3590 3591 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 3592 3593 dma_sync_single_for_device(priv->device, buf->sec_addr, 3594 len, DMA_FROM_DEVICE); 3595 } 3596 3597 buf->addr = page_pool_get_dma_addr(buf->page); 3598 3599 /* Sync whole allocation to device. This will invalidate old 3600 * data. 3601 */ 3602 dma_sync_single_for_device(priv->device, buf->addr, len, 3603 DMA_FROM_DEVICE); 3604 3605 stmmac_set_desc_addr(priv, p, buf->addr); 3606 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr); 3607 stmmac_refill_desc3(priv, rx_q, p); 3608 3609 rx_q->rx_count_frames++; 3610 rx_q->rx_count_frames += priv->rx_coal_frames; 3611 if (rx_q->rx_count_frames > priv->rx_coal_frames) 3612 rx_q->rx_count_frames = 0; 3613 3614 use_rx_wd = !priv->rx_coal_frames; 3615 use_rx_wd |= rx_q->rx_count_frames > 0; 3616 if (!priv->use_riwt) 3617 use_rx_wd = false; 3618 3619 dma_wmb(); 3620 stmmac_set_rx_owner(priv, p, use_rx_wd); 3621 3622 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE); 3623 } 3624 rx_q->dirty_rx = entry; 3625 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 3626 (rx_q->dirty_rx * sizeof(struct dma_desc)); 3627 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 3628 } 3629 3630 static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv, 3631 struct dma_desc *p, 3632 int status, unsigned int len) 3633 { 3634 int ret, coe = priv->hw->rx_csum; 3635 unsigned int plen = 0, hlen = 0; 3636 3637 /* Not first descriptor, buffer is always zero */ 3638 if (priv->sph && len) 3639 return 0; 3640 3641 /* First descriptor, get split header length */ 3642 ret = stmmac_get_rx_header_len(priv, p, &hlen); 3643 if (priv->sph && hlen) { 3644 priv->xstats.rx_split_hdr_pkt_n++; 3645 return hlen; 3646 } 3647 3648 /* First descriptor, not last descriptor and not split header */ 3649 if (status & rx_not_ls) 3650 return priv->dma_buf_sz; 3651 3652 plen = stmmac_get_rx_frame_len(priv, p, coe); 3653 3654 /* First descriptor and last descriptor and not split header */ 3655 return min_t(unsigned int, priv->dma_buf_sz, plen); 3656 } 3657 3658 static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv, 3659 struct dma_desc *p, 3660 int status, unsigned int len) 3661 { 3662 int coe = priv->hw->rx_csum; 3663 unsigned int plen = 0; 3664 3665 /* Not split header, buffer is not available */ 3666 if (!priv->sph) 3667 return 0; 3668 3669 /* Not last descriptor */ 3670 if (status & rx_not_ls) 3671 return priv->dma_buf_sz; 3672 3673 plen = stmmac_get_rx_frame_len(priv, p, coe); 3674 3675 /* Last descriptor */ 3676 return plen - len; 3677 } 3678 3679 /** 3680 * stmmac_rx - manage the receive process 3681 * @priv: driver private structure 3682 * @limit: napi bugget 3683 * @queue: RX queue index. 3684 * Description : this the function called by the napi poll method. 3685 * It gets all the frames inside the ring. 3686 */ 3687 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) 3688 { 3689 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 3690 struct stmmac_channel *ch = &priv->channel[queue]; 3691 unsigned int count = 0, error = 0, len = 0; 3692 int status = 0, coe = priv->hw->rx_csum; 3693 unsigned int next_entry = rx_q->cur_rx; 3694 struct sk_buff *skb = NULL; 3695 3696 if (netif_msg_rx_status(priv)) { 3697 void *rx_head; 3698 3699 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 3700 if (priv->extend_desc) 3701 rx_head = (void *)rx_q->dma_erx; 3702 else 3703 rx_head = (void *)rx_q->dma_rx; 3704 3705 stmmac_display_ring(priv, rx_head, DMA_RX_SIZE, true); 3706 } 3707 while (count < limit) { 3708 unsigned int buf1_len = 0, buf2_len = 0; 3709 enum pkt_hash_types hash_type; 3710 struct stmmac_rx_buffer *buf; 3711 struct dma_desc *np, *p; 3712 int entry; 3713 u32 hash; 3714 3715 if (!count && rx_q->state_saved) { 3716 skb = rx_q->state.skb; 3717 error = rx_q->state.error; 3718 len = rx_q->state.len; 3719 } else { 3720 rx_q->state_saved = false; 3721 skb = NULL; 3722 error = 0; 3723 len = 0; 3724 } 3725 3726 if (count >= limit) 3727 break; 3728 3729 read_again: 3730 buf1_len = 0; 3731 buf2_len = 0; 3732 entry = next_entry; 3733 buf = &rx_q->buf_pool[entry]; 3734 3735 if (priv->extend_desc) 3736 p = (struct dma_desc *)(rx_q->dma_erx + entry); 3737 else 3738 p = rx_q->dma_rx + entry; 3739 3740 /* read the status of the incoming frame */ 3741 status = stmmac_rx_status(priv, &priv->dev->stats, 3742 &priv->xstats, p); 3743 /* check if managed by the DMA otherwise go ahead */ 3744 if (unlikely(status & dma_own)) 3745 break; 3746 3747 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, DMA_RX_SIZE); 3748 next_entry = rx_q->cur_rx; 3749 3750 if (priv->extend_desc) 3751 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 3752 else 3753 np = rx_q->dma_rx + next_entry; 3754 3755 prefetch(np); 3756 3757 if (priv->extend_desc) 3758 stmmac_rx_extended_status(priv, &priv->dev->stats, 3759 &priv->xstats, rx_q->dma_erx + entry); 3760 if (unlikely(status == discard_frame)) { 3761 page_pool_recycle_direct(rx_q->page_pool, buf->page); 3762 buf->page = NULL; 3763 error = 1; 3764 if (!priv->hwts_rx_en) 3765 priv->dev->stats.rx_errors++; 3766 } 3767 3768 if (unlikely(error && (status & rx_not_ls))) 3769 goto read_again; 3770 if (unlikely(error)) { 3771 dev_kfree_skb(skb); 3772 skb = NULL; 3773 count++; 3774 continue; 3775 } 3776 3777 /* Buffer is good. Go on. */ 3778 3779 prefetch(page_address(buf->page)); 3780 if (buf->sec_page) 3781 prefetch(page_address(buf->sec_page)); 3782 3783 buf1_len = stmmac_rx_buf1_len(priv, p, status, len); 3784 len += buf1_len; 3785 buf2_len = stmmac_rx_buf2_len(priv, p, status, len); 3786 len += buf2_len; 3787 3788 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 3789 * Type frames (LLC/LLC-SNAP) 3790 * 3791 * llc_snap is never checked in GMAC >= 4, so this ACS 3792 * feature is always disabled and packets need to be 3793 * stripped manually. 3794 */ 3795 if (likely(!(status & rx_not_ls)) && 3796 (likely(priv->synopsys_id >= DWMAC_CORE_4_00) || 3797 unlikely(status != llc_snap))) { 3798 if (buf2_len) 3799 buf2_len -= ETH_FCS_LEN; 3800 else 3801 buf1_len -= ETH_FCS_LEN; 3802 3803 len -= ETH_FCS_LEN; 3804 } 3805 3806 if (!skb) { 3807 skb = napi_alloc_skb(&ch->rx_napi, buf1_len); 3808 if (!skb) { 3809 priv->dev->stats.rx_dropped++; 3810 count++; 3811 goto drain_data; 3812 } 3813 3814 dma_sync_single_for_cpu(priv->device, buf->addr, 3815 buf1_len, DMA_FROM_DEVICE); 3816 skb_copy_to_linear_data(skb, page_address(buf->page), 3817 buf1_len); 3818 skb_put(skb, buf1_len); 3819 3820 /* Data payload copied into SKB, page ready for recycle */ 3821 page_pool_recycle_direct(rx_q->page_pool, buf->page); 3822 buf->page = NULL; 3823 } else if (buf1_len) { 3824 dma_sync_single_for_cpu(priv->device, buf->addr, 3825 buf1_len, DMA_FROM_DEVICE); 3826 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 3827 buf->page, 0, buf1_len, 3828 priv->dma_buf_sz); 3829 3830 /* Data payload appended into SKB */ 3831 page_pool_release_page(rx_q->page_pool, buf->page); 3832 buf->page = NULL; 3833 } 3834 3835 if (buf2_len) { 3836 dma_sync_single_for_cpu(priv->device, buf->sec_addr, 3837 buf2_len, DMA_FROM_DEVICE); 3838 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 3839 buf->sec_page, 0, buf2_len, 3840 priv->dma_buf_sz); 3841 3842 /* Data payload appended into SKB */ 3843 page_pool_release_page(rx_q->page_pool, buf->sec_page); 3844 buf->sec_page = NULL; 3845 } 3846 3847 drain_data: 3848 if (likely(status & rx_not_ls)) 3849 goto read_again; 3850 if (!skb) 3851 continue; 3852 3853 /* Got entire packet into SKB. Finish it. */ 3854 3855 stmmac_get_rx_hwtstamp(priv, p, np, skb); 3856 stmmac_rx_vlan(priv->dev, skb); 3857 skb->protocol = eth_type_trans(skb, priv->dev); 3858 3859 if (unlikely(!coe)) 3860 skb_checksum_none_assert(skb); 3861 else 3862 skb->ip_summed = CHECKSUM_UNNECESSARY; 3863 3864 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 3865 skb_set_hash(skb, hash, hash_type); 3866 3867 skb_record_rx_queue(skb, queue); 3868 napi_gro_receive(&ch->rx_napi, skb); 3869 skb = NULL; 3870 3871 priv->dev->stats.rx_packets++; 3872 priv->dev->stats.rx_bytes += len; 3873 count++; 3874 } 3875 3876 if (status & rx_not_ls || skb) { 3877 rx_q->state_saved = true; 3878 rx_q->state.skb = skb; 3879 rx_q->state.error = error; 3880 rx_q->state.len = len; 3881 } 3882 3883 stmmac_rx_refill(priv, queue); 3884 3885 priv->xstats.rx_pkt_n += count; 3886 3887 return count; 3888 } 3889 3890 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget) 3891 { 3892 struct stmmac_channel *ch = 3893 container_of(napi, struct stmmac_channel, rx_napi); 3894 struct stmmac_priv *priv = ch->priv_data; 3895 u32 chan = ch->index; 3896 int work_done; 3897 3898 priv->xstats.napi_poll++; 3899 3900 work_done = stmmac_rx(priv, budget, chan); 3901 if (work_done < budget && napi_complete_done(napi, work_done)) { 3902 unsigned long flags; 3903 3904 spin_lock_irqsave(&ch->lock, flags); 3905 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 3906 spin_unlock_irqrestore(&ch->lock, flags); 3907 } 3908 3909 return work_done; 3910 } 3911 3912 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget) 3913 { 3914 struct stmmac_channel *ch = 3915 container_of(napi, struct stmmac_channel, tx_napi); 3916 struct stmmac_priv *priv = ch->priv_data; 3917 u32 chan = ch->index; 3918 int work_done; 3919 3920 priv->xstats.napi_poll++; 3921 3922 work_done = stmmac_tx_clean(priv, DMA_TX_SIZE, chan); 3923 work_done = min(work_done, budget); 3924 3925 if (work_done < budget && napi_complete_done(napi, work_done)) { 3926 unsigned long flags; 3927 3928 spin_lock_irqsave(&ch->lock, flags); 3929 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 3930 spin_unlock_irqrestore(&ch->lock, flags); 3931 } 3932 3933 return work_done; 3934 } 3935 3936 /** 3937 * stmmac_tx_timeout 3938 * @dev : Pointer to net device structure 3939 * Description: this function is called when a packet transmission fails to 3940 * complete within a reasonable time. The driver will mark the error in the 3941 * netdev structure and arrange for the device to be reset to a sane state 3942 * in order to transmit a new packet. 3943 */ 3944 static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue) 3945 { 3946 struct stmmac_priv *priv = netdev_priv(dev); 3947 3948 stmmac_global_err(priv); 3949 } 3950 3951 /** 3952 * stmmac_set_rx_mode - entry point for multicast addressing 3953 * @dev : pointer to the device structure 3954 * Description: 3955 * This function is a driver entry point which gets called by the kernel 3956 * whenever multicast addresses must be enabled/disabled. 3957 * Return value: 3958 * void. 3959 */ 3960 static void stmmac_set_rx_mode(struct net_device *dev) 3961 { 3962 struct stmmac_priv *priv = netdev_priv(dev); 3963 3964 stmmac_set_filter(priv, priv->hw, dev); 3965 } 3966 3967 /** 3968 * stmmac_change_mtu - entry point to change MTU size for the device. 3969 * @dev : device pointer. 3970 * @new_mtu : the new MTU size for the device. 3971 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 3972 * to drive packet transmission. Ethernet has an MTU of 1500 octets 3973 * (ETH_DATA_LEN). This value can be changed with ifconfig. 3974 * Return value: 3975 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3976 * file on failure. 3977 */ 3978 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 3979 { 3980 struct stmmac_priv *priv = netdev_priv(dev); 3981 int txfifosz = priv->plat->tx_fifo_size; 3982 3983 if (txfifosz == 0) 3984 txfifosz = priv->dma_cap.tx_fifo_size; 3985 3986 txfifosz /= priv->plat->tx_queues_to_use; 3987 3988 if (netif_running(dev)) { 3989 netdev_err(priv->dev, "must be stopped to change its MTU\n"); 3990 return -EBUSY; 3991 } 3992 3993 new_mtu = STMMAC_ALIGN(new_mtu); 3994 3995 /* If condition true, FIFO is too small or MTU too large */ 3996 if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB)) 3997 return -EINVAL; 3998 3999 dev->mtu = new_mtu; 4000 4001 netdev_update_features(dev); 4002 4003 return 0; 4004 } 4005 4006 static netdev_features_t stmmac_fix_features(struct net_device *dev, 4007 netdev_features_t features) 4008 { 4009 struct stmmac_priv *priv = netdev_priv(dev); 4010 4011 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 4012 features &= ~NETIF_F_RXCSUM; 4013 4014 if (!priv->plat->tx_coe) 4015 features &= ~NETIF_F_CSUM_MASK; 4016 4017 /* Some GMAC devices have a bugged Jumbo frame support that 4018 * needs to have the Tx COE disabled for oversized frames 4019 * (due to limited buffer sizes). In this case we disable 4020 * the TX csum insertion in the TDES and not use SF. 4021 */ 4022 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 4023 features &= ~NETIF_F_CSUM_MASK; 4024 4025 /* Disable tso if asked by ethtool */ 4026 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 4027 if (features & NETIF_F_TSO) 4028 priv->tso = true; 4029 else 4030 priv->tso = false; 4031 } 4032 4033 return features; 4034 } 4035 4036 static int stmmac_set_features(struct net_device *netdev, 4037 netdev_features_t features) 4038 { 4039 struct stmmac_priv *priv = netdev_priv(netdev); 4040 bool sph_en; 4041 u32 chan; 4042 4043 /* Keep the COE Type in case of csum is supporting */ 4044 if (features & NETIF_F_RXCSUM) 4045 priv->hw->rx_csum = priv->plat->rx_coe; 4046 else 4047 priv->hw->rx_csum = 0; 4048 /* No check needed because rx_coe has been set before and it will be 4049 * fixed in case of issue. 4050 */ 4051 stmmac_rx_ipc(priv, priv->hw); 4052 4053 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 4054 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++) 4055 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 4056 4057 return 0; 4058 } 4059 4060 /** 4061 * stmmac_interrupt - main ISR 4062 * @irq: interrupt number. 4063 * @dev_id: to pass the net device pointer (must be valid). 4064 * Description: this is the main driver interrupt service routine. 4065 * It can call: 4066 * o DMA service routine (to manage incoming frame reception and transmission 4067 * status) 4068 * o Core interrupts to manage: remote wake-up, management counter, LPI 4069 * interrupts. 4070 */ 4071 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 4072 { 4073 struct net_device *dev = (struct net_device *)dev_id; 4074 struct stmmac_priv *priv = netdev_priv(dev); 4075 u32 rx_cnt = priv->plat->rx_queues_to_use; 4076 u32 tx_cnt = priv->plat->tx_queues_to_use; 4077 u32 queues_count; 4078 u32 queue; 4079 bool xmac; 4080 4081 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 4082 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt; 4083 4084 if (priv->irq_wake) 4085 pm_wakeup_event(priv->device, 0); 4086 4087 /* Check if adapter is up */ 4088 if (test_bit(STMMAC_DOWN, &priv->state)) 4089 return IRQ_HANDLED; 4090 /* Check if a fatal error happened */ 4091 if (stmmac_safety_feat_interrupt(priv)) 4092 return IRQ_HANDLED; 4093 4094 /* To handle GMAC own interrupts */ 4095 if ((priv->plat->has_gmac) || xmac) { 4096 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats); 4097 int mtl_status; 4098 4099 if (unlikely(status)) { 4100 /* For LPI we need to save the tx status */ 4101 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 4102 priv->tx_path_in_lpi_mode = true; 4103 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 4104 priv->tx_path_in_lpi_mode = false; 4105 } 4106 4107 for (queue = 0; queue < queues_count; queue++) { 4108 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4109 4110 mtl_status = stmmac_host_mtl_irq_status(priv, priv->hw, 4111 queue); 4112 if (mtl_status != -EINVAL) 4113 status |= mtl_status; 4114 4115 if (status & CORE_IRQ_MTL_RX_OVERFLOW) 4116 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 4117 rx_q->rx_tail_addr, 4118 queue); 4119 } 4120 4121 /* PCS link status */ 4122 if (priv->hw->pcs) { 4123 if (priv->xstats.pcs_link) 4124 netif_carrier_on(dev); 4125 else 4126 netif_carrier_off(dev); 4127 } 4128 } 4129 4130 /* To handle DMA interrupts */ 4131 stmmac_dma_interrupt(priv); 4132 4133 return IRQ_HANDLED; 4134 } 4135 4136 #ifdef CONFIG_NET_POLL_CONTROLLER 4137 /* Polling receive - used by NETCONSOLE and other diagnostic tools 4138 * to allow network I/O with interrupts disabled. 4139 */ 4140 static void stmmac_poll_controller(struct net_device *dev) 4141 { 4142 disable_irq(dev->irq); 4143 stmmac_interrupt(dev->irq, dev); 4144 enable_irq(dev->irq); 4145 } 4146 #endif 4147 4148 /** 4149 * stmmac_ioctl - Entry point for the Ioctl 4150 * @dev: Device pointer. 4151 * @rq: An IOCTL specefic structure, that can contain a pointer to 4152 * a proprietary structure used to pass information to the driver. 4153 * @cmd: IOCTL command 4154 * Description: 4155 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 4156 */ 4157 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 4158 { 4159 struct stmmac_priv *priv = netdev_priv (dev); 4160 int ret = -EOPNOTSUPP; 4161 4162 if (!netif_running(dev)) 4163 return -EINVAL; 4164 4165 switch (cmd) { 4166 case SIOCGMIIPHY: 4167 case SIOCGMIIREG: 4168 case SIOCSMIIREG: 4169 ret = phylink_mii_ioctl(priv->phylink, rq, cmd); 4170 break; 4171 case SIOCSHWTSTAMP: 4172 ret = stmmac_hwtstamp_set(dev, rq); 4173 break; 4174 case SIOCGHWTSTAMP: 4175 ret = stmmac_hwtstamp_get(dev, rq); 4176 break; 4177 default: 4178 break; 4179 } 4180 4181 return ret; 4182 } 4183 4184 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 4185 void *cb_priv) 4186 { 4187 struct stmmac_priv *priv = cb_priv; 4188 int ret = -EOPNOTSUPP; 4189 4190 if (!tc_cls_can_offload_and_chain0(priv->dev, type_data)) 4191 return ret; 4192 4193 stmmac_disable_all_queues(priv); 4194 4195 switch (type) { 4196 case TC_SETUP_CLSU32: 4197 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data); 4198 break; 4199 case TC_SETUP_CLSFLOWER: 4200 ret = stmmac_tc_setup_cls(priv, priv, type_data); 4201 break; 4202 default: 4203 break; 4204 } 4205 4206 stmmac_enable_all_queues(priv); 4207 return ret; 4208 } 4209 4210 static LIST_HEAD(stmmac_block_cb_list); 4211 4212 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type, 4213 void *type_data) 4214 { 4215 struct stmmac_priv *priv = netdev_priv(ndev); 4216 4217 switch (type) { 4218 case TC_SETUP_BLOCK: 4219 return flow_block_cb_setup_simple(type_data, 4220 &stmmac_block_cb_list, 4221 stmmac_setup_tc_block_cb, 4222 priv, priv, true); 4223 case TC_SETUP_QDISC_CBS: 4224 return stmmac_tc_setup_cbs(priv, priv, type_data); 4225 case TC_SETUP_QDISC_TAPRIO: 4226 return stmmac_tc_setup_taprio(priv, priv, type_data); 4227 case TC_SETUP_QDISC_ETF: 4228 return stmmac_tc_setup_etf(priv, priv, type_data); 4229 default: 4230 return -EOPNOTSUPP; 4231 } 4232 } 4233 4234 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb, 4235 struct net_device *sb_dev) 4236 { 4237 int gso = skb_shinfo(skb)->gso_type; 4238 4239 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) { 4240 /* 4241 * There is no way to determine the number of TSO/USO 4242 * capable Queues. Let's use always the Queue 0 4243 * because if TSO/USO is supported then at least this 4244 * one will be capable. 4245 */ 4246 return 0; 4247 } 4248 4249 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues; 4250 } 4251 4252 static int stmmac_set_mac_address(struct net_device *ndev, void *addr) 4253 { 4254 struct stmmac_priv *priv = netdev_priv(ndev); 4255 int ret = 0; 4256 4257 ret = eth_mac_addr(ndev, addr); 4258 if (ret) 4259 return ret; 4260 4261 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0); 4262 4263 return ret; 4264 } 4265 4266 #ifdef CONFIG_DEBUG_FS 4267 static struct dentry *stmmac_fs_dir; 4268 4269 static void sysfs_display_ring(void *head, int size, int extend_desc, 4270 struct seq_file *seq) 4271 { 4272 int i; 4273 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 4274 struct dma_desc *p = (struct dma_desc *)head; 4275 4276 for (i = 0; i < size; i++) { 4277 if (extend_desc) { 4278 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 4279 i, (unsigned int)virt_to_phys(ep), 4280 le32_to_cpu(ep->basic.des0), 4281 le32_to_cpu(ep->basic.des1), 4282 le32_to_cpu(ep->basic.des2), 4283 le32_to_cpu(ep->basic.des3)); 4284 ep++; 4285 } else { 4286 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 4287 i, (unsigned int)virt_to_phys(p), 4288 le32_to_cpu(p->des0), le32_to_cpu(p->des1), 4289 le32_to_cpu(p->des2), le32_to_cpu(p->des3)); 4290 p++; 4291 } 4292 seq_printf(seq, "\n"); 4293 } 4294 } 4295 4296 static int stmmac_rings_status_show(struct seq_file *seq, void *v) 4297 { 4298 struct net_device *dev = seq->private; 4299 struct stmmac_priv *priv = netdev_priv(dev); 4300 u32 rx_count = priv->plat->rx_queues_to_use; 4301 u32 tx_count = priv->plat->tx_queues_to_use; 4302 u32 queue; 4303 4304 if ((dev->flags & IFF_UP) == 0) 4305 return 0; 4306 4307 for (queue = 0; queue < rx_count; queue++) { 4308 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4309 4310 seq_printf(seq, "RX Queue %d:\n", queue); 4311 4312 if (priv->extend_desc) { 4313 seq_printf(seq, "Extended descriptor ring:\n"); 4314 sysfs_display_ring((void *)rx_q->dma_erx, 4315 DMA_RX_SIZE, 1, seq); 4316 } else { 4317 seq_printf(seq, "Descriptor ring:\n"); 4318 sysfs_display_ring((void *)rx_q->dma_rx, 4319 DMA_RX_SIZE, 0, seq); 4320 } 4321 } 4322 4323 for (queue = 0; queue < tx_count; queue++) { 4324 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 4325 4326 seq_printf(seq, "TX Queue %d:\n", queue); 4327 4328 if (priv->extend_desc) { 4329 seq_printf(seq, "Extended descriptor ring:\n"); 4330 sysfs_display_ring((void *)tx_q->dma_etx, 4331 DMA_TX_SIZE, 1, seq); 4332 } else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) { 4333 seq_printf(seq, "Descriptor ring:\n"); 4334 sysfs_display_ring((void *)tx_q->dma_tx, 4335 DMA_TX_SIZE, 0, seq); 4336 } 4337 } 4338 4339 return 0; 4340 } 4341 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status); 4342 4343 static int stmmac_dma_cap_show(struct seq_file *seq, void *v) 4344 { 4345 struct net_device *dev = seq->private; 4346 struct stmmac_priv *priv = netdev_priv(dev); 4347 4348 if (!priv->hw_cap_support) { 4349 seq_printf(seq, "DMA HW features not supported\n"); 4350 return 0; 4351 } 4352 4353 seq_printf(seq, "==============================\n"); 4354 seq_printf(seq, "\tDMA HW features\n"); 4355 seq_printf(seq, "==============================\n"); 4356 4357 seq_printf(seq, "\t10/100 Mbps: %s\n", 4358 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 4359 seq_printf(seq, "\t1000 Mbps: %s\n", 4360 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 4361 seq_printf(seq, "\tHalf duplex: %s\n", 4362 (priv->dma_cap.half_duplex) ? "Y" : "N"); 4363 seq_printf(seq, "\tHash Filter: %s\n", 4364 (priv->dma_cap.hash_filter) ? "Y" : "N"); 4365 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 4366 (priv->dma_cap.multi_addr) ? "Y" : "N"); 4367 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n", 4368 (priv->dma_cap.pcs) ? "Y" : "N"); 4369 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 4370 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 4371 seq_printf(seq, "\tPMT Remote wake up: %s\n", 4372 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 4373 seq_printf(seq, "\tPMT Magic Frame: %s\n", 4374 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 4375 seq_printf(seq, "\tRMON module: %s\n", 4376 (priv->dma_cap.rmon) ? "Y" : "N"); 4377 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 4378 (priv->dma_cap.time_stamp) ? "Y" : "N"); 4379 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n", 4380 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 4381 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n", 4382 (priv->dma_cap.eee) ? "Y" : "N"); 4383 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 4384 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 4385 (priv->dma_cap.tx_coe) ? "Y" : "N"); 4386 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 4387 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n", 4388 (priv->dma_cap.rx_coe) ? "Y" : "N"); 4389 } else { 4390 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 4391 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 4392 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 4393 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 4394 } 4395 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 4396 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 4397 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 4398 priv->dma_cap.number_rx_channel); 4399 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 4400 priv->dma_cap.number_tx_channel); 4401 seq_printf(seq, "\tNumber of Additional RX queues: %d\n", 4402 priv->dma_cap.number_rx_queues); 4403 seq_printf(seq, "\tNumber of Additional TX queues: %d\n", 4404 priv->dma_cap.number_tx_queues); 4405 seq_printf(seq, "\tEnhanced descriptors: %s\n", 4406 (priv->dma_cap.enh_desc) ? "Y" : "N"); 4407 seq_printf(seq, "\tTX Fifo Size: %d\n", priv->dma_cap.tx_fifo_size); 4408 seq_printf(seq, "\tRX Fifo Size: %d\n", priv->dma_cap.rx_fifo_size); 4409 seq_printf(seq, "\tHash Table Size: %d\n", priv->dma_cap.hash_tb_sz); 4410 seq_printf(seq, "\tTSO: %s\n", priv->dma_cap.tsoen ? "Y" : "N"); 4411 seq_printf(seq, "\tNumber of PPS Outputs: %d\n", 4412 priv->dma_cap.pps_out_num); 4413 seq_printf(seq, "\tSafety Features: %s\n", 4414 priv->dma_cap.asp ? "Y" : "N"); 4415 seq_printf(seq, "\tFlexible RX Parser: %s\n", 4416 priv->dma_cap.frpsel ? "Y" : "N"); 4417 seq_printf(seq, "\tEnhanced Addressing: %d\n", 4418 priv->dma_cap.addr64); 4419 seq_printf(seq, "\tReceive Side Scaling: %s\n", 4420 priv->dma_cap.rssen ? "Y" : "N"); 4421 seq_printf(seq, "\tVLAN Hash Filtering: %s\n", 4422 priv->dma_cap.vlhash ? "Y" : "N"); 4423 seq_printf(seq, "\tSplit Header: %s\n", 4424 priv->dma_cap.sphen ? "Y" : "N"); 4425 seq_printf(seq, "\tVLAN TX Insertion: %s\n", 4426 priv->dma_cap.vlins ? "Y" : "N"); 4427 seq_printf(seq, "\tDouble VLAN: %s\n", 4428 priv->dma_cap.dvlan ? "Y" : "N"); 4429 seq_printf(seq, "\tNumber of L3/L4 Filters: %d\n", 4430 priv->dma_cap.l3l4fnum); 4431 seq_printf(seq, "\tARP Offloading: %s\n", 4432 priv->dma_cap.arpoffsel ? "Y" : "N"); 4433 seq_printf(seq, "\tEnhancements to Scheduled Traffic (EST): %s\n", 4434 priv->dma_cap.estsel ? "Y" : "N"); 4435 seq_printf(seq, "\tFrame Preemption (FPE): %s\n", 4436 priv->dma_cap.fpesel ? "Y" : "N"); 4437 seq_printf(seq, "\tTime-Based Scheduling (TBS): %s\n", 4438 priv->dma_cap.tbssel ? "Y" : "N"); 4439 return 0; 4440 } 4441 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap); 4442 4443 /* Use network device events to rename debugfs file entries. 4444 */ 4445 static int stmmac_device_event(struct notifier_block *unused, 4446 unsigned long event, void *ptr) 4447 { 4448 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 4449 struct stmmac_priv *priv = netdev_priv(dev); 4450 4451 if (dev->netdev_ops != &stmmac_netdev_ops) 4452 goto done; 4453 4454 switch (event) { 4455 case NETDEV_CHANGENAME: 4456 if (priv->dbgfs_dir) 4457 priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir, 4458 priv->dbgfs_dir, 4459 stmmac_fs_dir, 4460 dev->name); 4461 break; 4462 } 4463 done: 4464 return NOTIFY_DONE; 4465 } 4466 4467 static struct notifier_block stmmac_notifier = { 4468 .notifier_call = stmmac_device_event, 4469 }; 4470 4471 static void stmmac_init_fs(struct net_device *dev) 4472 { 4473 struct stmmac_priv *priv = netdev_priv(dev); 4474 4475 rtnl_lock(); 4476 4477 /* Create per netdev entries */ 4478 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); 4479 4480 /* Entry to report DMA RX/TX rings */ 4481 debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev, 4482 &stmmac_rings_status_fops); 4483 4484 /* Entry to report the DMA HW features */ 4485 debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev, 4486 &stmmac_dma_cap_fops); 4487 4488 rtnl_unlock(); 4489 } 4490 4491 static void stmmac_exit_fs(struct net_device *dev) 4492 { 4493 struct stmmac_priv *priv = netdev_priv(dev); 4494 4495 debugfs_remove_recursive(priv->dbgfs_dir); 4496 } 4497 #endif /* CONFIG_DEBUG_FS */ 4498 4499 static u32 stmmac_vid_crc32_le(__le16 vid_le) 4500 { 4501 unsigned char *data = (unsigned char *)&vid_le; 4502 unsigned char data_byte = 0; 4503 u32 crc = ~0x0; 4504 u32 temp = 0; 4505 int i, bits; 4506 4507 bits = get_bitmask_order(VLAN_VID_MASK); 4508 for (i = 0; i < bits; i++) { 4509 if ((i % 8) == 0) 4510 data_byte = data[i / 8]; 4511 4512 temp = ((crc & 1) ^ data_byte) & 1; 4513 crc >>= 1; 4514 data_byte >>= 1; 4515 4516 if (temp) 4517 crc ^= 0xedb88320; 4518 } 4519 4520 return crc; 4521 } 4522 4523 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double) 4524 { 4525 u32 crc, hash = 0; 4526 __le16 pmatch = 0; 4527 int count = 0; 4528 u16 vid = 0; 4529 4530 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { 4531 __le16 vid_le = cpu_to_le16(vid); 4532 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28; 4533 hash |= (1 << crc); 4534 count++; 4535 } 4536 4537 if (!priv->dma_cap.vlhash) { 4538 if (count > 2) /* VID = 0 always passes filter */ 4539 return -EOPNOTSUPP; 4540 4541 pmatch = cpu_to_le16(vid); 4542 hash = 0; 4543 } 4544 4545 return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double); 4546 } 4547 4548 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid) 4549 { 4550 struct stmmac_priv *priv = netdev_priv(ndev); 4551 bool is_double = false; 4552 int ret; 4553 4554 if (be16_to_cpu(proto) == ETH_P_8021AD) 4555 is_double = true; 4556 4557 set_bit(vid, priv->active_vlans); 4558 ret = stmmac_vlan_update(priv, is_double); 4559 if (ret) { 4560 clear_bit(vid, priv->active_vlans); 4561 return ret; 4562 } 4563 4564 if (priv->hw->num_vlan) { 4565 ret = stmmac_add_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 4566 if (ret) 4567 return ret; 4568 } 4569 4570 return 0; 4571 } 4572 4573 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid) 4574 { 4575 struct stmmac_priv *priv = netdev_priv(ndev); 4576 bool is_double = false; 4577 int ret; 4578 4579 if (be16_to_cpu(proto) == ETH_P_8021AD) 4580 is_double = true; 4581 4582 clear_bit(vid, priv->active_vlans); 4583 4584 if (priv->hw->num_vlan) { 4585 ret = stmmac_del_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 4586 if (ret) 4587 return ret; 4588 } 4589 4590 return stmmac_vlan_update(priv, is_double); 4591 } 4592 4593 static const struct net_device_ops stmmac_netdev_ops = { 4594 .ndo_open = stmmac_open, 4595 .ndo_start_xmit = stmmac_xmit, 4596 .ndo_stop = stmmac_release, 4597 .ndo_change_mtu = stmmac_change_mtu, 4598 .ndo_fix_features = stmmac_fix_features, 4599 .ndo_set_features = stmmac_set_features, 4600 .ndo_set_rx_mode = stmmac_set_rx_mode, 4601 .ndo_tx_timeout = stmmac_tx_timeout, 4602 .ndo_do_ioctl = stmmac_ioctl, 4603 .ndo_setup_tc = stmmac_setup_tc, 4604 .ndo_select_queue = stmmac_select_queue, 4605 #ifdef CONFIG_NET_POLL_CONTROLLER 4606 .ndo_poll_controller = stmmac_poll_controller, 4607 #endif 4608 .ndo_set_mac_address = stmmac_set_mac_address, 4609 .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid, 4610 .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid, 4611 }; 4612 4613 static void stmmac_reset_subtask(struct stmmac_priv *priv) 4614 { 4615 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state)) 4616 return; 4617 if (test_bit(STMMAC_DOWN, &priv->state)) 4618 return; 4619 4620 netdev_err(priv->dev, "Reset adapter.\n"); 4621 4622 rtnl_lock(); 4623 netif_trans_update(priv->dev); 4624 while (test_and_set_bit(STMMAC_RESETING, &priv->state)) 4625 usleep_range(1000, 2000); 4626 4627 set_bit(STMMAC_DOWN, &priv->state); 4628 dev_close(priv->dev); 4629 dev_open(priv->dev, NULL); 4630 clear_bit(STMMAC_DOWN, &priv->state); 4631 clear_bit(STMMAC_RESETING, &priv->state); 4632 rtnl_unlock(); 4633 } 4634 4635 static void stmmac_service_task(struct work_struct *work) 4636 { 4637 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 4638 service_task); 4639 4640 stmmac_reset_subtask(priv); 4641 clear_bit(STMMAC_SERVICE_SCHED, &priv->state); 4642 } 4643 4644 /** 4645 * stmmac_hw_init - Init the MAC device 4646 * @priv: driver private structure 4647 * Description: this function is to configure the MAC device according to 4648 * some platform parameters or the HW capability register. It prepares the 4649 * driver to use either ring or chain modes and to setup either enhanced or 4650 * normal descriptors. 4651 */ 4652 static int stmmac_hw_init(struct stmmac_priv *priv) 4653 { 4654 int ret; 4655 4656 /* dwmac-sun8i only work in chain mode */ 4657 if (priv->plat->has_sun8i) 4658 chain_mode = 1; 4659 priv->chain_mode = chain_mode; 4660 4661 /* Initialize HW Interface */ 4662 ret = stmmac_hwif_init(priv); 4663 if (ret) 4664 return ret; 4665 4666 /* Get the HW capability (new GMAC newer than 3.50a) */ 4667 priv->hw_cap_support = stmmac_get_hw_features(priv); 4668 if (priv->hw_cap_support) { 4669 dev_info(priv->device, "DMA HW capability register supported\n"); 4670 4671 /* We can override some gmac/dma configuration fields: e.g. 4672 * enh_desc, tx_coe (e.g. that are passed through the 4673 * platform) with the values from the HW capability 4674 * register (if supported). 4675 */ 4676 priv->plat->enh_desc = priv->dma_cap.enh_desc; 4677 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; 4678 priv->hw->pmt = priv->plat->pmt; 4679 if (priv->dma_cap.hash_tb_sz) { 4680 priv->hw->multicast_filter_bins = 4681 (BIT(priv->dma_cap.hash_tb_sz) << 5); 4682 priv->hw->mcast_bits_log2 = 4683 ilog2(priv->hw->multicast_filter_bins); 4684 } 4685 4686 /* TXCOE doesn't work in thresh DMA mode */ 4687 if (priv->plat->force_thresh_dma_mode) 4688 priv->plat->tx_coe = 0; 4689 else 4690 priv->plat->tx_coe = priv->dma_cap.tx_coe; 4691 4692 /* In case of GMAC4 rx_coe is from HW cap register. */ 4693 priv->plat->rx_coe = priv->dma_cap.rx_coe; 4694 4695 if (priv->dma_cap.rx_coe_type2) 4696 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 4697 else if (priv->dma_cap.rx_coe_type1) 4698 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 4699 4700 } else { 4701 dev_info(priv->device, "No HW DMA feature register supported\n"); 4702 } 4703 4704 if (priv->plat->rx_coe) { 4705 priv->hw->rx_csum = priv->plat->rx_coe; 4706 dev_info(priv->device, "RX Checksum Offload Engine supported\n"); 4707 if (priv->synopsys_id < DWMAC_CORE_4_00) 4708 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum); 4709 } 4710 if (priv->plat->tx_coe) 4711 dev_info(priv->device, "TX Checksum insertion supported\n"); 4712 4713 if (priv->plat->pmt) { 4714 dev_info(priv->device, "Wake-Up On Lan supported\n"); 4715 device_set_wakeup_capable(priv->device, 1); 4716 } 4717 4718 if (priv->dma_cap.tsoen) 4719 dev_info(priv->device, "TSO supported\n"); 4720 4721 /* Run HW quirks, if any */ 4722 if (priv->hwif_quirks) { 4723 ret = priv->hwif_quirks(priv); 4724 if (ret) 4725 return ret; 4726 } 4727 4728 /* Rx Watchdog is available in the COREs newer than the 3.40. 4729 * In some case, for example on bugged HW this feature 4730 * has to be disable and this can be done by passing the 4731 * riwt_off field from the platform. 4732 */ 4733 if (((priv->synopsys_id >= DWMAC_CORE_3_50) || 4734 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) { 4735 priv->use_riwt = 1; 4736 dev_info(priv->device, 4737 "Enable RX Mitigation via HW Watchdog Timer\n"); 4738 } 4739 4740 return 0; 4741 } 4742 4743 /** 4744 * stmmac_dvr_probe 4745 * @device: device pointer 4746 * @plat_dat: platform data pointer 4747 * @res: stmmac resource pointer 4748 * Description: this is the main probe function used to 4749 * call the alloc_etherdev, allocate the priv structure. 4750 * Return: 4751 * returns 0 on success, otherwise errno. 4752 */ 4753 int stmmac_dvr_probe(struct device *device, 4754 struct plat_stmmacenet_data *plat_dat, 4755 struct stmmac_resources *res) 4756 { 4757 struct net_device *ndev = NULL; 4758 struct stmmac_priv *priv; 4759 u32 queue, rxq, maxq; 4760 int i, ret = 0; 4761 4762 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv), 4763 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES); 4764 if (!ndev) 4765 return -ENOMEM; 4766 4767 SET_NETDEV_DEV(ndev, device); 4768 4769 priv = netdev_priv(ndev); 4770 priv->device = device; 4771 priv->dev = ndev; 4772 4773 stmmac_set_ethtool_ops(ndev); 4774 priv->pause = pause; 4775 priv->plat = plat_dat; 4776 priv->ioaddr = res->addr; 4777 priv->dev->base_addr = (unsigned long)res->addr; 4778 4779 priv->dev->irq = res->irq; 4780 priv->wol_irq = res->wol_irq; 4781 priv->lpi_irq = res->lpi_irq; 4782 4783 if (!IS_ERR_OR_NULL(res->mac)) 4784 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN); 4785 4786 dev_set_drvdata(device, priv->dev); 4787 4788 /* Verify driver arguments */ 4789 stmmac_verify_args(); 4790 4791 /* Allocate workqueue */ 4792 priv->wq = create_singlethread_workqueue("stmmac_wq"); 4793 if (!priv->wq) { 4794 dev_err(priv->device, "failed to create workqueue\n"); 4795 return -ENOMEM; 4796 } 4797 4798 INIT_WORK(&priv->service_task, stmmac_service_task); 4799 4800 /* Override with kernel parameters if supplied XXX CRS XXX 4801 * this needs to have multiple instances 4802 */ 4803 if ((phyaddr >= 0) && (phyaddr <= 31)) 4804 priv->plat->phy_addr = phyaddr; 4805 4806 if (priv->plat->stmmac_rst) { 4807 ret = reset_control_assert(priv->plat->stmmac_rst); 4808 reset_control_deassert(priv->plat->stmmac_rst); 4809 /* Some reset controllers have only reset callback instead of 4810 * assert + deassert callbacks pair. 4811 */ 4812 if (ret == -ENOTSUPP) 4813 reset_control_reset(priv->plat->stmmac_rst); 4814 } 4815 4816 /* Init MAC and get the capabilities */ 4817 ret = stmmac_hw_init(priv); 4818 if (ret) 4819 goto error_hw_init; 4820 4821 stmmac_check_ether_addr(priv); 4822 4823 /* Configure real RX and TX queues */ 4824 netif_set_real_num_rx_queues(ndev, priv->plat->rx_queues_to_use); 4825 netif_set_real_num_tx_queues(ndev, priv->plat->tx_queues_to_use); 4826 4827 ndev->netdev_ops = &stmmac_netdev_ops; 4828 4829 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 4830 NETIF_F_RXCSUM; 4831 4832 ret = stmmac_tc_init(priv, priv); 4833 if (!ret) { 4834 ndev->hw_features |= NETIF_F_HW_TC; 4835 } 4836 4837 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 4838 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6; 4839 if (priv->plat->has_gmac4) 4840 ndev->hw_features |= NETIF_F_GSO_UDP_L4; 4841 priv->tso = true; 4842 dev_info(priv->device, "TSO feature enabled\n"); 4843 } 4844 4845 if (priv->dma_cap.sphen) { 4846 ndev->hw_features |= NETIF_F_GRO; 4847 priv->sph = true; 4848 dev_info(priv->device, "SPH feature enabled\n"); 4849 } 4850 4851 if (priv->dma_cap.addr64) { 4852 ret = dma_set_mask_and_coherent(device, 4853 DMA_BIT_MASK(priv->dma_cap.addr64)); 4854 if (!ret) { 4855 dev_info(priv->device, "Using %d bits DMA width\n", 4856 priv->dma_cap.addr64); 4857 4858 /* 4859 * If more than 32 bits can be addressed, make sure to 4860 * enable enhanced addressing mode. 4861 */ 4862 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)) 4863 priv->plat->dma_cfg->eame = true; 4864 } else { 4865 ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32)); 4866 if (ret) { 4867 dev_err(priv->device, "Failed to set DMA Mask\n"); 4868 goto error_hw_init; 4869 } 4870 4871 priv->dma_cap.addr64 = 32; 4872 } 4873 } 4874 4875 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 4876 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 4877 #ifdef STMMAC_VLAN_TAG_USED 4878 /* Both mac100 and gmac support receive VLAN tag detection */ 4879 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX; 4880 if (priv->dma_cap.vlhash) { 4881 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 4882 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER; 4883 } 4884 if (priv->dma_cap.vlins) { 4885 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; 4886 if (priv->dma_cap.dvlan) 4887 ndev->features |= NETIF_F_HW_VLAN_STAG_TX; 4888 } 4889 #endif 4890 priv->msg_enable = netif_msg_init(debug, default_msg_level); 4891 4892 /* Initialize RSS */ 4893 rxq = priv->plat->rx_queues_to_use; 4894 netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key)); 4895 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 4896 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq); 4897 4898 if (priv->dma_cap.rssen && priv->plat->rss_en) 4899 ndev->features |= NETIF_F_RXHASH; 4900 4901 /* MTU range: 46 - hw-specific max */ 4902 ndev->min_mtu = ETH_ZLEN - ETH_HLEN; 4903 if (priv->plat->has_xgmac) 4904 ndev->max_mtu = XGMAC_JUMBO_LEN; 4905 else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) 4906 ndev->max_mtu = JUMBO_LEN; 4907 else 4908 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 4909 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu 4910 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range. 4911 */ 4912 if ((priv->plat->maxmtu < ndev->max_mtu) && 4913 (priv->plat->maxmtu >= ndev->min_mtu)) 4914 ndev->max_mtu = priv->plat->maxmtu; 4915 else if (priv->plat->maxmtu < ndev->min_mtu) 4916 dev_warn(priv->device, 4917 "%s: warning: maxmtu having invalid value (%d)\n", 4918 __func__, priv->plat->maxmtu); 4919 4920 if (flow_ctrl) 4921 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 4922 4923 /* Setup channels NAPI */ 4924 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 4925 4926 for (queue = 0; queue < maxq; queue++) { 4927 struct stmmac_channel *ch = &priv->channel[queue]; 4928 4929 spin_lock_init(&ch->lock); 4930 ch->priv_data = priv; 4931 ch->index = queue; 4932 4933 if (queue < priv->plat->rx_queues_to_use) { 4934 netif_napi_add(ndev, &ch->rx_napi, stmmac_napi_poll_rx, 4935 NAPI_POLL_WEIGHT); 4936 } 4937 if (queue < priv->plat->tx_queues_to_use) { 4938 netif_tx_napi_add(ndev, &ch->tx_napi, 4939 stmmac_napi_poll_tx, 4940 NAPI_POLL_WEIGHT); 4941 } 4942 } 4943 4944 mutex_init(&priv->lock); 4945 4946 /* If a specific clk_csr value is passed from the platform 4947 * this means that the CSR Clock Range selection cannot be 4948 * changed at run-time and it is fixed. Viceversa the driver'll try to 4949 * set the MDC clock dynamically according to the csr actual 4950 * clock input. 4951 */ 4952 if (priv->plat->clk_csr >= 0) 4953 priv->clk_csr = priv->plat->clk_csr; 4954 else 4955 stmmac_clk_csr_set(priv); 4956 4957 stmmac_check_pcs_mode(priv); 4958 4959 if (priv->hw->pcs != STMMAC_PCS_TBI && 4960 priv->hw->pcs != STMMAC_PCS_RTBI) { 4961 /* MDIO bus Registration */ 4962 ret = stmmac_mdio_register(ndev); 4963 if (ret < 0) { 4964 dev_err(priv->device, 4965 "%s: MDIO bus (id: %d) registration failed", 4966 __func__, priv->plat->bus_id); 4967 goto error_mdio_register; 4968 } 4969 } 4970 4971 ret = stmmac_phy_setup(priv); 4972 if (ret) { 4973 netdev_err(ndev, "failed to setup phy (%d)\n", ret); 4974 goto error_phy_setup; 4975 } 4976 4977 ret = register_netdev(ndev); 4978 if (ret) { 4979 dev_err(priv->device, "%s: ERROR %i registering the device\n", 4980 __func__, ret); 4981 goto error_netdev_register; 4982 } 4983 4984 if (priv->plat->serdes_powerup) { 4985 ret = priv->plat->serdes_powerup(ndev, 4986 priv->plat->bsp_priv); 4987 4988 if (ret < 0) 4989 goto error_serdes_powerup; 4990 } 4991 4992 #ifdef CONFIG_DEBUG_FS 4993 stmmac_init_fs(ndev); 4994 #endif 4995 4996 return ret; 4997 4998 error_serdes_powerup: 4999 unregister_netdev(ndev); 5000 error_netdev_register: 5001 phylink_destroy(priv->phylink); 5002 error_phy_setup: 5003 if (priv->hw->pcs != STMMAC_PCS_TBI && 5004 priv->hw->pcs != STMMAC_PCS_RTBI) 5005 stmmac_mdio_unregister(ndev); 5006 error_mdio_register: 5007 for (queue = 0; queue < maxq; queue++) { 5008 struct stmmac_channel *ch = &priv->channel[queue]; 5009 5010 if (queue < priv->plat->rx_queues_to_use) 5011 netif_napi_del(&ch->rx_napi); 5012 if (queue < priv->plat->tx_queues_to_use) 5013 netif_napi_del(&ch->tx_napi); 5014 } 5015 error_hw_init: 5016 destroy_workqueue(priv->wq); 5017 5018 return ret; 5019 } 5020 EXPORT_SYMBOL_GPL(stmmac_dvr_probe); 5021 5022 /** 5023 * stmmac_dvr_remove 5024 * @dev: device pointer 5025 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 5026 * changes the link status, releases the DMA descriptor rings. 5027 */ 5028 int stmmac_dvr_remove(struct device *dev) 5029 { 5030 struct net_device *ndev = dev_get_drvdata(dev); 5031 struct stmmac_priv *priv = netdev_priv(ndev); 5032 5033 netdev_info(priv->dev, "%s: removing driver", __func__); 5034 5035 stmmac_stop_all_dma(priv); 5036 5037 if (priv->plat->serdes_powerdown) 5038 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 5039 5040 stmmac_mac_set(priv, priv->ioaddr, false); 5041 netif_carrier_off(ndev); 5042 unregister_netdev(ndev); 5043 #ifdef CONFIG_DEBUG_FS 5044 stmmac_exit_fs(ndev); 5045 #endif 5046 phylink_destroy(priv->phylink); 5047 if (priv->plat->stmmac_rst) 5048 reset_control_assert(priv->plat->stmmac_rst); 5049 clk_disable_unprepare(priv->plat->pclk); 5050 clk_disable_unprepare(priv->plat->stmmac_clk); 5051 if (priv->hw->pcs != STMMAC_PCS_TBI && 5052 priv->hw->pcs != STMMAC_PCS_RTBI) 5053 stmmac_mdio_unregister(ndev); 5054 destroy_workqueue(priv->wq); 5055 mutex_destroy(&priv->lock); 5056 5057 return 0; 5058 } 5059 EXPORT_SYMBOL_GPL(stmmac_dvr_remove); 5060 5061 /** 5062 * stmmac_suspend - suspend callback 5063 * @dev: device pointer 5064 * Description: this is the function to suspend the device and it is called 5065 * by the platform driver to stop the network queue, release the resources, 5066 * program the PMT register (for WoL), clean and release driver resources. 5067 */ 5068 int stmmac_suspend(struct device *dev) 5069 { 5070 struct net_device *ndev = dev_get_drvdata(dev); 5071 struct stmmac_priv *priv = netdev_priv(ndev); 5072 u32 chan; 5073 5074 if (!ndev || !netif_running(ndev)) 5075 return 0; 5076 5077 phylink_mac_change(priv->phylink, false); 5078 5079 mutex_lock(&priv->lock); 5080 5081 netif_device_detach(ndev); 5082 stmmac_stop_all_queues(priv); 5083 5084 stmmac_disable_all_queues(priv); 5085 5086 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 5087 del_timer_sync(&priv->tx_queue[chan].txtimer); 5088 5089 /* Stop TX/RX DMA */ 5090 stmmac_stop_all_dma(priv); 5091 5092 if (priv->plat->serdes_powerdown) 5093 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 5094 5095 /* Enable Power down mode by programming the PMT regs */ 5096 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 5097 stmmac_pmt(priv, priv->hw, priv->wolopts); 5098 priv->irq_wake = 1; 5099 } else { 5100 mutex_unlock(&priv->lock); 5101 rtnl_lock(); 5102 if (device_may_wakeup(priv->device)) 5103 phylink_speed_down(priv->phylink, false); 5104 phylink_stop(priv->phylink); 5105 rtnl_unlock(); 5106 mutex_lock(&priv->lock); 5107 5108 stmmac_mac_set(priv, priv->ioaddr, false); 5109 pinctrl_pm_select_sleep_state(priv->device); 5110 /* Disable clock in case of PWM is off */ 5111 if (priv->plat->clk_ptp_ref) 5112 clk_disable_unprepare(priv->plat->clk_ptp_ref); 5113 clk_disable_unprepare(priv->plat->pclk); 5114 clk_disable_unprepare(priv->plat->stmmac_clk); 5115 } 5116 mutex_unlock(&priv->lock); 5117 5118 priv->speed = SPEED_UNKNOWN; 5119 return 0; 5120 } 5121 EXPORT_SYMBOL_GPL(stmmac_suspend); 5122 5123 /** 5124 * stmmac_reset_queues_param - reset queue parameters 5125 * @dev: device pointer 5126 */ 5127 static void stmmac_reset_queues_param(struct stmmac_priv *priv) 5128 { 5129 u32 rx_cnt = priv->plat->rx_queues_to_use; 5130 u32 tx_cnt = priv->plat->tx_queues_to_use; 5131 u32 queue; 5132 5133 for (queue = 0; queue < rx_cnt; queue++) { 5134 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 5135 5136 rx_q->cur_rx = 0; 5137 rx_q->dirty_rx = 0; 5138 } 5139 5140 for (queue = 0; queue < tx_cnt; queue++) { 5141 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 5142 5143 tx_q->cur_tx = 0; 5144 tx_q->dirty_tx = 0; 5145 tx_q->mss = 0; 5146 } 5147 } 5148 5149 /** 5150 * stmmac_resume - resume callback 5151 * @dev: device pointer 5152 * Description: when resume this function is invoked to setup the DMA and CORE 5153 * in a usable state. 5154 */ 5155 int stmmac_resume(struct device *dev) 5156 { 5157 struct net_device *ndev = dev_get_drvdata(dev); 5158 struct stmmac_priv *priv = netdev_priv(ndev); 5159 int ret; 5160 5161 if (!netif_running(ndev)) 5162 return 0; 5163 5164 /* Power Down bit, into the PM register, is cleared 5165 * automatically as soon as a magic packet or a Wake-up frame 5166 * is received. Anyway, it's better to manually clear 5167 * this bit because it can generate problems while resuming 5168 * from another devices (e.g. serial console). 5169 */ 5170 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 5171 mutex_lock(&priv->lock); 5172 stmmac_pmt(priv, priv->hw, 0); 5173 mutex_unlock(&priv->lock); 5174 priv->irq_wake = 0; 5175 } else { 5176 pinctrl_pm_select_default_state(priv->device); 5177 /* enable the clk previously disabled */ 5178 clk_prepare_enable(priv->plat->stmmac_clk); 5179 clk_prepare_enable(priv->plat->pclk); 5180 if (priv->plat->clk_ptp_ref) 5181 clk_prepare_enable(priv->plat->clk_ptp_ref); 5182 /* reset the phy so that it's ready */ 5183 if (priv->mii) 5184 stmmac_mdio_reset(priv->mii); 5185 } 5186 5187 if (priv->plat->serdes_powerup) { 5188 ret = priv->plat->serdes_powerup(ndev, 5189 priv->plat->bsp_priv); 5190 5191 if (ret < 0) 5192 return ret; 5193 } 5194 5195 mutex_lock(&priv->lock); 5196 5197 stmmac_reset_queues_param(priv); 5198 5199 stmmac_clear_descriptors(priv); 5200 5201 stmmac_hw_setup(ndev, false); 5202 stmmac_init_coalesce(priv); 5203 stmmac_set_rx_mode(ndev); 5204 5205 stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw); 5206 5207 stmmac_enable_all_queues(priv); 5208 5209 stmmac_start_all_queues(priv); 5210 5211 mutex_unlock(&priv->lock); 5212 5213 if (!device_may_wakeup(priv->device) || !priv->plat->pmt) { 5214 rtnl_lock(); 5215 phylink_start(priv->phylink); 5216 /* We may have called phylink_speed_down before */ 5217 phylink_speed_up(priv->phylink); 5218 rtnl_unlock(); 5219 } 5220 5221 phylink_mac_change(priv->phylink, true); 5222 5223 netif_device_attach(ndev); 5224 5225 return 0; 5226 } 5227 EXPORT_SYMBOL_GPL(stmmac_resume); 5228 5229 #ifndef MODULE 5230 static int __init stmmac_cmdline_opt(char *str) 5231 { 5232 char *opt; 5233 5234 if (!str || !*str) 5235 return -EINVAL; 5236 while ((opt = strsep(&str, ",")) != NULL) { 5237 if (!strncmp(opt, "debug:", 6)) { 5238 if (kstrtoint(opt + 6, 0, &debug)) 5239 goto err; 5240 } else if (!strncmp(opt, "phyaddr:", 8)) { 5241 if (kstrtoint(opt + 8, 0, &phyaddr)) 5242 goto err; 5243 } else if (!strncmp(opt, "buf_sz:", 7)) { 5244 if (kstrtoint(opt + 7, 0, &buf_sz)) 5245 goto err; 5246 } else if (!strncmp(opt, "tc:", 3)) { 5247 if (kstrtoint(opt + 3, 0, &tc)) 5248 goto err; 5249 } else if (!strncmp(opt, "watchdog:", 9)) { 5250 if (kstrtoint(opt + 9, 0, &watchdog)) 5251 goto err; 5252 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 5253 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 5254 goto err; 5255 } else if (!strncmp(opt, "pause:", 6)) { 5256 if (kstrtoint(opt + 6, 0, &pause)) 5257 goto err; 5258 } else if (!strncmp(opt, "eee_timer:", 10)) { 5259 if (kstrtoint(opt + 10, 0, &eee_timer)) 5260 goto err; 5261 } else if (!strncmp(opt, "chain_mode:", 11)) { 5262 if (kstrtoint(opt + 11, 0, &chain_mode)) 5263 goto err; 5264 } 5265 } 5266 return 0; 5267 5268 err: 5269 pr_err("%s: ERROR broken module parameter conversion", __func__); 5270 return -EINVAL; 5271 } 5272 5273 __setup("stmmaceth=", stmmac_cmdline_opt); 5274 #endif /* MODULE */ 5275 5276 static int __init stmmac_init(void) 5277 { 5278 #ifdef CONFIG_DEBUG_FS 5279 /* Create debugfs main directory if it doesn't exist yet */ 5280 if (!stmmac_fs_dir) 5281 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 5282 register_netdevice_notifier(&stmmac_notifier); 5283 #endif 5284 5285 return 0; 5286 } 5287 5288 static void __exit stmmac_exit(void) 5289 { 5290 #ifdef CONFIG_DEBUG_FS 5291 unregister_netdevice_notifier(&stmmac_notifier); 5292 debugfs_remove_recursive(stmmac_fs_dir); 5293 #endif 5294 } 5295 5296 module_init(stmmac_init) 5297 module_exit(stmmac_exit) 5298 5299 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 5300 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 5301 MODULE_LICENSE("GPL"); 5302